DESCRIPTION
The 38B5 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent
display automatic display circuit, 12-channel 10-bit A-D converter, a
serial I/O with automatic transfer function, which are available for
controlling musical instruments and household appliances.
The 38B5 group has variations of internal memory size and packag-
ing. For details, refer to the section on part numbering.
For details on availability of microcomputers in the 38B5 group, refer
to the section on group expansion.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FEATURES
•Basic machine-language instructions ....................................... 71
•The minimum instruction execution time .......................... 0.48
µ
s
(at 4.19 MHz oscillation frequency)
•Memory sizeROM............................................. 24K to 60K bytes
RAM ............................................ 512 to 2048 bytes
•Programmable input/output ports ............................................. 55
•High-breakdown-voltage output ports.......................................36
•Software pull-up resistors ......
(Ports P5, P61 to P65, P7, P84 to P87, P9)
•Interrupts .................................................. 21 sources, 16 vectors
•Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1
•Serial I/O1 (Clock-synchronized) .................................... 8-bit ✕ 1
......................(max. 256-byte automatic transfer function)
•Serial I/O2 (UART or Clock-synchronized)..................... 8-bit ✕ 1
Fig. 1 Pin Configuration of M38B57MC-XXXFP
Package type : 80P6N-A
80-pin plastic-molded QFP
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P2
0
/B
UZ02
/FLD
0
P2
1
/FLD
1
P2
2
/FLD
2
P2
3
/FLD
3
P2
4
/FLD
4
P2
5
/FLD
5
P2
6
/FLD
6
P2
7
/FLD
7
P0
0
/FLD
8
P0
3
/FLD
11
P0
4
/FLD
12
P0
5
/FLD
13
P0
6
/FLD
14
P0
7
/FLD
15
P1
1
/FLD
17
P1
2
/FLD
18
P1
3
/FLD
19
P1
4
/FLD
20
P1
5
/FLD
21
P1
6
/FLD
22
P1
7
/FLD
23
P7
1
/AN
1
P7
0
/AN
0
P6
5
/S
STB1
/AN
11
P6
4
/INT
4
/S
BUSY1
/AN
10
M38B57MC-XXXFP
P6
0
/CNTR
1
P6
3
/AN
9
P6
2
/S
RDY1
/AN
8
RESET
P9
1
/X
COUT
P9
0
/X
CIN
P4
4
/PWM
1
P4
3
/B
UZ01
P4
2
/INT
3
P4
1
/INT
1
P4
0
/INT
0
V
EE
P7
5
/AN
5
P7
6
/AN
6
P7
7
/AN
7
V
REF
AV
SS
P5
0
/S
IN1
P5
1
/S
OUT1
P5
2
/S
CLK11
P5
3
/S
CLK12
P5
4
/RxD
P5
5
/TxD
P5
6
/S
CLK21
P5
7
/S
RDY2/
S
CLK22
P8
7
/PWM
0
/FLD
39
P8
6
/RTP
1
/FLD
38
P8
3
/FLD
35
P8
2
/FLD
34
P8
1
/FLD
33
P8
0
/FLD
32
P3
7
/FLD
31
P3
6
/FLD
30
P3
5
/FLD
29
P3
4
/FLD
28
P3
3
/FLD
27
P3
2
/FLD
26
P3
1
/FLD
25
P3
0
/FLD
24
P8
5
/RTP
0
/FLD
37
P6
1
/CNTR
0
/CNTR
2
P4
5
/T
1OUT
X
IN
X
OUT
Vcc
P4
6
/T
3OUT
Vss
P1
0
/FLD
16
P0
1
/FLD
9
P0
2
/FLD
10
P4
7
/INT
2
P8
4
/FLD
36
P7
4
/AN
4
P7
3
/AN
3
P7
2
/AN
2
•PWM .............................................................................14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
•A-D converter.............................................. 10-bit ✕ 12 channels
•Fluorescent display function ........................ Total 40 control pins
•Interrupt interval determination function .....................................1
•Watchdog timer.............................................................20-bit ✕ 1
•Buzzer output............................................................................. 1
•2 Clock generating circuit
Main clock (XIN–XOUT) ......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) ......... Without internal feedback resistor
(
connect to external ceramic resonator or quartz-crystal oscillator
)
•Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
(at 4.19 MHz oscillation frequency and high-speed selected)
In middle-speed mode ............................................... 2.7 to 5.5 V
(at 4.19 MHz oscillation frequency and middle-speed selected)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency and low-speed selected)
•Power dissipation
In high-speed mode .......................................................... 35 mW
(at 4.19 MHz oscillation frequency)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
•Operating temperature range ...................................–20 to 85 °C
APPLICATION
Musical instruments, VCR, household appliances, etc.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 2 Functional Block Diagram
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)
FUNCTIONAL BLOCK
Port P0(8)
8
Port P1(8)
8
Port P2(8)
8
Port P3(8)
8
Port P4(8)
7
Port P5(8)
8
Port P6(6)
6
Port P7(8)
8
Port P8(8)
8
Port P9(2)
2
System clock generation
X
IN
-X
OUT
(main-clock)
X
CIN
-X
COUT
(sub-clock)
Timers
Timer X(16-bit)
Timer 1(8-bit)
Timer 2(8-bit)
Timer 3(8-bit)
Timer 4(8-bit)
Timer 5(8-bit)
Timer 6(8-bit)
A-D converter
(10-bit ✕ 12 channel)
CPU core
Watchdog timer
ROM
RAM
Build-in peripheral functions
Memory
I/O ports
PWM0(14-bit)
PWM1(8-bit)
Serial I/O
Serial I/O1(Clock-synchronized)
(256 byte automatic transfer)
Serial I/O2
(Clock-synchronized or UART)
FLD display function
40 control pins
(36 high-breakdown voltage ports)
Interrupt interval
determination function
1
Buzzer output
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Table 1 Pin Description (1)
Pin Name Function
VCC, VSS Power source • Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS.
VEE Pull-down • Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.
power source
VREF Reference • Reference voltage input pin for A-D converter.
voltage
AVSS Analog power • Analog power source input pin for A-D converter.
source • Connect to VSS.
______
RESET Reset input • Reset input pin for active “L.”
XIN Clock input • Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
•
Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00/FLD8– I/O port P0 • 8-bit I/O port. • FLD automatic display
P07/FLD15 • I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• A pull-down resistor is built in between port P0 and the VEE pin.
• CMOS compatible input level.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P10/FLD16– Output port P1 • 8-bit output port. • FLD automatic display
P17/FLD23 • A pull-down resistor is built in between port P1 and the VEE pin. pins
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P20/BUZ02/ I/O port P2 • 8-bit I/O port with the same function as port P0. • FLD automatic display
FLD0– • Low-voltage input level. pins
P27/FLD7• High-breakdown-voltage P-channel open-drain output structure. • Buzzer output pin (P20)
P30/FLD24– Output port P3 • 8-bit output port. • FLD automatic display
P37/FLD31 • A pull-down resistor is built in between port P3 and the VEE pin. pins
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P40/INT0, I/O port P4 • 7-bit I/O port with the same function as port P0. • Interrupt input pins
P41/INT1, • CMOS compatible input level.
P42/INT3• N-channel open-drain output structure.
P43/BUZ01 • Buzzer output pin
P44/PWM1• PWM output pin
(Timer output pin)
P45/T1OUT, • Timer output pin
P46/T3OUT
P47/INT2Input port P4 • 1-bit input port. • Interrupt input pin
• CMOS compatible input level.
Function except a port function
XOUT Clock output
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 2 Pin Description (2)
Function except a port function
Pin Name Function
P50/SIN1, I/O port P5 • 8-bit CMOS I/O port with the same function as port P0. • Serial I/O1 function pins
P51/SOUT1, • CMOS compatible input level.
P52/SCLK11, • CMOS 3-state output structure.
P53/SCLK12
P54/RXD, • Serial I/O2 function pins
P55/TXD,
P56/SCLK21,
________
P57/SRDY2/
SCLK22
P60/CNTR1I/O port P6 • 1-bit I/O port with the same function as port P0. • Timer input pin
• CMOS compatible input level.
• N-channel open-drain output structure.
P61/CNTR0/ • 5-bit CMOS I/O port with the same function as port P0. • Timer I/O pin
CNTR2• CMOS compatible input level.
________
P62/SRDY1/ • CMOS 3-state output structure. • Serial I/O1 function pin
AN8• A-D conversion input pin
P63/AN9• A-D conversion input pin
P64/INT4/ • Serial I/O1 function pin
SBUSY1/AN10,
• A-D conversion input pin
P65/SSTB1/ • Interrupt input pin (P64)
AN11
P70/AN0– I/O port P7 • 8-bit CMOS I/O port with the same function as port P0. • A-D conversion input pin
P77/AN7• CMOS compatible input level.
• CMOS 3-state output structure.
P80/FLD32– I/O port P8 • 4-bit I/O port with the same function as port P0.
•
FLD automatic display pins
P83/FLD35
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
P84/FLD36 • 4-bit CMOS I/O port with the same function as port P0.
P85/RTP0/ • Low-voltage input level.
•
FLD automatic display pins
FLD37,
P86/RTP1/
FLD38
P87/PWM0/
•
FLD automatic display pins
FLD39 • 14-bit PWM output
P90/XCIN, I/O port P9 • 2-bit CMOS I/O port with the same function as port P0. •
I/O pins for sub-clock generating
P91/XCOUT • CMOS compatible input level.
circuit (connect a ceramic resona-
• CMOS 3-state output structure.
tor or a quarts-crystal oscillator)
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
5
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PART NUMBERING
Fig. 3 Part Numbering
M38B5 7 M C - XXX FP
Product
Package type
FP : 80P6N-A package
FS : 80D0 package
ROM number
Omitted in some types.
ROM/PROM size
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used for
users.
Memory type
M
E : Mask ROM version
: EPROM or One Time PROM version
RAM size
0
1
2
3
4
5
6
7
8
9
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
GROUP EXPANSION
Mitsubishi plans to expand the 38B5 group as follows:
Memory Type
Support for Mask ROM, One Time PROM and EPROM versions.
Memory Size
ROM/PROM size .................................................. 24K to 60K bytes
RAM size ...........................................................1024 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Fig. 4 Memory Expansion Plan
Currently supported products are listed below.
Table 3 List of Supported Products
(P) ROM size (bytes)
Product RAM size (bytes) Package Remarks
ROM size for User ( )
Note : Products under development or planning : the development schedule and specifications may be revised without notice.
As of Jan. 1998
M38B57MC-XXXFP 49152
(49022) 1024 80P6N-A Mask ROM version
60K
56K
52K
48K
44K
36K
32K
28K
24K
20K
16K
12K
8K
4K
40K
ROM size (bytes)
256 512 768 1,024 1,536 2,048
RAM size (bytes)
M38B59EF
M38B57M6
Under development
M38B57MC
New product
Planning
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 38B5 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 Family instructions are as follows:
•The FST and SLW instructions cannot be used.
•The MUL, DIV, WIT and STP instructions can be used.
Fig. 5 Structure of CPU Mode Register
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit and
internal system clock control bits. The CPU mode register is allo-
cated at address 003B16.
CPU mode register
(
CPUM (CM) : address
003B
16
)
b7 b0
Stack page selection bit
0 : 0 page
1 : 1 page
Main clock (X
IN
-X
OUT
) stop bit
0 : oscillating
1 : stopped
Main clock division ratio selection bit
0 : f(X
IN
) (high-speed mode)
1 : f(X
IN
)/4 (middle-speed mode)
Internal system clock selection bit
0 : X
IN
–X
OUT
selection (middle-/high-speed mode)
1 : X
CIN
–X
COUT
selection (low-speed mode)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1
1 0 Not available
1 1
Port X
C
switch bit
0 : I/O port function (stop oscillating)
1 : X
CIN
-X
COUT
oscillating
function
X
COUT
drivability selection bit
0 : Low drive
1 : High drive
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
8
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Memory
Special function register (SFR) area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing pro-
grams.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
Fig. 6 Memory Map Diagram
0100
16
0000
16
0040
16
0440
16
FF00
16
FFDC
16
FFFE
16
FFFF
16
192
256
384
512
640
768
896
1024
1536
2048
XXXX
16
00FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
3000
16
2000
16
1000
16
F080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
3080
16
2080
16
1080
16
YYYY
16
ZZZZ
16
RAM
ROM
0EF0
16
0F00
16
0EFF
16
0FFF
16
Reserved area
SFR area 1
Not used (Note)
Interrupt vector area
ROM area
Reserved ROM area
(common ROM area,128 byte)
Zero page
Special page
RAM area
RAM size
(byte) Address
XXXX
16
ROM size
(byte) Address
YYYY
16
Reserved ROM area
Address
ZZZZ
16
SFR area 2
RAM area for Serial I/O automatic
transfer
RAM area for FLD automatic display
Note: When 1024 bytes or more are used as RAM area, this area can be used.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 7 Memory Map of Special Function Register (SFR)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Serial I/O2 transmit/receive buffer register (TB/RB)
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
PWM register (high-order) (PWMH)
PWM register (low-order) (PWM L)
Baud rate generator (BRG)
UART control register (UARTCON)
Serial I/O1 automatic transfer data pointer (SIO1DP)
Serial I/O1 control register 1 (SIO1CON1)
Serial I/O1 control register 2 (SIO1CON2)
Serial I/O1 register/Transfer counter (SIO1)
Serial I/O1 control register 3 (SIO1CON3)
Serial I/O2 control register (SIO2CON)
Serial I/O2 status register (SIO2STS)
Port P9 (P9)
Port P9 direction register (P9D)
0EF0
16
0EF1
16
0EF2
16
0EF3
16
0EF4
16
0EF5
16
0EF6
16
0EF7
16
Toff2 time set register (TOFF2)
Pull-up control register 1 (PULL1)
Pull-up control register 2 (PULL2)
P1FLDRAM write disable register (P1FLDRAM)
P3FLDRAM write disable register (P3FLDRAM)
FLDC mode register (FLDM)
Tdisp time set register (TDISP)
Toff1 time set register (TOFF1)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Timer X mode register 1 (TXM1)
Interrupt control register 2(ICON2)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Timer 6 (T6)
PWM control register (PWMCON)
Timer 6 PWM register (T6PWM)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
Watchdog timer control register (WDTCON)
Timer X (low-order) (TXL)
Timer X (high-order) (TXH)
Timer X mode register 2 (TXM2)
Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
A-D control register (ADCON)
A-D conversion register (low-order) (ADL)
A-D conversion register (high-order) (ADH)
Interrupt source switch register (IFR)
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
0EF8
16
0EF9
16
0EFA
16
0EFB
16
0EFC
16
0EFD
16
0EFE
16
0EFF
16
FLD data pointer (FLDDP)
Port P0FLD/port switch register (P0FPR)
Port P2FLD/port switch register (P2FPR)
Port P8FLD/port switch register (P8FPR)
Port P8FLD output control register (P8FLDCON)
Buzzer output control register (BUZCON)
MITSUBISHI MICROCOMPUTERS
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
I/O Ports
[Direction Registers] PiD
The 38B5 group has 55 programmable I/O pins arranged in eight
individual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, and each pin can be set to be input port or output port. When
“0” is written to the bit corresponding to a pin, that pin becomes an
input pin. When “1” is written to that pin, that pin becomes an output
pin. If data is read from a pin set to output, the value of the port
output latch is read, not the value of the pin itself. Pins set to input
(the bit corresponding to that pin must be set to “0”) are floating and
the value of that pin can be read. If a pin set to input is written to, only
the port output latch is written to and the pin remains floating.
[High-Breakdown-Voltage Output Ports]
The 38B5 group microprocessors have 5 ports with high-breakdown-
voltage pins (ports P0–P3 and P80–P83). The high-breakdown-volt-
age ports have P-channel open-drain output with Vcc- 45 V of break-
down voltage. Each pin in ports P0, P1, and P3 has an internal pull-
down resistor connected to VEE. At reset, the P-channel output tran-
sistor of each port latch is turned off, so that it goes to VEE level (“L”)
by the pull-down resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register (ad-
dress 0EF416) shows the rising transition of the output transistors for
reducing transient noise. At reset, bit 7 of the FLDC mode register is
set to “0” (strong drivability).
[Pull-up Control Register] PULL
Ports P5, P61–P65, P7, P84–P87 and P9 have built-in programmable
pull-up resistors. The pull-up resistors are valid only in the case that
the each control bit is set to “1” and the corresponding port direction
registers are set to input mode. Fig. 8 Structure of Pull-up Control Registers
(PULL1 and PULL2)
0: No pull-up
1: Pull-up
Pull-up control register 2
(PULL2 : address 0EF1
16
)
P7
0
, P7
1
pull-up control bit
P7
2
, P7
3
pull-up control bit
P7
4
, P7
5
pull-up control bit
P7
6
, P7
7
pull-up control bit
P8
4
, P8
5
pull-up control bit
P8
6
, P8
7
pull-up control bit
P9
0
, P9
1
pull-up control bit
Not used
(returns “0” when read)
b7 b0
0: No pull-up
1: Pull-up
Pull-up control register 1
(PULL1 : address 0EF0
16
)
P5
0
, P5
1
pull-up control bit
P5
2
, P5
3
pull-up control bit
P5
4
, P5
5
pull-up control bit
P5
6
, P5
7
pull-up control bit
P6
1
pull-up control bit
P6
2
, P6
3
pull-up control bit
P6
4
, P6
5
pull-up control bit
Not used
(returns “0” when read)
b7 b0
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 4 List of I/O Port Functions (1)
Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No.
P00/FLD8– Port P0 Input/output, CMOS compatible input level FLD automatic display function FLDC mode register (1)
P07/FLD15 individual bits High-breakdown voltage P-
Port P0FLD/port switch register
channel open-drain output
with pull-down resistor
P10/FLD16– Port P1 Output High-breakdown voltage P- FLDC mode register (2)
P17/FLD23 channel open-drain output
with pull-down resistor
P20/BUZ02/ Port P2 Input/output, Low-voltage input level Buzzer output (P20) FLDC mode register (3)
FLD0individual bits High-breakdown voltage P-
Port P2FLD/port switch register
P21/FLD1– channel open-drain output
Buzzer output control register
(1)
P27/FLD7
P30/FLD24– Port P3 Output High-breakdown voltage P- FLDC mode register (2)
P37/FLD31 channel open-drain output
with pull-down resistor
P40/INT0, Port P4 Input/output, CMOS compatible input level External interrupt input
Interrupt edge selection register
(4)
P41/INT1, individual bits N-channel open-drain output
P42/INT3
P43/BUZ01 Buzzer output
Buzzer output control register
(5)
P44/PWM1PWM output Timer 56 mode register (6)
P45/T1OUT Timer output Timer 12 mode register (7)
P46/T3OUT Timer output Timer 34 mode register (7)
P47/INT2Input CMOS compatible input level External interrput input I
nterrupt edge selection register
(8)
Interrupt interval determination
control register
P50/SIN1 Port P5 Input/output, CMOS compatible input level Serial I/O1 function I/O
Serial I/O1 control register 1, 2
(9)
P51/SOUT1, individual bits CMOS 3-state output (10)
P52/SCLK11,
P53/SCLK12
P54/RXD, Serial I/O2 function I/O Serial I/O2 control register (9)
P55/TXD, UART control register (10)
P56/SCLK21
________
P57/SRDY2/(11)
SCLK22
P60/CNTR1Port P6 CMOS compatible input level External count I/O
Interrupt edge selection register
(4)
N-channel open-drain output
P61/CNTR0/ CMOS compatible input level (12)
CNTR2CMOS 3-state output
________
P62/SRDY1/ Serial I/O1 function I/O
Serial I/O1 control register 1, 2
(13)
AN8A-D conversion input A-D control register
P63/AN9A-D conversion input A-D control register (14)
P64/INT4/ Serial I/O1 function I/O
Serial I/O1 control register 1, 2
(15)
SBUSY1/
AN10
A-D conversion input A-D control register
External interrupt input
Interrupt edge selection register
P65/SSTB1/ Serial I/O1 function I/O
Serial I/O1 control register 1, 2
(16)
AN11 A-D conversion input A-D control register
P70/AN0– Port P7 A-D conversion input A-D control register (14)
P77/AN7
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
12
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 5 List of I/O Port Functions (2)
Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No.
P80/FLD32– Port P8 Input/output, Low-voltage input level FLD automatic display function FLDC mode register (1)
P83/FLD35 individual bits High-breakdown voltage P-
Port P8FLD/port switch register
channel open-drain output
P84/FLD36 Low-voltage input level (17)
P85/RTP0/ CMOS 3-state output FLD automatic display function FLDC mode register (18)
FLD37, Real time port output
Port P8FLD/port switch register
P86/RTP1/Timer X mode register 2
FLD38
P87/PWM0/ FLD automatic display function FLDC mode register (19)
FLD39 PWM output
Port P8FLD/port switch register
PWM control register
P90/XCIN Port P9 CMOS compatible input level Sub-clock generating circuit I/O CPU mode register (20)
P91/XCOUT CMOS 3-state output (21)
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 9 Port Block Diagram (1)
(2) Ports P1, P3
(3) Port P2
0
(5) Port P4
3
(6) Port P4
4
(8) Port P4
7
(7) Ports P4
5
, P4
6
INT2 interrupt
input
* High-breakdown-voltage P-channel transistor
Notes 1: The dimmer signal sets the Toff timing.
2: A pull-down resistor is not built in to ports P2 and P8.
VEE
*
Timer 1 output bit
Timer 3 output bit
Timer 1 output
Timer 3 output
Dimmer signal (Note 1)
*
read
Buzzer control signal
Buzzer signal output
Timer 6 output selection bit
Timer 6 output
INT0
,
INT1
,
INT3 interrupt input
CNTR1 input
Timer 4 external clock input
(1) Ports P0, P2
1
–P2
7
, P8
0
–P8
3
Data bus
Local data
bus Port latch
Dimmer signal (Note 1)
*
FLD/Port
switch register
Direction register
read
VEE
(Note 2)
VEE
FLD/Port
switch register
Port latch
Direction register
Data bus
Local data
bus
(Note 2)
Data bus
Local data
bus Port latch
Dimmer signal (Note 1)
(4) Ports P4
0
–P4
2
, P6
0
Port latch
Direction register
Data bus
Buzzer control signal
Buzzer signal output
Port latch
Direction register
Data bus Port latch
Direction register
Data bus
Port latch
Direction register
Data bus
Data bus
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 10 Port Block Diagram (2)
Serial ready output
(9) Ports P50, P54
(13) Port P62(14) Ports P63, P7
(12) Port P61
Serial I/O input
Pull-up control
(10) Ports P51–P53, P55, P56
Serial clock input
Serial I/O2 mode selection bit
Output OFF control signal
T
X
D, S
OUT
or S
CLK
P5
2
,P5
3
,P5
6
P-channel output disable signal (P5
1
,P5
5
)
Timer X output
Timer X operating mode bit
CNTR
0
,CNTR
2
input
Timer2, TimerX external clock input
(11) Port P57
S
RDY2
output enable bit
Serial clock input
P6
2
/S
RDY1•
P6
4
/S
BUSY1
pin control bit
Serial ready output
A-D conversion input
Analog input pin selection bit
Serial ready input
Data bus Port latch
Direction register
Data bus Port latch
Direction register
Pull-up control
Pull-up control
Data bus Port latch
Direction register
Pull-up control
Data bus Port latch
Direction register
Pull-up control
Data bus Port latch
Direction register
Pull-up control
Data bus Port latch
Direction register
A-D conversion input
Analog input pin selection bit
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 11 Port Block Diagram (3)
(18) Ports P85, P86
(19) Port P87(20) Port P90
(21) Port P91
Port P90Oscillator
Port Xc switch bit
(17) Port P84
(16) Port P65
Sub-clock generating circuit input
Port Xc switch bit
P8
7
/PWM
output enable bit
PWM0 output
RTP output
Real time port
control bit
SSTB1 output
Pull-up control
(15) Port P64
Data bus
SBUSY1 output
INT4 interrupt input, SBUSY1 input
A-D conversion input
P62/SRDY1•P64/SBUSY1
pin control bit P65/SSTB1 pin control bit
Pull-up control
Port latch
Direction register
Analog input
pin selection
bit
Data bus Port latch
Direction register
A-D conversion input
Pull-up control
Port latch
Direction register
Data bus
Local data
bus
Dimmer signal
(Note)
FLD/Port
switch register
Pull-up control
Port latch
Direction register
Data bus
Local data
bus
Dimmer signal
(Note)
FLD/Port
switch register
Pull-up control
Port latch
Direction register
Data bus
Local data
bus
Dimmer signal
(Note)
FLD/Port
switch register
Pull-up control
Port latch
Direction register
Data bus
Port Xc switch bit Pull-up control
Port latch
Direction register
Data bus
* High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupts
Interrupts occur by twenty one sources: five external, fifteen internal,
and one software.
(1) Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are “1” and the interrupt disable flag
is “0.” Interrupt enable bits can be set or cleared by software. Inter-
rupt request bits can be cleared by software, but cannot be set by
software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occurs
at the same time the interrupt with highest priority is accepted first.
(2) Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Use
When the active edge of an external interrupt (INT0–INT4) is set or
when switching interrupt sources in the same vector address, the
corresponding interrupt request bit may also be set. Therefore, please
take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
MITSUBISHI MICROCOMPUTERS
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Vector Addresses (Note 1) Interrupt Request
Interrupt Source Priority Remarks
High Low Generating Conditions
Reset (Note 2) 1 FFFD16 FFFC16 At reset Non-maskable
INT02 FFFB16 FFFA16 At detection of either rising or falling edge of External interrupt
INT0 input (active edge selectable)
INT13 FFF916 FFF816 At detection of either rising or falling edge of External interrupt
INT1 input (active edge selectable)
INT24 FFF716 FFF616 At detection of either rising or falling edge of External interrupt
INT2 input (active edge selectable)
Remort control/ At 8-bit counter overflow Valid when interrupt interval
counter overflow determination is operating
Serial I/O1 5 FFF516 FFF416 At completion of data transfer Valid when serial I/O1 ordinary
mode is selected
Serial I/O1 auto- At completion of the last data transfer Valid when serial I/O1 automatic
matic transfer transfer mode is selected
Timer X 6 FFF316 FFF216 At timer X underflow
Timer 1 7 FFF116 FFF016 At timer 1 underflow
Timer 2 8 FFEF16 FFEE16 At timer 2 underflow STP release timer underflow
Timer 3 9 FFED16 FFEC16 At timer 3 underflow
Timer 4 10 FFEB16 FFEA16 At timer 4 underflow
Timer 5 11 FFE916 FFE816 At timer 5 underflow
Timer 6 12 FFE716 FFE616 At timer 6 underflow
Serial I/O2 receive
13 FFE516 FFE416 At completion of serial I/O2 data receive
INT314 FFE316 FFE216 At detection of either rising or falling edge of External interrupt
INT3 input (active edge selectable)
Serial I/O2 transmit
At completion of data transmit
INT415 FFE116 FFE016 At detection of either rising or falling edge of External interrupt
INT4 input (active edge selectable)
Valid when INT4 interrupt is selected
A-D conversion At completion of A-D conversion
Valid when A-D conversion is selected
FLD blanking 16 FFDF16 FFDE16 At falling edge of the last timing immediately Valid when FLD blanking
before blanking period starts interrupt is selected
FLD digit At rising edge of each digit
Valid when FLD digit interrupt is selected
BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt
Table 6 Interrupt Vector Addresses and Priority
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
MITSUBISHI MICROCOMPUTERS
38B5 Group
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 13 Structure of Interrupt Related Registers
Fig. 12 Interrupt Control
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
INT
0
interrupt enable bit
INT
1
interrupt enable bit
INT
2
interrupt enable bit
Remote controller/counter overflow interrupt
enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
INT
0
interrupt request bit
INT
1
interrupt request bit
INT
2
interrupt request bit
Remote controller/counter overflow interrupt
request bit
Serial I/O1 interrupt request bit
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt edge selection register
INT
0
interrupt edge selection bit
INT
1
interrupt edge selection bit
INT
2
interrupt edge selection bit
INT
3
interrupt edge selection bit
INT
4
interrupt edge selection bit
Not used (return "0" when read)
CNTR
0
pin edge
switch bit
CNTR
1
pin edge
switch bit
(INTEDGE : address 003A
16
)
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
Interrupt control register 1
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C
16
)
(ICON1 : address 003E
16
)
Interrupt request register 2
(IREQ2 : address 003D
16
)
Interrupt control register 2
0 : Interrupt disabled
1 : Interrupt enabled
(ICON2 : address 003F
16
)
Interrupt source switch register
INT
3
/serial I/O2 transmit
interrupt switch bit
0 : INT
3
interrupt
1 : Serial I/O2 transmit
interrupt
INT
4
/AD conversion
interrupt switch bit
0 : INT
4
interrupt
1 : A-D conversion
interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
(IFR : address 0039
16
)
0 : Rising edge count
1 : Falling edge count
INT
3
/serial I/O2 transmit interrupt enable bit
INT
4
interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
INT
3
/serial I/O2 transmit interrupt request bit
INT
4
interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O2 receive interrupt request bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O2 receive interrupt enable bit
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
19
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timers
8-Bit Timer
The 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
The count can be stopped by setting the stop bit of each timer to “1.”
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(XIN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1
underflow signal divided by 2 is output from the P45/T1OUT pin. The
waveform polarity changes each time timer 1 overflows. The active
edge of the external clock CNTR0 can be switched with the bit 6 of
the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2
is set to “0116.”
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3
underflow signal divided by 2 is output from the P46/T3OUT pin. The
waveform polarity changes each time timer 3 overflows. The active
edge of the external clock CNTR1 can be switched with the bit 7 of
the interrupt edge selection register.
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6
underflow signal divided by 2 is output from the P44/PWM1 pin. The
waveform polarity changes each time timer 6 overflows.
●Timer 6 PWM1 Mode
Timer 6 can output a rectangular waveform with “H” duty cycle n/
(n+m) from the P44/PWM1 pin by setting the timer 56 mode register
(refer to Figure 16). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Fig. 14 Structure of Timer Related Register
Timer 12 mode register
(T12M: address 002816)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR0
11 : Not available
Timer 1 output selection bit (P45)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Timer 34 mode register
(T34M: address 002916)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR1
11 : Not available
Timer 3 output selection bit (P46)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Timer 56 mode register
(T56M: address 002A16)
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/8 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P44)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7 b0
b7 b0
b7 b0
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
20
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 15 Block Diagram of Timer
XIN 1/8
P46/T3OUT
1/2
XCIN
“1”
“0”
“01”
“00”
“01”
“00”
“01”
“10”
“00”
“1”
“0”
“01”
“10”
“00”
“00”
“01”
P45/T1OUT
1/2
P61/CNTR0/CNTR2
“10”
1/2
PWM
P44/PWM1“1”
“0”
P60/CNTR1
1/64
1/2
“11”
“11”
1/16 “10”
“10”
Internal system clock
selection bit
Timer 1 count source
selection bit Timer 1 interrupt request
Data bus
Timer 1 latch (8)
Timer 1 (8)
FF16
Timer 1 count
stop bit
RESET
STP instruction
P45 latch
Timer 1 output selection bit
P45 direction register
Timer 2 count source
selection bit
Timer 2 latch (8)
Timer 2 (8)
Timer 2 count
stop bit
0116
Timer 3 count source
selection bit
Timer 3 latch (8)
Timer 3 (8)
Timer 3 count
stop bit
Timer 2 interrupt request
Timer 3 interrupt request
P46 latch
Rising/Falling
active edge switch
Timer 3 output selection bit
P46 direction register
Timer 4 count source
selection bit
Timer 4 latch (8)
Timer 4 (8)
Timer 4 count
stop bit
Rising/Falling
active edge switch
Timer 4 interrupt request
Timer 5 count source
selection bit
Timer 5 latch (8)
Timer 5 (8)
Timer 5 count
stop bit
Timer 5 interrupt request
P44 latch
Timer 6 output selection bit
P44 direction register
Timer 6 count source
selection bit
Timer 6 latch (8)
Timer 6 (8)
Timer 6 count
stop bit
Timer 6 PWM register (8)
Timer 6 operation
mode selection bit
Timer 6 interrupt request
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
21
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 16 Timing Chart of Timer 6 PWM1 Mode
ts
Timer 6
count source
Timer 6 PWM
mode
n
✕
ts
(n+m)
✕
ts
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m)
✕
ts) is output.
n : setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
m
✕
ts
Timer 6 interrupt request
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-Bit Timer
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode register 1, 2 and can be controlled the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the low-
order byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
●Timer X
Timer X is a down-counter. When the timer reaches “000016,” an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues down-
counting. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1.”
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR2 active edge switch bit is “0,” the timer counts while the input
signal of the CNTR2 pin is at “H.” When it is “1,” the timer counts
while the input signal of the CNTR2 pin is at “L.” When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
■ Note
•Timer X Write Control
If the timer X write control bit is “0,” when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1,” when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P85 and P86 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1,”
data are output without the timer X.) When the data for the real time
port is changed while the real time port function is valid, the changed
data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction regis-
ters to output mode.
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 18 Structure of Timer X Related Registers
b7 b0
Timer X mode register 1
(TXM1 : address 002E
16
)
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bits
b2 b1
0 0 : f(X
IN
)/2 or f(X
CIN
)/4
0 1 : f(X
IN
)/8 or f(X
CIN
)/16
1 0 : f(X
IN
)/64 or f(X
CIN
)/128
1 1 : Not available
Not used (returns "0" when read)
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR
2
active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse width measurement mode ; measures “H” periods
1 : • Event counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse width measurement mode ; measures “L” periods
Timer X stop control bit
0 : Count operating
1 : Count stop
Real time port control bit (P8
5
)
0 : Real time port function is invalid
1 : Real time port function is valid
Real time port control bit (P8
6
)
0 : Real time port function is invalid
1 : Real time port function is valid
P8
5
data for real time port
P8
6
data for real time port
Not used (returns "0" when read)
Timer X mode register 2
(TXM2 : address 002F
16
)
b7 b0
Fig. 17 Block Diagram of Timer X
CNTR
2
active
edge switch bit
CNTR
2
active
edge switch bit
Real time port
control bit
Real time port
control bit
S
“0”
“1”
“0”
“1” “10”
“00”,“01”,“11”
Q
QT
P6
1
/CNTR
0
/CNTR
2
CNTR
0
“1”
“0”
“1”
“0”
“1”
“0”
Q D
Q D
P8
5
P8
6
“1”
“0”
X
IN
X
CIN
“1”
“0”
1/2
1/2
1/8
1/64
P6
1
latch
Timer X (low-order) (8) Timer X (high-order) (8)
Timer X latch (high-order) (8)
Timer X latch (low-order) (8)
Data bus
Pulse output mode
P6
1
direction
register
Pulse width
measurement mode
Timer X operating
mode bit
Timer X stop
control bit
Pulse output mode
Count source selection bit
Internal system clock
selection bit
Divider
Timer X write
control bit
Timer X
interrupt request
Timer X mode register
write signal
P8
6
latch
P8
6
direction
register
P8
5
latch
P8
5
direction
register Latch
Latch
P8
5
data for real time port
Real time port
control bit (P8
5
)
P8
6
data for real time port
Real time port
control bit (P8
6
)
Timer X mode register
write signal
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Serial I/O
●Serial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
0F0016 to 0FFF16: addresses 0F6016 to 0FFF16 are also used as
Fig. 19 Block Diagram of Serial I/O1
FLD automatic display RAM).
________
The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11
pins each have a handshake I/O signal function and can select
either “H” active or “L” active for active logic.
Main
data bus
Serial I/O1
automatic transfer
controller
Local
data bus
Serial I/O automatic
transfer RAM
(0F0016—0FFF16)
Serial I/O1
control register 3
XCIN
XIN
Internal system
clock selection bit
Serial I/O1
automatic transfer
data pointer
Address decoder
Main address
bus Local address
bus
“1”
“0” 1/8
1/16
1/32
1/64
1/128
Serial I/O1
interrupt request
P64 latch
Serial I/O1 counter
Synchronous
circuit
Serial I/O1
synchronous clock
selection bit
“1”
P62 latch
P52/SCLK11
“0”
“1”
SCLK1
“0”
Internal synchronous
clock selection bits
1/256
P65 latch
P64/SBUSY1
P65/SSTB1
(P65/SSTB1 pin control bit)
Serial transfer
status flag
“0”
“1”
“0”
“1”
P62/SRDY1
“0”
“1”
P52 latch
P51/SOUT1
P50/SIN1
P51 latch
Serial I/O1 register (8)
“0”
“1” Serial transfer selection bits
1/2
Divider
1/4
Serial I/O1 clock
pin selection bit
P53/SCLK12 “1”
“0”
P53 latch
“0”
“1”
“0” “1”
Serial I/O1 clock
pin selection bits
P62/SRDY1•P64/SBUSY1
pin control bit
P62/SRDY1•P64/SBUSY1
pin control bit
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 20 Structure of Serial I/O1 Control Registers 1, 2
b7 b0
P6
2
/S
RDY1 •
P6
4
/S
BUSY1
pin control bits
0000: Pins P6
2
and P6
4
are I/O ports
0001: Not used
0010: P6
2
pin is an S
RDY1
output, P6
4
pin is an I/O port.
0011: P6
2
pin is an S
RDY1
output, P6
4
pin is an I/O port.
0100: P6
2
pin is an I/O port, P6
4
pin is an S
BUSY1
input.
0101: P6
2
pin is an I/O port, P6
4
pin is an S
BUSY1
input.
0110: P6
2
pin is an I/O port, P6
4
pin is an S
BUSY1
output.
0111: P6
2
pin is an I/O port, P6
4
pin is an S
BUSY1
output.
1000: P6
2
pin is an S
RDY1
input, P6
4
pin is an S
BUSY1
output.
1001: P6
2
pin is an S
RDY1
input, P6
4
pin is an S
BUSY1
output.
1010: P6
2
pin is an S
RDY1
input, P6
4
pin is an S
BUSY1
output.
1011: P6
2
pin is an S
RDY1
input, P6
4
pin is an S
BUSY1
output.
1100: P6
2
pin is an S
RDY1
output, P6
4
pin is an S
BUSY1
input.
1101: P6
2
pin is an S
RDY1
output, P6
4
pin is an S
BUSY1
input.
1110: P6
2
pin is an S
RDY1
output, P6
4
pin is an S
BUSY1
input.
1111: P6
2
pin is an S
RDY1
output, P6
4
pin is an S
BUSY1
input.
Serial I/O1 control register 2
(SIO1CON2 (SC12): address 001A
16
)
P5
1/
S
OUT1
P-channel output disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain (P-channel output is invalid.)
S
OUT1
pin control bit (at no-transfer serial data)
0: Output active
1: Output high-impedance
S
BUSY1
output • S
STB1
output function selection bit
(Valid in automatic transfer mode)
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
Serial transfer status flag
0: Serial transfer completion
1: Serial transferring
b7 b0
Serial I/O1 control register 1
(SIO1CON1 (SC11): address 0019
16
)
Serial I/O1 synchronous clock selection bits (P6
5
/S
STB1
pin control bit)
00: Internal synchronous clock (P6
5
pin is an I/O port.)
01: External synchronous clock (P6
5
pin is an I/O port.)
10: Internal synchronous clock (P6
5
pin is an S
STB1
output.)
11: Internal synchronous clock (P6
5
pin is an S
STB1
output.)
Transfer mode selection bit
0: Full duplex (transmit and receive) mode (P5
0
pin is an S
IN1
input.)
1: Transmit-only mode (P5
0
pin is an I/O port.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Serial I/O1 clock pin selection bit
0:S
CLK11
(P5
3/
S
CLK12
pin is an I/O port.)
1:S
CLK12
(P5
2/
S
CLK11
pin is an I/O port.)
Transfer direction selection bit
0: LSB first
1: MSB first
Serial transfer selection bits
00: Serial I/O disabled (pins P6
2
,P6
4
,P6
5
,and P5
0—
P5
3
are I/O ports)
01: 8-bits serial I/O
10: Not available
11: Automatic transfer serial I/O (8-bits)
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(1) Serial I/O1 Operation
Either the internal synchronous clock or external synchronous clock
can be selected by the serial I/O1 synchronous clock selection bits
(b2 and b3 of address 001916) of serial I/O1 control register 1 as
synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider where
7 different clocks are selected by the internal synchronous clock
selection bits (b5, b6 and b7 of address 001C16) of serial I/O1
control register 3.
________
The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11
pins each select either I/O port or handshake I/O signal by the
serial I/O1 synchronous clock selection bits (b2 and b3 of address
________
001916) of serial I/O1 control register 1 as well as the P62/SRDY1 •
P64/SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial
I/O1 control register 2.
For the SOUT1 being used as an output pin, either CMOS output or
N-channel open-drain output is selected by the P51/SOUT1 P-chan-
nel output disable bit (b7 of address 001A16) of serial I/O1 control
register 2.
Either output active or high-impedance can be selected as a SOUT1
pin state at serial non-transfer by the SOUT1 pin control bit (b6 of
address 001A16) of serial I/O1 control register 2. However, when
the external synchronous clock is selected, perform the following
setup to put the SOUT1 pin into a high-impedance state.
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1.”
When the SCLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the trans-
mit-only mode are available for serial transfer, one of which is se-
lected by the transfer mode selection bit (b5 of address 001916) of
serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6 of
address 001916) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or auto-
matic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 001916) of serial I/O1 control register 1, after comple-
tion of the above bit setup. Next, set the serial I/O initialization bit
(b4 of address 001916) of serial I/O1 control register 1 to “1” (Serial
I/O enable) .
When stopping serial transfer while data is being transferred, re-
gardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0.”
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C
16
)
Internal synchronous clock selection bits
000:f(X
IN
)/4 or f(X
CIN
)/8
001:f(X
IN
)/8 or f(X
CIN
)/16
010:f(X
IN
)/16 or f(X
CIN
)/32
011:f(X
IN
)/32 or f(X
CIN
)/64
100:f(X
IN
)/64 or f(X
CIN
)/128
101:f(X
IN
)/128 or f(X
CIN
)/256
110:f(X
IN
)/256 or f(X
CIN
)/512
Automatic transfer interval set bits
00000:2cycles of transfer clocks
00001:3cycles of transfer clocks
:
11110:32cycles of transfer clocks
11111:33cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
b7 b0
Fig. 21 Structure of Serial I/O1 Control Register 3
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
27
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(2) 8-bit Serial I/O Mode
Address 001B16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B16).
The serial transfer status flag (b5 of address 001A16) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which be-
comes a transfer start trigger and reset to “0” after completion of 8-
bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer clocks
are input to SCLK1. Therefore, the clock needs to be controlled ex-
ternally.
(3) Automatic Transfer Serial I/O Mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so the function of ad-
dress 001B16 is used as a transfer counter (1-byte units).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
Input the low-order 8 bits of the first data store address to be seri-
ally transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer inter-
val for each 1-byte data can be set by the automatic transfer inter-
val set bits (b0 to b4 of address 001C16) of serial I/O1 control regis-
ter 3 in the following cases:
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or a
combination of SBUSY1 output and SSTB1 output of the handshake
signal
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the SBUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A 16) of serial
I/O1 control register 2 as the signal for all transfer data, provided
that the automatic transfer interval setting is valid, a transfer inter-
val is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the SBUSY1 output •
SSTB1 output function selection bit (b4), the transfer interval for each
1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of SBUSY1 output and SSTB1
output as a signal for all transfer data, the transfer interval after the
end of transmission/reception of the last data is longer than the set
value by 2 cycles.
When the external synchronous clock is selected, automatic trans-
fer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes - 1” into the transfer counter
(address 001B16).
When the external synchronous clock is selected, write the value of
“number of transfer bytes - 1” into the transfer counter and input an
internal system clock interval of 5 cycles or more. After that, input
transfer clock to SCLK1.
As a transfer interval for each 1-byte data transfer, input an internal
system clock interval of 5 cycles or more from the clock rise time of
the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial
I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816) and the automatic transfer interval set
bits (b0 to b4 of address 001C16) are held in the latch.
When data is written into the transfer counter, the values latched in
the automatic transfer data pointer set bits (b0 to b7) and the auto-
matic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
Fig. 22 Structure of Serial I/O1 Automatic Transfer Data Pointer
b7 b0 Serial I/O1 automatic transfer data pointer
(SIO1DP: address 0018
16
)
Automatic transfer data pointer set bits
Specify the low-order 8 bits of the first data store address on the serial I/O automatic
transfer RAM. Data is written into the latch and read from the decrement counter.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FFF
16
Automatic transfer RAM
Transfer counter
Automatic transfer
data pointer
Serial I/O1 register
F52
16
F51
16
F50
16
F4F
16
F4E
16
F00
16
04
16
52
16
S
IN1
S
OUT1
Fig. 23 Automatic Transfer Serial I/O Operation
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
When the external synchronous clock is selected, input an “H” level
_________
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped. At this time,
the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 be-
come valid, enabling a transmit/receive operation, while an “L” level
signal is input into the SBUSY1 input and an “H” level signal is input
__________
into the SBUSY1 input.
__________
When changing the input values in the SBUSY1 input and the SBUSY1
input at these operations, change them when the SCLK1 input is in a
high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, en-
abling serial transfer by inputting a transfer clock to SCLK1, while an
“L” level signal is input into the SBUSY1 input and an “H” level signal
__________
is input into the SBUSY1 input.
3. SBUSY1 output signal
The SBUSY1 output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether the SBUSY1 output is to be active at trans-
fer of each 1-byte data or during transfer of all data can be selected
by the SBUSY1 output • SSTB1 output function selection bit (b4).
In the initial status, the status in which the serial I/O initialization bit
_________
(b4) is reset to “0,” the SBUSY1 output goes to “H” and the SBUSY1
output goes to “L.”
Fig. 25 SBUSY1 Input Operation (internal synchronous clock)
Fig. 26 SBUSY1 Input Operation (external synchronous clock)
(4) Handshake Signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/re-
ception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O
initialization bit (b4) is reset to “0,” the SSTB1 output goes to “L,” or
________
the SSTB1 output goes to “H.”
At the end of transmit/receive operation, when the data of the serial
I/O1 register is all output from SOUT1, pulses are output in the pe-
riod of 1 cycle of the transfer clock so as to cause the SSTB1 output
________
to go “H” or the SSTB1 output to go “L.” After that, each pulse is
returned to the initial status in which SSTB1 output goes to “L” or the
________
SSTB1 output goes to “H.”
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0.”
In the automatic transfer serial I/O mode, whether the SSTB1 output
is to be active at an end of each 1-byte data or after completion of
transfer of all data can be selected by the SBUSY1 output • SSTB1
output function selection bit (b4 of address 001A16) of serial I/O1
control register 2.
2. SBUSY1 input signal
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
__________
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal
__________
into the SBUSY1 input and an “H” level signal into the SBUSY1 input in
the period of 1.5 cycles or more of the transfer clock. Then, transfer
clocks are output from the SCLK1 output.
When an “H” level signal is input into the SBUSY1 input and an “L”
__________
level signal into the SBUSY1 input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immedi-
ately and the transfer clocks from the SCLK1 output is not stopped
until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
Fig. 24 SSTB1 Output Operation
S
STB1
S
CLK1
S
OUT1
Serial transfer
status flag
S
BUSY1
S
CLK1
S
OUT1
S
BUSY1
S
CLK1
S
OUT1
Invalid
(Output high-impedance)
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
30
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY1 out-
put function outputs in 1-byte units), the SBUSY1 output goes to “L”
_________
and the SBUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the SCLK1 output goes
to “L” at a start of transmit/receive operation.
In the automatic transfer serial I/O mode (the SBUSY1 output func-
tion outputs all transfer data), the SBUSY1 output goes to “L” and the
_________
SBUSY1 output goes to “H” when the first transmit data is written into
the serial I/O1 register (address 001B16).
When the external synchronous clock is selected, the SBUSY1 out-
__________
put goes to “L” and the SBUSY1 output goes to “H” when transmit
data is written into the serial I/O1 register to start a transmit opera-
tion, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY1 output re-
__________
turns to “H” and the SBUSY1 output returns to “L”, the initial status,
when the serial transfer status flag is set to "0", regardless of whether
the internal or external synchronous clock is selected.
Furthermore, in the automatic transfer serial I/O mode (SBUSY1 out-
put function outputs in 1-byte units), the SBUSY1 output goes to “H”
__________
and the SBUSY1 output goes to “L” each time 1-byte of receive data
is written into the automatic transfer RAM.
Fig. 27 SBUSY1 Output Operation
(internal synchronous clock, 8-bits serial I/O) Fig. 28 SBUSY1 Output Operation
(external synchronous clock, 8-bits serial I/O)
Fig. 29 SBUSY1 Output Operation in Automatic Transfer Serial I/O Mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
S
BUSY1
S
CLK1
S
OUT1
Serial transfer
status flag
Serial transfer
status flag
S
BUSY1
S
CLK1
Write to Serial
I/O1 register
S
CLK1
S
BUSY1
S
OUT1
Automatic transfer
interval
Serial transfer
status flag
Automatic transfer RAM
→Serial I/O1 register
Serial I/O1 register
→Automatic transfer RAM
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
31
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which informs
the serial transfer destination that transmit/receive is ready. In the
initial status, when the serial I/O initialization bit (b4) is reset to “0,”
________
the SRDY1 output goes to “L” and the SRDY1 output goes to “H”. After
transmitted data is stored in the serial I/O1 register (address 001B16)
and a transmit/receive operation becomes ready, the SRDY1 output
________
goes to “H” and the SRDY1 output goes to “L”. When a transmit/
receive operation is started and the transfer clock goes to “L”, the
________
SRDY1 output goes to “L” and the SRDY1 output goes to “H”.
5. SRDY1 input signal
The SRDY1 input signal becomes valid only when the SRDY1 input
and the SBUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the serial
transfer destination.
When the internal synchronous clock is selected, input a low level
_________
signal into the SRDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the SRDY1 input and an “L”
_________
level signal is input into the SRDY1 input for a period of 1.5 cycles or
more of transfer clock, transfer clocks are output from the SCLK1
output and a transmit/receive operation is started.
After the transmit/receive operation is started and an “L” level sig-
nal is input into the SRDY1 input and an “H” level signal into the
_________
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received, the
transfer clocks from the SCLK1 output is stopped. The handshake
unit of the 8-bit serial I/O and that of the automatic transfer serial
I/O are of 8 bits.
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
_________
To start a transmit/receive operation (SBUSY1 output: “L,” SBUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an “L”
_________
level signal into the SRDY1 input, and also write transmit data into
the serial I/O1 register.
Fig. 30 SRDY1 Output Operation
Fig. 31 SRDY1 Input Operation (internal synchronous clock)
S
RDY1
S
CLK1
Write to serial
I/O1 register
S
RDY1
S
CLK1
S
OUT1
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
32
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A: B:
SCLK1
SRDY1
SBUSY1 SBUSY1
SRDY1
SCLK1
A:
B:
Write to serial
I/O1 register
SCLK1
SRDY1
SBUSY1
Internal synchronous
clock selection External synchronous
clock selection
Write to serial
I/O1 register
A: B:
S
CLK1
S
RDY1
S
BUSY1
S
BUSY1
S
RDY1
S
CLK1
A:
B:
Write to serial
I/O1 register
S
CLK1
S
RDY1
S
BUSY1
Internal synchronous
clock selection External synchronous
clock selection
Write to serial
I/O1 register
Fig. 32 Handshake Operation at Serial I/O1 Mutual Connecting (1)
Fig. 33 Handshake Operation at Serial I/O1 Mutual Connecting (2)
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
33
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
●Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control reg-
Fig. 35 Operation of Clock Synchronous Serial I/O2 Function
Fig. 34 Block Diagram of Clock Synchronous Serial I/O2
ister (address 001D16) to “1.” For clock synchronous serial I/O, the
transmitter and the receiver must use the same clock for serial I/O2
operation. If an internal clock is used, transmit/receive is started by
a write signal to the serial I/O2 transmit/receive buffer register (TB/
RB) (address 001F16).
_________
When P57 (SCLK22) is selected as a clock I/O pin, SRDY2 output
function is invalid, and P56 (SCLK21) is used as an I/O port.
1/4
1/4
F/F
P5
6
/S
CLK21
P5
4
/R
X
D
P5
5
/T
X
D
P5
7
/S
RDY2
/
S
CLK22
“0”
“1”
“0”
“1”
X
IN
1/2
X
CIN
“1”
“0”
P5
7
/S
RDY2
/
S
CLK22
Serial I/O2 status register
Serial I/O2 control register
Receive buffer register
Address 001F
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O2 synchronous clock selection bit
Baud rate generator
Division ratio 1/(n+1)
Address 0016
16
BRG count source selection bit
Clock control circuitFalling edge detector
Transmit buffer register
Data bus
Address 001F
16
Shift clock Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001E
16
Data bus
Address 001D
16
Transmit shift register
Serial I/O2 clock I/O pin selection bit
Internal system clock selection bit
BRG clock
switch bit
Serial I/O2
clock I/O pin
selection bit
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transmit/Receive shift clock
(1/2
—
1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
Serial I/O2 input RxD
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F
16
)
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1.”
Receive enable signal
S
RDY2
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
34
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(2) Asynchronous Serial I/O (UART) Mode
The asynchronous serial I/O (UART) mode can be selected by clear-
ing the serial I/O2 mode selection bit (b6) of the serial I/O2 control
register (address 001D16) to “0.” Eight serial data transfer formats
can be selected and the transfer formats used by the transmitter
and receiver must be identical.
The transmit and receive shift registers each have a buffer (the two
buffers have the same address in memory). Since the shift register
cannot be written to or read from directly, transmit data is written to
the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can receive 2-byte data continuously.
Fig. 37 Operation of UART Serial I/O2 Function
Fig. 36 Block Diagram of UART Serial I/O2
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
ST
D
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1*
ST
D
0
D
1
SP D
0
D
1
ST SP
Transmit or receive clock
* Generated at 2nd bit in 2-stop
bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
Serial I/O2 input R
X
D
Write-in signal to
transmit buffer register
Serial I/O2 output T
X
D
Read-out signal from receive
buffer register
OE
PE FE
1/16
1/16
Transmit buffer register
Clock control circuit
P5
6
/S
CLK21
P5
4
/R
X
D
P5
5
/T
X
D
P5
7
/S
RDY2
/S
CLK22
“0”
“1”
1/4
“0”
“1”
X
IN
1/2
X
CIN
“1”
Data bus
Receive buffer register
Address 001F
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Division ratio 1/(n+1)
Address 0016
16
ST/SP/PA generator
Data bus
Transmit shift register
Address
001F
16
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address
001E
16
ST detector
UART control register
Address 0017
16
Character length selection bit
Address 001D
16
BRG count source
selection bit
Transmit interrupt source selection bit
Serial I/O2 synchronous
clock selection bit
Character length selection bit
7 bit
8 bit
Serial I/O2 control register
Serial I/O2 status register
SP detector
Serial I/O2 clock I/O pin
selection bit
Internal system clock selection bit
BRG clock
switch bit
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
35
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
[Serial I/O2 Control Register] SIO2CON (001D16)
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (001716)
This is a 5 bit register containing four control bits (b0 to b3), which
are valid when UART is selected and set the data format of data
receive/transfer, and one control bit (b4), which is always valid and
sets the output structure of the P55/TxD pin.
[Serial I/O2 Status Register] SIO2STS (001E 16)
The read-only serial I/O2 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O2 function
and various errors. Three of the flags (b4 to b6) are only valid in the
UART mode. The receive buffer full flag (b1) is cleared to “0” when
the receive buffer is read.
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O2 status regis-
ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively).
Writing “0” to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2
control register) also clears all the status flags, including the error
flags.
All bits of the serial I/O2 status register are initialized to “0” at reset,
but if the transmit enable bit (b4) of the serial I/O2 control register
has been set to “1,” the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become “1.”
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is "0".
[Baud Rate Generator] BRG (001616)
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register, the baud rate genera-
tor divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
Fig. 38 Structure of Serial I/O2 Related Register
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns "1" when read)
Serial I/O2 status register
(SIO2STS : address 001E16) Serial I/O2 control register
(SIO2CON : address 001D16)
b0 b0
b7 UART control register
(UARTCON : address 001716)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P55/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: XIN or XCIN (depends on internal system clock)
1: XCIN
Serial I/O2 clock I/O pin selection bit
0: SCLK21 (P57/SCLK22 pin is used as I/O port or SRDY2 output pin.)
1: SCLK22 (P56/SCLK21 pin is used as I/O port.)
Not used (return "1" when read)
b0
BRG count source selection bit (CSS)
0: f(XIN) or f(XCIN)/2 or f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
SRDY2 output enable bit (SRDY)
0: P57 pin operates as ordinary I/O pin
1: P57 pin operates as SRDY2 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P54 to P57 operate as ordinary I/O pins)
1: Serial I/O2 enabled
(pins P54 to P57 operate as serial I/O pins)
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
36
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FLD Controller
The 38B5 group has fluorescent display (FLD) drive and control cir-
cuits.
The FLD controller consists of the following components:
•40 pins for FLD control pins
•FLDC mode register
•FLD data pointer
•FLD data pointer reload register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•Port P8 FLD output control register
•FLD automatic display RAM (max. 160 bytes)
A gradation display mode can be used for bright/dark display as a
display function.
Fig. 39 Block Diagram for FLD Control Circuit
P2
0
/FLD
0
P2
1
/FLD
1
P2
2
/FLD
2
P2
3
/FLD
3
P2
4
/FLD
4
P2
5
/FLD
5
P2
6
/FLD
6
P2
7
/FLD
7
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0004
16
0EFA
16
8
0000
16
0EF9
16
8
P0
0
/FLD
8
P0
1
/FLD
9
P0
2
/FLD
10
P0
3
/FLD
11
P0
4
/FLD
12
P0
5
/FLD
13
P0
6
/FLD
14
P0
7
/FLD
15
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0002
16
8
P1
0
/FLD
16
P1
1
/FLD
17
P1
2
/FLD
18
P1
3
/FLD
19
P1
4
/FLD
20
P1
5
/FLD
21
P1
6
/FLD
22
P1
7
/FLD
23
0006
16
8
P3
0
/FLD
24
P3
1
/FLD
25
P3
2
/FLD
26
P3
3
/FLD
27
P3
4
/FLD
28
P3
5
/FLD
29
P3
6
/FLD
30
P3
7
/FLD
31
0010
16
0EFB
16
8
P8
0
/FLD
32
P8
1
/FLD
33
P8
2
/FLD
34
P8
3
/FLD
35
P8
4
/FLD
36
P8
5
/FLD
37
P8
6
/FLD
38
P8
7
/FLD
39
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0F60
16
0FFF
16
Main address bus
Local address bus
FLD automatic display RAM
Main
data bus Local
data bus
FLD blanking interrupt
FLD digit interrupt
FLDC mode register
(0EF4
16
)
FLD data pointer
reload register
(0EF8
16
)
FLD data pointer
(0EF8
16
)
Timing generator
Address
decoder
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
37
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
[FLDC Mode Register] FLDM
The FLDC mode register is a 8-bit register respectively which is used
to control the FLD automatic display and to set the blanking time
Tscan for key-scan.
Fig. 40 Structure of FLDC Mode Register
FLDC mode register
(FLDM: address 0EF416)
Automatic display control bit (P0, P1, P2, P3, P8)
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
Tscan control bits
00 : FLD digit interrupt (at rising edge of each digit)
01 : 1 ✕ Tdisp
10 : 2 ✕ Tdisp
11 : 3 ✕ Tdisp
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note)
Tdisp counter count source selection bit
0 : f(XIN)/16 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/128
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
b7 b0
FLD blanking interrupt
(at falling edge of the last digit)
Note: When a gradation display mode is selected, a number of timing is max. 16 timing.
(Set the timing number control bit to “0.”)
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
38
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 41 Segment/Digit Setting Example
FLD automatic display pins
When the automatic display control bits of the FLDC mode register
(address 0EF416) are set to “1,” the ports of P0, P1, P2, P3 and P8
are used as FLD automatic display pins.
When using the FLD automatic display mode, set each port to the
FLD pin or the general-purpose port using the respective switch reg-
ister in accordance with the number of segments and the number of
digits.
This setting is performed by writing a value into the FLD/port switch
register (addresses 0EF916 to 0EFB16) of each port.
This setting can be performed in units of bit. When “0” is set, the port
is set to the general-purpose port. When “1” is set, the port is set to
the FLD pin. There is no restriction on whether the FLD pin is to be
used as a segment pin or a digit pin.
Table 7 Pins in FLD Automatic Display Mode
Port Name Automatic Display Pins Setting Method
P0, P2, FLD0–FLD15 The individual bits of the FLD/port switch register (addresses 0EF916–0EFB16) can be set each pin
P80–P83FLD32–FLD35 either FLD port (“1”) or general-purpose port (“0”).
P1, P3 FLD16–FLD31 None (FLD only)
P84–P87FLD36–FLD39 The individual bits of the FLD/port switch register (address 0EFB16) can be set each pin to either
FLD port (“1”) or general-purpose port (“0”).
The output can be reversed by the port P8 FLD output control register (address 0EFC16).
The port output format is the CMOS output format. When using the port as a display pin, a driver
must be installed externally.
15
8
P2
4
P2
5
P2
6
P2
7
P2
0
P2
1
P2
2
P2
3
0
0
0
0
0
0
0
0
FLD
16
(DIG
1
)
FLD
17
(DIG
2
)
FLD
18
(DIG
3
)
FLD
19
(DIG
4
)
FLD
20
(SEG
4
)
FLD
21
(SEG
5
)
FLD
22
(SEG
6
)
FLD
23
(SEG
7
)
P0
4
P0
5
FLD
14
(SEG
2
)
FLD
15
(SEG
3
)
FLD
8
(SEG
1
)
P0
1
P0
2
P0
3
1
0
0
0
0
0
1
1
FLD
32
(SEG
12
)
FLD
33
(SEG
13
)
FLD
34
(SEG
14
)
FLD
35
(SEG
15
)
P8
4
P8
5
P8
6
P8
7
FLD
24
(SEG
8
)
FLD
25
(SEG
9
)
FLD
26
(SEG
10
)
FLD
27
(SEG
11
)
FLD
28
(DIG
5
)
FLD
29
(DIG
6
)
FLD
30
(DIG
7
)
FLD
31
(DIG
8
)
1
1
1
1
0
0
0
0
25
15
FLD
8
(SEG
9
)
FLD
9
(SEG
10
)
FLD
10
(SEG
11
)
FLD
11
(SEG
12
)
FLD
12
(SEG
13
)
FLD
13
(SEG
14
)
FLD
14
(SEG
15
)
FLD
15
(SEG
16
)
1
1
1
1
1
1
1
1
FLD
0
(SEG
1
)
FLD
1
(SEG
2
)
FLD
2
(SEG
3
)
FLD
3
(SEG
4
)
FLD
4
(SEG
5
)
FLD
5
(SEG
6
)
FLD
6
(SEG
7
)
FLD
7
(SEG
8
)
FLD
16
(DIG
1
)
FLD
17
(DIG
2
)
FLD
18
(DIG
3
)
FLD
19
(DIG
4
)
FLD
20
(DIG
5
)
FLD
21
(DIG
6
)
FLD
22
(DIG
7
)
FLD
23
(DIG
8
)
1
1
1
1
1
1
1
1
FLD
24
(DIG
9
)
FLD
25
(DIG
10
)
FLD
26
(DIG
11
)
FLD
27
(DIG
12
)
FLD
28
(DIG
13
)
FLD
29
(DIG
14
)
FLD
30
(DIG
15
)
FLD
31
(SEG
17
)
FLD
32
(SEG
18
)
FLD
33
(SEG
19
)
FLD
34
(SEG
20
)
FLD
35
(SEG
21
)
1
1
1
1
1
1
1
1
FLD
36
(SEG
22
)
FLD
37
(SEG
23
)
FLD
38
(SEG
24
)
FLD
39
(SEG
25
)
18
20
FLD
8
(DIG
1
)
FLD
9
(DIG
2
)
FLD
10
(DIG
3
)
FLD
11
(DIG
4
)
FLD
12
(DIG
5
)
FLD
13
(DIG
6
)
FLD
14
(DIG
7
)
FLD
15
(DIG
8
)
1
1
1
1
1
1
FLD
2
(SEG
1
)
FLD
3
(SEG
2
)
FLD
4
(SEG
3
)
FLD
5
(SEG
4
)
FLD
6
(SEG
5
)
FLD
7
(SEG
6
)
FLD
16
(DIG
9
)
FLD
17
(DIG
10
)
FLD
18
(DIG
11
)
FLD
19
(DIG
12
)
FLD
20
(DIG
13
)
FLD
21
(DIG
14
)
FLD
22
(DIG
15
)
FLD
23
(DIG
16
)
1
1
1
1
1
1
1
1
FLD
24
(DIG
17
)
FLD
25
(DIG
18
)
FLD
26
(DIG
19
)
FLD
27
(DIG
20
)
FLD
28
(SEG
7
)
FLD
29
(SEG
8
)
FLD
32
(SEG
11
)
FLD
33
(SEG
12
)
FLD
34
(SEG
13
)
FLD
35
(SEG
14
)
1
1
1
1
1
1
1
1
FLD
36
(SEG
15
)
FLD
37
(SEG
16
)
FLD
38
(SEG
17
)
FLD
39
(SEG
18
)
16
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P2
0
P2
1
P2
2
P2
3
FLD
4
(SEG
1
)
FLD
5
(SEG
2
)
FLD
6
(SEG
3
)
FLD
7
(SEG
4
)
FLD
8
(SEG
5
)
FLD
9
(SEG
6
)
FLD
10
(SEG
7
)
FLD
11
(SEG
8
)
FLD
12
(SEG
9
)
FLD
13
(SEG
10
)
FLD
14
(SEG
11
)
FLD
15
(SEG
12
)
FLD
16
(DIG
1
)
FLD
17
(DIG
2
)
FLD
18
(DIG
3
)
FLD
19
(DIG
4
)
FLD
20
(DIG
5
)
FLD
21
(DIG
6
)
FLD
22
(DIG
7
)
FLD
23
(DIG
8
)
FLD
24
(DIG
9
)
FLD
25
(DIG
10
)
FLD
26
(SEG
13
)
FLD
27
(SEG
14
)
FLD
28
(SEG
15
)
FLD
29
(SEG
16
)
P8
1
P8
0
P8
2
P8
3
P8
4
P8
5
P8
6
P8
7
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
P2
0
P2
1
FLD
30
(SEG
9
)
FLD
31
(SEG
10
)
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
P2
4
P2
5
Number of segments
Number of digits
Port P2
Setting example 1 Setting example 2 Setting example 3 Setting example 4
Port P0
Port P1
Port P3
Port P8
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
39
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FLD automatic display RAM
The FLD automatic display RAM uses the 160 bytes of addresses
0F6016 to 0FFF16. For FLD, the 3 modes of 16-timing ordinary mode,
16-timing•gradation display mode and 32-timing mode are available
depending on the number of timings and the presence/absence of
gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•Ordinary Mode
The 80 bytes of addresses 0FB016 to 0FFF16 are used as a FLD
display data store area. Because addresses 0F6016 to 0FAF16
are not used as the automatic display RAM, they can be the ordi-
nary RAM or serial I/O automatic reverse RAM.
(2) 16-timing•Gradation Display Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used. The 80
bytes of addresses 0FB016 to 0FFF16 are used as an FLD dis-
play data store area, while the 80 bytes of addresses 0F6016 to
0FAF16 are used as a gradation display control data store area.
(3) 32-timing Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used as an
FLD display data store area.
[FLD Data Pointer and FLD Data Pointer Reload Register]
FLDDP (0EF8
16
)
Both the FLD data pointer and FLD data pointer reload register are
8-bit registers assigned at address 0EF816. When writing data to this
address, the data is written to the FLD data pointer reload register;
when reading data from this address, the value in the FLD data pointer
is read.
Fig. 42 FLD Automatic Display RAM Assignment
16-timing•ordinary mode
0FFF
16
0FB0
16
0F60
16
0FFF
16
0F60
16
0FFF
16
0FB0
16
0F60
16
16-timing•gradation display mode 32-timing mode
1 to 32 timing display
data stored area
Gradation display
control data stored
area
1 to 16 timing display
data stored area
1 to 16 timing display
data stored area
Not used
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
40
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Data setup
(1) 16-timing•Ordinary Mode
The area of addresses 0FB016 to 0FFF16 are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB016,
the last data of FLD port P0 is stored at address 0FC016,
the last data of FLD port P1 is stored at address 0FD016,
the last data of FLD port P3 is stored at address 0FE016,
and the last data of FLD port P8 is stored at address 0FF016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB016, 0FC016, 0FD016, 0FE016, and
0FF016.
Set the FLD data pointer reload register to the value given by the
number of digits – 1. “1” is always written to bit 6, and “0” is
always written to bit 5. Note that “0” is always read from bits 6
and 5 when reading.
(2) 16-timing•Gradation Display Mode
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is
arranged at an address resulting from subtracting 005016 from
the display data store address of each timing and pin. Bright dis-
play is performed by setting “0,” and dark display is performed by
setting “1.”
(3) 32-timing Mode
The area of addresses 0F6016 to 0FFF16 are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0F6016,
the last data of FLD port P0 is stored at address 0F8016,
the last data of FLD port P1 is stored at address 0FA016,
the last data of FLD port P3 is stored at address 0FC016,
and the last data of FLD port P8 is stored at address 0FE016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0F6016, 0F8016, 0FA016, 0FC016, and
0FE016.
Set the FLD data pointer reload register to the value given by the
number of digits–1. “1” is always written to bit 6, and “0” is always
written to bit 5. Note that “0” is always read from bits 6 and 5
when reading.
Fig. 43 Example of Using the FLD Automatic Display RAM in
16-timing•Ordinary Mode
Number of FLD segments: 15
Number of timing: 8
(FLD data pointer reload register = 7)
Address
0FCF
16
0FB1
16
0FB2
16
0FB3
16
0FB4
16
0FB5
16
0FB6
16
0FB7
16
0FB8
16
0FB9
16
0FBA
16
0FBB
16
0FBC
16
0FBD
16
0FBE
16
0FBF
16
0FC0
16
0FC1
16
0FC2
16
0FC3
16
0FC4
16
0FC5
16
0FC6
16
0FC7
16
0FC8
16
0FC9
16
0FCA
16
0FCB
16
0FCC
16
0FCD
16
0FCE
16
0FD0
16
0FD1
16
0FD2
16
0FD3
16
0FD4
16
0FD5
16
0FD6
16
0FD7
16
0FD8
16
0FD9
16
0FDA
16
0FDB
16
0FDC
16
0FDD
16
0FDE
16
0FDF
16
0FE1
16
0FE2
16
0FE3
16
0FE4
16
0FE5
16
0FE6
16
0FE7
16
0FE8
16
0FE9
16
0FEA
16
0FEB
16
0FEC
16
0FED
16
0FEE
16
0FEF
16
0FE0
16
0FF1
16
0FF2
16
0FF3
16
0FF4
16
0FF5
16
0FF6
16
0FF7
16
0FF8
16
0FF9
16
0FFA
16
0FFB
16
0FFC
16
0FFD
16
0FFE
16
0FFF
16
0FF0
16
0FB0
16
The last timing
(The last data of FLDP2)
76543210
Bit
The last timing
(The last data of FLDP0)
The last timing
(The last data of FLDP1)
The last timing
(The last data of FLDP3)
The last timing
(The last data of FLDP8)
Timing for start
(The first data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP8)
FLDP8 data area
Note: shaded area is used for segment.
shaded area is used for digit.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
41
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 44 Example of Using the FLD Automatic Display RAM in 16-timing•Gradation Display Mode
0FCF16
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FE016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
0FF016
0FB016
0F7F16
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
7654 210
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0F9016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
0FA016
3
76543210
Bit
Address
Number of FLD segments: 25
Number of timing: 15
(FLD data pointer reload register = 14)
The last timing
(The last data of FLDP2)
Note: shaded area is used for segment.
shaded area is used for digit.
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
Bit
Address
The last timing
(The last data of FLDP2)
FLDP2 gradation
display data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 gradation
display data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 gradation
display data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 gradation
display data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 gradation
display data area
Timing for start
(The first data of FLDP8)
Note: shaded area is used for gradation display data.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
42
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 45 Example of Using the FLD Automatic Display RAM in 32-timing Mode
0F7F
16
0F60
16
0F61
16
0F62
16
0F63
16
0F64
16
0F65
16
0F66
16
0F67
16
0F68
16
0F69
16
0F6A
16
0F6B
16
0F6C
16
0F6D
16
0F6E
16
0F6F
16
0F70
16
0F71
16
0F72
16
0F73
16
0F74
16
0F75
16
0F76
16
0F77
16
0F78
16
0F79
16
0F7A
16
0F7B
16
0F7C
16
0F7D
16
0F7E
16
7654 21
0F80
16
0F81
16
0F82
16
0F83
16
0F84
16
0F85
16
0F86
16
0F87
16
0F88
16
0F89
16
0F8A
16
0F8B
16
0F8C
16
0F8D
16
0F8E
16
0F8F
16
Bit
Address
0F91
16
0F92
16
0F93
16
0F94
16
0F95
16
0F96
16
0F97
16
0F98
16
0F99
16
0F9A
16
0F9B
16
0F9C
16
0F9D
16
0F9E
16
0F9F
16
0F90
16
0FA1
16
0FA2
16
0FA3
16
0FA4
16
0FA5
16
0FA6
16
0FA7
16
0FA8
16
0FA9
16
0FAA
16
0FAB
16
0FAC
16
0FAD
16
0FAE
16
0FAF
16
0FA0
16
3 0
76543210
Bit
Address
0FCF
16
0FB1
16
0FB2
16
0FB3
16
0FB4
16
0FB5
16
0FB6
16
0FB7
16
0FB8
16
0FB9
16
0FBA
16
0FBB
16
0FBC
16
0FBD
16
0FBE
16
0FBF
16
0FC0
16
0FC1
16
0FC2
16
0FC3
16
0FC4
16
0FC5
16
0FC6
16
0FC7
16
0FC8
16
0FC9
16
0FCA
16
0FCB
16
0FCC
16
0FCD
16
0FCE
16
0FD0
16
0FD1
16
0FD2
16
0FD3
16
0FD4
16
0FD5
16
0FD6
16
0FD7
16
0FD8
16
0FD9
16
0FDA
16
0FDB
16
0FDC
16
0FDD
16
0FDE
16
0FDF
16
0FE1
16
0FE2
16
0FE3
16
0FE4
16
0FE5
16
0FE6
16
0FE7
16
0FE8
16
0FE9
16
0FEA
16
0FEB
16
0FEC
16
0FED
16
0FEE
16
0FEF
16
0FE0
16
0FF1
16
0FF2
16
0FF3
16
0FF4
16
0FF5
16
0FF6
16
0FF7
16
0FF8
16
0FF9
16
0FFA
16
0FFB
16
0FFC
16
0FFD
16
0FFE
16
0FFF
16
0FF0
16
0FB0
16
Number of FLD segments: 18
Number of timing: 20
(FLD data pointer reload register = 19)
The last timing
(The last data of FLDP3)
Note: shaded area is used for segment.
shaded area is used for digit.
FLDP3 data area
Timing for start
(The first data of FLDP1)
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 data area
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
43
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Digit data protect function
The FLD automatic display RAM is provided with a data protect
function that disables the RAM area data to be rewritten as digit
data.
This function can disable data from being written in optional bits in
the RAM area corresponding to P1 to P3. A programming load can
be reduced by protecting an area that requires no change after
data such as digit data is written.
Write digit data beforehand; then set “1” in the corresponding bits.
With this, the setting is completed.
The data protect area becomes the maximum RAM area of P1 and
P3. For example, when bit 0 of P1 is protected in the 16-
timing•ordinary mode, bits 0 of RAM addresses 0FD016 to 0FDF16
can be protected. Likewise, in the 16-timing•gradation display mode,
bits 0 of addresses 0FD016 to 0FDF16 and 0F8016 to 0F8F16 can be
protected. In the 32-timing mode, bits 0 of addresses 0FA016 to
0FBF16 can be protected.
Fig. 46 Structure of FLDRAM Write Disable Register
b7 b0
P1FLDRAM write disable register
(P1FLDRAM : address 0EF2
16
)
FLDRAM corresponding to P1
0
FLDRAM corresponding to P1
1
FLDRAM corresponding to P1
2
FLDRAM corresponding to P1
3
FLDRAM corresponding to P1
4
FLDRAM corresponding to P1
5
FLDRAM corresponding to P1
6
FLDRAM corresponding to P1
7
b7 b0
0: Operating normally
1: Write disabled
P3FLDRAM write disable register
(P3FLDRAM : address 0EF3
16
)
FLDRAM corresponding to P3
0
FLDRAM corresponding to P3
1
FLDRAM corresponding to P3
2
FLDRAM corresponding to P3
3
FLDRAM corresponding to P3
4
FLDRAM corresponding to P3
5
FLDRAM corresponding to P3
6
FLDRAM corresponding to P3
7
0: Operating normally
1: Write disabled
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
44
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 48 Example of Using the FLD Automatic Display RAM
Using Grid Scan Type
Setting method when using the grid scan type FLD
When using the grid scan type FLD, set “1” in the RAM area corre-
sponding to the digit ports that output “1” at each timing. Set “0” in
the RAM area corresponding to the other digit ports.
Fig. 47 Example of Digit Timing Using Grid Scan Type
DIG10 (P3
1
)
DIG9 (P3
0
)
DIG8 (P1
7
)
DIG2 (P1
1
)
DIG1 (P1
0
)
Number of timing: 10
The first second third.......................9th 10th
Segment output
0FCF
16
0FB0
16
0FB1
16
0FB2
16
0FB3
16
0FB4
16
0FB5
16
0FB6
16
0FB7
16
0FB8
16
0FB9
16
0FBA
16
0FBB
16
0FBC
16
0FBD
16
0FBE
16
0FBF
16
0FC0
16
0FC1
16
0FC2
16
0FC3
16
0FC4
16
0FC5
16
0FC6
16
0FC7
16
0FC8
16
0FC9
16
0FCA
16
0FCB
16
0FCC
16
0FCD
16
0FCE
16
7654 210
0FD0
16
0FD1
16
0FD2
16
0FD3
16
0FD4
16
0FD5
16
0FD6
16
0FD7
16
0FD8
16
0FD9
16
0FDA
16
0FDB
16
0FDC
16
0FDD
16
0FDE
16
0FDF
16
Bit
Address
0FE1
16
0FE2
16
0FE3
16
0FE4
16
0FE5
16
0FE6
16
0FE7
16
0FE8
16
0FE9
16
0FEA
16
0FEB
16
0FEC
16
0FED
16
0FEE
16
0FEF
16
0FE0
16
0FF1
16
0FF2
16
0FF3
16
0FF4
16
0FF5
16
0FF6
16
0FF7
16
0FF8
16
0FF9
16
0FFA
16
0FFB
16
0FFC
16
0FFD
16
0FFE
16
0FFF
16
0FF0
16
3
11
1
1
1
1
1
1
1
1
0000000
0000000
0000000
0000000
000000
000000
00000
00000
00000000
000
000
00
00
0
0
0
0
0
0
00
00
00
00
00
00
0
0
00
Number of FLD segments: 16
Number of timing: 10
(FLD data pointer reload register = 9)
The last timing
(The last data of FLDP2)
Note: shaded area is used for segment.
shaded area is used for digit.
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
45
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timing setting
Each timing is set by the FLDC mode register, Tdisp time set regis-
ter, Toff1 time set register, and Toff2 time set register.
•Tdisp time setting
Set the Tdisp time by the Tdisp counter count source selection bit of
the FLDC mode register and the Tdisp time set register.
Supposing that the value of the Tdisp time set register is n, the
Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count source
synchronization).
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Tdisp time set register is 200
(C816), the Tdisp time is: Tdisp = (200+1) ✕ 4 (at XIN= 4 MHz) = 804
µs. When reading the Tdisp time set register, the value in the
counter is read out.
•Toff1 time setting
Set the Toff1 time by the Toff1 time set register.
Supposing that the value of the Toff1 time set register is n1, the
Toff1 time is represented as Toff1 = n1 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff1 time set register is 30
(1E16), Toff1 = 30 ✕ 4 (at XIN = 4 MHz) = 120 µs.
•Toff2 time setting
Set the Toff2 time by the Toff2 time set register.
Supposing that the value of the Toff2 time set register is n2, the
Toff2 time is represented as Toff2 = n2 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff2 time set register is 180
(B416), Toff2 = 180 ✕ 4 (at XIN = 4 MHz) = 720 µs.
This Toff2 time setting is valid only for FLD ports which are in the
gradation display mode and whose gradation display control RAM
value is “1.”
FLD automatic display start
To perform FLD automatic display, set the following registers.
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•FLDC mode register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•FLD data pointer
FLD automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register (address 0EF416), and the automatic dis-
play is started by writing “1” to bit 1. During FLD automatic display,
bit 1 of the FLDC mode register (address 0EF416) always keeps “1,”
and FLD automatic display can be interrupted by writing “0” to bit 1.
Key-scan
When a key-scan is performed with the segment during key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 0EF416).
2. Set the port corresponding to the segment for key-scan to the
output port.
3. Perform the key-scan.
4. After the key-scan is performed, write “1” to bit 0 of FLDC mode
register (address 0EF416).
■ Note
When performing a key-scan according to the above steps 1 to 4,
take the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 0EF416).
2. Do not set “1” in the ports corresponding to digits.
P84 to P87 FLD Output Reverse Function
P84 to P87 are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
The output polarity can be reversed by setting bit 0 of the port P8
FLD output control register to “1.”
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
46
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 50 Structure of P8FLD Output Control Register
Fig. 49 FLDC Timing
P8FLD output control register
(P8FLDCON: address 0EFC16)
P84–P87 FLD output reverse bits
0: Output normally
1: Reverse output
Not available (returns “0” when read)
b7 b0
Toff1 Tdisp
Segment
Digit
Segment
Digit output
Segment setting by software
FLD blanking interrupt request occurs
at the falling edge of the last timing.
FLD digit interrupt request occurs at the rising
edge of digit (each timing).
Tdisp Tscan
Repeat synchronous
Tn Tn-1 Tn-2 T4 T3 T2 T1
Toff1 Toff2
Segment
Digit When a gradation display mode is selected
Pin under the condition that bit 5 of the
FLDC mode register is “1,” and the
corresponding gradation display control
data value is “1.”
Tdisp
n: Number of timing
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
47
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter
The 38B5 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored
in the A-D conversion register (high-order) (address 003416), and
the low-order 2 bits of the same result are stored in bit 7 and bit 6 of
the A-D conversion register (low-order) (address 003316).
During A-D conversion, do not read these registers.
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
A-D conversion is started by setting “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P77/AN7–P70/
________
AN0, and P65/SSTB1/AN11–P62/SRDY1/AN8 and inputs it to the com-
parator.
When port P64 is selected as an analog input pin, an external inter-
rupt function (INT4) is invalid.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
Fig. 52 Block Diagram of A-D Converter
conversion interrupt request bit to “1.”
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 250 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
Fig. 51 Structure of A-D Control Register
Data bus
AV
SS
V
REF
A-D interrupt request
b7 b0
4
P7
0
/AN
0
P7
1
/AN
1
P7
2
/AN
2
P7
3
/AN
3
P7
4
/AN
4
P7
5
/AN
5
P7
6
/AN
6
P7
7
/AN
7
P6
2
/S
RDY1
/AN
8
P6
3
/AN
9
P6
4
/INT
4
/S
BUSY1
/AN
10
P6
5
/S
STB1
/AN
11
A-D control register
Channel selector
Comparator
A-D control circuit
A-D conversion register (H) A-D conversion register (L)
(Address 0034
16
)(Address 0033
16
)
Resistor ladder
AD conversion result stored bits
A-D conversion register (high-order)
(ADH: address 0034
16
)
b7 b0
Analog input pin selection bits
0000: P7
0
/AN
0
0001: P7
1
/AN
1
0010: P7
2
/AN
2
0011: P7
3
/AN
3
0100: P7
4
/AN
4
0101: P7
5
/AN
5
0110: P7
6
/AN
6
0111: P7
7
/AN
7
1000: P6
2
/S
RDY1
/AN
8
1001: P6
3
/AN
9
1010: P6
4
/INT
4
/S
BUSY1
/AN
10
1011: P6
5
/S
STB1
/AN
11
A-D control register
(ADCON: address 0032
16
)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7 b0
Not used (returns “0” when read)
AD conversion result stored bits
A-D conversion register (low-order)
(ADL: address 0033
16
)
b7 b0
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
48
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Pulse Width Modulation (PWM)
The 38B5 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the XIN clock.
The explanation in the rest of this data sheet assumes XIN = 4 MHz.
14
1/2
X
IN
(4MHz)
P8
7
/PWM
0
bit7 bit0
bit5
MSB LSB
PWM
bit7 bit0
Data bus
X
CIN
“1”
“0”
PWM register (high-order)
(address 0014
16
)
PWM register (low-order)
(address 0015
16
)
It is set to “1”
when write.
PWM latch (14-bit)
14-bit PWM circuit
When an internal
system clock
selection bit is set
to “0” Timing
generating
unit for PWM
(64 µs cycle)
(4096 µs cycle)
P8
7
/PWM output
selection bit
P8
7
direction
register
P8
7
/PWM output
selection bit
P8
7
latch
Fig. 53 PWM Block Diagram
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
49
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
1. Data setup
The PWM output pin also function as port P87. Set port P87 to be the
PWM output pin by setting bit 0 of the PWM control register (address
002616) to “1.” The high-order 8 bits of output data are set in the
high-order PWM register PWMH (address 001416) and the low-order
6 bits are set in the low-order PWM register PWML (address 001516).
2. PWM operation
The timing of the 14-bit PWM function is shown in Figure 56.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an “H” level signal
is output during each sub-period. There are 64 sub-periods in each
period, and each sub-period t is 256 ✕ τ (= 64 µs) long. The signal’s
“H” has a length equal to N times τ, and its minimum resolution = 250
ns.
The last bit of the sub-period becomes the ADD bit which is specified
either “H” or “L,” by the contents of PWML. As shown in Table 8, the
ADD bit is decided either “H” or “L.”
That is, only in the sub-period tm shown in Table 8 in the PWM cycle
period T = 64t, the “H” duration is lengthened during the minimum
resolution width τ period in comparison with the other period.
For example, if the high-order eight bits of the 14-bit data are “0316”
and the low-order six bits are “0516,” the length of the “H” level output
in sub-periods t8, t24, t32, t40 and t56 is 4 τ, and its length 3 τ in all other
sub-periods.
Time at the “H” level of each sub-period almost becomes equal be-
cause the time becomes length set in the high-order 8 bits or be-
comes the value plus τ, and this sub-period t (= 64 µs, approximate
15.6 kHz) becomes cycle period approximately.
3. Transfer from register to latch
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each sub-
period (every 64 µs). When the PWML register is read, the contents
of the latch are read. However, bit 7 of the PWML register indicates
whether the transfer to the PWM latch is completed; the transfer is
completed when bit 7 is “0.”
Table 8 Relationship between Low-order 6-bit Data and Setting
Period of ADD Bit
Low-order
6-bit data
Sub-periods tm lengthened (m = 0 to 63)
0 0 0 0 0 0 None
0 0 0 0 0 1 m = 32
0 0 0 0 1 0 m = 16, 48
0 0 0 1 0 0 m = 8, 24, 40, 56
0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60
0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
1 0 0 0 0 0 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
LSB
Fig. 54 PWM Timing
15.75 µs
64 µs64 µs 64 µs 64 µs64 µs
m = 0 m = 7 m = 8 m = 9 m = 63
16.0 µs15.75 µs 15.75 µs 15.75 µs 15.75 µs 15.75 µs
Pulse width modulation register H: 00111111
Pulse width modulation register L: 000101
Sub-periods where “H” pulse width is 16.0 µs: m = 8, 24, 32, 40, 56
Sub-periods where “H” pulse width is 15.75 µs: m = all other values
4096 µs
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
50
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 56 14-bit PWM Timing
Fig. 55 Structure of PWM Control Register
P8
7
/PWM output selection bit
0: I/O port
1: PWM output
Not used (return “0” when read)
PWM control register
(PWMCON: address 0026
16
)
b7 b0
6A 6A 6A 6A 6A 6B 6A 6A 6A 6A 6A 6A 6A 6A6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B
5 5 5 5 555555 5555
6A 6A 6B 6B 6B 6A 6B 6B 6B 6A 6B 6B 6B 6A6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A
4 3 4 4 3 4 4 3 4
6B 6A 69 68 67 02 01 6A 69 68 67 02 01
02 01 00 FF FE FD 97 96 95 02 01 00FC FF FE FD 97 96 95FC
ADD ADD
1653
16
1A93
16
1AA4
16
1AA4
16
1EE4
16
1EF5
16
T = 4096 µs
t = 64 µs
13
16
A4
16
24
16
35
16
7B
16
6A
16
59
16
Data 35
16
stored at address 0015
16
t = 64 µs
τ
= 0.25 µs
“H” period length specified by PWMH
1
2
B5
16
2
PWM register
(high-order)
PWM register
(low-order)
PWM latch
(14-bit)
Data 6A
16
stored at address 0014
16
Data 24
16
stored at address 0015
16
Bit 7 cleared after transfer
Transfer from register to latch
Data 7B
16
stored at address 0014
16
Transfer from register to latch
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
PWM output
(Example 1)
Low-order 6-bits
output
H = 6A
16
L = 24
16
6B
16
............36 times
(107) 6A
16
............28 times
(106)
PWM output
(Example 2)
Low-order 6 bits
output
H = 6A
16
L = 18
16
6B
16
............24 times 6A
16
............40 times
PWM output
8-bit counter
The ADD portions with
additional
τ
are determined
either “H” or “L” by low-order
6-bit data.
Minimum bit width
(64 64 µs)
✕
106 ✕ 64 + 24
(256 0.25 µs)
256 (64 µs), fixed
τ
106 ✕ 64 + 36
✕
………
……… ……… ………
………
............
.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
51
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupt Interval Determination Function
The 38B5 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from the
rising edge (falling edge) of an input signal pulse on the P47/INT2 pin
to the rising edge (falling edge) of the signal pulse that is input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16).
2. Set bit 0 of the interrupt interval determination control register
(address 003116) to “1” (interrupt interval determination operat-
ing).
3. Select the sampling clock of 8-bit binary up counter by setting bit
1 of the interrupt interval determination control register. When
writing “0,” f(XIN)/128 is selected (the sampling interval: 32 µs at
f(XIN) = 4.19 MHz); when “1,” f(XIN)/256 is selected (the sampling
interval: 64 µs at f(XIN) = 4.19 MHz).
4. When the signal of polarity which is set on the INT2 pin (rising or
falling edge) is input, the 8-bit binary up counter starts count-
ing up of the selected counter sampling clock.
5. When the signal of polarity above 4 is input again, the value of the
8-bit binary up counter is transferred to the interrupt interval
determination register (address 003016), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter continues to count up again from “0016.”
6. When count value reaches “FF16,” the 8-bit binary up counter stops
counting up. Then, simultaneously when the next counter sam-
pling clock is input, the counter sets value “FF16” to the interrupt
interval determination register to generate the counter overflow
interrupt request.
Fig. 57 Interrupt Interval Determination Circuit Block Diagram
Noise filter
The P47/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00.”
2. The P47/INT2 input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in a series
of three sampling, the signal is recognized as the interrupt
signal, and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control
register to “1,” the interrupt request can occur at both rising and
falling edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
Note: In the low-speed mode (CM7 = 1), the interrupt interval deter-
mination function cannot operate.
f(X
IN
)/128
f(X
IN
)/256
1/128
1/64
1/32
f(X
IN
)
Counter sampling
clock selection bit
INT
2
interrupt input
Noise filter
8-bit binary up
counter
Interrupt interval
determination register
address 0030
16
Data bus
Divider
One-sided/both-sided
detection selection bit
Noise filter sampling
clock selection bit
Counter overflow
interrupt request
or remote control
interrupt request
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
52
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 60 Interrupt Interval Determination Operation Example (at both-sided edge active)
Fig. 59 Interrupt Interval Determination Operation Example (at rising edge active)
Fig. 58 Structure of Interrupt Interval Determination Control Register
Interrupt interval determination control register
(IIDCON: address 0031
16
)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(X
IN
)/128
1 : f(X
IN
)/256
Noise filter sampling clock selection bits (INT
2
)
00 : Filter stop
01 : f(X
IN
)/32
10 : f(X
IN
)/64
11 : f(X
IN
)/128
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection (can be used when using a noise filter)
Not used (return “0” when read)
b7 b0
Remote control
interrupt request
0123456
123
0
FE FF
N
FF
0
FF
6
6
N
1
N
(When IIDCON
4
= “0”)
Noise filter
sampling clock
INT
2
pin
Acceptance of
interrupt
Counter sampling
clock
8-bit binary up
counter value
Interrupt interval
determination
register value Remote control
interrupt request Counter overflow
interrupt request
011
0
FE FF
2 FF
23
3
FF
2
N
N
N
32
2
2
0121
01
0
2
Remote control
interrupt request
(When IIDCON
4
= “1”)
Noise filter
sampling clock
INT
2
pin
Acceptance of
interrupt
Counter sampling
clock
8-bit binary up
counter value
Interrupt interval
determination
register value Remote control
interrupt request Counter overflow
interrupt request
Remote control
interrupt request Remote control
interrupt request
~
~
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 62 Structure of Watchdog Timer Control Register
“0,” the underflow signal of watchdog timer L becomes the count
source. The detection time is set then to f(XIN) = 2.1 s at 4 MHz
frequency and f(XCIN) = 512 s at 32 kHz frequency.
When this bit is set to “1,” the count source becomes the signal
divided by 8 for f(XIN) (or divided by 16 for f(XCIN)). The detection
time in this case is set to f(XIN) = 8.2 ms at 4 MHz frequency and
f(XCIN) = 2 s at 32 KHz frequency. This bit is cleared to “0” after
resetting.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 002B16) permits
disabling the STP instruction when the watchdog timer is in opera-
tion.
When this bit is “0,” the STP instruction is enabled.
When this bit is “1,” the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1,” it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
■ Note
When releasing the stop mode, the watchdog timer performs its count
operation even in the stop release waiting time. Be careful not to
cause the watchdog timer H to underflow in the stop release waiting
time, for example, by writing data in the watchdog timer control reg-
ister (address 002B16) before executing the STP instruction.
Fig. 61 Block Diagram of Watchdog Timer
X
IN
Data bus
X
CIN
“1”
“0”
Internal system clock
selection bit
(Note)
“0”
“1”
1/8
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
Watchdog timer H (12)
“FFF
16
” is set
when watchdog
timer control
register is written
to.
Internal reset
RESET
Watchdog timer L (8)
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
STP instruction
“FF
16
” is set when
watchdog timer
control register is
written to.
1/2
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(X
IN
)/8 or f(X
CIN
)/16
Watchdog timer H (for read-out of high-order 6 bit)
Watchdog timer control register
(WDTCON : address 002B
16
)
b7
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software runaway). The watchdog timer consists of an 8-bit watch-
dog timer L and a 12-bit watchdog timer H.
●Standard operation of watchdog timer
When any data is not written into the watchdog timer control register
(address 002B16) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 002B16) and
an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 002B16) may be started
before an underflow. When the watchdog timer control register
(address 002B16) is read, the values of the 6 high-order bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
002B16), a watchdog timer H is set to “FFF16” and a watchdog timer
L to “FF16.”
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 002B16) permits
selecting a watchdog timer H count source. When this bit is set to
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
54
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Buzzer Output Circuit
The 38B5 group has a buzzer output circuit. One of 1 kHz, 2 kHz and
4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the buzzer
output control register (address 0EFD16). Either P43/BUZ01 or P20/
BUZ02/FLD0 can be selected as a buzzer output port by the output
port selection bits (b2 and b3 of address 0EFD16).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Fig. 63 Block Diagram of Buzzer Output Circuit
Fig. 64 Structure of Buzzer Output Control Register
f(X
IN
)
1/1024
1/2048
1/4096
Port latch
Buzzer output
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Divider
Buzzer output control register
(BUZCON: address 0EFD16)
Output frequency selection bits (XIN = 4.19 MHz)
00 : 1 kHz (f(XIN)/4096)
01 : 2 kHz (f(XIN)/2048)
10 : 4 kHz (f(XIN)/1024)
11 : Not available
Output port selection bits
00 : P20 and P43 function as ordinary ports.
01 : P43/BUZ01 functions as a buzzer output.
10 : P20/BUZ02/FLD0 functions as a buzzer output.
11 : Not available
Buzzer output ON/OFF bit
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (return “0” when read)
b7 b0
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
55
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
RESET
Internal
reset
Data
φ
Address
SYNC
X
IN
: about 4000 cycles
X
IN
???? ?FFFC FFFD
AD
H
, AD
L
1: The frequency relation of f(X
IN
) and f(
φ
) is f(X
IN
)=4
•
f(
φ
).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Notes
AD
L
AD
H
Reset Circuit
______
To reset the microcomputer, RESET pin should be held at an “L”
______
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between 2.7 V and 5.5 V, and
the oscillation should be stable), reset is released. After the reset is
completed, the program starts from the address contained in address
FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.5 V for VCC of 2.7 V
(switching to the high-speed mode, a power source voltage must be
between 4.0 V and 5.5 V).
Fig. 66 Reset Sequence
Fig. 65 Reset Circuit Example
(Note)
0.2V
CC
0V
0V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage ; Vcc=2.7 V
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
56
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 67 Internal Status at Reset
0016
0016
3F16
FF16
FF16
002A16
002B16
002C16
002D16
002E16
002F16
003216
X: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Address Register contents Address Register contents
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
FF16
FF16
FF16
0016
0016
0016
000016
000116
000216
000416
000516
000616
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001716
001916
001A16
001C16
001D16
001E16
002016
002116
002216
002316
002416
002516
002616
002816
Timer 4
Port P0
Port P0 direction register
Port P1
Port P2
Port P2 direction register
Port P3
Port P4
Port P4 direction register
Port P5
Port P5 direction register
Port P6
Port P6 direction register
Port P7
Port P7 direction register
Port P8
Port P8 direction register
UART control register
Serial I/O1 control register 1
Serial I/O1 control register 2
Serial I/O1 control register 3
Serial I/O2 control register
Serial I/O2 status register
Timer 1
Timer 2
Timer 3
Timer 5
Timer 6
PWM control register
Timer 12 mode register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
0016
002916
Timer 34 mode register
(33)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
Timer 56 mode register
Watchdog timer control register
Timer X (low-order)
Timer X (high-order)
Timer X mode register 1
Timer X mode register 2
Interrupt interval determination
control register
A-D control register
0016
0016
0016
0016
0016
0016
0016
FF16
0016
0016
003916
003A16
003B16
003C16
003D16
003E16
003F16
0EF016
0EF116
0EF216
0EF316
0EF416
0EF516
0EF616
0EF716
0EF916
0EFA16
0EFB16
0EFC16
0EFD16
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60) Port P8FLD output control register
FLDC mode register
Interrupt source switch register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Pull-up control register 1
Pull-up control register 2
P1FLDRAM write disable register
P3FLDRAM write disable register
Tdisp time set register
Toff1 time set register
Toff2 time set register
Port P0FLD/port switch register
Port P2FLD/port switch register
Port P8FLD/port switch register
FF16
0016
0016
0016
0016
0016
0016
1016
Port P9
Port P9 direction register
(34)
FFFC16 contents
(PS)
(PCH)
(PCL)
(61)
(62)
(63) Program counter
Buzzer output control register
Processor status register
FFFD16 contents
1
✕
003116
0016
0016
0016
0016
8016
0016
0016
0016
0016
8016
FF16
0116
FF16
010010 00
0016
0016
0016
0016
✕✕✕✕✕✕
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
57
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Clock Generating Circuit
The 38B5 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No
external resistor is needed between XIN and XOUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
●Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. After
reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of XIN.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
■Note
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set bit
5 of the CPU mode register to “1.” When the main clock XIN is re-
started (by setting the main clock stop bit to “0”), set enough time for
oscillation to stabilize.
By clearing furthermore the XCOUT drivability selection bit (b3) of CPU
mode register to “0,” low power consumption operation of less than
200 µA (f(XCIN) = 32 kHz) can be realized by reducing the drivability
between XCIN and XCOUT. At reset or during STP instruction execu-
tion this bit is set to “1” and a strong drivability that has an easy
oscillation start is set.
●Oscillation control
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116.”
Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before execut-
ing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 1 underflows. This allows time for the clock circuit oscilla-
tion to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of XIN and XCIN are the same as the state
before executing the WIT instruction. The internal system clock re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
Fig. 68 Ceramic Resonator Circuit
Fig. 69 External Clock Input Circuit
X
IN
X
OUT
External oscillation circuit
V
CC
V
SS
open
X
CIN
X
COUT
External oscillation circuit
or external pulse
open
V
CC
V
SS
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf Rd
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
58
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 70 Clock Generating Circuit Block Diagram
WIT instruction STP instruction
Timing
φ
(internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
(Note 3)
S
R
Q
1/4
XIN XOUT
XCOUT
XCIN
Interrupt request
Reset
Interrupt disable flag l
1/2
1/2
Port XC
switch bit (Note 3)
“1” “0”
“1”
Timer 1 count source
selection bit (Note 2)
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Internal system clock
selection bit (Notes 1, 3)
“1”
“0”
Timer 1 Timer 2
Timer 2 count source
selection bit (Note 2)
“0”
Main clock division ratio
selection bits (Note 3)
“1”
“0”
“1”
“0”
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1.”
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
59
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 71 State Transitions of System Clock
CM4 : Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(XIN) (High-speed mode)
1: f(XIN)/4 (Middle-speed mode)
CM7: Internal system clock selection bit
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
Reset
CM
4
CM
7
CM
4
CM
5
CM
6
CM
6
CPU mode register
(CPUM : address 003B
16
)
b7 b4
CM
7
CM
5
CM
6
CM
6
“0”“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”“1”
“0”“1”
“0”“1”
CM
4
“1”
“0”
CM
4
“0”
“1”
“0”
“1”
CM
5
“1”
“0”
“0”
“1”
CM
5
“0”
“1”
“0”
“1”
“0”
“1”
CM
6
CM
6
CM
6
CM
6
CM
7
=0(4 MHz selected)
CM
6
=1(middle-speed)
CM
5
=0(X
IN
oscillating)
CM
4
=0(32 kHz stopped)
1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode.
6: The example assumes that 4 MHz is being applied to the X
IN
pin and 32 kHz to the X
CIN
pin.
φ
indicates the internal system clock.
Middle-speed mode
(
φ
=1 MHz)
Middle-speed mode
(
φ
=1 MHz)
CM
7
=0(4 MHz selected)
CM
6
=0(high-speed)
CM
5
=0(X
IN
oscillating)
CM
4
=0(32 kHz stopped)
High-speed mode
(
φ
=4 MHz)
CM
7
=0(4 MHz selected)
CM
6
=0(high-speed)
CM
5
=0(X
IN
oscillating)
CM
4
=1(32 kHz oscillating)
High-speed mode
(
φ
=4 MHz)
CM
7
=1(32 kHz selected)
CM
6
=0(high-speed)
CM
5
=0(X
IN
oscillating)
CM
4
=1(32 kHz oscillating)
Low-speed mode
(
φ
=16 kHz)
CM
7
=1(32 kHz selected)
CM
6
=0(high-speed)
CM
5
=1(X
IN
stopped)
CM
4
=1(32 kHz oscillating)
CM
7
=0(4 MHz selected)
CM
6
=1(middle-speed)
CM
5
=0(X
IN
oscillating)
CM
4
=1(32 kHz oscillating)
CM
7
=1(32 kHz selected)
CM
6
=1(middle-speed)
CM
5
=0(X
IN
oscillating)
CM
4
=1(32 kHz oscillating)
Low-speed mode
(
φ
=16 kHz)
CM
7
=1(32 kHz selected)
CM
6
=1(middle-speed)
CM
5
=1(X
IN
stopped)
CM
4
=1(32 kHz oscillating)
Low-power dissipation mode
( =16 kHz)
φ
Low-power dissipation mode
( =16 kHz)
φ
Notes
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
60
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before ex-
ecuting a SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents of
the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before ex-
ecuting a serial I/O transfer and serial I/O automatic transfer.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to ex-
ecute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same of the XIN
frequency in high-speed mode.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
The XCOUT drivability selection bit (the CPU mode register) is set to
“1” (high drive) in order to start oscillating.
NOTES ON USE
Notes on Built-in EPROM Version
The P47 pin of the One Time PROM version or the EPROM version
functions as the power source input pin of the internal EPROM.
Therefore, this pin is set at low input impedance, thereby being af-
fected easily by noise.
To prevent a malfunction due to noise, insert a resistor (approx. 5
kΩ) in series with the P47 pin.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
61
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical cop-
ies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and the
EPROM version can be read or programmed with a general purpose
PROM programmer using a special programming adapter. Set the
address of PROM programmer in the user ROM area.
Table 9 Special Programming Adapter
Package Name of Programming Adapter
80P6N-A PCA7438F-80A
80D0 PCA7438L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 72 is recommended to verify programming.
Fig. 72 Programming and Testing of One Time PROM Version
Programming with PROM
programmer
Screening (Note)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Note:
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
62
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ConditionsSymbol Ratings Unit
Parameter
VCC
VEE
VI
VI
VI
VI
VI
VO
VO
VO
Pd
Topr
Tstg
Power source voltage
Pull-down power source voltage
Input voltage P47, P50–P57, P61–P65, P70–
P77, P84–P87, P90, P91
Input voltage P40–P46, P60
Input voltage P00–P07, P20–P27, P80–P83
Input voltage RESET, XIN
Input voltage XCIN
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
Output voltage P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91, XOUT,
XCOUT
Output voltage P40–P46, P60
Power dissipation
Operating temperature
Storage temperature
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 10 Absolute Maximum Ratings
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
–0.3 to 7.0
VCC – 45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to 13
VCC – 45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC – 45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to 13
600
–20 to 85
–40 to 125
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
5.5
5.5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.25VCC
0.16VCC
0.2VCC
0.2VCC
0.2VCC
4.0
2.7
VCC – 43
2.0
0
0.75VCC
0.4VCC
0.8VCC
0.52VCC
0.8VCC
0.8VCC
0
0
0
0
0
Power source voltage
Pull-down power source voltage
Analog reference voltage (when A-D converter is used)
Analog power source voltage
Analog input voltage AN0–AN11
“H” input voltage P40–P47, P50–P57, P60–P65,
P70–P77, P90, P91
“H” input voltage P84–P87
“H” input voltage P00–P07
“H” input voltage P20–P27, P80–P83
“H” input voltage ____________
RESET
“H” input voltage XIN, XCIN
“L” input voltage P40–P47, P50–P57, P60–P65,
P70–P77, P90, P91
“L” input voltage P84–P87
“L” input voltage P00–P07, P20–P27, P80–P83
“L” input voltage ____________
RESET
“L” input voltage XIN, XCIN
Min. Typ. Max.
Symbol Parameter Unit
VCC
VSS
VEE
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Power source voltage in high-speed mode
in middle-/low-speed mode 5.0
5.0
0
0
RECOMMENDED OPERATING CONDITIONS
Table 11 Recommended Operating Conditions (1) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Limits
“H” total peak output current (Note 1) P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
“H” total peak output current (Note 1) P50–P57, P61–P65, P70–P77, P90, P91
“L” total peak output current (Note 1) P50–P57, P60–P65, P70–P77, P90, P91
“L” total peak output current (Note 1) P40–P46, P84–P87
“H” total average output current (Note 1) P00–P07, P10–P17, P20–P27,
P30–P37, P80–P87
“H” total average output current (Note 1) P50–P57, P61–P65, P70–P77, P90, P91
“L” total average output current (Note 1) P50–P57, P60–P65, P70–P77, P90, P91
“L” total average output current (Note 1) P40–P46, P84–P87
“H” peak output current (Note 2) P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
“H” peak output current (Note 2) P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
“L” peak output current (Note 2) P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
“L” peak output current (Note 2) P40–P46, P60
“H” average output current (Note 3) P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
“H” average output current (Note 3) P50–P57, P60–P65, P70–P77,
P84–P87, P90, P91
“L” average output current (Note 3) P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
“L” average output current (Note 3) P40–P46, P60
–240
–60
100
60
–120
–30
50
30
–40
–10
10
30
–18
–5
5
15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an
average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
64
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 12 Recommended Operating Conditions (2) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Clock input frequency for timers 2, 4, and X (duty cycle 50 %)
Main clock input oscillation frequency (Note 1)
Sub-clock input oscillation frequency (Note 1, 2)
Symbol Parameter Limits Unit
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
kHz
MHz
kHz
250
4.2
50
Max.Typ.Min.
32.768
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
ELECTRICAL CHARACTERISTICS
Table 13 Electrical Characteristics (1) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
“H” output voltage P50–P57, P60–P65, P70–P77,
P84–P87, P90, P91
“L” output voltage P50–P57, P61–P65, P84–P87,
P90, P91
“L” output voltage P40–P46, P60
Hysteresis P40–P42, P44–P47, P5, P60,
P61, P64
Hysteresis RESET, XIN
Hysteresis XCIN
“H” input current P47, P50–P57, P61–P65,
P70–P77, P84–P87
“H” input current P40–P46, P60
“H” input current P20–P27, P80–P83 (Note)
“H” input current RESET, XCIN
“H” input current XIN
“L” input current P40–P47, P60
“L” input current P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
“L” input current P20–P27, P80–P83 (Note)
“L” input current RESET, XCIN
“L” input current XIN
Output load current P00–P07, P10–P17, P30–P37
Output leak current P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
“H” read current
RAM hold voltage
VOH
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IIL
ILOAD
ILEAK
IREADH
VRAM
IOH = –18 mA
IOH = –10 mA
IOL = 10 mA
IOL = 15 mA
VI = VCC
VI = 12 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
VI = VSS
Pull-up “off”
VCC = 5 V, VI = VSS
Pull-up “on”
VCC = 3 V, VI = VSS
Pull-up “on”
VI = VSS
VI = VSS
VI = VSS
VEE = VCC–43 V, VOL = VCC
Output transistors “off”
VEE = VCC–43 V, VOL = VCC
–43 V Output transistors “off”
VI = 5 V
When clock is stopped
Test conditions
VCC–2.0
VCC–2.0
2.0
2.0
5.0
10.0
5.0
5.0
–5.0
–5.0
–140
–45
–5.0
–5.0
900
–10
5.5
0.6
0.4
0.5
0.5
4.0
–70
–25
–4.0
600
1
–30
–6.0
300
2
Note: Except when reading ports P2 or P8.
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
65
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 14 Electrical Characteristics (2) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Test conditions
ICC Power source current 7.5
1
3
1
60
20
0.6
0.1
15
200
40
1
10
mA
mA
mA
mA
µA
µA
mA
µA
µA
High-speed mode
f(XIN) = 4.2 MHz
f(XCIN) = 32 kHz
Output transistors “off”
High-speed mode
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = 32 kHz
Output transistors “off”
Middle-speed mode
f(XIN) = 4.2 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32 kHz
Low-power dissipation mode (CM3 = 0)
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32 kHz (in WIT state)
Low-power dissipation mode (CM3 = 0)
Output transistors “off”
Increment when A-D conversion is executed
All oscillation stopped (in STP state)
Output transistors “off” Ta = 25°C
Ta = 85°C
A-D CONVERTER CHARACTERISTICS
Table 15 A-D Converter Characteristics
(VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, f(XIN) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Test conditions
—
—
TCONV
IVREF
IIA
RLADDER
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Reference input current
Analog port input current
Ladder resistor
VCC = VREF = 5.12 V
VREF = 5.0 V 61
50
±1
150
0.5
35
10
±2.5
62
200
5.0
Bits
LSB
tc(
φ
)
µA
µA
kΩ
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
66
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
TIMING REQUIREMENTS
Table 16 Timing Requirements (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
____________
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “H” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input set up time
Serial I/O input hold time
2.0
238
60
60
20
5.0
5.0
4.0
1.6
1.6
80
80
0.95
400
400
200
200
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
SWITCHING CHARACTERISTICS
Table 17 Switching Characteristics (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
ns
ns
ns
ns
ns
ns
ns
µs
tWH(SCLK)
tWL(SCLK)
td(SCLK–SOUT)
tv(SCLK–SOUT)
tr(SCLK)
tf(SCLK)
tr(Pch–strg)
tr(Pch–weak)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
P-channel high-breakdown voltage
output rising time (Note 1)
P-channel high-breakdown voltage
output rising time (Note 2)
0.2 tc
40
40
55
1.8
tC(SCLK)/2–160
tC(SCLK)/2–160
0
Test conditions
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
VEE = VCC–43 V
CL = 100 pF
VEE = VCC–43 V
Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.
2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.
Fig. 73 Circuit for Measuring Output Switching Characteristics
C
L
Serial I/O clock
output port C
L
V
EE
High-breakdown
P-channel open-
drain output port
P5
2
/S
CLK11
,
P5
3
/S
CLK12
,
P5
6
/S
CLK21
,
P5
7
/S
CLK22
P0,P1,P2,
P3,P8
0–
P8
3
Note: Ports P2 and P8 need external resistors.
(Note)
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
67
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 74 Timing Diagram
0.2VCC
tWL(XCIN)
0.8VCC
tWH(XCIN)
tC(XCIN)
XCIN
0.2VCC
tWL(XIN)
0.8VCC
tWH(XIN)
tC(XIN)
XIN
0.2VCC 0.8VCC
tW(RESET)
RESET
0.2VCC
tWL(CNTR)
0.8VCC
tWH(CNTR)
tC(CNTR)
CNTR0,CNTR1
0.2VCC
tWL(INT)
0.8VCC
tWH(INT)
INT0–INT4
0.2VCC
td(SCLK-SOUT)
0.2VCC
0.8VCC
0.8VCC
tr
tsu(SIN-SCLK)th(SCLK-SIN)
tv(SCLK-SOUT)
tC(SCLK)
tWL(SCLK)tWH(SCLK)
SOUT
SIN
SCLK
tf(SCLK)
Timing Diagram
© 1998 MITSUBISHI ELECTRIC CORP.
\KI-9802 Printed in Japan (ROD) 2
New publication, effective Feb. 1998.
Specifications subject to change without notice.
Notes regarding these materials
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¡Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Rev. Rev.
No. date
1.0 First Edition 980202
REVISION DESCRIPTION LIST 38B5 GROUP DATA SHEET
(1/1)
Revision Description
