3803 Group (Spec.H) REJ03B0017-0200Z Rev.2.00 2003.05.28 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3803 group (Spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3803 group (Spec. H) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A-D converter and D-A converters. FEATURES Basic machine-language instructions ...................................... 71 Minimum instruction execution time ................................ 0.24 s (at 16.8 MHz oscillation frequency) Memory size ROM ............................................................... 16 K to 32 K bytes RAM ................................................................. 640 to 1024 bytes Programmable input/output ports ............................................ 56 Software pull-up resistors ................................................. Built-in Interrupts 21 sources, 16 vectors ................................................................. (external 8, internal 12, software 1) Timers ........................................................................... 16-bit 1 8-bit 4 (with 8-bit prescaler) Watchdog timer ............................................................ 16-bit 1 Serial I/O ...................... 8-bit 2 (UART or Clock-synchronized) 8-bit 1 (Clock-synchronized) PWM ............................................ 8-bit 1 (with 8-bit prescaler) A-D converter ............................................. 10-bit 16 channels (8-bit reading enabled) D-A converter ................................................. 8-bit 2 channels LED direct drive port .................................................................. 8 Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V At 12.5 MHz oscillation frequency ............................ 4.0 to 5.5 V At 8.4 MHz oscillation frequency) ............................. 2.7 to 5.5 V At 4.2 MHz oscillation frequency .............................. 2.2 to 5.5 V At 2.1 MHz oscillation frequency) ............................. 2.0 to 5.5 V In middle-speed mode At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V At 12.5 MHz oscillation frequency ............................ 2.7 to 5.5 V At 8.4 MHz oscillation frequency) ............................. 2.2 to 5.5 V At 6.3 MHz oscillation frequency) ............................. 1.8 to 5.5 V In low-speed mode At 32 kHz oscillation frequency ................................. 1.8 to 5.5 V Power dissipation In high-speed mode ................................................ 40 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ................................................... 45 W (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range .................................... -20 to 85C Packages SP .................................................. 64P4B (64-pin 750 mil SDIP) FP ....................................... 64P6N-A (64-pin 14 14 mm QFP) HP ..................................... 64P6Q-A (64-pin 10 10 mm LQFP) KP ..................................... 64P6U-A (64-pin 14 14 mm LQFP) Currently support products are listed below. Table 1 Support products Product name ROM size (bytes) ROM size for User in ( ) M38034M4H-XXXSP M38034M4H-XXXFP M38034M4H-XXXHP M38034M4H-XXXKP M38037M6H-XXXSP M38037M6H-XXXFP M38037M6H-XXXHP M38037M6H-XXXKP M38037M8H-XXXSP M38037M8H-XXXFP M38037M8H-XXXHP M38037M8H-XXXKP Rev.2.00 2003.05.28 RAM size (bytes) 16384 (16254) 640 24576 (24446) 1024 32768 (32638) 1024 page 1 of 81 Package 64P4B 64P6N-A 64P6Q-A 64P6U-A 64P4B 64P6N-A 64P6Q-A 64P6U-A 64P4B 64P6N-A 64P6Q-A 64P6U-A Remarks Mask ROM version Mask ROM version Mask ROM version 3803 Group (Spec.H) P15 P16 P17 34 33 36 35 P13 P14 37 P11/INT01 P12 P06/AN14 38 P05/AN13 42 40 P04/AN12 43 39 P03/AN11 44 P07/AN15 P10/INT41 P02/AN10 46 45 41 P00/AN8 P01/AN9 48 47 PIN CONFIGURATION (TOP VIEW) P37/SRDY3 49 32 P20(LED0) P36/SCLK3 50 31 P21(LED1) P35/TXD3 51 30 P22(LED2) P34/RXD3 52 29 P23(LED3) P33 53 28 P24(LED4) P32 54 27 P25(LED5) P31/DA2 55 26 P26(LED6) P30/DA1 56 VCC 57 VREF 58 AVSS 59 P67/AN7 M38034M4H-XXXFP/HP/KP M38037M6H-XXXFP/HP/KP M38037M8H-XXXFP/HP/KP 25 P27(LED7) 24 VSS 23 XOUT 22 XIN 60 21 P40/INT40/XCOUT 16 P43/INT2 15 14 P45/TXD1 13 P46/SCLK1 P44/RXD1 12 P47/SRDY1/CNTR2 11 P50/SIN2 9 10 8 P53/SRDY2 P52/SCLK2 7 P54/CNTR0 P51/SOUT2 6 P55/CNTR1 P42/INT1 5 17 P56/PWM 64 4 CNVSS P63/AN3 3 18 P60/AN0 63 P57/INT3 RESET P64/AN4 1 P41/INT00/XCIN 19 2 20 62 P62/AN2 61 P61/AN1 P66/AN6 P65/AN5 Package type : 64P6N-A/64P6Q-A/64P6U-A Fig. 1 3803 group (Spec. H) pin configuration Table 2 List of package (Spec. H) Product name ROM size (bytes) ROM size for User in ( ) M38034M4H-XXXFP M38037M6H-XXXFP M38037M8H-XXXFP M38034M4H-XXXHP M38037M6H-XXXHP M38037M8H-XXXHP M38034M4H-XXXKP M38037M6H-XXXKP M38037M8H-XXXKP 16384 (16254) 24576 (24446) 32768 (32638) 16384 (16254) 24576 (24446) 32768 (32638) 16384 (16254) 24576 (24446) 32768 (32638) Package 64P6N-A 64P6Q-A 64P6U-A Rev.2.00 2003.05.28 page 2 of 81 RAM size (bytes) 640 1024 1024 640 1024 1024 640 1024 1024 Remarks Mask ROM version Mask ROM version Mask ROM version 3803 Group (Spec.H) PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38034M6H-XXXSP M38037M6H-XXXSP M38037M8H-XXXSP VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32 P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) Package type : 64P4B Fig. 2 3803 group (Spec. H) pin configuration Table 3 List of package (Spec. H) Package Product name ROM size (bytes) ROM size for User in ( ) 64P4B M38034M4H-XXXSP M38037M6H-XXXSP M38037M8H-XXXSP 16384 (16254) 24576 (24446) 32768 (32638) Rev.2.00 2003.05.28 page 3 of 81 RAM size (bytes) 640 1024 1024 Remarks Mask ROM version Rev.2.00 2003.05.28 28 29 Fig. 3 Functional block diagram page 4 of 81 3 VREF AVSS 2 A-D converter (10) I/O port P6 4 5 6 7 8 9 10 11 P6(8) Clock generating circuit 31 ROM INT3 PWM(8) I/O port P5 12 13 14 15 16 17 18 19 P5(8) SI/O2(8) A P4(8) INT00 INT1 INT2 INT40 P3(8) I/O port P4 27 I/O port P3 P2(8) I/O port P2 (LED drive) I/O port P1 I/O port P0 49 50 51 52 53 54 55 56 P0(8) Timer Y (8) Timer X (8) Timer 2 (8) Timer 1 (8) INT01 INT41 41 42 43 44 45 46 47 48 P1(8) Timer Z (16) Prescaler Y (8) Prescaler X (8) Prescaler 12 (8) CNTR2 CNTR1 26 CNVSS 33 34 35 36 37 38 39 40 CNTR0 SI/O3(8) 57 58 59 60 61 62 63 64 D-A D-A converter converter 2 (8) 1 (8) PS PC L S Y X 20 21 22 23 24 25 28 29 SI/O1(8) PC H C P U Data bus 1 32 RESET 30 Reset input V CC X IN X OUT X CIN X COUT V SS Clock Clock Sub-clock Sub-clock input output input output RAM FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B) 3803 Group (Spec.H) FUNCTIONAL BLOCK 3803 Group (Spec.H) PIN DESCRIPTION Table 4 Pin description Pin Functions Name VCC, VSS Function except a port function *Apply voltage of 1.8 V - 5.5 V to Vcc, and 0 V to Vss. CNVSS Power source CNVSS input VREF Reference voltage *Reference voltage input pin for A-D and D-A converters. AVSS Analog power source *Analog power source input pin for A-D and D-A converters. RESET XIN Reset input Clock input XOUT Clock output P00/AN8- P07/AN15 I/O port P0 P10/INT01 P11/INT41 I/O port P1 *This pin controls the operation mode of the chip. *Normally connected to VSS. *Connect to VSS. *Reset input pin for active "L". *When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *8-bit CMOS I/O port. *A-D converter input pin *I/O direction register allows each pin to be individually programmed as either input or output. *Interrupt input pin *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled in a bit unit. P12-P17 P20-P27 *Input and output pins for the clock generating circuit. *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. I/O port P2 *P20-P27 are enabled to output large current for LED drive. P30/DA1 P31/DA2 *8-bit CMOS I/O port. I/O port P3 P32, P33 *P30, P31, P34-P37 are CMOS 3-state output structure. *Serial I/O3 function pin *P32, P33 are N-channel open-drain output structure. P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 *Pull-up control of P30, P31, P34-P37 is enabled in a bit unit. P40/INT40/ XCOUT P41/INT00/ XCIN *Interrupt input pin *I/O direction register allows each pin to be individually *Sub-clock generating I/O pin programmed as either input or output. (resonator connected) *CMOS compatible input level. *Interrupt input pin *CMOS 3-state output structure. *8-bit CMOS I/O port. I/O port P4 P42/INT1 P43/INT2 *Pull-up control is enabled in a bit unit. P44/RxD1 P45/TxD1 P46/SCLK1 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 I/O port P5 *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. P54/CNTR0 *CMOS 3-state output structure. P55/CNTR1 *Pull-up control is enabled in a bit unit. P56/PWM P57/INT3 Rev.2.00 *Serial I/O1 function pin *Serial I/O1, timer Z function pin P47/SRDY1 /CNTR2 P60/AN0- P67/AN7 *D-A converter input pin *I/O direction register allows each pin to be individually programmed as either input or output. *Timer X function pin *Timer Y function pin *PWM output pin *Interrupt input pin *A-D converter input pin I/O port P6 2003.05.28 *Serial I/O2 function pin page 5 of 81 3803 Group (Spec.H) PART NUMBERING Product name M3803 7 M 8 H - XXX SP Package type SP : 64P4B FP : 64P6N-A HP : 64P6Q-A KP : 64P6U-A ROM number - : standard Omitted in the flash memory version. H- : Minner spec. change product ROM size 9 : 36864 bytes 1 : 4096 bytes A: 40960 bytes 2 : 8192 bytes B: 45056 bytes 3 : 12288 bytes C: 49152 bytes 4 : 16384 bytes D: 53248 bytes 5 : 20480 bytes E: 57344 bytes 6 : 24576 bytes F : 61440 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user's ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes Fig. 4 Part numbering Rev.2.00 2003.05.28 page 6 of 81 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes 3803 Group (Spec.H) GROUP EXPANSION Packages GROUP EXPANSION 64P4B ......................................... 64-pin shrink plastic-molded DIP 64P6N-A .................................... 0.8 mm-pitch plastic molded QFP 64P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP 64P6U-A .................................. 0.8 mm-pitch plastic molded LQFP Mitsubishi plans to expand the 3803 group (Spec. H) as follows. Memory Type Support for mask ROM version. Memory Size Mask ROM size ................................................. 16 K to 32 K bytes RAM size ............................................................ 640 to 1024 bytes Memory Expansion Plan ROM size (bytes) ROM exteranal : Under development As of Mar. 2003 : Mass production M38039MF M38039FF 60K M38039FFH 48K M38039MC M38037M8H 32K 28K 24K M38037M6H 20K M38034M4H 16K 12K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (bytes) Note 1: Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Note 2: See the 3803/3804 group data sheet about 3803 group products other than 3803 group (spec. H) because there are electrical characteristics differences and so on. Fig. 5 Memory expansion plan Rev.2.00 2003.05.28 page 7 of 81 3803 Group (Spec.H) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) [Stack Pointer (S)] The 3803 group (Spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 10. Store registers other than those described in Figure 10 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 PCH Stack pointer b0 Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig.6 740 Family CPU register structure Rev.2.00 2003.05.28 page 8 of 81 3803 Group (Spec.H) On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) - 1 M (S) (PCL) (S) (S)- 1 (S) M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) (S) - 1 (PCL) Push return address on stack (S) - 1 (PS) Push contents of processor status register on stack (S) - 1 Interrupt Service Routine Execute RTS (S) (PCH) I Flag is set from "0" to "1" Fetch the jump vector Execute RTI Note: Condition for acceptance of an interrupt (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) POP contents of processor status register from stack POP return address from stack Interrupt enable flag is "1" Interrupt disable flag is "0" Fig. 7 Register push and pop at interrupt generation and subroutine call Table 5 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP Rev.2.00 2003.05.28 page 9 of 81 3803 Group (Spec.H) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. *Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. *Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". *Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". *Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic. *Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". *Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. *Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. *Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 6 Set and clear instructions of each bit of processor status register Set instruction Clear instruction Rev.2.00 2003.05.28 SET V flag - N flag - CLT CLV - C flag SEC Z flag - I flag SEI D flag SED B flag - T flag CLC - CLI CLD - page 10 of 81 3803 Group (Spec.H) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. b7 b0 1 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to "1". Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig.8 Structure of CPU mode register Rev.2.00 2003.05.28 page 11 of 81 3803 Group (Spec.H) MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting "1" to bit 0 of MISRG (address 001016). However, by setting this bit to "1", the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 9 shows the structure of MISRG. Middle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to "1" in the condition that the middle-speed mode automatic switch set bit is "1" while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). (2) Bits 1, 2, 3 of address 0010 16: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary: set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3803 group (Spec. H) has the built-in function which automatically switches from low to middle-speed mode by program. b7 b0 MISRG (MISRG : address 001016) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1: Automatically set disabled Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enabled (Note) Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start (Note) Not used (return "0" when read) (Do not write "1" to this bit) Note: When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (3B16) change. Fig. 9 Structure of MISRG Rev.2.00 2003.05.28 page 12 of 81 3803 Group (Spec.H) MEMORY Special Function Register (SFR) Area Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Special Page RAM Access to this area with only 2 bytes is possible in the special page addressing mode. RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) Address XXXX16 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 000016 SFR area Zero page 004016 010016 RAM XXXX16 Not used 0FF016 0FFF16 SFR area Not used YYYY16 ROM area Reserved ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 Fig. 10 Memory map diagram Rev.2.00 2003.05.28 page 13 of 81 (128 bytes) ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page 3803 Group (Spec.H) 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) 000816 Port P4 (P4) 002816 Timer Z low-order (TZL) 000916 Port P4 direction register (P4D) 002916 Timer Z high-order (TZH) 000A16 Port P5 (P5) 002A16 Timer Z mode register (TZM) 000B16 Port P5 direction register (P5D) 002B16 PWM control register (PWMCON) 000C16 Port P6 (P6) 002C16 PWM prescaler (PREPWM) 000D16 Port P6 direction register (P6D) 002D16 PWM register (PWM) 000E16 Timer 12, X count source selection register (T12XCSS) 002E16 000F16 Timer Y, Z count source selection register (TYZCSS) 002F16 Baud rate generator 3 (BRG3) 001016 MISRG 003016 Transmit/Receive buffer register 3 (TB3/RB3) 001116 Reserved 003116 Serial I/O3 status register (SIO3STS) 001216 Reserved 003216 Serial I/O3 control register (SIO3CON) 001316 Reserved 003316 UART3 control register (UART3CON) 001416 Reserved 003416 AD/DA control register (ADCON) 001516 Reserved 003516 A-D conversion register 1 (AD1) 001616 Reserved 003616 D-A1 conversion register (DA1) 001716 Reserved 003716 D-A2 conversion register (DA2) 001816 Transmit/Receive buffer register 1 (TB1/RB1) 003816 A-D conversion register 2 (AD2) 001916 Serial I/O1 status register (SIO1STS) 003916 Interrupt source selection register (INTSEL) 001A16 Serial I/O1 control register (SIO1CON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART1 control register (UART1CON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG1) 003C16 Interrupt request register 1 (IREQ1) 001D16 Serial I/O2 control register (SIO2CON) 003D16 Interrupt request register 2 (IREQ2) 001E16 Watchdog timer control register (WDTCON) 003E16 Interrupt control register 1 (ICON1) 001F16 Serial I/O2 register (SIO2) 003F16 Interrupt control register 2 (ICON2) Reserved area: Do not write any data to these addresses, because these areas are reserved. Fig. 11 Memory map of special function register (SFR) Rev.2.00 2003.05.28 page 14 of 81 0FF016 Port P0 pull-up control register (PULL0) 0FF116 Port P1 pull-up control register (PULL1) 0FF216 Port P2 pull-up control register (PULL2) 0FF316 Port P3 pull-up control register (PULL3) 0FF416 Port P4 pull-up control register (PULL4) 0FF516 Port P5 pull-up control register (PULL5) 0FF616 Port P6 pull-up control register (PULL6) 3803 Group (Spec.H) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin be- comes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 7 I/O port function Pin P00/AN8-P07/AN15 P10/INT41 P11/INT01 P12-P17 P20/LED0- P27/LED7 P30/DA1 P31/DA2 P32 P33 P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT00/XCIN P41/INT40/XCOUT Name Port P0 Port P1 I/O Structure CMOS compatible input level CMOS 3-state output Non-Port Function A-D converter input External interrupt input Related SFRs Ref.No. AD/DA control register Interrupt edge selection register (1) (2) (3) Port P2 Port P3 Port P4 CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output D-A converter output Serial I/O3 function I/O Serial I/O3 control register UART3 control register (6) (7) (8) (9) CMOS compatible input level CMOS 3-state output External interrupt input Sub-clock generating circuit Interrupt edge selection register CPU mode register Interrupt edge selection register (10) (11) Serial I/O1 function I/O Serial I/O1 control register UART1 control register Serial I/O1 function I/O Timer Z function I/O Serial I/O1 control register Timer Z mode register Serial I/O2 control register (6) (7) (8) (12) P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1/CNTR2 Port P5 P60/AN0-P67/AN7 Port P6 CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output Serial I/O2 function I/O Timer X, Y function I/O Timer XY mode register PWM output External interrupt input PWM control register Interrupt edge selection register AD/DA control register A-D converter input Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.2.00 2003.05.28 page 15 of 81 (4) (5) External interrupt input P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 AD/DA control register (2) (13) (14) (15) (16) (17) (18) (2) (1) 3803 Group (Spec.H) (1) Ports P0, P6 (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Pull-up control bit Direction register Data bus Direction register Port latch Data bus Port latch A-D converter input Analog input pin selection bit (3) Ports P12 to P17, P2 Interrupt input (4) Ports P30, P31 Pull-up control bit Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch D-A converter output DA1 output enable (P30) DA2 output enable (P31) (6) Ports P34, P44 (5) Ports P32, P33 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Data bus Direction register Port latch Data bus Port latch Serial I/O input (7) Ports P35, P45 (8) Ports P36, P46 Pull-up control bit Serial I/O synchronous clock selection bit Pull-up control bit Serial I/O enable bit P-channel output disable bit Serial I/O enable bit Transmit enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Direction register Data bus Data bus Port latch Serial I/O output Port latch Serial I/O clock output Serial I/O external clock input Fig. 12 Port block diagram (1) Rev.2.00 2003.05.28 page 16 of 81 3803 Group (Spec.H) (10) Port P40 (9) Port P37 Pull-up control bit Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Port XC switch bit Direction register Direction register Data bus Port latch Data bus Port latch INT40 interrupt input Serial I/O3 ready output Oscillator Port P41 Port XC switch bit (11) Port P41 (12) Port P47 Pull-up control bit Port XC switch bit Pull-up control bit Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Direction register Data bus Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Port latch Data bus Port latch INT00 interrupt input Sub-clock generating circuit input Timer output Serial I/O1 ready output CNTR2 interrupt input (14) Port P51 (13) Port P50 Pull-up control bit Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Data bus Direction register Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 13 Port block diagram (2) Rev.2.00 2003.05.28 page 17 of 81 P-channel output disable bit 3803 Group (Spec.H) (15) Port P52 (16) Port P53 Pull-up control bit Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit SRDY2 enable bit Direction register Direction register Port latch Data bus Data bus Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM output enable bit Direction register Data bus Direction register Data bus Port latch Pulse output mode PWM output Timer output CNTR interrupt input Fig. 14 Port block diagram (3) Rev.2.00 2003.05.28 Port latch page 18 of 81 3803 Group (Spec.H) b7 b0 Port P0 pull-up control register (PULL0: address 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P1 pull-up control register (PULL1: address 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Fig. 15 Structure of port pull-up control register (1) Rev.2.00 2003.05.28 page 19 of 81 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec.H) b7 b0 Port P2 pull-up control register (PULL2: address 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P3 pull-up control register (PULL3: address 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return "0" when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Fig. 16 Structure of port pull-up control register (2) Rev.2.00 2003.05.28 page 20 of 81 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec.H) b7 b0 Port P4 pull-up control register (PULL4: address 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P5 pull-up control register (PULL5: address 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Fig. 17 Structure of port pull-up control register (3) Rev.2.00 2003.05.28 page 21 of 81 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec.H) b7 b0 Port P6 pull-up control register (PULL6: address 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Fig. 18 Structure of port pull-up control register (4) Rev.2.00 2003.05.28 page 22 of 81 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3803 Group (Spec.H) INTERRUPTS The 3803 group (Spaec. H)'s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt. When several interrupt requests occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Source Selection Which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 003916). 1. INT0 or Timer Z 2. CNTR1 or Serial I/O3 reception 3. Serial I/O2 or Timer Z 7. INT4 or CNTR2 8. A-D converter or serial I/O3 transmission External Interrupt Pin Selection The occurrence sources of the external interrupt INT0 and INT4 can be selected from either input from INT00 and INT40 pin, or input from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16). Rev.2.00 2003.05.28 page 23 of 81 Notes When setting the followings, the interrupt request bit may be set to "1". *When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16) *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection register (address 003916) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit or the interrupt source select bit to "1". Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). 3803 Group (Spec.H) Table 8 Interrupt vector addresses and priority Interrupt Source Priority Vector Addresses (Note 1) Low High FFFD16 FFFC16 FFFB16 FFFA16 Interrupt Request Generating Conditions Reset (Note 2) INT0 1 2 Timer Z INT1 3 FFF916 FFF816 At detection of either rising or falling edge of INT1 input 4 FFF716 FFF616 At completion of serial I/O1 data reception 5 FFF516 FFF416 At completion of serial I/O1 transmission shift or when transmission buffer is empty Timer X Timer Y Timer 1 Timer 2 CNTR0 6 7 8 9 10 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFF216 FFF016 FFEE16 FFEC16 At timer X underflow FFEA16 At detection of either rising or falling edge of CNTR0 input CNTR1 11 FFE916 FFE816 At detection of either rising or falling edge of CNTR1 input Serial I/O1 reception Serial I/O1 transmission At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At timer Y underflow At timer 1 underflow Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected STP release timer underflow At timer 2 underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Serial I/O3 reception Serial I/O2 12 FFE716 FFE616 Valid when serial I/O2 is selected Timer Z INT2 At completion of serial I/O2 data transmission or reception At timer Z underflow 13 FFE516 FFE416 At detection of either rising or falling edge of INT2 input INT3 14 FFE316 FFE216 At detection of either rising or falling edge of INT3 input INT4 15 FFE116 FFE016 At detection of either rising or falling edge of INT4 input External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) At completion of serial I/O3 data reception CNTR2 A-D converter Serial I/O3 transmission 16 BRK instruction 17 FFDF16 FFDD16 FFDE16 FFDC16 At detection of either rising or falling edge of CNTR2 input At completion of A-D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty Valid when serial I/O3 is selected At BRK instruction execution Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.2.00 2003.05.28 page 24 of 81 3803 Group (Spec.H) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Fig. 19 Interrupt control Rev.2.00 2003.05.28 page 25 of 81 Interrupt request 3803 Group (Spec.H) b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns "0" when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns "0" when read) b7 b0 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) b7 b0 INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns "0" when read) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Not used (Do not write "1" to these bits.) (Do not write "1" to these bits simultaneously.) INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt Not used (Do not write "1" to this bit.) CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A-D converter interrupt 1 : Serial I/O3 transmit interrupt Fig. 20 Structure of interrupt-related registers Rev.2.00 2003.05.28 page 26 of 81 3803 Group (Spec.H) TIMERS 8-bit Timers Timer X and Timer Y The 3803 group (Spec. H) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches "0016", an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to "1". Timer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B 16). When these bits are "00" (high-speed mode) or "01" (middle-speed mode), XIN is selected. When these bits are"10" (low-speed mode), XCIN is selected. Prescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. Prescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN). The count source is selected by the timer 12, X count source selection register (address 000E16) and the timer Y, Z count source selection register (address 000F16 ) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN); and f(XCIN). Rev.2.00 2003.05.28 page 27 of 81 The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode Mode selection This mode can be selected by setting "00" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). Explanation of operation The timer count operation is started by setting "0" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches "0016", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse output mode Mode selection This mode can be selected by setting "01" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). Explanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. Regardless of the timer counting or not the output of CNTR0/CNTR1 pin is initialized to the level of specified by their active edge switch bits when writing to the timer. When the CNTR0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. Switching the CNTR0 or CNTR1 active edge switch bit will reverse the output level of the corresponding CNTR0 or CNTR1 pin. Precautions Set the double-function port of CNTR0/CNTR1 pin and port P5 4/ P55 to output in this mode. 3803 Group (Spec.H) (3) Event counter mode Mode selection This mode can be selected by setting "10" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). Explanation of operation The operation is the same as the timer mode's except that the timer counts signals input from the CNTR 0 or CNTR 1 pin. The valid edge for the count operation depends on the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. Precautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. (4) Pulse width measurement mode Mode selection This mode can be selected by setting "11" to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). Explanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is "1", the timer counts during the term of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input ("L" term). When it is "0", the timer counts during the term of one rising edge input until the next falling edge input ("H" term). Precautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. The count operation can be stopped by setting "1" to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). The interrupt request bit is set to "1" each time the timer underflows. *Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Rev.2.00 2003.05.28 page 28 of 81 3803 Group (Spec.H) "00" "01" XIN (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Clock for timer 12 Clock for timer Y XCIN Main clock division ratio selection bits Count source selection bit Clock for timer X "10" Data bus Prescaler X latch (8) f(XCIN) Pulse width measurement mode Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge switch bit "0" P54/CNTR0 Event counter mode Timer X latch (8) Timer X (8) Timer X count stop bit To CNTR0 interrupt request bit "1 " CNTR0 active edge switch bit "1" Port P54 direction register To timer X interrupt request bit "0" Port P54 latch Q Toggle flip-flop T Q R Timer X latch write pulse Pulse output mode Pulse output mode Data bus Count source selection bit Clock for timer Y Prescaler Y latch (8) Pulse width measurement mode f(XCIN) Prescaler Y (8) P55/CNTR1 CNTR1 active edge switch bit "0" Event counter mode Timer Y latch (8) Timer mode Pulse output mode Timer Y (8) To timer Y interrupt request bit Timer Y count stop bit To CNTR1 interrupt request bit "1" CNTR1 active edge switch bit "1" Q Toggle flip-flop T Q Port P55 direction register Port P55 latch "0" R Timer Y latch write pulse Pulse output mode Pulse output mode Data bus Prescaler 12 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.2.00 2003.05.28 page 29 of 81 3803 Group (Spec.H) b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0 : Count start 1 : Count stop Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR1 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0 : Count start 1 : Count stop Fig. 22 Structure of timer XY mode register Rev.2.00 2003.05.28 page 30 of 81 3803 Group (Spec.H) b7 b0 Timer 12, X count source selection register (T12XCSS : address 000E16) Timer 12 count source selection bits b3b2b1b0 1010 : 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) b7 1011 : 1100 : 1101 : 1110 : 1111 : Not used Not used b0 Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3b2b1b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers Rev.2.00 2003.05.28 page 31 of 81 1011 : 1100 : 1101 : 1110 : 1111 : Not used Not used 3803 Group (Spec.H) 16-bit Timer (2) Event counter mode The timer Z is a 16-bit timer. When the timer reaches "000016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to "1". When reading/writing to the timer Z, perform reading/writing to both the high-order byte and the low-order byte. When reading the timer Z, read from the high-order byte first, followed by the low-order byte. Do not perform the writing to the timer Z between read operation of the high-order byte and read operation of the low-order byte. When writing to the timer Z, write to the low-order byte first, followed by the high-order byte. Do not perform the reading to the timer Z between write operation of the low-order byte and write operation of the high-order byte. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16). Mode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "1" to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16). When it is "0", the rising edge is valid. When it is "1", the falling edge is valid. Interrupt The interrupt at an underflow is the same as the timer mode's. Explanation of operation The operation is the same as the timer mode's. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure 26 shows the timing chart of the timer/event counter mode. (1) Timer mode Mode selection This mode can be selected by setting "000" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. Interrupt When an underflow occurs, the INT0/timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16) is set to "1". Explanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting "0" to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16). When the timer reaches "000016", an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. Rev.2.00 2003.05.28 page 32 of 81 (3) Pulse output mode Mode selection This mode can be selected by setting "001" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. Interrupt The interrupt at an underflow is the same as the timer mode's. Explanation of operation The operation is the same as the timer mode's. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the output starts with "H" level. When it is "1", the output starts with "L" level. Precautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure 27 shows the timing chart of the pulse output mode. 3803 Group (Spec.H) (4) Pulse period measurement mode (5) Pulse width measurement mode Mode selection This mode can be selected by setting "010" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. Interrupt The interrupt at an underflow is the same as the timer mode's. When the pulse period measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to "1". Explanation of operation The cycle of the pulse which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the timer counts during the term from one falling edge of CNTR2 pin input to the next falling edge. When it is "1", the timer counts during the term from one rising edge input to the next rising edge input. When the valid edge of measurement completion/start is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and "FFFF16" is set to the timer. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. Figure 28 shows the timing chart of the pulse period measurement mode. Mode selection This mode can be selected by setting "011" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. Interrupt The interrupt at an underflow is the same as the timer mode's. When the pulse widths measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to "1". Explanation of operation The pulse width which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is "0", the timer counts during the term from one rising edge input to the next falling edge input ("H" term). When it is "1", the timer counts during the term from one falling edge of CNTR2 pin input to the next rising edge of input ("L" term). When the valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. When the timer Z underflows, the timer Z interrupt occurs and "FFFF16" is set to the timer Z. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. "FFFF16" is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. Figure 29 shows the timing chart of the pulse width measurement mode. Rev.2.00 2003.05.28 page 33 of 81 3803 Group (Spec.H) (6) Programmable waveform generating mode Mode selection This mode can be selected by setting "100" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(X CIN); or f(XCIN) can be selected as the count source. Interrupt The interrupt at an underflow is the same as the timer mode's. Explanation of operation The operation is the same as the timer mode's. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR2 pin. Precautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. Figure 30 shows the timing chart of the programmable waveform generating mode. (7) Programmable one-shot generating mode Mode selection This mode can be selected by setting "101" to the timer Z operating mode bits (bits 2 to 0) and setting "0" to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. Interrupt The interrupt at an underflow is the same as the timer mode's. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A16). When it is "0", the falling edge active is selected; when it is "1", the rising edge active is selected. When the valid edge of the INT1 pin is detected, the INT1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16) is set to "1". Explanation of operation *"H" one-shot pulse; Bit 5 of timer Z mode register = "0" The output level of the CNTR2 pin is initialized to "L" at mode selection. When trigger generation (input signal to INT 1 pin) is detected, "H" is output from the CNTR2 pin. When an underflow occurs, "L" is output. The "H" one-shot pulse width is set by the setting value to the timer Z register low-order and high-order. When trigger generating is detected during timer count stop, al- Rev.2.00 2003.05.28 page 34 of 81 though "H" is output from the CNTR2 pin, "H" output state continues because an underflow does not occur. *"L" one-shot pulse; Bit 5 of timer Z mode register = "1" The output level of the CNTR2 pin is initialized to "H" at mode selection. When trigger generation (input signal to INT 1 pin) is detected, "L" is output from the CNTR2 pin. When an underflow occurs, "H" is output. The "L" one-shot pulse width is set by the setting value to the timer Z low-order and high-order. When trigger generating is detected during timer count stop, although "L" is output from the CNTR2 pin, "L" output state continues because an underflow does not occur. Precautions Set the double-function port of CNTR2 pin and port P47 to output, and of INT1 pin and port P42 to input in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure 31 shows the timing chart of the programmable one-shot generating mode. Notes regarding all modes Timer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation "writing data only to the latch" is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation "writing data to both the latch and the timer at the same time" is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. Timer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. Switch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit. Switch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Usage of CNTR2 pin as normal I/O port To use the CNTR2 pin as normal I/O port P47, set timer Z operating mode bits (b2, b1, b0) of timer Z mode register (address 002A16) to "000". 3803 Group (Spec.H) P42/INT1 CNTR2 active edge Data bus Programmable one-shot switch bit "1" generating mode Programmable one-shot generating circuit Programmable one-shot generating mode "0" To INT1 interrupt request bit Programmable waveform generating mode Output level latch D Q T Pulse output mode S Q T Q CNTR2 active edge switch "0"bit "1" Pulse output mode "001" "100" "101" Timer Z operating mode bits Timer Z low-order latch Timer Z high-order latch Timer Z low-order Timer Z high-order Port P47 latch To timer Z interrupt request bit Port P47 direction register Pulse period measurement mode Pulse width measurement mode Edge detection circuit "1" "0" CNTR2 active edge switch bit XIN Clock for timer Z P47/CNTR2 Fig. 24 Block diagram of timer Z Rev.2.00 2003.05.28 page 35 of 81 f(XCIN) "0" Timer/Event counter mode switch bit Timer Z count stop bit Count source selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider XCIN To CNTR2 interrupt request bit "1" 3803 Group (Spec.H) b7 b0 Timer Z mode register (TZM : address 002A16) Timer Z operating mode bits b2b1b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : "L" output 1 : "H" output CNTR2 active edge switch bit 0 : *Event counter mode: Count at rising edge *Pulse output mode: Start outputting "H" *Pulse period measurement mode: Measurement between two falling edges *Pulse width measurement mode: Measurement of "H" term *Programmable one-shot generating mode: After start outputting "L", "H" one-shot pulse generated *Interrupt at falling edge 1 : *Event counter mode: Count at falling edge *Pulse output mode: Start outputting "L" *Pulse period measurement mode: Measurement between two rising edges *Pulse width measurement mode: Measurement of "L" term *Programmable one-shot generating mode: After start outputting "H", "L" one-shot pulse generated *Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (Note) 0 : Timer mode 1 : Event counter mode Note: When selecting the modes except the timer/event counter mode, set "0" to this bit. Fig. 25 Structure of timer Z mode register Rev.2.00 2003.05.28 page 36 of 81 3803 Group (Spec.H) FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig. 26 Timing chart of timer/event counter mode FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR2 pin CNTR2 CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 27 Timing chart of pulse output mode Rev.2.00 2003.05.28 page 37 of 81 3803 Group (Spec.H) 000016 T3 T2 T1 FFFF16 TR FFFF16 + T1 TR T2 T3 FFFF16 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges) 000016 T3 T2 T1 FFFF16 TR FFFF16 + T2 Signal input from CNTR2 pin T3 T1 CNTR2 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of "L" width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 29 Timing chart of pulse width measurement mode (Measuring "L" term) Rev.2.00 2003.05.28 page 38 of 81 3803 Group (Spec.H) FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L T3 T1 T2 TR TR TR TR CNTR2 CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 30 Timing chart of programmable waveform generating mode FFFF16 L TR Signal input from INT1 pin Signal output from CNTR2 pin L TR L CNTR2 TR L CNTR2 L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = "0"; Falling edge active) Fig. 31 Timing chart of programmable one-shot generating mode ("H" one-shot pulse generating) Rev.2.00 2003.05.28 page 39 of 81 3803 Group (Spec.H) (1) Clock Synchronous Serial I/O Mode SERIAL I/O Serial I/O1 Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Serial I/O1 control register Address 001816 Receive buffer register 1 P44/RXD1 Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register 1 Shift clock Clock control circuit P46/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 1/4 Address 001C16 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY1 F/F Clock control circuit Falling-edge detector Shift clock P45/TXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 32 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD1 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD1 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 33 Operation of clock synchronous serial I/O1 Rev.2.00 2003.05.28 page 40 of 81 3803 Group (Spec.H) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 P44/RXD1 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) OE Receive buffer register 1 Character length selection bit ST detector 7 Receive shift register 1 bits 8 bits PE FE 1/16 UART1 control register Address 001B16 SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+ f(XIN) 1) Baud rate generator (f(XCIN) in low-speed mode) Address 001C16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P45/TXD1 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Character length selection bit Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 34 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 TBE=0 TSC=1] TBE=1 ST D0 D1 SP ST D0 SP D1 ] 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 Serial input RXD1 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 35 Operation of UART serial I/O1 Rev.2.00 2003.05.28 page 41 of 81 3803 Group (Spec.H) [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD1 pin. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.2.00 2003.05.28 page 42 of 81 3803 Group (Spec.H) b7 b0 Serial I/O1 status register (SIO1STS : address 001916) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 UART1 control register (UART1CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Fig. 36 Structure of serial I/O1 control registers Rev.2.00 2003.05.28 page 43 of 81 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins) 3803 Group (Spec.H) Notes concerning serial I/O1 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation Note Clear the serial I/O1 enable bit and the transmit enable bit to "0" (serial I/O and transmit disabled). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation Note Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to "0". Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. 1.2 Stop of receive operation Note Clear the receive enable bit to "0" (receive disabled), or clear the serial I/O1 enable bit to "0" (serial I/O disabled). 2.2 Stop of receive operation Note Clear the receive enable bit to "0" (receive disabled). 1.3 Stop of transmit/receive operation Note Clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to "0" (serial I/O disabled) (refer to 1.1). Rev.2.00 2003.05.28 page 44 of 81 2.3 Stop of transmit/receive operation Note 1 (only transmission operation is stopped) Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to "0". Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. Note 2 (only receive operation is stopped) Clear the receive enable bit to "0" (receive disabled). 3803 Group (Spec.H) 3. SRDY1 output of reception side Note When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY1 output enable bit, and the transmit enable bit to "1" (transmit enabled). 4. Setting serial I/O1 control register again Note Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O control register Set both the transmit enable bit Can be set with the LDM instruction at the same time (TE) and the receive enable bit (RE), or one of them to "1" 5. Data transmission control with referring to transmit shift register completion flag Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK1 input level. Also, write data to the transmit buffer register at "H" of the SCLK1 input level. Rev.2.00 2003.05.28 page 45 of 81 7. Transmit interrupt request when transmit enable bit is set Note When using the transmit interrupt, take the following sequence. Set the serial I/O1 transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O1 transmit interrupt request bit to "0" after 1 or more instruction has executed. Set the serial I/O1 transmit interrupt enable bit to "1" (enabled). Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and the transmit shift register shift completion flag are also set to "1". Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. 3803 Group (Spec.H) Serial I/O2 b7 b0 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) [Serial I/O2 Control Register (SIO2CON)] 001D16 Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 signal output The serial I/O2 control register contains eight bits which control various serial I/O2 functions. SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Fig. 37 Structure of serial I/O2 control register 1/8 Internal synchronous clock selection bits Divider 1/16 f(XIN) (f(XCIN) in low-speed mode) Data bus 1/32 1/64 1/128 1/256 P53 latch P53/SRDY2 Serial I/O2 synchronous clock selection bit "1" SRDY2 "1 " SRDY2 output enable bit Synchronization circuit SCLK2 "0 " "0" External clock P52 latch "0 " P52/SCLK2 "1 " Serial I/O2 port selection bit Serial I/O counter 2 (3) P51 latch "0 " P51/SOUT2 "1 " Serial I/O2 port selection bit Serial I/O2 register (8) P50/SIN2 Address 001F16 Fig. 38 Block diagram of serial I/O2 Rev.2.00 2003.05.28 page 46 of 81 Serial I/O2 interrupt request 3803 Group (Spec.H) Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Fig. 39 Timing of serial I/O2 Rev.2.00 2003.05.28 page 47 of 81 3803 Group (Spec.H) Serial I/O3 (1) Clock Synchronous Serial I/O Mode Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 003216) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O3 control register Address 003016 Receive buffer register 3 P34/RXD3 Address 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register 3 Shift clock Clock control circuit P36/SCLK3 Serial I/O3 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 3 1/4 Address 002F16 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P37/SRDY3 Clock control circuit Falling-edge detector F/F Shift clock P35/TXD3 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 3 Transmit buffer register 3 Address 003016 Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Data bus Fig. 40 Block diagram of clock synchronous serial I/O3 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD3 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD3 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY3 Write pulse to receive/transmit buffer register (address 003016) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 41 Operation of clock synchronous serial I/O3 Rev.2.00 2003.05.28 page 48 of 81 3803 Group (Spec.H) (2) Asynchronous Serial I/O (UART) Mode two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit of the serial I/O3 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Serial I/O3 control register Address 003216 Address 003016 P34/RXD3 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive buffer register 3 OE Character length selection bit ST detector 7 bits Receive shift register 3 1/16 8 bits PE FE UART3 control register SP detector Address 003316 Clock control circuit Serial I/O3 synchronous clock selection bit P36/SCLK3 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator 3 (f(XCIN) in low-speed mode) Address 002F16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P35/TXD3 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 3 Character length selection bit Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Transmit buffer register 3 Address 003016 Data bus Fig. 42 Block diagram of UART serial I/O3 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD3 TBE=0 TSC=1] TBE=1 ST D0 D1 SP ST D0 SP D1 ] 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 Serial input RXD3 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 43 Operation of UART serial I/O3 Rev.2.00 2003.05.28 page 49 of 81 3803 Group (Spec.H) [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P35/TXD3 pin. [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.2.00 2003.05.28 page 50 of 81 3803 Group (Spec.H) b7 b0 Serial I/O3 status register (SIO3STS : address 003116) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b0 Serial I/O3 control register (SIO3CON : address 003216) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O3 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY3 output enable bit (SRDY) 0: P37 pin operates as normal I/O pin 1: P37 pin operates as SRDY3 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O3 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O3 enable bit (SIOE) 0: Serial I/O disabled (pins P34 to P37 operate as normal I/O pins) 1: Serial I/O enabled (pins P34 to P37 operate as serial I/O pins) b7 b0 UART3 control register (UART3CON : address 003316) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P35/TXD3 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 44 Structure of serial I/O3 control registers Rev.2.00 2003.05.28 page 51 of 81 3803 Group (Spec.H) Notes concerning serial I/O3 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation Note Clear the serial I/O3 enable bit and the transmit enable bit to "0" (serial I/O and transmit disabled). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation Note Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to "0". Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to "1" at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. 1.2 Stop of receive operation Note Clear the receive enable bit to "0" (receive disabled), or clear the serial I/O3 enable bit to "0" (serial I/O disabled). 2.2 Stop of receive operation Note Clear the receive enable bit to "0" (receive disabled). 1.3 Stop of transmit/receive operation Note Clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O3 enable bit to "0" (serial I/O disabled) (refer to 1.1). Rev.2.00 2003.05.28 page 52 of 81 2.3 Stop of transmit/receive operation Note 1 (only transmission operation is stopped) Clear the transmit enable bit to "0" (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to "0". Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to "0" (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. Note 2 (only receive operation is stopped) Clear the receive enable bit to "0" (receive disabled). 3803 Group (Spec.H) 3. SRDY3 output of reception side Note When signals are output from the SRDY3 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY3 output enable bit, and the transmit enable bit to "1" (transmit enabled). 4. Setting serial I/O3 control register again Note Set the serial I/O3 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O3 control register Set both the transmit enable bit Can be set with the LDM instruction at the same time (TE) and the receive enable bit (RE), or one of them to "1" 5. Data transmission control with referring to transmit shift register completion flag Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK3 input level. Also, write data to the transmit buffer register at "H" of the SCLK input level. Rev.2.00 2003.05.28 page 53 of 81 7. Transmit interrupt request when transmit enable bit is set Note When using the transmit interrupt, take the following sequence. Set the serial I/O3 transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O3 transmit interrupt request bit to "0" after 1 or more instruction has executed. Set the serial I/O3 transmit interrupt enable bit to "1" (enabled). Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and the transmit shift register shift completion flag are also set to "1". Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. 3803 Group (Spec.H) PULSE WIDTH MODULATION (PWM) PWM Operation The 3803 group (Spec. H) has PWM functions with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input X CIN or that clock input divided by 2 in low-speed mode. When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the "H" term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 (n+1) / f(XIN) = 31.875 (n+1) s (when f(XIN) = 8 MHz) Output pulse "H" term = PWM period m / 255 = 0.125 (n+1) m s (when f(XIN) = 8 MHz) 31.875 m (n+1) s 255 PWM output T = [31.875 (n+1)] s m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source is f(XIN)) Fig. 45 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch PWM register latch PWM prescaler PWM register Count source selection bit "0" XIN Port P56 or XCIN 1/2 "1" Port P56 latch PWM enable bit Fig. 46 Block diagram of PWM function Rev.2.00 2003.05.28 page 54 of 81 3803 Group (Spec.H) b7 b0 PWM control register (PWMCON : address 002B16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return "0" when read) Fig. 47 Structure of PWM control register A B B = C T2 T C PWM output T PWM register write signal PWM prescaler write signal T T2 (Changes "H" term from "A" to "B".) (Changes PWM period from "T" to "T2".) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 48 PWM output timing when PWM register or PWM prescaler is changed Rev.2.00 2003.05.28 page 55 of 81 3803 Group (Spec.H) A-D CONVERTER [A-D Conversion Register 1, 2 (AD1, AD2)] 003516, 003816 The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. Bit 7 of the A-D conversion register 2 is the conversion mode selection bit. When this bit is set to "0," the A-D converter becomes the 10-bit A-D mode. When this bit is set to "1," that becomes the 8-bit A-D mode. The conversion result of the 8-bit A-D mode is stored in the A-D conversion register 1. As for 10-bit A-D mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the A-D conversion registers 1, 2 after A-D conversion is completed (in Figure 50). As for 10-bit A-D mode, the 8-bit reading inclined to MSB is performed when reading the A-D converter register 1 after A-D conversion is started; and when the A-D converter register 1 is read after reading the A-D converter register 2, the 8-bit reading inclined to LSB is performed. Channel Selector The channel selector selects one of ports P67/AN7 to P60/AN0 or P07/AN15 to P00/AN8, and inputs the voltage to the comparator. Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the A-D conversion registers 1, 2. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. b7 b0 AD/DA control register (ADCON : address 003416) Analog input pin selection bits 1 b2 b1 b0 0 0 0 0 1 1 1 1 [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A-D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, and changes to "1" when an A-D conversion ends. Writing "0" to this bit starts the A-D conversion. 0: P60/AN0 or P00/AN8 1: P61/AN1 or P01/AN9 0: P62/AN2 or P02/AN10 1: P63/AN3 or P03/AN11 0: P64/AN4 or P04/AN12 1: P65/AN5 or P05/AN13 0: P66/AN6 or P06/AN14 1: P67/AN7 or P07/AN15 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Analog input pin selection bit 2 0: AN0 to AN7 side 1: AN8 to AN15 side Comparison Voltage Generator The comparison voltage generator divides the voltage between VREF and AVSS into 1024, and that outputs the comparison voltage in the 10-bit A-D mode (256 division in 8-bit A-D mode). The A-D converter successively compares the comparison voltage Vref in each mode, dividing the VREF voltage (see below), with the input voltage. * 10-bit A-D mode (10-bit reading) Vref = VREF n (n = 0-1023) 1024 * 10-bit A-D mode (8-bit reading) Vref = VREF n (n = 0-255) 256 * 8-bit A-D mode Vref = VREF (n-0.5) (n = 1-255) 256 =0 (n = 0) 0 0 1 1 0 0 1 1 Not used (returns "0" when read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Fig. 49 Structure of AD/DA control register 10-bit reading (Read address 003816 before 003516) b7 A-D conversion register 2 0 (AD2: address 003816) A-D conversion register 1 (AD1: address 003516) b0 b9 b8 b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : Bits 2 to 6 of address 003816 become "0" at reading. 8-bit reading (Read only address 003516) b7 b0 A-D conversion register 1 b9 b8 b7 b6 b5 b4 b3 b2 (AD1: address 003516) Fig. 50 Structure of 10-bit A-D mode reading Rev.2.00 2003.05.28 page 56 of 81 3803 Group (Spec.H) Data bus AD/DA control register (Address 003416) b7 b0 4 A-D control circuit Comparator Channel selector P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 2003.05.28 10 Resistor ladder VREF AVSS Fig. 51 Block diagram of A-D converter Rev.2.00 A-D conversion register 2 A-D conversion register 1 page 57 of 81 AD converter interrupt request (Address 003816) (Address 003516) 3803 Group (Spec.H) D-A CONVERTER The 3803 group (Spec. H) has two internal D-A converters (DA1 and DA2) with 8-bit resolution. The D-A conversion is performed by setting the value in each D-A conversion register. The result of D-A conversion is output from the DA1 or DA2 pin by setting the DA output enable bit to "1". When using the D-A converter, the corresponding port direction register bit (P30/DA1 or P31/DA2) must be set to "0" (input status). The output analog voltage V is determined by the value n (decimal notation) in the D-A conversion register as follows: Data bus D-A1 conversion register (8) V = VREF n/256 (n = 0 to 255) Where VREF is the reference voltage. DA1 output enable bit R-2R resistor ladder P30/DA1 D-A2 conversion register (8) At reset, the D-A conversion registers are cleared to "0016", and the DA output enable bits are cleared to "0", and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. DA2 output enable bit R-2R resistor ladder P31/DA2 Fig. 52 Block diagram of D-A converter "0" DA1 output enable bit R R R R R R R 2R P30/DA1 "1" 2R 2R MSB D-A1 conversion register "0" "1" AVSS Fig. 53 Equivalent connection circuit of D-A converter (DA1) 2003.05.28 2R 2R 2R 2R 2R LSB VREF Rev.2.00 2R page 58 of 81 3803 Group (Spec.H) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Watchdog Timer Initial Value Watchdog timer L is set to "FF16" and watchdog timer H is set to "FF16" by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. Watchdog Timer Operations The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once. XCIN "10" Main clock division ratio selection bits (Note) XIN "FF16" is set when watchdog timer control register is written to. When bit 6 of the watchdog timer control register is kept at "0", the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note). The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP instruction is disabled by writing "1" to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a "1" is written to this bit, it cannot be programmed to "0" again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is "0": when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is "1": when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 s Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not underflow during this period. Data bus "FF16" is set when watchdog timer control register is written to. "0" Watchdog timer L (8) 1/16 "1" "00" "01" Watchdog timer H (8) Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit RESET Internal reset Reset release time waiting Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 54 Block diagram of Watchdog timer b0 b7 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 55 Structure of Watchdog timer control register Rev.2.00 2003.05.28 page 59 of 81 3803 Group (Spec.H) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 16 cycles or more of XIN. Then the RESET pin is returned to an "H" level (the power source voltage should be between 1.8 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.36 V for VCC of 1.8 V. Poweron RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.2VCC Note : Reset release voltage ; Vcc=2.7 V RESET VCC Power source voltage detection circuit Fig. 56 Reset circuit example XIN RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. ? Data ? ? ? ADL ADH SYNC XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 57 Reset sequence Rev.2.00 2003.05.28 page 60 of 81 3803 Group (Spec.H) Address Register contents Address Register contents (1) Port P0 (P0) 000016 0016 (34) Timer Z (low-order) (TZL) 002816 FF16 (2) Port P0 direction register (P0D) 000116 0016 (35) Timer Z (high-order) (TZH) 002916 FF16 (3) Port P1 (P1) 000216 0016 (36) Timer Z mode register (TZM) 002A16 0016 (4) Port P1 direction register (P1D) 000316 0016 (37) PWM control register (PWMCON) 002B16 0016 (5) Port P2 (P2) 000416 0016 (38) PWM prescaler (PREPWM) 002C16 X X X X X X X X (6) Port P2 direction register (P2D) 000516 0016 (39) PWM register (PWM) 002D16 X X X X X X X X (7) Port P3 (P3) 000616 0016 (40) Baud rate generator 3 (BRG3) 002F16 X X X X X X X X (8) Port P3 direction register (P3D) 000716 0016 (41) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (9) Port P4 (P4) 000816 0016 (42) Serial I/O3 status register (SIO3STS) 003116 1 0 0 0 0 0 0 0 (10) Port P4 direction register (P4D) 000916 0016 (43) Serial I/O3 control register (SIO3CON) 003216 (11) Port P5 (P5) 000A16 0016 (44) UART3 control register (UART3CON) 003316 1 1 1 0 0 0 0 0 (12) Port P5 direction register (P5D) 000B16 0016 (45) AD/DA control register (ADCON) 003416 0 0 0 0 1 0 0 0 (13) Port P6 (P6) 000C16 0016 (46) A-D conversion register 1 (AD1) 003516 X X X X X X X X (14) Port P6 direction register (P6D) 000D16 0016 (47) D-A1 conversion register (DA1) 003616 0016 (15) Timer 12, X count source selection register (T12XCSS) 000E16 0 0 1 1 0 0 1 1 (48) D-A2 conversion register (DA2) 003716 0016 (16) Timer Y, Z count source selection register (TYZCSS) 000F16 0 0 1 1 0 0 1 1 (49) A-D conversion register 2 (AD2) 003816 0 0 0 0 0 0 X X (50) Interrupt source selection register (INTSEL) 003916 (51) Interrupt edge selection register (INTEDGE) 003A16 0016 (52) CPU mode register (CPUM) 003B16 0 1 0 0 1 0 0 0 (53) Interrupt request register 1 (IREQ1) 003C16 0016 0016 (17) MISRG 001016 (18) Transmit/Receive buffer register 1 (TB1/RB1) 001816 X X X X X X X X (19) Serial I/O1 status register (SIO1STS) 0016 0016 001916 1 0 0 0 0 0 0 0 (20) Serial I/O1 control register (SIO1CON) 001A16 0016 (21) UART1 control register (UART1CON) 001B16 1 1 1 0 0 0 0 0 (54) Interrupt request register 2 (IREQ2) 003D16 0016 (22) Baud rate generator 1 (BRG1) 001C16 X X X X X X X X (55) Interrupt control register 1 (ICON1) 003E16 0016 (23) Serial I/O2 control register (SIO2CON) 001D16 (56) Interrupt control register 2 (ICON2) 003F16 0016 (24) Watchdog timer control register (WDTCON) 001E16 0 0 1 1 1 1 1 1 (57) Port P0 pull-up control register (PULL0) 0FF016 0016 (25) Serial I/O2 register (SIO2) 001F16 X X X X X X X X (58) Port P1 pull-up control register (PULL1) 0FF116 0016 (26) Prescaler 12 (PRE12) 002016 FF16 (59) Port P2 pull-up control register (PULL2) 0FF216 0016 (27) Timer 1 (T1) 002116 0116 (60) Port P3 pull-up control register (PULL3) 0FF316 0016 (28) Timer 2 (T2) 002216 FF16 (61) Port P4 pull-up control register (PULL4) 0FF416 0016 (29) Timer XY mode register (TM) 002316 0016 (62) Port P5 pull-up control register (PULL5) 0FF516 0016 (30) Prescaler X (PREX) 002416 FF16 (63) Port P6 pull-up control register (PULL6) 0FF616 0016 (31) Timer X (TX) 002516 FF16 (64) Processor status register (PS) (32) Prescaler Y (PREY) 002616 FF16 (65) Program counter (PCH) FFFD16 contents (33) Timer Y (TY) 002716 FF16 (PCL) FFFC16 contents 0016 Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 58 Internal status at reset Rev.2.00 2003.05.28 page 61 of 81 X X X X X 1 XX 3803 Group (Spec.H) CLOCK GENERATING CIRCUIT The 3803 group (Spec. H) has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Frequency Control (1) Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock is half the frequency of XIN. (3) Low-speed mode Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit is "0," the prescaler 12 is set to "FF16" and timer 1 is set to "0116." When the oscillation stabilizing time set after STP instruction released bit is "1," set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Set the timer 1 interrupt enable bit to disabled ("0") before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 1 underflows. The internal clock is supplied for the first time, when timer 1 underflows. Therefore make sure not to set the timer 1 interrupt request bit to "1" before the STP instruction stops the oscillator. When the oscillator is restarted by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not be generated. The internal clock is half the frequency of XCIN. (2) Wait mode (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Note *If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). *When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded. Rev.2.00 2003.05.28 page 62 of 81 3803 Group (Spec.H) XCIN XCOUT Rf XIN XOUT Rd CCIN CCOUT CIN COUT Fig. 59 Ceramic resonator circuit XCIN XCOUT XIN Open Open External oscillation circuit External oscillation circuit VCC VSS VCC VSS Fig. 60 External clock input circuit Rev.2.00 XOUT 2003.05.28 page 63 of 81 3803 Group (Spec.H) XCOUT XCIN "0" "1" Port XC switch bit XOUT XIN Main clock division ratio selection bits (Note 1) Low-speed mode 1/2 Divider Prescaler 12 1/4 High-speed or middle-speed mode (Note 3) Timer 1 Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode Timing (internal clock) High-speed or low-speed mode Main clock stop bit Q S R S Q STP instruction WIT instruction R Reset Q S R STP instruction Reset Interrupt disable flag l Interrupt request Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to "1". 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG is "0", timer 1 is set "0116" and prescaler 12 is set "FF16" automatically. When bit 0 of MISRG is "1", set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. Fig. 61 System clock generating circuit block diagram Rev.2.00 2003.05.28 page 64 of 81 3803 Group (Spec.H) Reset C "0 M4 CM " "1 6 " 1" " "0 " " "0 CM " 0" "1 M6 " C " "1 4 CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) CM6 "1""0" C "0 M7 CM " "1 6 "1 " " "0 " C M4 "1""0" C M4 "1""0" CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) Middle-speed mode (f()=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) High-speed mode (f()=4 MHz) C M6 "1""0" High-speed mode (f()=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) C M7 "1""0" Middle-speed mode (f()=1 MHz) Low-speed mode (f()=16 kHz) C M5 "1""0" CM7=1 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) Low-speed mode (f()=16 kHz) CM7=1 CM6=0 CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 ( High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal clock. Fig. 62 State transitions of system clock Rev.2.00 2003.05.28 page 65 of 81 3803 Group (Spec.H) NOTES ON USAGE Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (V CC pin) and analog power source input pin (AV SS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1 F is recommended. Rev.2.00 2003.05.28 page 66 of 81 3803 Group (Spec.H) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 9 Absolute maximum ratings Symbol Parameter VCC Power source voltages VI Input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, VREF VI Input voltage P32, P33 ____________ VI Input voltage RESET, XIN VI Input voltage CNVSS VO Output voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, XOUT VO Output voltage P32, P33 Pd Power dissipation Topr Operating temperature Tstg Storage temperature Note: In flat package, this value is 300 mW. Rev.2.00 2003.05.28 page 67 of 81 Conditions All voltages are based on Vss. Output transistors are cut off. Ta = 25C Ratings -0.3 to 6.5 -0.3 to VCC +0.3 Unit V V -0.3 to 5.8 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 V V V V -0.3 to 5.8 1000 (Note) -20 to 85 -65 to 125 V mW C C 3803 Group (Spec.H) Recommended operating conditions Table 10 Recommended operating conditions (VCC = 1.8 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter VCC Power source voltage (Note 1) VSS VIH Power source voltage "H" input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 "H" input voltage P32, P33 "H" input voltage ____________ RESET, XIN, XCIN, CNVSS "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37,P40-P47, P50-P57, P60-P67 "L" input voltage ____________ RESET, CNVSS VIH VIH VIL VIL VIL "L" input voltage XIN, XCIN Conditions When start oscillating (Note 2) High-speed mode f(XIN) 2.1 MHz f() = f(XIN)/2 f(XIN) 4.2 MHz f(XIN) 8.4 MHz f(XIN) 12.5 MHz f(XIN) 16.8 MHz f(XIN) 6.3 MHz Middle-speed mode f(XIN) 8.4 MHz f() = f(XIN)/8 f(XIN) 12.5 MHz f(XIN) 16.8 MHz Min. 2.2 2.0 2.2 2.7 4.0 4.5 1.8 2.2 2.7 4.5 Limits Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit 1.8 VCC < 2.7 V 0.85VCC VCC V V V V V V V V V V V V 2.7 VCC 5.5 V 0.8VCC VCC V VCC < 2.7 V VCC 5.5 V VCC < 2.7 V VCC 5.5 V VCC < 2.7 V 0.85VCC 0.8VCC 0.85VCC 0.8VCC 0 5.5 5.5 VCC VCC 0.16VCC V V V V V 2.7 VCC 5.5 V 0 0.2VCC V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC 5.5 V 0 0 0 0.16VCC 0.2VCC 0.16VCC V V V 1.8 2.7 1.8 2.7 1.8 Notes 1: When using A-D converter, see A-D converter recommended operating conditions. 2: The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. Rev.2.00 2003.05.28 page 68 of 81 3803 Group (Spec.H) Table 11 Recommended operating conditions (VCC = 1.8 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol f(XIN) Parameter Main clock input oscillation frequency (Note 1) Conditions High-speed mode f() = f(XIN)/2 Limits Min. Typ. 2.0 VCC < 2.2 V 2.2 VCC < 2.7 V 2.7 VCC < 4.0 V 4.0 VCC < 4.5 V Middle-speed mode f() = f(XIN)/8 4.5 VCC 5.5 V 1.8 VCC < 2.2 V 2.2 VCC < 2.7 V 2.7 VCC < 4.5 V 4.5 VCC 5.5 V f(XCIN) Sub-clock input oscillation frequency (Notes 1, 2) 32.768 Max. (20VCC-36)1.05 2 (24VCC-40.8)1.05 3 (9VCC-0.3)1.05 3 (24VCC-60)1.05 3 16.8 (15VCC-9)1.05 3 (24VCC-28.8)1.05 3 (15VCC+39)1.1 7 16.8 50 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz Notes 1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.2.00 2003.05.28 page 69 of 81 3803 Group (Spec.H) Table 12 Recommended operating conditions (VCC = 1.8 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) IOH(peak) "H" total peak output current "H" total peak output current "L" total peak output current "L" total peak output current "L" total peak output current "H" total average output current "H" total average output current "L" total average output current "L" total average output current "L" total average output current "H" peak output current IOL(peak) "L" peak output current IOL(peak) IOH(avg) "L" peak output current "H" average output current IOL(avg) "L" average output current IOL(avg) "L" average output current P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 (Note 1) P40-P47, P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P30-P37 (Note 1) P20-P27 (Note 1) P40-P47,P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 (Note 1) P40-P47,P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P30-P37 (Note 1) P20-P27 (Note 1) P40-P47,P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 (Note 2) P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 (Note 2) P20-P27 (Note 2) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 (Note 3) P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 (Note 3) P20-P27 (Note 3) Min. Limits Typ. Max. -80 -80 80 80 80 -40 -40 40 40 40 -10 Unit mA mA mA mA mA mA mA mA mA mA mA 10 mA 20 -5 mA mA 5 mA 10 mA Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. Rev.2.00 2003.05.28 page 70 of 81 3803 Group (Spec.H) Electrical characteristics Table 13 Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol VOH VOL VT+-VT- VT+-VT- VT+-VT- IIH IIH IIH IIL IIL IIL IIL VRAM Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 Hysteresis CNTR0, CNTR1, CNTR2, INT0-INT4 Hysteresis RxD1, SCLK1, SIN2, SCLK2, RxD3, SCLK3 ____________ Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 ____________ "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 ____________ "L" input current RESET,CNVSS "L" input current XIN "L" input current (at Pull-up) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 RAM hold voltage Test conditions IOH = -10 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 1.8 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V Limits Min. Typ. Max. VCC-2.0 V VCC-1.0 V 2.0 V 1.0 V 0.4 V 0.5 V 0.5 VI = VCC (Pin floating. Pull-up transistors "off") 5.0 VI = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors "off") VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped Unit 5.0 4.0 -5.0 V A A A A -80 -4.0 -210 -420 A A A -30 -70 -140 A VCC V -5.0 1.8 Note 1: P35 is measured when the P35/TxD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is "0". P45 is measured when the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". Rev.2.00 2003.05.28 page 71 of 81 3803 Group (Spec.H) Table 14 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, Ta = -20 to 85 C, f(XCIN)=32.768kHZ (Stoped in middle-speed mode), Output transistors "off", AD converter not operated) Limits Symbol ICC Parameter Power source current Test conditions High-speed mode VCC = 5V VCC = 3V Middle-speed mode VCC = 5V VCC = 3V Low-speed mode VCC = 5V VCC = 3V VCC = 2V In STP state (All oscillation stopped) Increment when A-D conversion is executed Rev.2.00 2003.05.28 page 72 of 81 f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 2.1 MHz f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 6.3 MHz f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state Ta = 25 C Ta = 85 C f(XIN) = 16.8 MHz, VCC = 5V In Middle-, high-speed mode Min. Typ. Max. 8.0 6.5 5.0 2.5 2.0 1.9 1.0 0.6 4.0 3.0 2.5 1.8 1.5 1.2 1.0 55 40 15 8 6 3 0.1 15.0 12.0 9.0 5.0 3.6 3.8 2.0 1.2 7.0 6.0 5.0 3.3 3.0 2.4 2.0 200 70 40 15 15 6 1.0 10 500 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A 3803 Group (Spec.H) A-D converter characteristics Table 15 A-D converter recommended operating conditions (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V,Ta = -20 to 85 C, unless otherwise noted) Symbol Power source voltage (When A-D converter is used) Analog reference voltage Analog power source voltage Analog input voltage Main clock oscillation frequency (When A-D converter is used) VCC VREF AVSS VIA f(XIN) Limits Conditions Parameter Min. 8-bit A-D mode (Note 1) 10-bit A-D mode (Note 2) Typ. 5.0 5.0 2.0 2.2 2.0 Max. Unit 5.5 5.5 VCC V 0 High-speed mode f() = f(XIN)/2 Middle-speed mode f() = f(XIN)/8 2.0 VCC < 2.2 V 0 0.5 2.2 VCC < 2.7 V 0.5 2.7 VCC < 4.0 V 0.5 4.0 VCC < 4.5 V 0.5 4.5 VCC 5.5 V 2.0 VCC < 2.2 V 0.5 2.0 2.2 VCC < 2.7 V 2.0 2.7 VCC < 4.5 V 2.0 4.5 VCC 5.5 V 2.0 VCC (20VCC-36)1.05 2 (24VCC-40.8)1.05 3 (9VCC-0.3)1.05 3 (24VCC-60)1.05 3 16.8 (15VCC-9)1.05 3 (24VCC-28.8)1.05 3 (15VCC+39)1.1 7 16.8 V V V MHZ Note 1: 8-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is "1". 2: 10-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is "0". Table 16 A-D converter characteristics (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter - Resolution - Absolute accuracy (excluding quantization error) Test conditions 8-bit A-D mode (Note 1) 10-bit A-D mode (Note 2) 8-bit A-D mode (Note 1) 10-bit A-D mode (Note 2) tCONV Conversion time Min. Limits Typ. 2.0 VCC < 2.2 V 2.2 VCC 5.5 V 2.2 VCC < 2.7 V 2.7 VCC 5.5 V 8-bit A-D mode (Note 1) 10-bit A-D mode (Note 2) RLADDER Ladder resistor IVREF Reference power at A-D converter operated VREF = 5.0 V source input current at A-D converter operated VREF = 5.0 V II(AD) A-D port inout current 12 50 35 150 Max. 8 10 3 2 5 4 50 61 100 200 5 5 Unit bit LSB 2tc(XIN) k A A A Note 1: 8-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is "1". 2: 10-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is "0". D-A converter characteristics Table 17 D-A converter characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol - - tsu RO IVREF Parameter Resolution Absolute accuracy Test conditions Limits Min. 4.0 VCC 5.5 V 2.7 VCC < 4.0 V Setting time Output resistor Reference power source input current (Note 1) 2 Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016". Rev.2.00 2003.05.28 Typ. page 73 of 81 3.5 Max. 8 1.0 2.5 3 5 3.2 Unit bit % % s k mA 3803 Group (Spec.H) Timing requirements and switching characteristics Table 18 Timing requirements (1) (In high-speed mode) (VCC = 2.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) Reset input "L" pulse width Main clock XIN input cycle time tWH(XIN) Main clock XIN input "H" pulse width tWL(XIN) Main clock XIN input "L" pulse width tC(XCIN) tWH(XCIN) tWL(XCIN) tC(CNTR) Sub-clock XCIN input cycle time Sub-clock XCIN input "H" pulse width Sub-clock XCIN input "L" pulse width CNTR0-CNTR2 input cycle time tWH(CNTR) CNTR0-CNTR2 input "H" pulse width tWL(CNTR) CNTR0-CNTR2 input "L" pulse width tWH(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "H" pulse width tWL(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "L" pulse width Rev.2.00 Limits Parameter 2003.05.28 page 74 of 81 Min. 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 16 59.5 10000/(86VCC-219) 26103/(82VCC-3) 10000/(84VCC-143) 10000/(105VCC-189) 25 4000/(86VCC-219) 10000/(82VCC-3) 4000/(84VCC-143) 4000/(105VCC-189) 25 4000/(86VCC-219) 10000/(82VCC-3) 4000/(84VCC-143) 4000/(105VCC-189) 20 5 5 120 160 250 500 1000 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 Typ. Max. Unit XIN cycle ns ns ns s s s ns ns ns ns ns 3803 Group (Spec.H) Table 19 Timing requirements (2) (In high-speed mode) (VCC = 2.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter tC(SCLK1), tC(SCLK3) Serial I/O1, serial I/O3 clock input cycle time (Note) tWH(SCLK1), tWH(SCLK3) Serial I/O1, serial I/O3 clock input "H" pulse width (Note) tWL(SCLK1), tWL(SCLK3) Serial I/O1, serial I/O3 clock input "L" pulse width (Note) tsu(RxD1-SCLK1), tsu(RxD3-SCLK3) Serial I/O1, serial I/O3 clock input setup time th(SCLK1-RxD1), th(SCLK3-RxD3) Serial I/O1, serial I/O3 clock input hold time tC(SCLK2) Serial I/O2 clock input cycle time tWH(SCLK2) Serial I/O2 clock input "H" pulse width tWL(SCLK2) Serial I/O2 clock input "L" pulse width tsu(SIN2-SCLK2) Serial I/O2 clock input setup time th(SCLK2-SIN2) Serial I/O2 clock input hold time 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V 4.5VCC5.5 V 4.0VCC<4.5 V 2.7VCC<4.0 V 2.2VCC<2.7 V 2.0VCC<2.2 V Note : When bit 6 of address 001A16 and bit 6 of address 003216 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are "0" (UART). Rev.2.00 2003.05.28 page 75 of 81 Min. 250 320 500 1000 2000 120 150 240 480 950 120 150 240 480 950 70 90 100 200 400 32 40 50 100 200 500 650 1000 2000 4000 200 260 400 950 2000 200 260 400 950 2000 100 130 200 400 800 100 130 150 300 600 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns 3803 Group (Spec.H) Table 20 Timing requirements (3) (In middle-speed mode) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) Reset input "L" pulse width Main clock XIN input cycle time tWH(XIN) Main clock XIN input "H" pulse width tWL(XIN) Main clock XIN input "L" pulse width tC(XCIN) tWH(XCIN) tWL(XCIN) tC(CNTR) Sub-clock XCIN input cycle time tWH(CNTR) CNTR0-CNTR2 input "H" pulse width tWL(CNTR) CNTR0-CNTR2 input "L" pulse width tWH(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "H" pulse width tWL(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input "L" pulse width Rev.2.00 Limits Parameter Sub-clock XCIN input "H" pulse width Sub-clock XCIN input "L" pulse width CNTR0-CNTR2 input cycle time 2003.05.28 page 76 of 81 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V Min. 16 59.5 10000/(24VCC+61) 10000/(82VCC-96) 10000/(52VCC-31) 25 4000/(24VCC+61) 4000/(82VCC-96) 4000/(52VCC-31) 25 4000/(24VCC+61) 4000/(82VCC-96) 4000/(52VCC-31) 20 5 5 120 160 250 320 48 64 115 150 48 64 115 150 48 64 115 150 48 64 115 150 Typ. Max. Unit XIN cycle ns ns ns s s s ns ns ns ns ns 3803 Group (Spec.H) Table 21 Timing requirements (4) (In middle-speed mode) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter tC(SCLK1), tC(SCLK3) Serial I/O1, serial I/O3 clock input cycle time (Note) tWH(SCLK1), tWH(SCLK3) Serial I/O1, serial I/O3 clock input "H" pulse width (Note) tWL(SCLK1), tWL(SCLK3) Serial I/O1, serial I/O3 clock input "L" pulse width (Note) tsu(RxD1-SCLK1), tsu(RxD3-SCLK3) Serial I/O1, serial I/O3 clock input setup time th(SCLK1-RxD1), th(SCLK3-RxD3) Serial I/O1, serial I/O3 clock input hold time tC(SCLK2) Serial I/O2 clock input cycle time tWH(SCLK2) Serial I/O2 clock input "H" pulse width tWL(SCLK2) Serial I/O2 clock input "L" pulse width tsu(SIN2-SCLK2) Serial I/O2 clock input setup time th(SCLK2-SIN2) Serial I/O2 clock input hold time 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V 4.5VCC5.5 V 2.7VCC<4.5 V 2.2VCC<2.7 V 1.8VCC<2.2 V Note : When bit 6 of address 001A16 and bit 6 of address 003216 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are "0" (UART). Rev.2.00 2003.05.28 page 77 of 81 Min. 250 320 500 650 120 150 240 310 120 150 240 310 70 90 100 130 32 40 50 65 500 650 1000 1300 200 260 400 520 200 260 400 520 100 130 200 260 100 130 150 200 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns 3803 Group (Spec.H) Timing diagram in single-chip mode tC(CNTR) tWL(CNTR) tWH(CNTR) CNTR0, CNTR1, CNTR2 INT1, INT2, INT3 INT00, INT40 INT01, INT41 0.8 VCC 0.2 VCC tWL(INT) tWH(INT) 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) XIN 0.8VCC 0.2VCC tC(XCIN) tWL(XCIN) tWH(XCIN) XCIN 0.8VCC 0.2VCC tC(SCLK1), tC(SCLK2), tC(SCLK3) tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) SCLK1 SCLK2 SCLK3 RXD1 RXD3 SIN2 TXD1 TXD3 SOUT2 Fig. 63 Timing diagram (in single-chip mode) Rev.2.00 2003.05.28 page 78 of 81 tWH(SCLK1), tWH(SCLK2), tWH(SCLK3) 0.8VCC 0.2VCC tsu(RxD1-SCLK1), tsu(SIN2-SCLK2), tsu(RxD3-SCLK3) 0.8VCC 0.2VCC th(SCLK1-RxD1), th(SCLK2-SIN2), th(SCLK3-RxD3) 3803 Group (Spec.H) PACKAGE OUTLINE 64P6N-A Plastic 64pin 1414mm body QFP EIAJ Package Code QFP64-P-1414-0.80 Lead Material Alloy 42 Weight(g) 1.11 MD e JEDEC Code - HD ME D b2 49 64 1 48 I2 HE E Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y 33 16 A 32 L1 c A2 17 F e A1 b y b2 I2 MD ME L Detail F 64P4B Dimension in Millimeters Max Nom Min 3.05 - - 0.2 0 0.1 - 2.8 - 0.45 0.35 0.3 0.2 0.15 0.13 14.2 14.0 13.8 14.2 14.0 13.8 0.8 - - 17.1 16.8 16.5 17.1 16.8 16.5 0.8 0.6 0.4 1.4 - - 0.1 - - 10 - 0 - 0.5 - - - 1.3 - 14.6 - - 14.6 - Plastic 64pin 750mil SDIP EIAJ Package Code SDIP64-P-750-1.78 Lead Material Alloy 42 Weight(g) 7.9 33 1 32 E 64 e1 c JEDEC Code - Symbol A1 L A A2 D e SEATING PLANE Rev.2.00 2003.05.28 page 79 of 81 b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Max Nom Min 5.08 - - - - 0.38 - 3.8 - 0.6 0.5 0.4 1.3 1.0 0.9 1.05 0.75 0.65 0.32 0.25 0.2 56.6 56.4 56.2 17.15 17.0 16.85 - 1.778 - - 19.05 - - - 2.8 15 - 0 3803 Group (Spec.H) 64P6Q-A MMP Plastic 64pin 1010mm body LQFP Weight(g) - Lead Material Cu Alloy MD ME JEDEC Code - e EIAJ Package Code LQFP64-P-1010-0.50 b2 HD D 64 49 1 I2 Recommended Mount Pad 48 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 33 16 17 32 A F e x L M Detail F x y c A1 y b A3 A3 A2 L1 b2 I2 MD ME Lp MMP 64P6U-A EIAJ Package Code LQFP64-P-1414-0.8 Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 9.9 10.0 10.1 9.9 10.0 10.1 0.5 - - 11.8 12.0 12.2 11.8 12.0 12.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 - - 0.1 - 0 10 - - 0.225 1.0 - - 10.4 - - 10.4 - - Plastic 64pin 1414mm body LQFP Weight(g) Lead Material Cu Alloy MD e JEDEC Code - D 64 ME b2 HD 49 l2 1 48 Recommended Mount Pad 16 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 33 17 A 32 L1 F A3 A2 e A3 x M L c b A1 y x y Lp Detail F Rev.2.00 2003.05.28 page 80 of 81 b2 I2 MD ME Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.32 0.37 0.45 0.105 0.125 0.175 13.9 14.1 14.0 13.9 14.1 14.0 0.8 - - 16.0 15.8 16.2 15.8 16.2 16.0 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.2 0.1 - - 0 8 - 0.225 - - - - 0.95 - 14.4 - 14.4 - - 3803 Group (Spec.H) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Renesas Technology Corporation, All rights reserved. Printed in Japan. Rev.2.00 2003.05.28 page 81 of 81 3803 Group (Spec.H) Data Sheet REVISION HISTORY Rev. Date Description Summary Page 1.00 Sep. 3, 2001 - 2.00 May. 28, 2003 1,2,6,7 5 7 23 64 First edition issued *Delete the following :"*:KP package is under development." *Table 4 pin description VCC,VSS Apply voltage of 2.7-5.5V 1.8V-5.5V *Fig.5 Memory expansion plan As of Dec. 2002 As of Mar. 2003 *Notes (address 3A16) (address 003A16), (address 2316) (address 002316), (address 2A16) (address 002A16), (address 3916) (address 003916) *Fig.61 System clock generating circuit block diagram Divider Divider Prescaler 12 Main clock division ratio selection bits (Note 1) FF16 (Note 3) 0116 Middle-speed mode R 73 75 75,77 76,78 79 Main clock division ratio selection bits (Note 1) Middle-speed mode (Note 3) STP instruction Timer 1 Reset or STP instruction (Note 2) Timing (internal clock) High-speed or low-speed mode Reset Q S Q S 69 Reset or STP instruction (Note 2) Timing (internal clock) High-speed or low-speed mode 68 Prescaler 12 Timer 1 R STP instruction *Table 10 Recommended operating conditions Add : VIL "L" input voltage XIN, XCIN 1.8VCC5.5V Min. 0 *Table 11 Recommended operating conditions f(XIN) High-speed mode f()=f(XIN)/2 2.2VCC4.0V 2.7VCC4.0V *Table 16 A-D converter characteristics VCC 8bit A-D mode, 10bit A-D mode Max. 5.0 5.5 *Table 17 D-A converter characteristics VCC = 4.0 to 5.5V 4.0VCC5.5V, VCC = 2.7 to 4.0V 2.7VCC<4.0V *Table 16 A-D converter characteristics, Table 17 D-A converter characteristics Resolution Unit Bits bit *Table 18 Timing requirements (1) (In high-speed mode) tC(XIN) Main clock XIN input cycle time 2.7VCC<4.0 Min. 2.6103/(82VCC-3) 26103/(82VCC-3) *Table 18 Timing requirements (1) (In high-speed mode), Table 20 Timing requirements (3) (In middle-speed mode) tWH(XCIN) Sub-clock input "H" pulse width Sub-clock XCIN input "H" pulse width tWL(XCIN) Sub-clock input "L" pulse width Sub-clock XCIN input "L" pulse width *Table 19 Timing requirements (2) (In high-speed mode), Table 20 Timing requirements (4) (In middle-speed mode) tCL(SCLK2) tWL(SCLK2) *Fig.63 Timing diagram (in single-chip mode) Delete the following underline parts : SCLK1 SCLK2 SCLK3 tf , tr TXD1 TXD3 SOUT2 td(SCLK1-TXD1), td(SCLK2-SOUT2), td(SCLK3-TXD3) tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3) (1/1)