TPS780DDC
TSOT23-5
(TOPVIEW)
OUT
V /FB
SET
IN
GND
EN
1
2
3
5
4
TPS780DRV
2mmx2mmSON-6
(TOPVIEW)
IN
GND
EN
6
5
4
OUT
N/C
V FB/
SET
1
2
3
Thermal
Pad
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
150mA, Low-Dropout Regulator, Ultralow-Power, I
Q
500nA
with Pin-Selectable, Dual-Level Output Voltage
Check for Samples: TPS780 Series
The VSET pin allows the end user to switch between
1FEATURES two voltage levels on-the-fly through a
2• Low IQ: 500nA microprocessor-compatible input. This LDO is
• 150mA, Low-Dropout Regulator with Pin- designed specifically for battery-powered applications
Selectable Dual Voltage Level Output where dual-level voltages are needed. With ultralow
IQ(500nA), microprocessors, memory cards, and
• Low Dropout: 200mV at 150mA smoke detectors are ideal applications for this device.
• 3% Accuracy Over Load/Line/Temperature The ultralow-power and selectable dual-level output
• Available in Dual-Level, Fixed Output Voltages voltages allow designers to customize power
from 1.5V to 4.2V Using Innovative Factory consumption for specific applications. Designers can
EPROM Programming now shift to a lower voltage level in a battery-powered
• Available in an Adjustable Version from 1.22V design when the microprocessor is in sleep mode,
to 5.25V or a Dual-Level Output Version further reducing overall system power consumption.
The two voltage levels are preset at the factory
• VSET Pin Toggles Output Voltage Between Two through a unique architecture using an EPROM. The
Factory-Programmed Voltage Levels EPROM technique allows for numerous output
• Stable with a 1.0μF Ceramic Capacitor voltage options between VSET low (1.5V to 4.2V) and
• Thermal Shutdown and Overcurrent Protection VSET high (2.0V to 3.0V) in the fixed output version
only. Consult with your local factory representative for
• CMOS Logic Level-Compatible Enable Pin exact voltage options and ordering information;
• Available in DDC (TSOT23-5) or DRV (2mm × minimum order quantities may apply.
2mm SON-6) Package Options The TPS780 series are designed to be compatible
with the TI MSP430 and other similar products. The
APPLICATIONS enable pin is compatible with standard CMOS logic.
• TI MSP430 Attach Applications This LDO is stable with any output capacitor greater
than 1.0μF. Therefore, implementations of this device
• Power Rails with Programming Mode require minimal board space because of miniaturized
• Dual Voltage Levels for Power-Saving Mode packaging and a potentially small output capacitor.
• Wireless Handsets, Smartphones, PDAs, MP3 The TPS780 series IQ(500nA) also come with
Players, and Other Battery-Operated Handheld thermal shutdown and current limit to protect the
Products device during fault conditions. All packages have an
operating temperature range of TJ= –40°C to
+125°C. For more cost-sensitive applications
DESCRIPTION requiring a dual-level voltage option and only on par
The TPS780 family of low-dropout (LDO) regulators IQ, consider the TPS781 series, with an IQof 1.0μA
offer the benefits of ultralow power (IQ= 500nA), and dynamic voltage scaling.
miniaturized packaging (2×2 SON-6), and selectable
dual-level output voltage levels. An adjustable version
is also available, but does not have the capability to
shift voltage levels.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1) (2)
PRODUCT VOUT
TPS780vvvxxx yyy z VVV is the nominal output voltage for VOUT(HIGH) and corresponds to VSET pin low.
XXX is the nominal output voltage for VOUT(LOW) and corresponds to VSET pin high.
YYY is the package designator.
Zis the tape and reel quantity (R = 3000, T = 250).
Adjustable version(3) (4)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Additional output voltage combinations are available on a quick-turn basis using innovative, factory EPROM programming. Minimum-
order quantities apply; contact your sales representative for details and availability.
(3) To order the adjustable version, use TPS78001YYYZ.
(4) The device is either fixed voltage, dual-level VOUT, or adjustable voltage only. Device design does not permit a fixed and adjustable
output simultaneously.
ABSOLUTE MAXIMUM RATINGS(1)
At TJ= –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
PARAMETER TPS780 Series UNIT
Input voltage range, VIN –0.3 to +6.0 V
Enable and VSET voltage range, VEN and VVSET –0.3 to VIN + 0.3(2) V
Output voltage range, VOUT –0.3 to VIN + 0.3V V
Maximum output current, IOUT Internally limited
Output short-circuit duration Indefinite
Total continuous power dissipation, PDISS See the Dissipation Ratings table
Human body model (HBM) 2 kV
ESD rating Charged device model (CDM) 500 V
Operating junction temperature range, TJ–40 to +125 °C
Storage temperature range, TSTG –55 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) VEN and VVSET absolute maximum rating are VIN + 0.3V or +6.0V, whichever is less.
DISSIPATION RATINGS DERATING FACTOR
BOARD PACKAGE RθJC RθJA ABOVE TA= +25°C TA< +25°C TA= +70°C TA= +85°C
High-K(1) DRV 20°C/W 65°C/W 15.4mW/°C 1540mW 845mW 615mW
High-K(1) DDC 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mW
(1) The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(NOM) + 0.5V or 2.2V, whichever is greater; IOUT =
100μA, VVSET = VEN = VIN, COUT = 1.0μF, fixed or adjustable, unless otherwise noted. Typical values at TJ= +25°C.
TPS780 Series
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.2 5.5 V
Nominal TJ= +25°C, VSET = high/low –2 ±1 +2 %
VOUT (1) DC output accuracy Over VIN, IOUT, VOUT + 0.5V ≤VIN ≤5.5V, –3.0 ±2.0 +3.0 %
temperature 0mA ≤IOUT ≤150mA, VSET = high/low
Internal reference(2)
VFB TJ= +25°C, VIN = 4.0V, IOUT = 75mA 1.216 V
(adjustable version only)
Output voltage range(3) (4)
VOUT_RANGE VIN = 5.5V, IOUT = 100μA(2) VFB 5.25 V
(adjustable version only)
ΔVOUT/ΔVIN Line regulation VOUT(NOM) + 0.5V ≤VIN ≤5.5V, IOUT = 5mA –1 +1 %
ΔVOUT/ΔIOUT Load regulation 0mA ≤IOUT ≤150mA –2 +2 %
VDO Dropout voltage(5) VIN = 95% VOUT(NOM), IOUT = 150mA 250 mV
BW = 100Hz to 100kHz, VIN = 2.2V,
VNOutput noise voltage 86 μVRMS
VOUT = 1.2V, IOUT = 1mA
VSET high (output VOUT(LOW)
VHI 1.2 VIN V
selected), or EN high (enabled)
VSET low (output VOUT(HIGH)
VLO 0 0.4 V
selected), or EN low (disabled)
ICL Output current limit VOUT = 0.90 × VOUT(NOM) 150 230 400 mA
IOUT = 0mA(6) 420 800 nA
IGND Ground pin current IOUT = 150mA 5 μA
VEN ≤0.4V, 2.2V ≤VIN < 5.5V,
ISHDN Shutdown current (IGND) 18 130 nA
TJ= –40°C to +100°C
IVSET VSET pin current VEN = VVSET = 5.5V 70 nA
IEN EN pin current VEN = VVSET = 5.5V 40 nA
FB pin current(7)
IFB VIN = 5.5V, VOUT = 1.2V, IOUT = 100μA 10 nA
(adjustable version only) f = 10Hz 40 dB
VIN = 4.3V,
PSRR Power-supply rejection ratio VOUT = 3.3V, f = 100Hz 20 dB
IOUT = 150mA f = 1kHz 15 dB
VOUT transition time (high-to-low) VOUT_LOW = 2.2V, VOUT(HIGH) = 3.3V,
tTR(H→L) 800 μs
VOUT = 97% × VOUT(HIGH) IOUT = 10mA
VOUT transition time (low-to-high) VOUT_HIGH = 3.3V, VOUT(LOW) = 2.2V,
tTR(L→H) 800 μs
VOUT = 97% × VOUT(LOW) IOUT = 10mA
COUT = 1.0μF, VOUT = 10% VOUT(NOM) to
tSTR Startup time(8) 500 μs
VOUT = 90% VOUT(NOM)
IOUT = 150mA, COUT = 1.0μF, VOUT = 2.8V,
tSHDN Shutdown time(9) VOUT = 90% VOUT(NOM) to VOUT = 10% 500(10) μs
VOUT(NOM)
Shutdown, temperature increasing +160 °C
TSD Thermal shutdown temperature Reset, temperature decreasing +140 °C
TJOperating junction temperature –40 +125 °C
(1) The output voltage for VSET = low/high is programmed at the factory.
(2) Adjustable version only.
(3) No VSET pin on the adjustable version.
(4) No dynamic voltage scaling on the adjustable version.
(5) VDO is not measured for devices with VOUT(NOM) < 2.3V because minimum VIN = 2.2V.
(6) IGND = 800nA (max) up to +100°C.
(7) The TPS78001 FB pin is tied to VOUT. Adjustable version only.
(8) Time from VEN = 1.2V to VOUT = 90% (VOUT(NOM)).
(9) Time from VEN = 0.4V to VOUT = 10% (VOUT(NOM)).
(10) See Shutdown in the Application Information section for more details.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
TPS780DRV
2mmx2mmSON-6
(TOPVIEW)
IN
GND
EN
6
5
4
OUT
N/C
V FB/
SET
1
2
3
Thermal
Pad(1)
TPS780DDC
TSOT23-5
(TOPVIEW)
OUT
V /FB
SET
IN
GND
EN
1
2
3
5
4
Thermal
Shutdown
10kW
Current
Limit
Bandgap
IN
EN
OUT
EPROM
MUX
VSET/FB(1)
LOGIC
Active
Pull-
Down
GND
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
(1) Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions.
PIN CONFIGURATIONS
(2) It is recommended that the SON package thermal pad be connected to ground.
Table 2. TERMINAL FUNCTIONS
TERMINAL
NAME DRV DDC DESCRIPTION
Regulated output voltage pin. A small (1μF) ceramic capacitor is needed from this pin to
OUT 1 5 ground to assure stability. See the Input and Output Capacitor Requirements in the
Application Information section for more details.
N/C 2 — Not connected.
Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions. Driving the select
VSET/FB 3 4 pin (VSET) below 0.4V selects preset output voltage high. Driving the VSET pin over 1.2V
selects preset output voltage low.
Driving the enable pin (EN) over 1.2V turns on the regulator. Driving this pin below 0.4V puts
EN 4 3 the regulator into shutdown mode, reducing operating current to 18nA typical.
GND 5 2 Ground pin.
Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input
IN 6 1 capacitor = 1.0μF. Both input and output capacitor grounds should be tied back to the IC
ground with no significant impedance between them.
Thermal pad Thermal pad — It is recommended that the SON package thermal pad be connected to ground.
4Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
V (%)
OUT
3
2
1
0
-1
-2
-3
TJ=+85°C
T 40- °
J= C
TJ=+25°C
0 25 50 75 100 125 150
I (mA)
OUT
V (%)
OUT
1.5
1.0
0.5
0
-0.5
-1.0
TJ=+125°C
TJ=+25°C
T = 40- °
JC
TJ=+85°C
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
V (%)
OUT
3
2
1
0
-1
-2
-3
TJ=+85°C
T = 40- °
JC
TJ=+25°C
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
V (%)
OUT
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
T =+85°
JC
T = 40- °
JC
T =+25°
JC
2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
V (%)
OUT
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
TJ=+85°C
TJ=+25°C
T = 40- °
JC
TJ=+125°C
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
V (%)
OUT
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
TJ=+125°C
T = 40- °
JC
TJ=+25°C
TJ=+85°C
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
LINE REGULATION LINE REGULATION
IOUT = 5mA, VOUT = 1.22V (typ) IOUT = 5mA, VVSET = 1.2V, VOUT = 2.2V (typ)
TPS78001 TPS780330220
Figure 1. Figure 2.
LINE REGULATION LINE REGULATION
IOUT = 150mA, VVSET = 1.2V, VOUT = 2.2V (typ) IOUT = 5mA, VVSET = 0.4V, VOUT = 3.3V (typ)
TPS780330220 TPS780330220
Figure 3. Figure 4.
LINE REGULATION LOAD REGULATION
IOUT = 150mA, VVSET = 0.4V, VOUT = 3.3V (typ) VOUT = 3.3V
TPS780330220 TPS78001
Figure 5. Figure 6.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
0 25 50 75 100 125 150
I (mA)
OUT
V (V V-
DO IN OUT)(mV)
200
180
160
140
120
100
80
60
40
20
0
TJ=+85°C
T = 40- °
JC
TJ=+125°C
TJ=+25°C
0 25 50 75 100 125 150
I (mA)
OUT
V (V V-
DO IN OUT)(mV)
250
200
150
100
50
0
TJ=+125°C
TJ=+85°C
T = 40- °
JC
TJ=+25°C
0 25 50 75 100 125 150
I (mA)
OUT
V (%)
OUT
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
TJ=+85°C
T = 40- °
JC
TJ=+25°C
0 25 50 75 100 125 150
I (mA)
OUT
V (%)
OUT
3
2
1
0
-1
-2
-3
TJ=+85°C
T = 40- °
JC
TJ=+25°C
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
LOAD REGULATION LOAD REGULATION
VVSET = 1.2V, VIN = 2.7V, VOUT = 2.2V VVSET = 0.4V, VIN = 3.8V, VOUT = 3.3V
TPS780330220 TPS780330220
Figure 7. Figure 8.
DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ) VVSET = 0.4V, VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS78001 TPS780330220
Figure 9. Figure 10.
6Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
-40 -25 -10 1251109580655035205
Temperature( C)°
V (V V-
DO IN OUT)(mV)
250
200
150
100
50
0
150mA
100mA
50mA
10mA
-40 -25 -10 1251109580655035205
Temperature( C)°
V (V V-
DO IN OUT)(mV)
250
200
150
100
50
0
150mA
100mA
50mA
10mA
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs
TEMPERATURE TEMPERATURE
VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ) VVSET = 0.4V, VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS78001 TPS780330220
Figure 11. Figure 12.
GROUND PIN CURRENT GROUND PIN CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 50mA, VOUT = 1.22V IOUT = 150mA, VOUT = 1.22V
TPS78001 TPS78001
Figure 13. Figure 14.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
I ( A)m
GND
12
11
10
9
8
7
6
5
4
3
2
1
0
T =+125 C
J°
T =+85 C
J°
T = 40- °
JC
T =+25 C
J°
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
I (nA)
GND
1000
900
800
700
600
500
400
300
200
100
0
TJ=+125°C
TJ=+85°C
TJ= 40- °C
TJ=+25°C
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
I (nA)
GND
1000
900
800
700
600
500
400
300
200
100
0
T =+125 C°
J
T =+85 C°
J
T = 40- °
JC
T =+25 C°
J
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
GROUND PIN CURRENT GROUND PIN CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 0mA, VVSET = 1.2V, VOUT = 2.2V IOUT = 1mA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220 TPS780330220
Figure 15. Figure 16.
GROUND PIN CURRENT GROUND PIN CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 50mA, VVSET = 1.2V, VOUT = 2.2V IOUT = 150mA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220 TPS780330220
Figure 17. Figure 18.
8Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I ( A)m
GND
6
5
4
3
2
1
0
T =+125 C°
J
T =+85 C°
J
T 40- °
J= C
T =+25 C°
J
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I ( A)m
GND
9
8
7
6
5
4
3
2
1
0
T =+125 C°
J
T =+85 C°
J
TJ=-40°C
T =+25 C°
J
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I (nA)
GND
1000
900
800
700
600
500
400
300
200
100
0
T =+125 C°
J
T =+85 C°
J
TJ= 40- °C
T =+25 C°
J
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I (nA)
GND
1000
900
800
700
600
500
400
300
200
100
0
T°
J=+125 C
T°
J=+85 C
TJ= 40- °C
T°
J=+25 C
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
GROUND PIN CURRENT GROUND PIN CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 0mA, VVSET = 0.4V, VOUT = 3.3V IOUT = 1mA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220 TPS780330220
Figure 19. Figure 20.
GROUND PIN CURRENT GROUND PIN CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 50mA, VVSET = 0.4V, VOUT = 3.3V IOUT = 150mA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220 TPS780330220
Figure 21. Figure 22.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
I (nA)
GND
60
50
40
30
20
10
0
TJ=+85°C
T = 40- °
JC
TJ=+25°C
2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
CurrentLimit(mA)
280
270
260
250
240
230
220
210
200
T =+85 C°
J
T = 40- °
JC
T =+25 C°
J
0 25 50 75 100 125 150
I (mA)
OUT
I ( A)m
GND
10
8
6
4
2
0
T =+125 C°
J
T =+85 C°
J
T = 40- °
JC
T =+25 C°
J
0 25 50 75 100 125 150
I (mA)
OUT
I ( A)m
GND
10
8
6
4
2
0
T =+125 C°
J
T =+85 C°
J
TJ= 40- °C
T =+25 C°
J
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
GROUND PIN CURRENT GROUND PIN CURRENT
vs vs
OUTPUT CURRENT OUTPUT CURRENT
VVSET = 1.2V, VIN = 5.5V, VOUT = 2.2V VVSET = 0.4V, VIN = 5.5V, VOUT = 3.3V
TPS780330220 TPS780330220
Figure 23. Figure 24.
SHUTDOWN CURRENT CURRENT LIMIT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 0mA, VVSET = 0.4V VOUT = 90% VOUT (typ), VOUT = 1.22V (typ)
TPS78001 TPS78001
Figure 25. Figure 26.
10 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
I (nA)
VSET
1.0
0.8
0.6
0.4
0.2
0
TJ=+85°CT = 40- °
JCTJ=+25°C
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
CurrentLimit(mA)
300
290
280
270
260
250
240
230
220
210
200
T =+125 C°
J
T =+85 C°
J
T = 40- °
JC
T =+25 C°
J
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
CurrentLimit(mA)
300
290
280
270
260
250
240
230
220
210
200
TJ=+125°C
TJ=+85°C
T = 40- °
JC
TJ=+25°C
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
CURRENT LIMIT CURRENT LIMIT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
VVSET = 1.2V, VOUT = 95% VOUT (typ), VOUT = 2.2V (typ) VVSET = 0.4V, VOUT = 95% VOUT (typ), VOUT = 3.3V (typ)
TPS780330220 TPS780330220
Figure 27. Figure 28.
FEEDBACK PIN CURRENT VSET PIN CURRENT
vs vs
TEMPERATURE INPUT VOLTAGE
IOUT = 0mA, VOUT = 1.22V IOUT = 100μA, VVSET = 1.2V, VOUT = 2.2V
TPS78001 TPS780330220
Figure 29. Figure 30.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
I (nA)
EN
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T =+85 C°
JTJ= 40- °C
T =+25 C°
J
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I (nA)
EN
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TJ=+85°CT = 40- °
JC
TJ=+25°C
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I (nA)
VSET
2.5
2.0
1.5
1.0
0.5
0
-0.5
TJ=+125°C
TJ=+85°CT = 40- °
JC
TJ=+25°C
2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
V (V)
IN
I (nA)
EN
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T =+85 C°
JT 40°
J=-C
T =+25 C°
J
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
VSET PIN CURRENT ENABLE PIN CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 100μA, VVSET = 0.4V, VOUT = 3.3V IOUT = 1mA, VOUT = 1.22V
TPS780330220 TPS78001
Figure 31. Figure 32.
ENABLE PIN CURRENT ENABLE PIN CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 100μA, VVSET = 1.2V, VOUT = 2.2V IOUT = 100μA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220 TPS780330220
Figure 33. Figure 34.
12 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
-40 -25 -10 1251109580655035205
Temperature( C)°
%V (V)
OUT
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-40 -25 -10 1251109580655035205
Temperature( C)°
%DVOUT (V)
1
0
-1
-2
150mA
0.1mA
5mA
-40 -25 -10 1251109580655035205
Temperature( C)°
V (V)
EN
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
V On
EN
V Off
EN
-40 -25 -10 1251109580655035205
Temperature( C)°
V (V)
EN
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
V On
EN
V Off
EN
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
ENABLE PIN HYSTERESIS ENABLE PIN HYSTERESIS
vs vs
TEMPERATURE TEMPERATURE
IOUT = 1mA, TPS78001 IOUT = 1mA, TPS780330220
Figure 35. Figure 36.
%ΔVOUT %ΔVOUT
vs vs
TEMPERATURE TEMPERATURE
IOUT = 1mA, VIN = 3.8V, VOUT = 3.3V VVSET = 1.2V, VIN = 2.7V, VOUT = 2.2V (typ)
TPS78001 TPS780330220
Figure 37. Figure 38.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
10 10M100 1k 10k 100k 1M
Frequency(Hz)
PSRR(dB)
80
70
60
50
40
30
20
10
0
150mA
50mA
1mA
Voltage(1V/div)
Time(20ms/div)
LoadCurrent
Enable VOUT
VIN V =0.0Vto
IN 5.0V
V =3.3V
OUT
I =150mA
OUT
C =10 Fm
OUT
0V
Current(50mA/div)
-40 -25 -10 1251109580655035205
Temperature( C)°
% V (V)DOUT
3
2
1
0
-1
-2
-3
150mA
0.1mA
5mA
10 100 1k 10k 100k
Frequency(Hz)
OutputSpectralNoiseDensity( V/ )m ÖHz
100
10
1
0.1
0.01
0.001
150mA
109 VmRMS
50mA
109 VmRMS
1mA
108 VmRMS
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
%ΔVOUT OUTPUT SPECTRAL NOISE DENSITY
vs vs
TEMPERATURE FREQUENCY
VVSET = 0.4V, VIN = 3.8V, VOUT = 3.3V (typ) CIN = 1μF, COUT = 2.2μF, VVSET = 1.2V, VIN = 2.7V
TPS780330220 TPS780330220
Figure 39. Figure 40.
RIPPLE REJECTION
vs INPUT VOLTAGE RAMP
FREQUENCY vs
VIN = 2.7V, VOUT = 1.2V, COUT = 2.2μF OUTPUT VOLTAGE
TPS78001 TPS780330220
Figure 41. Figure 42.
14 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Voltage
(100mV/div)
Time (5ms/div)
Load
Current
V = 5.5V
IN
V = 3.3V
OUT
I = 5mA to 15mA
OUT
C = 10 Fm
OUT
VOUT
Enable
VIN
Current
(10mA/div)
0A
Voltage
(100mV/div)
Time (2ms/div)
Load
Current
V = 5.5V
IN
V = 3.3V
OUT
I = 17mA to 60mA
OUT
C = 10 Fm
OUT
VIN
VOUT
Enable
0A
Current
(20mA/div)
1V/div
Time(200 s/div)m
V =4.0Vto4.5V
IN
V =2.2V
OUT
I =150mA
OUT
SlewRate=1V/ sm
VIN
VOUT
1V/div
Time(200 s/div)m
V =4.0Vto4.5V
IN
V =3.3V
OUT
I =150mA
OUT
SlewRate=1V/ sm
VIN
VOUT
Voltage(1V/div)
Time(20ms/div)
V =5.5V
IN
V =3.3V
OUT
I =150mA
OUT
C =10 Fm
OUT
VIN
VOUT LoadCurrent
Enable
0V
Current(50mA/div)
Voltage(1V/div)
Time(1ms/div)
LoadCurrent
V =0.0Vto5.5V
IN
V =2.2V
OUT
I =100mA
OUT
C =10 Fm
OUT
VSET
VIN
VOUT
0A
0V
Current(50mA/div)
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
OUTPUT VOLTAGE INPUT VOLTAGE
vs vs
ENABLE (SLOW RAMP) DELAY TO OUTPUT
TPS780330220 TPS780330220
Figure 43. Figure 44.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
TPS780330220 TPS780330220
Figure 45. Figure 46.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
TPS780330220 TPS780330220
Figure 47. Figure 48.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Voltage(1V/div)
Time(50ms/div)
VSET
V =5.5V
IN
V =3.3V
OUT
I =150mA
OUT
to100mA
C =10 Fm
OUT
VIN
VOUT
LoadCurrent
0A
50mA
100mA
Current(50mA/div)
1V/div
Time(500ms/div)
VIN =5.0V
Enable=VIN
IOUT =150mA
V Transitioningfrom2.2Vto3.3V
OUT
VOUT
VSET
1V/div
Time(500 s/div)m
V =5.0V
IN
I =150mA
OUT
V Transitioningfrom3.3Vto2.2V
OUT
VOUT
VSET
Voltage(1V/div)
Time(1ms/div)
LoadCurrent
V =5.50V
IN
V =3.3V
OUT
I =150mA
OUT
COUT =10mF
VIN VOUT
Enable
0V
Current(50mA/div)
Voltage(1V/div)
Time(1ms/div)
Load
Current
V =5.5V
IN
V =3.3V
OUT
I =150mA
OUT
C =10 Fm
OUT
VIN VOUT
Enable
0V
Current(50mA/div)
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100μA, VEN = VVSET = VIN, COUT = 1μF, and CIN = 1μF, unless otherwise noted.
ENABLE PIN
vs ENABLE PIN
OUTPUT VOLTAGE RESPONSE vs
AND OUTPUT CURRENT OUTPUT VOLTAGE DELAY
TPS780330220 TPS780330220
Figure 49. Figure 50.
VSET PIN TOGGLE VSET PIN TOGGLE
TPS780330220 TPS780330220
Figure 51. Figure 52.
VSET PIN TOGGLE (SLOW RAMP)
TPS780330220
Figure 53.
16 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
TPS78001
GND
EN
IN OUT
VIN VOUT
1 Fm
1 Fm
FB
R1
R2
V =V (1+)´
OUT FB
R
R
1
2
TPS780
GND
EN
VSET
IN OUT
VIN VOUT
1 Fm
1 Fm
4.2Vto5.5V 2.2Vto3.3V
On
Off
V High=V
SET OUT(LOW)
V Low=V
SET OUT(HIGH)
R1 2
= 1 R- ´
V
V
OUT
FB
()
V =V 1+´
OUT FB
R
R
1
2
()
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
APPLICATION INFORMATION
Regulator
APPLICATION EXAMPLES The output voltage of the TPS78001 adjustable
regulator is programmed using an external resistor
The TPS780 series of LDOs typically take less than divider as shown in Figure 55. The output voltage
800μs to transition from a lower voltage of 2.2V to a operating range is 1.2V to 5.1V, and is calculated
higher voltage of 3.3V under an output load of using Equation 1:
150mA; see Figure 51. Additionally, the TPS780
series contain active pull-down circuitry that
automatically pulls charge out of the voltage capacitor (1)
to transition the output voltage from the higher
voltage to the lower voltage, even with no load Where:
connected. Output voltage overshoots and VFB = 1.216V typ (the internal reference voltage)
undershoots are minimal under this load condition. Resistors R1and R2should be chosen for
The TPS780 series typically take less than 800μs to approximately 1.2μA divider current. Lower value
transition from VSET low (3.3V to 2.2V), or VSET high resistors can be used for improved noise
(2.2V to 3.3V); see Figure 51 and Figure 52. Both performance, but the solution consumes more power.
output states of the TPS780 series are factory- Higher resistor values should be avoided because
programmable between 1.5V to 4.2V. Note that leakage current into/out of FB across R1/R2creates
during startup or steady-state conditions, it is an offset voltage that artificially increases/decreases
important that the EN pin and VSET pin voltages never the feedback voltage and thus erroneously
exceed VIN + 0.3V. decreases/increases VOUT.Table 3 lists several
common output voltages and resistor values. The
recommended design procedure is to choose R2=
1MΩto set the divider current at 1.2μA, and then
calculate R1using Equation 2:
(2)
Figure 54. Typical Application Circuit
The TPS780 is also used effectively in dynamic
voltage scaling (DVS) applications. DVS applications
are required to dynamically switch between a high
operational voltage to a low standby voltage in order
to reduce power consumption. Modern multimillion
gate microprocessors fabricated with the latest sub-
micron processes save power by transitioning to a Figure 55. TPS78001 Adjustable LDO Regulator
lower voltage to reduce leakage currents while Programming
maintaining content. This architecture enables the
microprocessor to transition quickly into an
operational state (wake up) without requiring a reload Table 3. Output Voltage Programming Guide
of the states from external memory, or a reboot. OUTPUT VOLTAGE R1R2
Programming the TPS78001 Adjustable LDO 1.8V 0.499MΩ1MΩ
2.8V 1.33MΩ1MΩ
5.0V 3.16MΩ1MΩ
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
TPS780
GND
VIN VOUT
MSP430
VSS
VCC
I/O
V =3.6V
CC
5mA
Active
Mode
700nAI
LPM3/SleepMode
Q
V =2.2V
CC
Current
1 Fm1 Fm
2.2Vto3.6V
VSET
LDO
GND
VIN VOUT
1 Fm1 Fm
MSP430
VSS
VCC
I/O
V =3.0V
CC
5mA
Active
Mode
3.0V
1.6 AI
LPM3/SleepMode
mQ
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
Powering the MSP430 Microcontroller
Several versions of the TPS780 are ideal for
powering the MSP430 microcontroller.Table 4 shows
potential applications of some voltage versions.
Table 4. Typical MSP430 Applications
VOUT(HIGH) VOUT(LOW)
DEVICE (TYP) (TYP) APPLICATION
VOUT, MIN > 1.800V
required by many
MSP430s. Allows
TPS780360200 3.6V 2.0V lowest power
consumption
operation.
VOUT, MIN > 2.200V
required by some
TPS780360220 3.6V 2.2V MSP430s FLASH
operation.
VOUT, MIN > 2.700V
required by some
TPS780360300 3.6V 3.0V MSP430s FLASH
operation. Figure 56. Typical LDO without DVS
VOUT, MIN < 3.600V
required by some
TPS780360220 3.6V 2.2V MSP430s. Allows
highest speed
operation.
The TPS780 family offers many output voltage
versions to allow designers to optimize the supply
voltage for the processing speed required of the
MSP430. This flexible architecture minimizes the
supply current consumed by the particular MSP430
application. The MSP430 total system power can be
reduced by substituting the 500nA IQTPS780 series
LDO in place of an existing ultra-low IQLDO (typical
best case = 1μA). Additionally, DVS allows for
increasing the clock speed in active mode (MSP430
VCC = 3.6V). The 3.6V VCC reduces the MSP430 time
in active mode. In low-power mode, MSP430 system
power can be further reduced by lowering the
MSP430 VCC to 2.2V in sleep mode.
Key features of the TPS780 series are an ultralow
quiescent current (500nA), DVS, and miniaturized
packaging. The TPS780 family are available in SON- Figure 57. TPS780 with Integrated DVS
6 and TSOT-23 packages. Figure 56 shows a typical
MSP430 circuit powered by an LDO without DVS.
Figure 57 is an MSP430 circuit using a TPS780 LDO The other benefit of DVS is that it allows a higher VCC
that incorporates an integrated DVS, thus simplifying voltage on the MSP430, increasing the clock speed
the circuit design. In a circuit without DVS, as and reducing the active mode dwell time.
Figure 56 illustrates, VCC is always at 3.0V. When the
MSP430 goes into sleep mode, VCC remains at 3.0V;
if DVS is applied, VCC could be reduced in sleep
mode. In Figure 57, the TPS780 LDO with integrated
DVS maintains 3.6V VCC until a logic high signal from
the MSP430 forces VOUT to level shift VOUT from 3.6V
down to 2.2V, thus reducing power in sleep mode.
18 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
The total system power savings is outlined in Table 5, capacitor may be necessary if large, fast rise-time
Table 6, and Table 7.InTable 5, the MSP430 power load transients are anticipated, or if the device is not
savings are calculated for various MSP430 devices located near the power source. If source impedance
using a TPS780 series with integrated DVS versus a is not sufficiently low, a 0.1μF input capacitor may be
standard ultralow IQLDO without DVS. In Table 6, the necessary to ensure stability.
TPS780 series quiescent power is calculated for a VIN The TPS780 is designed to be stable with standard
of 4.2V, with the same VIN used for the ultralow IQceramic capacitors with values of 1.0μF or larger at
LDO. Quiescent power dissipation in an LDO is the the output. X5R- and X7R-type capacitors are best
VIN voltage times the ground current, because zero because they have minimal variation in value and
load is applied. After the dissipation power is ESR over temperature. Maximum ESR should be less
calculated for the individual LDOs in Table 6, simple than 1.0Ω. With tolerance and dc bias effects, the
subtraction outputs the LDO power savings using the minimum capacitance required to ensure stability is
TPS780 series. Table 7 calculates the total system 1μF.
power savings using a TPS780 series LDO in place
of an ultralow IQ1.2μA LDO in an MSP430F1121 BOARD LAYOUT RECOMMENDATIONS TO
application. There are many different versions of the IMPROVE PSRR AND NOISE PERFORMANCE
MSP430. Actual power savings will vary depending
on the selected device. To improve ac performance (such as PSRR, output
noise, and transient response), it is recommended
INPUT AND OUTPUT CAPACITOR that the printed circuit board (PCB) be designed with
REQUIREMENTS separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
Although an input capacitor is not required for device. In addition, the ground connection for the
stability, it is good analog design practice to connect output capacitor should connect directly to the GND
a 0.1μF to 1.0μF low equivalent series resistance pin of the device. High ESR capacitors may degrade
(ESR) capacitor across the input supply near the PSRR.
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
Table 5. DVS MSP430 Power Savings with the TPS780 Series on selected MSP430 Devices
LPM3 AT VCC = 3V, LPM3 AT VCC = 3.0V LPM3 AT VCC = LPM3 AT VCC = 2.2V
IQ× IQ2.2V, IQ× IQμW SAVINGS
DEVICE (μA) (μW) (μA) (μW) USING ONLY DVS
MSP430F1121 1.6 4.8 0.7 1.5 3.3
MSP430F149 1.6 4.8 0.9 2.0 2.8
MSP430F2131 0.9 2.7 0.7 1.5 1.2
MSP430F249 1.0 3.0 0.9 2.0 1.0
MSP430F413 0.9 2.7 0.7 1.5 1.2
MSP430F449 1.6 4.8 1.1 2.4 2.4
Table 6. Typical Ultralow IQLDO Quiescent Power Dissipation Versus the TPS780 Series
MSP430 SYSTEM
TYPICAL ULTRALOW IQTPS780 SERIES TPS780 SERIES AT POWER SAVINGS
TYPICAL ULTRALOW IQLDO AT +25°C AMBIENT TYPICAL IQAT +25°C +25C AMBIENT, POWER USING THE TPS780
LDO AT +25°C AMBIENT POWER DISSIPATION AMBIENT DISSIPATION SERIES
QUIESCENT POWER
IQIQ× VIN = 4.2V TPS780 IQIQ× VIN = 4.2V DISSIPATION SAVINGS
(μA) (μW) (μA) (μW) (μW)
1.20 5.04 0.42 1.76 3.28
Table 7. Total System Power Dissipation
TOTAL SYSTEM POWER IN
LDO DISSIPATION MSP430 DISSIPATION SLEEP MODE 3
Typical 1.2μA LDO, no DVS 5.04μW 4.8μW(1) 9.84μW
TPS780 Series with DVS 1.76μW 1.5μW(1) 3.26μW
(1) Value taken from Table 5 and relative to the MSP430F1121.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
TPS780
GND
EN
VSET
IN OUT
V High=V
SET OUT(LOW)
V Low=V
SET OUT(HIGH)
VIN VOUT
1 Fm
1 Fm
4.2Vto5.5V 2.2Vto3.3V
t=3
10k RWL
´
10kW+RL
COUT
´
TPS780
GND
EN
VSET
IN OUT
VIN VOUT
1 Fm
1 Fm
4.2Vto5.5V 2.2V
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
INTERNAL CURRENT LIMIT
The TPS780 series are internally current-limited to
protect the regulator during fault conditions. During
current limit, the output sources a fixed amount of
current that is largely independent of output voltage.
For reliable operation, the device should not be
operated in a current limit state for extended periods
of time.
The PMOS pass element in the TPS780 series has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of Figure 59. Circuit to Tie Both EN and VSET High
rated output current may be appropriate. DROPOUT VOLTAGE
SHUTDOWN The TPS780 series use a PMOS pass transistor to
The enable pin (EN) is active high and is compatible achieve low dropout. When (VIN – VOUT) is less than
with standard and low-voltage CMOS levels. When the dropout voltage (VDO), the PMOS pass device is
shutdown capability is not required, EN should be the linear region of operation and the input-to-output
connected to the IN pin, as shown in Figure 58.resistance is the RDS(ON) of the PMOS pass element.
Figure 59 shows both EN and VSET connected to IN. VDO approximately scales with output current
The TPS780 series, with internal active output pull- because the PMOS device behaves like a resistor in
down circuitry, discharges the output to within 5% dropout. As with any linear regulator, PSRR and
VOUT with a time (t) shown in Equation 3:transient response are degraded as (VIN – VOUT)
approaches dropout. This effect is shown in the
Typical Characteristics section. Refer to application
report SLVA207, Understanding LDO Dropout,
(3) available for download from www.ti.com.
Where: TRANSIENT RESPONSE
RL= output load resistance
COUT = output capacitance As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. For
more information, see Figure 48.
ACTIVE VOUT PULL-DOWN
In the TPS780 series, the active pull-down discharges
VOUT when the device is off. However, the input
voltage must be greater than 2.2V for the active pull-
down to work.
MINIMUM LOAD
The TPS780 series are stable with no output load.
Traditional PMOS LDO regulators suffer from lower
Figure 58. Circuit Showing EN Tied High when loop gain at very light output loads. The TPS780
Shutdown Capability is Not Required series employ an innovative, low-current circuit under
very light or no-load conditions, resulting in improved
output voltage regulation performance down to zero
output current. See Figure 47 for the load transient
response.
20 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
P =(V V ) I- ´
D IN OUT OUT
TI Information — Selective Disclosure
TPS780 Series
www.ti.com
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
THERMAL INFORMATION
The internal protection circuitry of the TPS780 series
THERMAL PROTECTION has been designed to protect against overload
conditions. However, it is not intended to replace
Thermal protection disables the output when the proper heatsinking. Continuously running the TPS780
junction temperature rises to approximately +160°C, series into thermal shutdown degrades device
allowing the device to cool. Once the junction reliability.
temperature cools to approximately +140°C, the
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient POWER DISSIPATION
temperature, the thermal protection circuit may cycle The ability to remove heat from the die is different for
on and off again. This cycling limits the dissipation of each package type, presenting different
the regulator, protecting it from damage as a result of considerations in the PCB layout. The PCB area
overheating. around the device that is free of other components
Any tendency to activate the thermal protection circuit moves the heat from the device to the ambient air.
indicates excessive power dissipation or an Performance data for JEDEC low- and high-K boards
inadequate heatsink. For reliable operation, junction are given in the Dissipation Ratings table. Using
temperature should be limited to +125°C maximum. heavier copper increases the effectiveness in
To estimate the margin of safety in a complete design removing heat from the device. The addition of plated
(including heatsink), increase the ambient through-holes to heat-dissipating layers also
temperature until the thermal protection is triggered; improves the heatsink effectiveness. Power
use worst-case loads and signal conditions. For good dissipation depends on input voltage and load
reliability, thermal protection should trigger at least conditions. Power dissipation (PD) is equal to the
+35°C above the maximum expected ambient product of the output current times the voltage drop
condition of your particular application. This across the output pass element (VIN to VOUT), as
configuration produces a worst-case junction shown in Equation 4:
temperature of +125°C at the highest expected (4)
ambient temperature and worst-case load.
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS780 series are available from the Texas
Instruments web site at www.ti.com through the
TPS780 series product folders.
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2008) to Revision D Page
• Updated Figure 47 and Figure 48 ....................................................................................................................................... 15
22 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 3-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS78001DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78001DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78001DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78001DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78001DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78001DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78001DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78001DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780180300DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780180300DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780230300DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780230300DRVT ACTIVE SON DRV 6 250 TBD Call TI Call TI
TPS780270200DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780270200DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780270200DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780270200DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780300250DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 3-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS780300250DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780330220DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780330220DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780330220DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780330220DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS780330220DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780330220DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780330220DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS780330220DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 3-Aug-2012
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS78001DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78001DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78001DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78001DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS780180300DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS780180300DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS780230300DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS780270200DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS780270200DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS780300250DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS780300250DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS780330220DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS780330220DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS780330220DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS780330220DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS78001DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS78001DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS78001DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS78001DRVT SON DRV 6 250 203.0 203.0 35.0
TPS780180300DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS780180300DRVT SON DRV 6 250 203.0 203.0 35.0
TPS780230300DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS780270200DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS780270200DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS780300250DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS780300250DRVT SON DRV 6 250 203.0 203.0 35.0
TPS780330220DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS780330220DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS780330220DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS780330220DRVT SON DRV 6 250 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2012
Pack Materials-Page 2
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