December 2002
Adva nce Information
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AS7C25512NTD32A
AS7C25512NTD36A
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Features
• Organization: 524,288 words × 32 or 36 bits
•NTD
™1 architecture for efficient bus operation
• Fast clock speeds to 250 MHz in LVTTL/LVCMOS
• Fast clock to data access: 2.6/2.8/3/3.4 ns
•Fast OE
access time: 2.6/2.8/3/3.4 ns
• Fully synchronous operation
• Flow-through or pipelined mode
• Asynchronous output enable co ntrol
1. NTDTM is a trademark of Alliance Semiconductor Corporation.
• Available in 100-pin TQFP and 165-ball BG A pa ckage
• Byte write enables
• Clock enable for operation hold
•Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycle s
• Interleaved or linear burst mod es
• Snooze mode for standby operation
Logic block diagram
Selection guide
-250 -225 -200 -166 Units
Minimum cycle time 4 4 5 6 ns
Maximum pipelined clock frequency 250 225 200 166 MHz
Maximum pipelined clock access time 2.6 2.8 3.0 3.4 ns
Maximum operating current 450 425 400 350 mA
Maximum standby current 160 150 130 120 mA
Maximum CMOS standb y current (DC) 70 70 70 70 mA
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Pin and ball assignment
165-ball BGA - top view
100-pin TQFP - top view
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Functional description
The AS7C25512NTD32A/36A family is a high performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) organized as
524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 16Mb+ sync hronous SRAM uses the No Turnaround Delay (NTD™) arch itecture, featur ing an enhanced write operation
that impro v es band width o ver pipelined burst de vice s. In a normal pipelined burst device , the write data, command, and address are a ll a pplied
to the device on the same clock edge. If a read command follo ws this write command, the system must wait f o r two 'dead' cycles for v alid data
to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-
write operations.
NTD™ devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle fl ow-
through read latency. Write data is applied two cycles after the wri te command and address, al lowing the read pipeline to clear. With NTD™,
write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perf orm write cycles . Byte write enable controls write access to specific b ytes, or can be tied lo w f or full 18 bit writes. Write
enable signals , along with the wr ite address, are registered on a r ising edge of the cloc k. Write data is applied to the device two cloc k cycles
later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal
operations. Outputs go to a high impedance state when the device is de-selected by any of the three c hip enable inputs. In pipelined mode, a
two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perf orm burst read, write and deselect ope rations. When ADV is high , exte rnal addresses, chip select, R/W pins
are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can
be stalled using the CEN=1, the clock enable input.
The AS7C25512NTD32A/36A operates with a 2.5V ± 5% power supply for the device core (VDD). These devices are available in a 100-pin
TQFP package and 165 BGA Ball Grid Array package.
Capacitance
Burst order
Parameter Symbol Signals Test conditio ns Max Unit
Input capacitance CIN Address and control pins Vin = 0V 5 pF
I/O capacitance CI/O I/O pins Vin = Vout = 0V 7 pF
Interleaved burst order LBO = 1 Linear burst order LBO = 0
A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0
Starting address 0 0 0 1 1 0 1 1 Starting Address 0 0 0 1 1 0 1 1
First increment 0 1 0 0 1 1 1 0 First increment 0 1 1 0 1 1 0 0
Second increment 1 0 1 1 0 0 0 1 Second increment 1 0 1 1 0 0 0 1
Third increment 1 1 1 0 0 1 0 0 Third increment 1 1 0 0 0 1 1 0
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Signal descriptions
Absolute maximum ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a str ess r ating only, and functional operation of
the device a t these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Signal I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is ac ti ve.
CE0, CE1,
CE2 ISYNC
Synchronous chip enab les . Sampled at the rising edge of CLK, when AD V/LD is asserted. Are
ignored when ADV/LD is high.
ADV/LD ISYNC
Advance or Load. When sampled high, the internal burst a ddress counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
R/W ISYNC
A high during LOAD initiates a READ operation. A lo w during LOAD initiates a WRITE
operation. Is ignore d when ADV/LD is high.
BW[a,b,c,d] ISYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO ISTATIC
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This input should be static when the
device is in operation.
FT ISTATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
TDO O SYNC Serial data-ou t to the JTAG circuit. Delivers data on the negativ e edge of TCK. (BGA only)
TDI I SYNC Serial data-in to the JTA G circuit. Sampled on the rising edge of TCK. (BGA only)
TMS I SYNC This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)
TCK O SYNC Serial data-ou t to the JTAG circuit. Delivers data on the negativ e edge of TCK. (BGA only)
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connects.
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.3 +3.6 V
Input v o ltage relative to GND (input pins) VIN –0.3 VDD + 0.3 V
Input v o ltage relative to GND (I/O pins) VIN –0.3 VDDQ + 0.3 V
P ower dissipation PD–1.8W
DC output current IOUT –50mA
Storage temperature (pla stic) Tstg –65 +150 oC
Temperature under bias (junction) Tbias –65 +150 oC
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Synchronous truth table
Key: X = don’t care, L = low, H = high
State diagram for NTD SRAM
Recommended operating conditions
CE0 CE1 CE2 ADV/LD R/W BW[a,b] OE CEN Address source CLK Operation
H X X L X X X L NA L to H Deselect, high-Z
X L X L X X X L NA L to H Deselect, high-Z
X X H L X X X L NA L to H Deselect, high-Z
L H L L H X X L External L to H Begin read
LHL L L L XLExternal L to HBegin write
XXX H XX
1
1 Should be low for burst write, unless specific bytes need to be inhibited
X L Burst counter L to H Burst2
2 Refer to state diagram below.
X X X X X X X H Stall L to H Inhibit the CLK
Parameter Symbol Min Nominal Max Unit
Supply voltage VDD, VDDQ 2.35 2.5 2.65 V
GND 0.0 0.0 0.0
Input voltages
Address and
control pins VIH 2.0 – VDD + 0.3 V
VIL –0.51
1 VIL min = –2.0V for pulse width less than 0.2 x tRC.
–0.4
I/O pins VIH 2.0 – VDDQ + 0.3 V
VIL -0.51–0.4
Ambient operating temperature TA0–70° C
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DC electrical characteristics for 2.5V I/O operation
Parameter Sym Test conditions
250 225 200 166
Unit
Min Max Min Max Min Max Min Max
Input leakage current1
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loadin g.
| ILI |V
DD = Max, Vin = GND to VDD –2–2–2– 2µA
Output leakage
current | ILO | OE ≥ VIH, VDD = Max,
Vout = GND to VDD -11-11-11-1 1µA
Operating power
supply current ICC CE = VIL, CE = VIH, CE = VIL,
f = fmax, Iout = 0 mA – 450 – 425 – 400 – 350 mA
Standby po w er supply
current2
2 LBO pin has an internal pull-up and input leakage = ±10 mA.
ISB Deselected, f = fmax – 160 – 150 – 130 – 120
mA
ISB1
Deselected, f = 0,
all VIN ≤ 0.2V
or ≥ (VDD, VDDQ) – 0.2V –70–70–70– 70
ISB2 Deselected, f = fMax,
ZZ ≥ (VDD, VDDQ) – 0.2V,
all VIN ≤ VIL or ≥ VIH –30–30–30– 30
Output voltag e VOL IOL = 2 mA, VDDQ = 2.65V – 0.7 – 0.7 – 0.7 – 0.7 V
VOH IOH = –2 mA, VDDQ = 2.35V 1.7 – 1.7 – 1.7 – 1.7 –
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Timing characteristics over operating range
Parameter Sym 250 225 200 166 Unit Notes1
1 See “Notes” on page 17
Min Max Min Max Min Max Min Max
Clock frequency FMAX - 250 - 225 - 200 - 166 MHz
Cycle time (pipelined mode) tCYC 4-4.4-5-6- ns
Cycle time (flow-through mode) tCYCF 6.5 - 6.9 - 7.5 - 8.5 - ns
Clock access time (pipelined mode) tCD - 2.6 - 2.8 - 3.0 - 3.4 ns
Clock access time (flow-through mode) tCDF - 6.5 - 6.9 - 7.5 - 8.5 ns
Output enable low to data valid tOE - 2.6 - 2.8 - 3.0 - 3.4 ns
Clock high to output low Z tLZC 0 - 0 - 0 - 0 - ns 2,3,4
Data output invalid fr om clock high tOH 1.5 - 1.5 - 1.5 - 1.5 - ns 4
Output enable low to output low Z tLZOE 0 - 0 - 0 - 0 - ns 2,3,4
Output enable high to output high Z tHZOE - 2.6 - 2.8 - 3.0 - 3.4 ns 2,3,4
Clock high to output high Z tHZC - 2.6 - 2.8 - 3.0 - 3.4 ns 2,3,4
Clock high to output high Z tHZCN - 1.5 - 1.5 - 1.5 - 1.5 ns 5
Clock high pulse width tCH 1.5 - 1.8 - 1.8 - 1.8 - ns 8
Clock low pulse width tCL 1.5 - 1.8 - 1.8 - 2.2 - ns 8
Address and Control setup to clock high tAS 1.2 - 1.4 - 1.4 - 1.5 - ns 9
Data setup to clock high tDS 1.2 - 1.4 - 1.4 - 1.5 - ns 9
Write setup to clock high tWS 1.2 - 1.4 - 1.4 - 1.5 - ns 9
Chip select setup to clock high tCSS 1.2 - 1.4 - 1.4 - 1.5 - ns 9
Address hold from clock high tAH 0.3 - 0.4 - 0.4 - 0.5 - ns 9
Data hold from clock high tDH 0.3 - 0.4 - 0.4 - 0.5 - ns 9
Write hold from clock high tWH 0.3 - 0.4 - 0.4 - 0.5 - ns 9
Chip select hold from clock high tCSH 0.3 - 0.4 - 0.4 - 0.5 - ns 9
Clock enable setup to clock high tCENS 1.2 - 1.4 - 1.4 - 1.5 - ns 9
Clock enable hold from clock high tCENH 0.3 - 0.4 - 0.4 - 0.5 - ns 9
ADV setup to clock high tADVS 1.2 - 1.4 - 1.4 - 1.5 - ns 9
ADV hold from clock high tADVH 0.3 - 0.4 - 0.4 - 0.5 - ns 9
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IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the
critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully
compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
Disabling the JTAG feature
If the JTAG function is not being implemented, its pins/balls can be left unconnected. At power-up, the device will come up in a reset state
which will not interfere with the operation of the device.
Test access port (TAP)
Test clock (TCK)
The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can lea ve this pin/ball unconnected if the
TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.
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TAP controller state diagram TAP controller block diagram
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Test data-in (TDI)
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between
TDI and TDO is chosen by the instr uction that is loaded into the TAP instruction register. For infor mation on loading the instruction register,
see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test data-out (TDO)
The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state
machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP
Controller State Diagram.)
Performing a TAP RESET
You can perform a RESET by forcing TMS high (VDD) for five r isi ng edges of TCK. This RESE T does not affect the operation of the SRAM and
can be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP registers
Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is
output on the TDO pin/ball on the falling edge of TCK.
Instruction register
You can serially load thr ee-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/
balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at pow er up and also if the
controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault
isolation of the board-level series test data path.
Bypass register
To save time when serially shifting data through registers, it is sometimes advantageous to skip cer tain chips. The bypass register is a single-bit
register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The
bypass register is set low (Vss) when the BYPASS instruction is executed.
Boundary scan register
The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 70-bit-long
register and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and SAMPLE Z
instructions can be used to capture the contents of the I/O ring.
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM
package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.
Identification (ID) register
The ID register has a vendor code and other information described in the Identification register def initions table . The ID register is loaded with
a vendor-specific, 32-bit code dur ing the Capture-DR state when the IDCODE command is loaded in the instr uction register. The IDCODE is
hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.
TAP instruction set
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Eight different instr uctions are possible with the 3-bit instr uction register. All combinations are listed in the Instruction Codes table. Three of
these instructions are reserved and should not be used.
Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot
preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed.
Instru ctions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During
this state, instr uctions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instr uction once it is
shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP
controller. The TAP controller, ho w ever, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM
outputs in a high-Z state.
EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1.
IDCODE
The IDCODE instr uction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
The IDCODE instr uction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instr uction register
between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.
SAMPLE Z
The SAMPLE Z instruction causes the boundar y scan register to be connected between the TDI and TDO pins/balls when the TAP contro ll er is
in a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of
data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a 1149.1
mandatory instr uction, but the PRELOAD portion of this instr uction is not implemented in this device. The TAP controller, therefore, is not
fully 1149.1 compliant.
Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output
can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not har m the device, but
there is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captur es the correct value of a signal, the SRAM signal must be stabilized long enough to meet the
TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a
design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and
ignore the value of the CK and CK# captured in the bounder scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins.
Note that since the PRELOAD part of th e command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/
PRELOAD instruction will have the same effect as the Pause-DR command.
BYPASS
The advantage of the BYPASS instr uction is that it shortens the boundary scan path when multiple devices are connected together on a board.
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed betw een
TDI and TDO.
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Reserved
Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.
TAP timing diagram
TAP AC electrical characteristics
For notes 1 and 2, +10oC ≤ TJ ≤ +110oC and +2.4V ≤ VDD ≤ +2.6V.
Description Symbol Min Max Units
Clock
Clock cycle time tTHTH 100 ns
Clock frequency fTF 10 MHz
Clock high time tTHTL 40 ns
Clock low time tTLTH 40 ns
Output Times
TCK low to TDO unknown tTLOX 0ns
TCK low to TDO valid tTLOV 20 ns
TDI valid to TCK high tDVTH 10 ns
TCK high to TDI invalid tTHDX 10 ns
Setup Times
TMS setup tMVTH 10 ns
Capture setup tCS1
1 tCS and tCH refer to the setup and hold time requirements of latc hing data
from the boundary scan register.
2 Test conditions are specified using th e load in the figure TAP AC output
load equivalent.
10 ns
Hold Times
TMS hold tTHMX 10 ns
Capture hold tCH110 ns
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TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted)
1. All voltage referenced to VSS(GND).
2. Overshoot: VIH(AC) ≤ VDD + 1.5V for t ≤ tKHKH/2
Undershoot:VIL(AC) ≥ -0.5 for t ≤ tKHKH/2
Power-up: VIH ≤ +2.6V and VDD ≤ 2.4V and VDDQ ≤ 1.4V for t ≤ 200ms
During nor mal operation, VDDQ must not exceed VDD. Control input signals (suc h as LD, R/W, etc.) may not have pulsed widths less than
tKHKL(Min) or operate at frequencies exceeding fKF(Max).
Description Conditions Symbol Min Max Units Notes
Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V 1, 2
Input low (logic 0) voltage VIL -0.3 0.7 V 1, 2
Input leakage current 0V ≤ VIN ≤ VDD ILI-5.0 5.0 µA
Output leakage current Outputs disabled,
0V ≤ VIN ≤ VDDQ(DQx) ILO-5.0 5.0 µA
Output low voltage IOLC = 100µAV
OL1 0.2 V 1
Output low voltage IOLT = 2mA VOL2 0.7 V 1
Output high voltage IOHS = -100µAV
OH1 2.1 V 1
Output high voltage IOHT = -2mA VOH2 1.7 V 1
Input pulse lev els. . . . . . . . . . . . . . . Vss to 2. 5V
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing reference lev els. . . . . . . . . . 1.25V
Output ref erence levels . . . . . . . . . . . . . . 1. 25V
Test load termination supply voltage. . . . 1.25V
TAP AC test conditions TAP AC output load equivalent
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Identification register definitions
Scan register sizes
Instruction codes
Instruction field 512K x 32/36 Description
Revision number (31:28) xxxx Reserved for version number.
Device depth (27:23) xxxxx/xxxxx Defines the depth of 512K words.
Device width (22:18) xxxxx/xxxxx Defines the width of x32 or x36 bits.
Device ID (17:12) xxxxxx Reserved f or future use.
JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor.
ID register presence indicator (0) 1 Indica tes the presence of an ID register.
Register name Bit size
Instruction 3
Bypass 1
ID 32
Boundary scan x18:51 x36:70
Instruction Code Description
EXTEST 000 Captures I/O ring contents . Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captur es I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high-Z state.
Reserved 011 Do not use. This instruction is reserved for futur e use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
Reserved 101 Do not use. This instruction is reserved for futur e use.
Reserved 110 Do not use. This instruction is reserved for futur e use.
BYPASS 111 Places the bypass r egister between TDI and TDO. This operation does not affect SRAM
operations.
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165-ball BGA boundary scan order (x36)
Bit #s Signal Name Ball ID
1SA 8P
2SA 9R
3SA 9P
4SA 10R
5SA 10P
6SA 11R
7SA 8R
8DQPa 11N
9 DQa 11M
10 DQa 11L
11 DQa 11K
12 DQa 11J
13 DQa 10M
14 DQa 10L
15 DQa 10K
16 DQa 10J
17 ZZ 11H
18 DQb 11G
19 DQb 11F
20 DQb 11E
21 DQb 11D
22 DQb 10G
23 DQb 10F
24 DQb 10E
25 DQb 10D
26 DQPb 11C
27 SA 10B
28 SA 10A
29 SA 9A
30 SA 9B
31 ADV/LD 8A
32 OE 8B
33 CEN 7A
34 R/W 7B
35 CLK 6B
36 CE2 6A
Bit #s Signal Name Ball ID
37 BWa 5B
38 BWb 5A
39 BWc 4A
40 BWd 4B
41 CE1 3B
42 CE0 3A
43 SA 2A
44 SA 2B
45 DQPc 1C
46 DQc 1D
47 DQc 1E
48 DQc 1F
49 DQc 1G
50 DQc 2D
51 DQc 2E
52 DQc 2F
53 DQc 2G
54 FT 1H
55 DQd 1J
56 DQd 1K
57 DQd 1L
58 DQd 1M
59 DQd 2J
60 DQd 2K
61 DQd 2L
62 DQd 2M
63 DQPd 1N
64 LB0 1R
65 SA 3P
66 SA 3R
67 SA 4P
68 SA 4R
69 SA1 6P
70 SA0 6R
71 –
72 –
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Key to switching waveforms
Timing waveform of read/write cycle
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AC test conditions
Notes
1) For test conditions, see “AC test conditions”, Figures A, B, and C
2) This parameter m easured with output load condition in Figure C.
3) This pa ra meter is sa mpled, but not 100% tested.
4) tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
5) tCH is measured high above VIH, and tCL is measured low below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all r ising edges of CL K. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/W and BW[a,b,c,d].
8) Chip select refers to CE0, CE1, and CE2.
• Output load: For tLZC, tLZOE, tHZOE, and tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
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Package dimensions
100-pin quad flat pack (TQFP)
165-ball BGA (ball grid array)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b0.22 0.38
c0.09 0.20
D13.90 14.10
E19.90 20.10
e0.65 nominal
Hd 15.90 16.10
He 21.90 22.10
L0.45 0.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
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© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective c ompanies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contain ed here in r epresent s Al liance ’s best data and/or estimates at the time of issuance. Alliance re ser ves the right to change or correct this data at any time, without notice. If the product described herein is
under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to
operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express
or implied warranties related to the sale and/or use of Alliance products including liability or warranties relate d to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as
express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products ar e made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user , and the inclusion of Alliance products in such life-supporting s ystems
implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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Ordering information
Part numbering guide
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 25 = 2.5V
3. Organization:
512 = 512k
4. NTD™ = No Turn-Around Delay. Pipelined/flow -through mode (each device works in both modes)
5. Organization: 32 = x 32, 36 = x 36
6. Production version: A = first production version
7. Clock speed (MHz)
8. Package type: TQ = TQFP; B = BGA
9. Operating tempera tur e: C = commercial (
0
°
C to 70
°
C); I = industrial (
-40
°
C to 85
°
C)
Package & Width –250 MHz –225 MHz –200 MHz –166 MHz
TQFP x32 AS7C25512NTD32A-
250TQC
AS7C25512NTD32A-
225TQC AS7C25512NTD32A-
200TQC AS7C25512NTD32A-
166TQC
AS7C25512NTD32AA-
225TQI AS7C25512NTD32A-
200TQI AS7C25512NTD32A-
166TQI
TQFP x36 AS7C25512NTD36A-
250TQC
AS7C25512NTD36A-
225TQC AS7C25512NTD36A-
200TQC AS7C25512NTD36A-
166TQC
AS7C25512NTD36A-
225TQI AS7C25512NTD36A-
200TQI AS7C25512NTD36A-
166TQI
BGA x32 AS7C25512NTD32A-
250BC
AS7C25512NTD32A-
225BC AS7C25512NTD32A-
200BC AS7C25512NTD32A-
166BC
AS7C25512NTD32A-
225BI AS7C25512NTD32A-
200BI AS7C25512NTD32A-
166BI
BGA x36 AS7C25512NTD36A-
250BC
AS7C25512NTD36A-
225BC AS7C25512NTD36A-
200BC AS7C25512NTD36A-
166BC
AS7C25512NTD36A-
225BI AS7C25512NTD36A-
200BI AS7C25512NTD36A-
166BI
AS7C 25 512 NTD 32/36 A–XXX TQ or B C/I
1
23
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