0.0 0.2 0.4 0.6 0.8 1.0
40
50
60
70
80
90
100
EFFICIENCY (%)
LOAD CURRENT (A)
VIN = 4.5V
VIN = 9V
VIN = 12v
VIN = 24V
VIN = 42v
0.0 0.2 0.4 0.6 0.8 1.0
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
ûVOUT(%)
LOAD CURRENT (A)
VIN = 4.5V
VIN = 9V
VIN = 12V
VIN = 24V
VIN = 42V
LMR24210
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SNVS738G –OCTOBER 2011–REVISED APRIL 2013
LMR24210 SIMPLE SWITCHER
®
42Vin, 1.0A Step-Down Voltage Regulator
Check for Samples: LMR24210
1FEATURES APPLICATIONS
23• Input Voltage Range of 4.5V to 42V • Point-of-Load Conversions from 5V, 12V and
24V Rails
• Output Voltage Range of 0.8V to 24V • Space Constrained Applications
• Output Current up to 1.0A • Industrial Distributed Power Applications
• Integrated low RDS(ON) Synchronous MOSFETs
for High Efficiency • Power Meters
• Up to 1 MHz Switching Frequency DESCRIPTION
• Low Shutdown Iq, 25 µA Typical The LMR24210 Synchronously Rectified Buck
• Programmable Soft-Start Converter features all required functions to implement
• No Loop Compensation Required a highly efficient and cost effective buck regulator. It
is capable of supplying 1A to loads with an output
• COT Architecture with ERM voltage as low as 0.8V. Dual N-Channel synchronous
• 28-Bump DSBGA (2.45 x 3.64 x 0.60 mm) MOSFET switches allow a low component count, thus
Packaging reducing complexity and minimizing board size.
• Fully Enabled for WEBENCH®Power Designer Different from most other COT regulators, the
LMR24210 does not rely on output capacitor ESR for
PERFORMANCE BENEFITS stability, and is designed to work exceptionally well
• Tiny Overall Solution Reduces System Cost with ceramic and other very low ESR output
capacitors. It requires no loop compensation, results
• Integrated Synchronous MOSFETs Provides in a fast load transient response and simple circuit
High Efficiency at Low Output Voltages implementation. The operating frequency remains
• COT with ERM Architecture Requires No Loop nearly constant with line variations due to the inverse
Compensation, Reduces Component Count, relationship between the input voltage and the on-
and Provides Ultra Fast Transient Response time. The operating frequency can be externally
programmed up to 1 MHz. Protection features include
• Stable with Low ESR Capacitors VCC under-voltage lock-out, output over-voltage
protection, thermal shutdown, and gate drive under-
voltage lock-out. The LMR24210 is available in the
small DSBGA low profile chip-scale package.
System Performance
Efficiency vs Load Current VOUT Regulation vs Load Current
(VOUT = 3.3V) (VOUT = 3.3V)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VIN VIN BST SW AGND RON EN
SW SW SW SW
SW SW SW SW VCC SS
PGND PGND PGND VCC FB
A B C D E F G
4
3
2
1PGN
D
Top Mark
AGND AGND AGND
AGND
AGND
LMR24210
LMR24210
SNVS738G –OCTOBER 2011–REVISED APRIL 2013
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Typical Application
Figure 1. Connection Diagram
Figure 2. 28-Ball DSBGA (Balls Facing Down)
See YPA0028 Package
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PIN DESCRIPTIONS
Ball Name Description Application Information
A2, A3, B2, B3, SW Switching Node Internally connected to the source of the main MOSFET
C2, C3, D2, D3, and the drain of the Synchronous MOSFET. Connect to
D4 the inductor.
A4, B4 VIN Input supply voltage Supply pin to the device. Nominal input range is 4.5V to
42V.
C4 BST Connection for bootstrap capacitor Connect a 33 nF capacitor from the SW pin to this pin. An
internal diode charges the capacitor during the main
MOSFET off-time.
E3, E4, F1, F2, AGND Analog Ground Ground for all internal circuitry other than the PGND pin.
F3, G3
G2 SS Soft-start An 8 µA internal current source charges an external
capacitor to provide the soft- start function.
G1 FB Feedback Internally connected to the regulation and over-voltage
comparators. The regulation setting is 0.8V at this pin.
Connect to feedback resistors.
G4 EN Enable Connect a voltage higher than 1.26V to enable the
regulator. Leaving this input open circuit will enable the
device at internal UVLO level.
F4 RON On-time Control An external resistor from the VIN pin to this pin sets the
main MOSFET on-time.
E1, E2 VCC Start-up regulator Output Nominally regulated to 6V. Connect a capacitor of not less
than 680 nF between the VCC and AGND pins for stable
operation.
A1, B1, C1, D1 PGND Power Ground Synchronous MOSFET source connection. Tie to a ground
plane.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VIN, RON to AGND -0.3V to 43.5V
SW to AGND -0.3V to 43.5V
SW to AGND (Transient) -2V (< 100ns)
VIN to SW -0.3V to 43.5V
BST to SW -0.3V to 7V
All Other Inputs to AGND -0.3V to 7V
ESD Rating Human Body Model(3) ±2kV
Storage Temperature Range -65°C to +150°C
Junction Temperature (TJ) 150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.
Operating Ratings(1)
Supply Voltage Range (VIN) 4.5V to 42V
Junction Temperature Range (TJ)−40°C to +125°C
Thermal Resistance (θJA) 28-ball DSBGA(2) 50°C/W
For soldering specifications see SNOA549
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
(2) θJA calculations were performed in general accordance with JEDEC standards JESD51–1 to JESD51–11.
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Electrical Characteristics
Specifications with standard type are for TJ= 25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 18V, VOUT = 3.3V.(1)
Symbol Parameter Conditions Min Typ Max Units
Start-Up Regulator, VCC
VCC VCC output voltage CCC = 680nF, no load 5.0 6.0 7.2 V
VIN - VCC VIN - VCC dropout voltage ICC = 20mA 350 mV
IVCCL VCC current limit (2) VCC = 0V 40 65 mA
VCC-UVLO VCC under-voltage lockout threshold VIN increasing 3.55 3.75 3.95 V
(UVLO)
VCC-UVLO-HYS VCC UVLO hysteresis VIN decreasing – DSBGA 150 mV
package
tVCC-UVLO-D VCC UVLO filter delay 3 µs
IIN IIN operating current No switching, VFB = 1V 0.7 1mA
IIN-SD IIN operating current, Device shutdown VEN = 0V 25 40 µA
Switching Characteristics
RDS-UP-ON Main MOSFET RDS(on) 0.18 0.375 Ω
RDS- DN-ON Syn. MOSFET RDS(on) 0.11 0.225 Ω
VG-UVLO Gate drive voltage UVLO VBST - VSW increasing 3.3 4V
Soft-start
ISS SS pin source current VSS = 0.5V 11 µA
Current Limit
ICL Syn. MOSFET current limit threshold LMR24210 1.2 1.8 2.6 A
ON/OFF Timer
ton ON timer pulse width VIN = 10V, RON = 100 kΩ1.38 µs
VIN = 30V, RON = 100 kΩ0.47
ton-MIN ON timer minimum pulse width 150 ns
toff OFF timer pulse width 260 ns
Enable Input
VEN EN Pin input threshold VEN rising 1.13 1.18 1.23 V
VEN-HYS Enable threshold hysteresis VEN falling 90 mV
Regulation and Over-Voltage Comparator
VFB In-regulation feedback voltage VSS ≥0.8V 0.784 0.8 0.816 V
TJ=−40°C to +125°C
VFB-OV Feedback over-voltage threshold 0.888 0.920 0.945 V
IFB FB pin current 5 nA
Thermal Shutdown
TSD Thermal shutdown temperature TJrising 165 °C
TSD-HYS Thermal shutdown temperature TJfalling 20 °C
hysteresis
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
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0 10 20 30 40 50
0
100
200
300
400
500
600
700
800
900
1000
SWITCHING FREQENCY (kHZ)
VIN(v)
Ron = 12.4k; L = 3.3H, Io = 0.4A
Ron = 12.4k; L = 3.3H, Io = 1A
Ron = 12.4k; L = 8.2H, Io = 0.4A
Ron = 12.4k; L = 8.2H, Io = 1A
Ron = 7.68k; L = 3.3H, Io = 0.4A
Ron = 7.68k; L = 3.3H, Io = 1A
Ron = 7.68k; L = 8.2H, Io = 0.4A
Ron = 7.68k; L = 8.2H, Io = 1A
LMR24210
SNVS738G –OCTOBER 2011–REVISED APRIL 2013
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Typical Performance Characteristics
Unless otherwise specified all curves are taken at VIN = 18V with the configuration in the typical application circuit for VOUT =
3.3V (Figure 27) TA= 25°C.
VCC vs ICC VCC vs VIN
Figure 3. Figure 4.
ton vs VIN Switching Frequency, fSW vs VIN, VOUT=0.8V,
Figure 5. Figure 6.
VFB vs Temperature RDS(on) vs Temperature
Figure 7. Figure 8.
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10V/Div
1V/Div
500 mA/Div
TIME (5 ms/DIV)
VIN
IO
VO
2V/DIV
1V/DIV
200 mA/Div
TIME (1 ms/DIV)
VEN
IO
VO
0.0 0.2 0.4 0.6 0.8 1.0
40
50
60
70
80
90
100
EFFICIENCY (%)
LOAD CURRENT (A)
VIN = 4.5V
VIN = 9V
VIN = 12v
VIN = 24V
VIN = 42v
0.0 0.2 0.4 0.6 0.8 1.0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
ûVOUT(%)
LOAD CURRENT (A)
VIN = 4.5V
VIN = 9V
VIN = 12V
VIN = 24V
VIN = 42V
0.0 0.2 0.4 0.6 0.8 1.0
40
50
60
70
80
90
100
EFFICIENCY (%)
LOAD CURRENT (A)
VIN = 4.5V
VIN = 9V
VIN = 12v
VIN = 24V
VIN = 42v
0.0 0.2 0.4 0.6 0.8 1.0
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
ûVOUT(%)
LOAD CURRENT (A)
VIN = 4.5V
VIN = 9V
VIN = 12V
VIN = 24V
VIN = 42V
LMR24210
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SNVS738G –OCTOBER 2011–REVISED APRIL 2013
Typical Performance Characteristics (continued)
Unless otherwise specified all curves are taken at VIN = 18V with the configuration in the typical application circuit for VOUT =
3.3V (Figure 27) TA= 25°C.
Efficiency vs Load Current VOUT Regulation vs Load Current
(VOUT = 3.3V) (VOUT = 3.3V)
Figure 9. Figure 10.
Efficiency vs Load Current VOUT Regulation vs Load Current
(VOUT = 0.8V) (VOUT = 0.8V)
Figure 11. Figure 12.
Power Up Enable Transient
(VOUT = 3.3V, 1A Loaded) (VOUT = 3.3V, 1A Loaded)
Figure 13. Figure 14.
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20 mV/Div
500 mA/Div
TIME (200 Ps/DIV)
IL
'VO
5V/Div
500 mA/Div
TIME (20 Ps/DIV)
VSW
IL
20 mV/Div
5V/Div
500 mA/Div
TIME (5 Ps/DIV)
VSW
IL
'VO
20 mV/DIV
5V/DIV
500 mA/DIV
TIME (2 Ps/DIV)
VSW
IL
'VO
2V/DIV
2V/DIV
500 mA/DIV
TIME (0.1 ms/DIV)
VEN
IO
VO
LMR24210
SNVS738G –OCTOBER 2011–REVISED APRIL 2013
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Typical Performance Characteristics (continued)
Unless otherwise specified all curves are taken at VIN = 18V with the configuration in the typical application circuit for VOUT =
3.3V (Figure 27) TA= 25°C.
Shutdown Transient Continuous Mode Operation
(VOUT = 3.3V, 1A Loaded) (VOUT = 3.3V, 1A Loaded)
Figure 15. Figure 16.
Discontinuous Mode Operation DCM to CCM Transition
(VOUT = 3.3V, 0.050A Loaded) (VOUT = 3.3V, 0.50A - 1A Load)
Figure 17. Figure 18.
Load Transient
(VOUT = 3.3V, 0.20A - 1A Load,)
Figure 19.
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VOUT
1.3 x 10-10 x RON
fSW =
(VIN ± VOUT) x RON2
VOUT (VIN - 1) x L x 1.18 x 1020 x IOUT
fSW =
LMR24210
SNVS738G –OCTOBER 2011–REVISED APRIL 2013
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FUNCTIONAL DESCRIPTION
The LMR24210 Step Down Switching Regulator features all required functions to implement a cost effective,
efficient buck power converter capable of supplying 1A to a load. It contains Dual N-Channel main and
synchronous MOSFETs. The Constant ON-Time (COT) regulation scheme requires no loop compensation,
results in fast load transient response and simple circuit implementation. The regulator can function properly
even with an all ceramic output capacitor network, and does not rely on the output capacitor’s ESR for stability.
The operating frequency remains constant with line variations due to the inverse relationship between the input
voltage and the on-time. The valley current limit detection circuit, with the limit set internally at 1.8A, inhibits the
main MOSFET until the inductor current level subsides.
The LMR24210 can be applied in numerous applications and can operate efficiently for inputs as high as 42V.
Protection features include output over-voltage protection, thermal shutdown, VCC under-voltage lock-out and
gate drive under-voltage lock-out. The LMR24210 is available in a small DSBGA chip scale package.
COT Control Circuit Overview
COT control is based on a comparator and a one-shot on-timer, with the output voltage feedback (feeding to the
FB pin) compared with an internal reference of 0.8V. If the voltage of the FB pin is below the reference, the main
MOSFET is turned on for a fixed on-time determined by a programming resistor RON and the input voltage VIN,
upon which the on-time varies inversely. Following the on-time, the main MOSFET remains off for a minimum of
260 ns. Then, if the voltage of the FB pin is below the reference, the main MOSFET is turned on again for
another on-time period. The switching will continue to achieve regulation.
The regulator will operate in the discontinuous conduction mode (DCM) at a light load, and the continuous
conduction mode (CCM) with a heavy load. In the DCM, the current through the inductor starts at zero and
ramps up to a peak during the on-time, and then ramps back to zero before the end of the off-time. It remains
zero and the load current is supplied entirely by the output capacitor. The next on-time period starts when the
voltage at the FB pin falls below the internal reference. The operating frequency in the DCM is lower and varies
larger with the load current as compared with the CCM. Conversion efficiency is maintained since conduction
loss and switching loss are reduced with the reduction in the load and the switching frequency respectively. The
operating frequency in the DCM can be calculated approximately as follows:
(1)
In the continuous conduction mode (CCM), the current flows through the inductor in the entire switching cycle,
and never reaches zero during the off-time. The operating frequency remains relatively constant with load and
line variations. The CCM operating frequency can be calculated approximately as follows:
(2)
Please consider Equation 4 and Equation 5 when choosing the switching frequency.
The output voltage is set by two external resistors RFB1 and RFB2. The regulated output voltage is
VOUT = 0.8V x (RFB1 + RFB2)/RFB2 (3)
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fSW(MAX) = VOUT
VIN(MAX) x 150 ns
VIN
1.3 x 10-10 x RON
ton =
LMR24210
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Startup Regulator (VCC)
A startup regulator is integrated within the LMR24210. The input pin VIN can be connected directly to a line
voltage up to 42V. The VCC output regulates at 6V, and is current limited to 65 mA. Upon power up, the regulator
sources current into an external capacitor CVCC, which is connected to the VCC pin. For stability, CVCC must be at
least 680 nF. When the voltage on the VCC pin is higher than the under-voltage lock-out (UVLO) threshold of
3.75V, the main MOSFET is enabled and the SS pin is released to allow the soft-start capacitor CSS to charge.
The minimum input voltage is determined by the dropout voltage of the regulator and the VCC UVLO falling
threshold (≊3.7V). If VIN is less than ≊4.0V, the regulator shuts off and VCC goes to zero.
Regulation Comparator
The feedback voltage at the FB pin is compared to a 0.8V internal reference. In normal operation (the output
voltage is regulated), an on-time period is initiated when the voltage at the FB pin falls below 0.8V. The main
MOSFET stays on for the on-time, causing the output voltage and consequently the voltage of the FB pin to rise
above 0.8V. After the on-time period, the main MOSFET stays off until the voltage of the FB pin falls below 0.8V
again. Bias current at the FB pin is nominally 5 nA.
Zero Coil Current Detect
The current of the synchronous MOSFET is monitored by a zero coil current detection circuit which inhibits the
synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the DCM
operation, which improves the efficiency at a light load.
Over-Voltage Comparator
The voltage at the FB pin is compared to a 0.92V internal reference. If it rises above 0.92V, the on-time is
immediately terminated. This condition is known as over-voltage protection (OVP). It can occur if the input
voltage or the output load changes suddenly. Once the OVP is activated, the main MOSFET remains off until the
voltage at the FB pin falls below 0.92V. The synchronous MOSFET will stay on to discharge the inductor until the
inductor current reduces to zero, and then switches off.
ON-Time Timer, Shutdown
The on-time of the LMR24210 main MOSFET is determined by the resistor RON and the input voltage VIN. It is
calculated as follows:
(4)
The inverse relationship of ton and VIN gives a nearly constant frequency as VIN is varied. RON should be selected
such that the on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a minimum of
150 ns for ton. This limits the maximum operating frequency, which is governed by the following equation:
(5)
The LMR24210 can be remotely shutdown by pulling the voltage of the EN pin below 1V. In this shutdown mode,
the SS pin is internally grounded, the on-timer is disabled, and bias currents are reduced. Releasing the EN pin
allows normal operation to resume because the EN pin is internally pulled up.
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ILR = (VIN - VOUT) x ton
L
LMR24210
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Figure 20. Shutdown Implementation
Current Limit
Current limit detection is carried out during the off-time by monitoring the re-circulating current through the
synchronous MOSFET. Referring to Simplified Functional Block Diagram, when the main MOSFET is turned off,
the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current
exceeds 1.8A, the current limit comparator toggles, and as a result disabling the start of the next on-time period.
The next switching cycle starts when the re-circulating current falls back below 1.8A (and the voltage at the FB
pin is below 0.8V). The inductor current is monitored during the on-time of the synchronous MOSFET. As long as
the inductor current exceeds 1.8A, the main MOSFET will remain inhibited to achieve current limit. The operating
frequency is lower during current limit due to a longer off-time.
Figure 21 illustrates an inductor current waveform. On average, the output current IOUT is the same as the
inductor current IL, which is the average of the rippled inductor current. In case of current limit (the current limit
portion of Figure 21), the next on-time will not initiate until the current drops below 1.8A (assume the voltage at
the FB pin is lower than 0.8V). During each on-time the current ramps up an amount equal to:
(6)
During current limit, the LMR24210 operates in a constant current mode with an average output current IOUT(CL)
equal to 1.8A + ILR / 2.
Figure 21. Inductor Current - Current Limit Operation
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N-Channel MOSFET and Driver
The LMR24210 integrates an N-Channel main MOSFET and an associated floating high voltage main MOSFET
gate driver. The gate drive circuit works in conjunction with an external bootstrap capacitor CBST and an internal
high voltage diode. CBST connecting between the BST and SW pins powers the main MOSFET gate driver during
the main MOSFET on-time. During each off-time, the voltage of the SW pin falls to approximately -1V, and CBST
charges from VCC through the internal diode. The minimum off-time of 260 ns provides enough time for charging
CBST in each cycle.
Soft-Start
The soft-start feature allows the converter to gradually reach a steady state operating point, thereby reducing
startup stresses and current surges. Upon turn-on, after VCC reaches the under-voltage threshold, an 8 µA
internal current source charges up an external capacitor CSS connecting to the SS pin. The ramping voltage at
the SS pin (and the non-inverting input of the regulation comparator as well) ramps up the output voltage VOUT in
a controlled manner.
The soft start time duration to reach steady state operation is given by the formula:
tSS = VREFx CSS / 8µA = 0.8V x CSS / 8µA (7)
This equation can be rearranged as follows:
CSS= tSSx 8µA / 0.8V (8)
Use of a 4.7nF capacitor results in a 0.5ms soft-start duration. This is a recommended value. Note that high
values of CSS capacitance will cause more output voltage drop when a load transient goes across the DCM-CCM
boundary. If a fast load transient response is desired for steps between DCM and CCM mode the softstart
capacitor value should be less than 18nF (which corresponds to a soft-start time of 1.8ms).
An internal switch grounds the SS pin if any of the following three cases happens: (i) VCC is below the under-
voltage lock-out threshold; (ii) a thermal shutdown occurs; or (iii) the EN pin is grounded. Alternatively, the output
voltage can be shut off by connecting the SS pin to ground using an external switch. Releasing the switch allows
the SS pin to ramp up and the output voltage to return to normal. The shutdown configuration is shown in
Figure 22.
Figure 22. Alternate Shutdown Implementation
Thermal Protection
The junction temperature of the LMR24210 should not exceed the maximum limit. Thermal protection is
implemented by an internal Thermal Shutdown circuit, which activates (typically) at 165°C to make the controller
enter a low power reset state by disabling the main MOSFET, disabling the on-timer, and grounding the SS pin.
Thermal protection helps prevent catastrophic failures from accidental device overheating. When the junction
temperature falls back below 145°C (typical hysteresis = 20°C), the SS pin is released and normal operation
resumes.
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0 25 50 75 100 125
0.0
0.2
0.4
0.6
0.8
1.0
1.2
MAXIMUM IOUT(A)
AMBIENT TEMPERATURE (°C)
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Thermal Derating
Temperature rise increases with frequency, load current, input voltage and smaller board dimensions. On a
typical board, the LMR24210 is capable of supplying 1A below an ambient temperature of 90°C under worst case
operation with input voltage of 42V. Figure 23 shows a thermal derating curve for the output current without
thermal shutdown against ambient temperature up to 125°C. Obtaining 1A output current is possible at higher
temperature by increasing the PCB ground plane area, adding airflow or reducing the input voltage or operating
frequency.
θJA=40°C/W, Vo = 3.3V, fs = 500kHz
(tested on the evaluation board)
Figure 23. Thermal Derating Curve
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L = ILR x fSW x VIN
VOUT x (VIN - VOUT)
1.3 x 10-10
VIN(MAX) x 150 ns
RON t
LMR24210
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SNVS738G –OCTOBER 2011–REVISED APRIL 2013
APPLICATIONS INFORMATION
EXTERNAL COMPONENTS
The following guidelines can be used to select external components.
RFB1 and RFB2 : These resistors should be chosen from standard values in the range of 1.0 kΩto 10 kΩ,
satisfying the following ratio:
RFB1/RFB2 = (VOUT/0.8V) - 1 (9)
For VOUT = 0.8V, the FB pin can be connected to the output directly with a pre-load resistor drawing more than
20 µA. This is needed because the converter operation needs a minimum inductor current ripple to maintain
good regulation when no load is connected.
RON:Equation 2 can be used to select RON if a desired operating frequency is selected. But the minimum value
of RON is determined by the minimum on-time. It can be calculated as follows:
(10)
If RON calculated from Equation 2 is smaller than the minimum value determined in Equation 10, a lower
frequency should be selected to re-calculate RON by Equation 2. Alternatively, VIN(MAX) can also be limited in
order to keep the frequency unchanged. The relationship of VIN(MAX) and RON is shown in Figure 24.
On the other hand, the minimum off-time of 260 ns can limit the maximum duty ratio.
Figure 24. Maximum VIN for selected RON
L: The main parameter affected by the inductor is the amplitude of inductor current ripple (ILR). Once ILR is
selected, L can be determined by:
where
• VIN is the maximum input voltage and
• fSW is determined from Equation 2. (11)
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LMR24210
SNVS738G –OCTOBER 2011–REVISED APRIL 2013
www.ti.com
If the output current IOUT is determined, by assuming that IOUT = IL, the higher and lower peak of ILR can be
determined. Beware that the higher peak of ILR should not be larger than the saturation current of the inductor
and current limits of the main and synchronous MOSFETs. Also, the lower peak of ILR must be positive if CCM
operation is required.
Figure 25. Inductor selection for VOUT = 3.3V
Figure 26. Inductor selection for VOUT = 0.8V
Figure 25 and Figure 26 show curves on inductor selection for various VOUT and RON. For small RON, according
to Equation 10, VIN is limited. Some curves are therefore limited as shown in the figures.
CVCC:The capacitor on the VCC output provides not only noise filtering and stability, but also prevents false
triggering of the VCC UVLO at the main MOSFET on/off transitions. CVCC should be no smaller than 680 nF for
stability, and should be a good quality, low ESR, ceramic capacitor.
16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR24210
tSS = 8 PA
CSS x 0.8V
CIN = 'VIN
IOUT x ton
LMR24210
www.ti.com
SNVS738G –OCTOBER 2011–REVISED APRIL 2013
COUT and COUT3:COUT should generally be no smaller than 10 µF. Experimentation is usually necessary to
determine the minimum value for COUT, as the nature of the load may require a larger value. A load which
creates significant transients requires a larger COUT than a fixed load.
COUT3 is a small value ceramic capacitor located close to the LMR24210 to further suppress high frequency noise
at VOUT. A 100 nF capacitor is recommended.
CIN and CIN3:The function of CIN is to supply most of the main MOSFET current during the on-time, and limit the
voltage ripple at the VIN pin, assuming that the voltage source connecting to the VIN pin has finite output
impedance. If the voltage source’s dynamic impedance is high (effectively a current source), CIN supplies the
average input current, but not the ripple current.
At the maximum load current, when the main MOSFET turns on, the current to the VIN pin suddenly increases
from zero to the lower peak of the inductor’s ripple current and ramps up to the higher peak value. It then drops
to zero at turn-off. The average current during the on-time is the load current. For a worst case calculation, CIN
must be capable of supplying this average load current during the maximum on-time. CIN is calculated from:
where
• IOUT is the load current
• ton is the maximum on-time
•ΔVIN is the allowable ripple voltage at VIN (12)
CIN3’s purpose is to help avoid transients and ringing due to long lead inductance at the VIN pin. A low ESR 0.1
µF ceramic chip capacitor located close to the LMR24210 is recommended.
CBST:A 33 nF high quality ceramic capacitor with low ESR is recommended for CBST since it supplies a surge
current to charge the main MOSFET gate driver at turn-on. Low ESR also helps ensure a complete recharge
during each off-time.
CSS:The capacitor at the SS pin determines the soft-start time, i.e. the time for the reference voltage at the
regulation comparator and the output voltage to reach their final value. The time is determined from the following
equation:
(13)
CFB:If the output voltage is higher than 1.6V, CFB is needed in the Discontinuous Conduction Mode to reduce the
output ripple. The recommended value for CFB is 10 nF.
PC BOARD LAYOUT
The LMR24210 regulation, over-voltage, and current limit comparators are very fast and may respond to short
duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as
possible, and all external components must be as close to their associated pins of the LMR24210 as possible.
Refer to the Simplified Functional Block Diagram, the loop formed by CIN, the main and synchronous MOSFET
internal to the LMR24210, and the PGND pin should be as small as possible. The connection from the PGND pin
to CIN should be as short and direct as possible. Vias should be added to connect the ground of CIN to a ground
plane, located as close to the capacitor as possible. The bootstrap capacitor CBST should be connected as close
to the SW and BST pins as possible, and the connecting traces should be thick. The feedback resistors and
capacitor RFB1, RFB2, and CFB should be close to the FB pin. A long trace running from VOUT to RFB1 is generally
acceptable since this is a low impedance node. Ground RFB2 directly to the AGND pin. The output capacitor COUT
should be connected close to the load and tied directly to the ground plane. The inductor L should be connected
close to the SW pin with as short a trace as possible to reduce the potential for EMI (electromagnetic
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
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LMR24210
SNVS738G –OCTOBER 2011–REVISED APRIL 2013
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interference) generation. If it is expected that the internal dissipation of the LMR24210 will produce excessive
junction temperature during normal operation, making good use of the PC board’s ground plane can help
considerably to dissipate heat. Additionally the use of thick traces, where possible, can help conduct heat away
from the LMR24210. Judicious positioning of the PC board within the end product, along with the use of any
available air flow (forced or natural convection) can help reduce the junction temperature.
Package Considerations
The die has exposed edges and can be sensitive to ambient light. For applications with direct high intensitiy
ambient red, infrared, LED or natural light it is recommended to have the device shielded from the light source to
avoid abnormal behavior.
Figure 27. Typical Application Schematic for VOUT = 3.3V
Figure 28. Typical Application Schematic for VOUT = 0.8V
18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
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LMR24210
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SNVS738G –OCTOBER 2011–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMR24210
PACKAGE OPTION ADDENDUM
www.ti.com 21-Jul-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMR24210TL/NOPB ACTIVE DSBGA YPA 28 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 SJ5B
LMR24210TLX/NOPB ACTIVE DSBGA YPA 28 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 SJ5B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 21-Jul-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMR24210TL/NOPB DSBGA YPA 28 250 178.0 12.4 2.64 3.84 0.76 8.0 12.0 Q1
LMR24210TLX/NOPB DSBGA YPA 28 1000 178.0 12.4 2.64 3.84 0.76 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR24210TL/NOPB DSBGA YPA 28 250 210.0 185.0 35.0
LMR24210TLX/NOPB DSBGA YPA 28 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-May-2013
Pack Materials-Page 2
MECHANICAL DATA
YPA0028
www.ti.com
TLC28XXX (Rev A)
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
4215064/A 12/12
NOTES:
0.600
±0.075
E
D
D: Max =
E: Max =
3.676 mm, Min =
2.48 mm, Min =
3.615 mm
2.419 mm
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