XC2V500-6FGG256I - Xilinx, Inc.

trademarks are the property of their respective owners.

DS031 (v3.5) November 5, 2007 www.xilinx.com

Product Specification 1

Module 1:

Introduction and Overview

7pages

• Summary of Features

• General Description

• Architecture

• Device/Package Combinations and Maximum I/O

• Ordering Examples

Module 2:

Functional Description

41 pages

• Detailed Description

- Input/Output Blocks (IOBs)

- Digitally Controlled Impedance (DCI)

- Configurable Logic Blocks (CLBs)

- 18-Kb Block SelectRAM™ Resources

- 18-Bit x 18-Bit Multipliers

- Global Clock Multiplexer Buffers

- Digital Clock Manager (DCM)

•Routing

• Creating a Design

• Configuration

Module 3:

DC and Switching Characteristics

43 pages

• Electrical Characteristics

• Performance Characteristics

• Switching Characteristics

• Pin-to-Pin Output Parameter Guidelines

• Pin-to-Pin Input Parameter Guidelines

• DCM Timing Parameters

• Source-Synchronous Switching Characteristics

Module 4:

Pinout Information

226 pages

• Pin Definitions

•Pinout Tables

- CS144/CSG144 Chip-Scale BGA Package

- FG256/FGG256 Fine-Pitch BGA Package

- FG456/FGG456 Fine-Pitch BGA Package

- FG676/FGG676 Fine-Pitch BGA Package

- BG575/BGG575 Standard BGA Package

- BG728/BGG728 Standard BGA Package

- FF896 Flip-Chip Fine-Pitch BGA Package

- FF1152 Flip-Chip Fine-Pitch BGA Package

- FF1517 Flip-Chip Fine-Pitch BGA Package

- BF957Flip-Chip BGA Package

IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision

History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.

1Virtex-II Platform FPGAs:

Complete Data Sheet

DS031 (v3.5) November 5, 2007 Product Specification

trademarks are the property of their respective owners.

DS031-1 (v3.5) November 5, 2007 www.xilinx.com Module 1 of 4

Product Specification 1

Summary of Virtex-II™ Features

• Industry First Platform FPGA Solution

• IP-Immersion Architecture

- Densities from 40K to 8M system gates

- 420 MHz internal clock speed (Advance Data)

- 840+ Mb/s I/O (Advance Data)

• SelectRAM™ Memory Hierarchy

- 3 Mb of dual-port RAM in 18 Kbit block SelectRAM

resources

- Up to 1.5 Mb of distributed SelectRAM resources

• High-Performance Interfaces to External Memory

- DRAM interfaces

· SDR / DDR SDRAM

·Network FCRAM

· Reduced Latency DRAM

- SRAM interfaces

· SDR / DDR SRAM

· QDR™ SRAM

- CAM interfaces

• Arithmetic Functions

- Dedicated 18-bit x 18-bit multiplier blocks

- Fast look-ahead carry logic chains

• Flexible Logic Resources

- Up to 93,184 internal registers / latches with Clock

Enable

- Up to 93,184 look-up tables (LUTs) or cascadable

16-bit shift registers

- Wide multiplexers and wide-input function support

- Horizontal cascade chain and sum-of-products

support

- Internal 3-state bussing

• High-Performance Clock Management Circuitry

- Up to 12 DCM (Digital Clock Manager) modules

· Precise clock de-skew

· Flexible frequency synthesis

· High-resolution phase shifting

- 16 global clock multiplexer buffers

• Active Interconnect Technology

- Fourth generation segmented routing structure

- Predictable, fast routing delay, independent of

fanout

• SelectIO™-Ultra Technology

- Up to 1,108 user I/Os

- 19 single-ended and six differential standards

- Programmable sink current (2 mA to 24 mA) per I/O

- Digitally Controlled Impedance (DCI) I/O: on-chip

termination resistors for single-ended I/O standards

- PCI-X compatible (133 MHz and 66 MHz) at 3.3V

- PCI compliant (66 MHz and 33 MHz) at 3.3V

- CardBus compliant (33 MHz) at 3.3V

- Differential Signaling

· 840 Mb/s Low-Voltage Differential Signaling I/O

(LVDS) with current mode drivers

· Bus LVDS I/O

· Lightning Data Transport (LDT) I/O with current

driver buffers

· Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O

· Built-in DDR input and output registers

- Proprietary high-performance SelectLink

Technology

· High-bandwidth data path

· Double Data Rate (DDR) link

· Web-based HDL generation methodology

• Supported by Xilinx Foundation™ and Alliance

Series™ Development Systems

- Integrated VHDL and Verilog design flows

- Compilation of 10M system gates designs

- Internet Team Design (ITD) tool

• SRAM-Based In-System Configuration

- Fast SelectMAP configuration

- Triple Data Encryption Standard (DES) security

option (Bitstream Encryption)

- IEEE 1532 support

- Partial reconfiguration

- Unlimited reprogrammability

- Readback capability

• 0.15 µm 8-Layer Metal Process with 0.12 µm

High-Speed Transistors

•1.5V (V

CCINT) Core Power Supply, Dedicated 3.3V

VCCAUX Auxiliary and VCCO I/O Power Supplies

• IEEE 1149.1 Compatible Boundary-Scan Logic

Support

• Flip-Chip and Wire-Bond Ball Grid Array (BGA)

Packages in Three Standard Fine Pitches (0.80 mm,

1.00 mm, and 1.27 mm)

• Wire-Bond BGA Devices Available in Pb-Free

Packaging (www.xilinx.com/pbfree)

• 100% Factory Tested

7Virtex-II Platform FPGAs:

Introduction and Overview

DS031-1 (v3.5) November 5, 2007 Product Specification

Virtex-II Platform FPGAs: Introduction and Overview

DS031-1 (v3.5) November 5, 2007 www.xilinx.com Module 1 of 4

Product Specification 2

General Description

The Virtex-II family is a platform FPGA developed for high

performance from low-density to high-density designs that

are based on IP cores and customized modules. The family

delivers complete solutions for telecommunication, wire-

less, networking, video, and DSP applications, including

PCI, LVDS, and DDR interfaces.

The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal

process and the Virtex-II architecture are optimized for high

speed with low power consumption. Combining a wide vari-

ety of flexible features and a large range of densities up to

10 million system gates, the Virtex-II family enhances pro-

grammable logic design capabilities and is a powerful alter-

native to mask-programmed gates arrays. As shown in

Table 1, the Virtex-II family comprises 11 members, ranging

from 40K to 8M system gates.

Packaging

Offerings include ball grid array (BGA) packages with

0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra-

ditional wire-bond interconnects, flip-chip interconnect is

used in some of the BGA offerings. The use of flip-chip

interconnect offers more I/Os than is possible in wire-bond

versions of the similar packages. Flip-chip construction

offers the combination of high pin count with high thermal

capacity.

Wire-bond packages CS, FG, and BG are optionally avail-

abe in Pb-free versions CSG, FGG, and BGG. See Virtex-II

Ordering Examples, page 6.

Table 2 shows the maximum number of user I/Os available.

The Virtex-II device/package combination table (Ta b l e 6 at

the end of this section) details the maximum number of I/Os

for each device and package using wire-bond or flip-chip

technology.

Table 1: Virtex-II Field-Programmable Gate Array Family Members

Device

System

Gates

CLB

(1 CLB = 4 slices = Max 128 bits)

Multiplier

Blocks

SelectRAM Blocks

DCMs

Max I/O

Pads(1)

Array

Row x Col. Slices

Maximum

Distributed

RAM Kbits

18 Kbit

Blocks

Max RAM

(Kbits)

XC2V40 40K 8 x 8 256 8 4 4 72 4 88

XC2V80 80K 16 x 8 512 16 8 8 144 4 120

XC2V250 250K 24 x 16 1,536 48 24 24 432 8 200

XC2V500 500K 32 x 24 3,072 96 32 32 576 8 264

XC2V1000 1M 40 x 32 5,120 160 40 40 720 8 432

XC2V1500 1.5M 48 x 40 7,680 240 48 48 864 8 528

XC2V2000 2M 56 x 48 10,752 336 56 56 1,008 8 624

XC2V3000 3M 64 x 56 14,336 448 96 96 1,728 12 720

XC2V4000 4M 80 x 72 23,040 720 120 120 2,160 12 912

XC2V6000 6M 96 x 88 33,792 1,056 144 144 2,592 12 1,104

XC2V8000 8M 112 x 104 46,592 1,456 168 168 3,024 12 1,108

Notes:

1. See details in Table 2, “Maximum Number of User I/O Pads”.

Table 2: Maximum Number of User I/O Pads

Device Wire-Bond Flip-Chip

XC2V40 88 -

XC2V80 120 -

XC2V250 200 -

XC2V500 264 -

XC2V1000 328 432

XC2V1500 392 528

XC2V2000 - 624

XC2V3000 516 720

XC2V4000 - 912

XC2V6000 - 1,104

XC2V8000 - 1,108

Virtex-II Platform FPGAs: Introduction and Overview

DS031-1 (v3.5) November 5, 2007 www.xilinx.com Module 1 of 4

Product Specification 3

Architecture

Virtex-II Array Overview

Virtex-II devices are user-programmable gate arrays with

various configurable elements. The Virtex-II architecture is

optimized for high-density and high-performance logic

designs. As shown in Figure 1, the programmable device is

comprised of input/output blocks (IOBs) and internal

configurable logic blocks (CLBs).

Programmable I/O blocks provide the interface between

package pins and the internal configurable logic. Most

popular and leading-edge I/O standards are supported by

the programmable IOBs.

The internal configurable logic includes four major elements

organized in a regular array.

• Configurable Logic Blocks (CLBs) provide functional

elements for combinatorial and synchronous logic,

including basic storage elements. BUFTs (3-state

buffers) associated with each CLB element drive

dedicated segmentable horizontal routing resources.

• Block SelectRAM memory modules provide large

18 Kbit storage elements of dual-port RAM.

• Multiplier blocks are 18-bit x 18-bit dedicated

multipliers.

• DCM (Digital Clock Manager) blocks provide

self-calibrating, fully digital solutions for clock

distribution delay compensation, clock multiplication

and division, coarse- and fine-grained clock phase

shifting.

A new generation of programmable routing resources called

Active Interconnect Technology interconnects all of these

elements. The general routing matrix (GRM) is an array of

routing switches. Each programmable element is tied to a

switch matrix, allowing multiple connections to the general

routing matrix. The overall programmable interconnection is

hierarchical and designed to support high-speed designs.

All programmable elements, including the routing

resources, are controlled by values stored in static memory

cells. These values are loaded in the memory cells during

configuration and can be reloaded to change the functions

of the programmable elements.

Virtex-II Features

This section briefly describes Virtex-II features.

Input/Output Blocks (IOBs)

IOBs are programmable and can be categorized as follows:

• Input block with an optional single-data-rate or

double-data-rate (DDR) register

• Output block with an optional single-data-rate or DDR

directly or through a single or DDR register

• Bidirectional block (any combination of input and output

configurations)

These registers are either edge-triggered D-type flip-flops

or level-sensitive latches.

IOBs support the following single-ended I/O standards:

• LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)

• PCI-X compatible (133 MHz and 66 MHz) at 3.3V

• PCI compliant (66 MHz and 33 MHz) at 3.3V

• CardBus compliant (33 MHz) at 3.3V

• GTL and GTLP

Figure 1: Virtex-II Architecture Overview

Global Clock Mux

DCM DCM IOB

CLB

Programmable I/Os

Block SelectRAM Multiplier

Configurable Logic

DS031_28_100900

Virtex-II Platform FPGAs: Introduction and Overview

DS031-1 (v3.5) November 5, 2007 www.xilinx.com Module 1 of 4

Product Specification 4

• HSTL (Class I, II, III, and IV)

• SSTL (3.3V and 2.5V, Class I and II)

•AGP-2X

The digitally controlled impedance (DCI) I/O feature auto-

matically provides on-chip termination for each I/O element.

The IOB elements also support the following differential sig-

naling I/O standards:

•LVDS

• BLVDS (Bus LVDS)

•ULVDS

•LDT

• LVPECL

Two adjacent pads are used for each differential pair. Two or

four IOB blocks connect to one switch matrix to access the

routing resources.

Configurable Logic Blocks (CLBs)

CLB resources include four slices and two 3-state buffers.

Each slice is equivalent and contains:

• Two function generators (F & G)

• Two storage elements

• Arithmetic logic gates

• Large multiplexers

• Wide function capability

• Fast carry look-ahead chain

• Horizontal cascade chain (OR gate)

The function generators F & G are configurable as 4-input

look-up tables (LUTs), as 16-bit shift registers, or as 16-bit

distributed SelectRAM memory.

In addition, the two storage elements are either edge-trig-

gered D-type flip-flops or level-sensitive latches.

Each CLB has internal fast interconnect and connects to a

switch matrix to access general routing resources.

Block SelectRAM Memory

The block SelectRAM memory resources are 18 Kb of

dual-port RAM, programmable from 16K x 1 bit to 512 x 36

bits, in various depth and width configurations. Each port is

totally synchronous and independent, offering three

"read-during-write" modes. Block SelectRAM memory is

cascadable to implement large embedded storage blocks.

Supported memory configurations for dual-port and sin-

gle-port modes are shown in Tabl e 3 .

A multiplier block is associated with each SelectRAM mem-

ory block. The multiplier block is a dedicated 18 x 18-bit

multiplier and is optimized for operations based on the block

SelectRAM content on one port. The 18 x 18 multiplier can

be used independently of the block SelectRAM resource.

Read/multiply/accumulate operations and DSP filter struc-

tures are extremely efficient.

Both the SelectRAM memory and the multiplier resource

are connected to four switch matrices to access the general

routing resources.

Global Clocking

The DCM and global clock multiplexer buffers provide a

complete solution for designing high-speed clocking

schemes.

Up to 12 DCM blocks are available. To generate de-skewed

internal or external clocks, each DCM can be used to elimi-

nate clock distribution delay. The DCM also provides 90-,

180-, and 270-degree phase-shifted versions of its output

clocks. Fine-grained phase shifting offers high-resolution

phase adjustments in increments of 1/256 of the clock

period. Very flexible frequency synthesis provides a clock

output frequency equal to any M/D ratio of the input clock

frequency, where M and D are two integers. For the exact

timing parameters, see Virtex-II Electrical Characteristics.

Virtex-II devices have 16 global clock MUX buffers, with up

to eight clock nets per quadrant. Each global clock MUX

buffer can select one of the two clock inputs and switch

glitch-free from one clock to the other. Each DCM block is

able to drive up to four of the 16 global clock MUX buffers.

Routing Resources

The IOB, CLB, block SelectRAM, multiplier, and DCM ele-

ments all use the same interconnect scheme and the same

access to the global routing matrix. Timing models are

shared, greatly improving the predictability of the perfor-

mance of high-speed designs.

There are a total of 16 global clock lines, with eight available

per quadrant. In addition, 24 vertical and horizontal long

lines per row or column as well as massive secondary and

local routing resources provide fast interconnect. Virtex-II

buffered interconnects are relatively unaffected by net

fanout and the interconnect layout is designed to minimize

crosstalk.

Horizontal and vertical routing resources for each row or

column include:

• 24 long lines

• 120 hex lines

• 40 double lines

• 16 direct connect lines (total in all four directions)

Tabl e 3 : Dual-Port And Single-Port Configurations

16K x 1 bit 2K x 9 bits

8K x 2 bits 1K x 18 bits

4K x 4 bits 512 x 36 bits

Virtex-II Platform FPGAs: Introduction and Overview

DS031-1 (v3.5) November 5, 2007 www.xilinx.com Module 1 of 4

Product Specification 5

Boundary Scan

Boundary scan instructions and associated data registers

support a standard methodology for accessing and config-

uring Virtex-II devices that complies with IEEE standards

1149.1 — 1993 and 1532. A system mode and a test mode

are implemented. In system mode, a Virtex-II device per-

forms its intended mission even while executing non-test

boundary-scan instructions. In test mode, boundary-scan

test instructions control the I/O pins for testing purposes.

The Virtex-II Test Access Port (TAP) supports BYPASS,

PRELOAD, SAMPLE, IDCODE, and USERCODE non-test

instructions. The EXTEST, INTEST, and HIGHZ test instruc-

tions are also supported.

Configuration

Virtex-II devices are configured by loading data into internal

configuration memory, using the following five modes:

• Slave-serial mode

• Master-serial mode

• Slave SelectMAP mode

• Master SelectMAP mode

• Boundary-Scan mode (IEEE 1532)

A Data Encryption Standard (DES) decryptor is available

on-chip to secure the bitstreams. One or two triple-DES key

sets can be used to optionally encrypt the configuration

information.

Readback and Integrated Logic Analyzer

Configuration data stored in Virtex-II configuration memory

can be read back for verification. Along with the configura-

tion data, the contents of all flip-flops/latches, distributed

SelectRAM, and block SelectRAM memory resources can

be read back. This capability is useful for real-time debug-

ging.

The Integrated Logic Analyzer (ILA) core and software pro-

vides a complete solution for accessing and verifying

Virtex-II devices.

Virtex-II Device/Package Combinations

and Maximum I/O

Wire-bond and flip-chip packages are available. Ta ble 4 and

Tabl e 5 show the maximum possible number of user I/Os in

wire-bond and flip-chip packages, respectively. Ta ble 6

shows the number of available user I/Os for all device/pack-

age combinations.

• CS denotes wire-bond chip-scale ball grid array (BGA)

(0.80 mm pitch).

• CSG denotes Pb-free wire-bond chip-scale ball grid

array (BGA) (0.80 mm pitch).

• FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).

• FGG denotes Pb-free wire-bond fine-pitch BGA (1.00

mm pitch).

• BG denotes standard BGA (1.27 mm pitch).

• BGG denotes Pb-free standard BGA (1.27 mm pitch).

• FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).

• BF denotes flip-chip BGA (1.27 mm pitch).

The number of I/Os per package include all user I/Os except

the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,

PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,

DXP, and RSVD) and VBATT.

Tabl e 4 : Wire-Bond Packages Information

Package(1)

CS144/

CSG144

FG256/

FGG256

FG456/

FGG456

FG676/

FGG676

BG575/

BGG575

BG728/

BGG728

Pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27

Size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35

I/Os 92 172 324 484 408 516

Notes:

1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Ordering Examples (Module 1).

Tabl e 5 : Flip-Chip Packages Information

Package FF896 FF1152 FF1517 BF957

Pitch (mm) 1.00 1.00 1.00 1.27

Size (mm) 31 x 31 35 x 35 40 x 40 40 x 40

I/Os 624 824 1,108 684

Virtex-II Platform FPGAs: Introduction and Overview

DS031-1 (v3.5) November 5, 2007 www.xilinx.com Module 1 of 4

Product Specification 6

Virtex-II Ordering Examples

Tabl e 6 : Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information)

Package(1,2)

Available I/Os

XC2V

250

XC2V

500

XC2V

1000

XC2V

1500

XC2V

2000

XC2V

3000

XC2V

4000

XC2V

6000

XC2V

8000

CS144/CSG144889292--------

FG256/FGG25688120172172172------

FG456/FGG456--200264324------

FG676/FGG676 - - - - - 392 456 484 - - -

FF896 ----432528624----

FF1152 - - - - - - - 720 824 824 824

FF1517 - - - - - - - - 912 1,104 1,108

BG575/BGG575----328392408----

BG728/BGG728 - - - - - - - 516 - - -

BF957 - - - - - - 624 684 684 684 -

Notes:

1. All devices in a particular package are pinout (footprint) compatible. In addition, the FG456/FGG456 and FG676/FGG676 packages

are compatible, as are the FF896 and FF1152 packages.

2. Wire-bond packages CS144, FG256, FG456, FG676, BG575, and BG728 are also available in Pb-free versions CSG144, FGG256, FGG456,

FGG676, BGG575, and BGG728. See Virtex-II Ordering Examples for details on how to order.

Figure 2: Virtex-II Ordering Example. Regular Package

Example: XC2V1000-5FG456C

Device Type Temperature Range

C = Commercial (Tj = 0˚C to +85˚C)

I = Industrial (Tj = –40˚C to +100˚C)

Number of Pins

Package Type

Speed Grade

(-4, -5, -6)

DS031_35_033001

Figure 3: Virtex-II Ordering Example. Pb-Free Package

Example: XC2V3000-6BGG728C

Device Type Temperature Range

C = Commercial (Tj = 0˚C to +85˚C)

I = Industrial (Tj = –40˚C to +100˚C)

Number of Pins

Pb-Free Package

Package Type

Speed Grade

(-4, -5, -6)

DS031_35a_061804

Virtex-II Platform FPGAs: Introduction and Overview

DS031-1 (v3.5) November 5, 2007 www.xilinx.com Module 1 of 4

Product Specification 7

Revision History

This section records the change history for this module of the data sheet.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND

CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED

WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE

SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE

PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES

THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

Virtex-II Data Sheet

The Virtex-II Data Sheet contains the following modules:

•Virtex-II Platform FPGAs: Introduction and Overview

(Module 1)

•Virtex-II Platform FPGAs: Functional Description

(Module 2)

•Virtex-II Platform FPGAs: DC and Switching

Characteristics (Module 3)

•Virtex-II Platform FPGAs: Pinout Information

(Module 4)

Date Version Revision

11/07/00 1.0 Early access draft.

12/06/00 1.1 Initial release.

01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II

Switching Characteristics sections.

01/25/01 1.3 The data sheet was divided into four modules (per the current style standard).

04/02/01 1.5 Skipped v1.4 to sync up modules. Reverted to traditional double-column format.

07/30/01 1.6 Made minor changes to items listed under Summary of Virtex-II™ Features.

10/02/01 1.7 Minor edits.

07/16/02 1.8 Updated Virtex-II Device/Package Combinations shown in Tabl e 6 .

09/26/02 1.9 Updated Tabl e 2 and Ta b l e 6 to reflect supported Virtex-II Device/Package Combinations.

08/01/03 2.0 All Virtex-II devices and speed grades now Production. See Table 13, Module 3.

03/29/04 2.0.1 Recompiled for backward compatibility with Acrobat 4 and above. No content changes.

06/24/04 3.3 Added references to available Pb-free wire-bond packages. (Revision number advanced to

level of complete data sheet.)

03/01/05 3.4 No changes in Module 1 for this revision.

11/05/07 3.5 Updated copyright notice and legal disclaimer.

trademarks are the property of their respective owners.

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 1

Detailed Description

Input/Output Blocks (IOBs)

Virtex-II™ I/O blocks (IOBs) are provided in groups of two or

four on the perimeter of each device. Each IOB can be used

as input and/or output for single-ended I/Os. Two IOBs can

be used as a differential pair. A differential pair is always

connected to the same switch matrix, as shown in Figure 1.

IOB blocks are designed for high performances I/Os, sup-

porting 19 single-ended standards, as well as differential

signaling with LVDS, LDT, Bus LVDS, and LVPECL.

Note: Differential I/Os must use the same clock.

Supported I/O Standards

Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-

puts that support a wide variety of I/O signaling standards.

In addition to the internal supply voltage (VCCINT =1.5V),

output driver supply voltage (VCCO) is dependent on the I/O

standard (see Ta bl e 1 and Ta ble 2 ). An auxiliary supply volt-

age (VCCAUX = 3.3 V) is required, regardless of the I/O

standard used. For exact supply voltage absolute maximum

ratings, see DC Input and Output Levels in Module 3.

All of the user IOBs have fixed-clamp diodes to VCCO and to

ground. As outputs, these IOBs are not compatible or com-

pliant with 5V I/O standards. As inputs, these IOBs are not

normally 5V tolerant, but can be used with 5V I/O standards

when external current-limiting resistors are used. For more

details, see the “5V Tolerant I/Os“ Tech Topic at www.xil-

inx.com.

Tabl e 3 lists supported I/O standards with Digitally Con-

trolled Impedance. See Digitally Controlled Impedance

(DCI), page 8.

0Virtex-II Platform FPGAs:

Functional Description

DS031-2 (v3.5) November 5, 2007 Product Specification

Figure 1: Virtex-II Input/Output Tile

IOB

PAD4

IOB

PAD3

Differential Pair

IOB

PAD2

IOB

PAD1

Differential Pair

Switch

Matrix

DS031_30_101600

Tabl e 1 : Supported Single-Ended I/O Standards

IOSTANDARD

Attribute

Output

VCCO

Input

VCCO

Input

VREF

Board

Termination

Voltage (V TT)

LVTT L 3.3 3 .3 N/R (3) N/R

LVCMOS33 3.3 3.3 N/R N/R

LVCMOS25 2.5 2.5 N/R N/R

LVCMOS18 1.8 1.8 N/R N/R

LVCMOS15 1.5 1.5 N/R N/R

PCI33_3 3.3 3.3 N/R N/R

PCI66_3 3.3 3.3 N/R N/R

PCI-X 3.3 3.3 N/R N/R

GTL Note (1) Note (1) 0.8 1.2

GTLP Note (1) Note (1) 1.0 1.5

HSTL_I 1.5 N/R 0.75 0.75

HSTL_II 1.5 N/R 0.75 0.75

HSTL_III 1.5 N/R 0.9 1.5

HSTL_IV 1.5 N/R 0.9 1.5

HSTL_I_18 1.8 N/R 0.9 0.9

HSTL_II_18 1.8 N/R 0.9 0.9

HSTL_III _18 1.8 N/R 1.1 1.8

HSTL_IV_18 1.8 N/R 1.1 1.8

SSTL18_I(2) 1.8 N/R 0.9 0.9

SSTL18_II 1.8 N/R 0.9 0.9

SSTL2_I 2.5 N/R 1.25 1.25

SSTL2_II 2.5 N/R 1.25 1.25

SSTL3_I 3.3 N/R 1.5 1.5

SSTL3_II 3.3 N/R 1.5 1.5

AGP-2X/AGP 3.3 N/R 1.32 N/R

Notes:

1. VCCO of GTL or GTLP should not be lower than the termination

voltage or the voltage seen at the I/O pad. Example: If the pin High

level is 1.5V, connect VCCO to 1.5V.

2. SSTL18_I is not a JEDEC-supported standard.

3. N/R = no requirement.

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 2

Logic Resources

IOB blocks include six storage elements, as shown in

Figure 2.

Each storage element can be configured either as an

edge-triggered D-type flip-flop or as a level-sensitive latch.

On the input, output, and 3-state path, one or two DDR reg-

isters can be used.

Double data rate is directly accomplished by the two regis-

ters on each path, clocked by the rising edges (or falling

edges) from two different clock nets. The two clock signals

are generated by the DCM and must be 180 degrees out of

phase, as shown in Figure 3. There are two input, output,

and 3-state data signals, each being alternately clocked out.

Tabl e 2 : Supported Differential Signal I/O Standards

I/O Standard

Output

VCCO

Input

VCCO

Input

VREF

Output

VOD

LVPECL_33 3.3 N/R(1) N/R 0.490 - 1.220

LDT_25 2.5 N/R N/R 0.500 - 0.700

LVDS_33 3.3 N/R N/R 0.250 - 0.400

LVDS_25 2.5 N/R N/R 0.250 - 0.400

LVDSEXT_33 3.3 N/R N/R 0.440 - 0.820

LVDSEXT_25 2.5 N/R N/R 0.440 - 0.820

BLVDS_25 2.5 N/R N/R 0.250 - 0.450

ULVDS_25 2.5 N/R N/R 0.500 - 0.700

Notes:

1. N/R = no requirement.

Tabl e 3 : Supported DCI I/O Standards

I/O

Standard

Output

VCCO

Input

VCCO

Input

VREF

Termination

Type

LVDCI_33(1) 3.3 3.3 N/R(4) Series

LVDCI_DV2_33(1) 3.3 3.3 N/R Series

LVDCI_25(1) 2.5 2.5 N/R Series

LVDCI_DV2_25(1) 2.5 2.5 N/R Series

LVDCI_18(1) 1.8 1.8 N/R Series

LVDCI_DV2_18(1) 1.8 1.8 N/R Series

LVDCI_15(1) 1.5 1.5 N/R Series

LVDCI_DV2_15(1) 1.5 1.5 N/R Series

GTL_DCI 1.2 1.2 0.8 Single

GTLP_DCI 1.5 1.5 1.0 Single

HSTL_I_DCI 1.5 1.5 0.75 Split

HSTL_II_DCI 1.5 1.5 0.75 Split

HSTL_III_DCI 1.5 1.5 0.9 Single

HSTL_IV_DCI 1.5 1.5 0.9 Single

HSTL_I_DCI_18 1.8 1.8 0.9 Split

HSTL_II_DCI_18 1.8 1.8 0.9 Split

HSTL_III_DCI_18 1.8 1.8 1.1 Single

HSTL_IV_DCI_18 1.8 1.8 1.1 Single

SSTL18_I_DCI(3) 1.8 1.8 0.9 Split

SSTL18_II_DCI 1.8 1.8 0.9 Split

SSTL2_I_DCI(2) 2.5 2.5 1.25 Split

SSTL2_II_DCI(2) 2.5 2.5 1.25 Split

SSTL3_I_DCI(2) 3.3 3.3 1.5 Split

SSTL3_II_DCI(2) 3.3 3.3 1.5 Split

LVDS_25_DCI 2.5 2.5 N/R Split

LVDSEXT_25_DCI 2.5 2.5 N/R Split

Notes:

1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled

impedance buffers, matching the reference resistors or half of

the reference resistors.

2. These are SSTL compatible.

3. SSTL18_I is not a JEDEC-supported standard.

4. N/R = no requirement.

Figure 2: Virtex-II IOB Block

Reg

OCK1

Reg

OCK2

Reg

ICK1

Reg

ICK2

DDR mux Input

PAD

3-State

Reg

OCK1

Reg

OCK2

DDR mux

Output

IOB

DS031_29_100900

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 3

The DDR mechanism shown in Figure 3 can be used to mir-

ror a copy of the clock on the output. This is useful for prop-

agating a clock along the data that has an identical delay. It

is also useful for multiple clock generation, where there is a

unique clock driver for every clock load. Virtex-II devices

can produce many copies of a clock with very little skew.

Each group of two registers has a clock enable signal (ICE

for the input registers, OCE for the output registers, and

TCE for the 3-state registers). The clock enable signals are

active High by default. If left unconnected, the clock enable

for that storage element defaults to the active state.

Each IOB block has common synchronous or asynchronous

set and reset (SR and REV signals).

SR forces the storage element into the state specified by the

SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.

SRLOW forces a logic “0”. When SR is used, a second input

(REV) forces the storage element into the opposite state. The

reset condition predominates over the set condition. The ini-

tial state after configuration or global initialization state is

defined by a separate INIT0 and INIT1 attribute. By default,

the SRLOW attribute forces INIT0, and the SRHIGH attribute

forces INIT1.

For each storage element, the SRHIGH, SRLOW, INIT0,

and INIT1 attributes are independent. Synchronous or

asynchronous set / reset is consistent in an IOB block.

All the control signals have independent polarity. Any

inverter placed on a control input is automatically absorbed.

Each register or latch (independent of all other registers or

latches) (see Figure 4) can be configured as follows:

• No set or reset

• Synchronous set

• Synchronous reset

• Synchronous set and reset

• Asynchronous set (preset)

• Asynchronous reset (clear)

• Asynchronous set and reset (preset and clear)

The synchronous reset overrides a set, and an asynchro-

nous clear overrides a preset.

Figure 3: Double Data Rate Registers

CLK1

DDR MUX

FDDR

CLK2

(50/50 duty cycle clock)

CLOCK

CLK1

DDR MUX

DCM

FDDR

CLK2

180°0°

DS031_26_100900

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 4

Input/Output Individual Options

Each device pad has optional pull-up and pull-down in all

SelectI/O-Ultra configurations. Each device pad has

optional weak-keeper in LVTTL, LVCMOS, and PCI

SelectI/O-Ultra configurations, as illustrated in Figure 5.

Values of the optional pull-up and pull-down resistors are in

the range 10 - 60 KΩ, which is the specification for VCCO

when operating at 3.3V (from 3.0 to 3.6V only). The clamp

diode is always present, even when power is not.

The optional weak-keeper circuit is connected to each user

I/O pad. When selected, the circuit monitors the voltage on

the pad and weakly drives the pin High or Low. If the pin is

connected to a multiple-source signal, the weak-keeper

holds the signal in its last state if all drivers are disabled.

Maintaining a valid logic level in this way eliminates bus

chatter. An enabled pull-up or pull-down overrides the

weak-keeper circuit.

LVTTL sinks and sources current up to 24 mA. The current

is programmable for LVTTL and LVCMOS SelectI/O-Ultra

standards (see Tabl e 4 ). Drive-strength and slew-rate con-

trols for each output driver, minimize bus transients. For

LVDCI and LVDCI_DV2 standards, drive strength and

slew-rate controls are not available.

Figure 4: Register / Latch Configuration in an IOB Block

LATCH

SR REV

D1 Q1

CK1

LATCH

SR REV

FF1

FF2

DDR MUX

CK2

REV

(O/T) CLK1

(OQ or TQ)

(O/T) CE

(O/T) 1

(O/T) CLK2

(O/T) 2

Attribute INIT1

INIT0

SRHIGH

SRLOW

Attribute INIT1

INIT0

SRHIGH

SRLOW Reset Type

SYNC

ASYNC

DS031_25_110300

Shared

by all

registers

Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra

Standards

VCCO

Weak

Keeper

Program

Delay

OBUF

IBUF

Program

Current

Clamp

Diode

PAD

VCCAUX = 3.3V

DS031_23_022205

VCCINT = 1.5V

10KΩ –

60KΩ

10KΩ –

60KΩ

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 5

Figure 6 shows the SSTL2, SSTL3, and HSTL configura-

tions. HSTL can sink current up to 48 mA. (HSTL IV)

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. Virtex-II

uses two memory cells to control the configuration of an I/O

as an input. This is to reduce the probability of an I/O con-

figured as an input from flipping to an output when sub-

jected to a single event upset (SEU) in space applications.

Prior to configuration, all outputs not involved in configura-

tion are forced into their high-impedance state. The

pull-down resistors and the weak-keeper circuits are inac-

tive. The dedicated pin HSWAP_EN controls the pull-up

resistors prior to configuration. By default, HSWAP_EN is

set high, which disables the pull-up resistors on user I/O

pins. When HSWAP_EN is set low, the pull-up resistors are

activated on user I/O pins.

All Virtex-II IOBs support IEEE 1149.1 compatible Bound-

ary-Scan testing.

Input Path

The Virtex-II IOB input path routes input signals directly to

internal logic and / or through an optional input flip-flop or

latch, or through the DDR input registers. An optional delay

element at the D-input of the storage element eliminates

pad-to-pad hold time. The delay is matched to the internal

clock-distribution delay of the Virtex-II device, and when

used, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of the

low-voltage signaling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold voltage, VREF

. The need to supply VREF imposes

constraints on which standards can be used in the same

bank. See I/O banking description.

Output Path

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output and / or the

3-state signal can be routed to the buffer directly from the

internal logic or through an output / 3-state flip-flop or latch,

or through the DDR output / 3-state registers.

Each output driver can be individually programmed for a

wide range of low-voltage signaling standards. In most sig-

naling standards, the output High voltage depends on an

externally supplied VCCO voltage. The need to supply VCCO

imposes constraints on which standards can be used in the

same bank. See I/O banking description.

I/O Banking

Some of the I/O standards described above require VCCO

and VREF voltages. These voltages are externally supplied

and connected to device pins that serve groups of IOB

blocks, called banks. Consequently, restrictions exist about

which I/O standards can be combined within a given bank.

Eight I/O banks result from dividing each edge of the FPGA

into two banks, as shown in Figure 7 and Figure 8. Each

bank has multiple VCCO pins, all of which must be con-

nected to the same voltage. This voltage is determined by

the output standards in use.

Tabl e 4 : LVTTL and LVCMOS Programmable Currents (Sink and Source)

SelectI/O-Ultra Programmable Current (Worst-Case Guaranteed Minimum)

LVTTL 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA

LVCMOS33 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA

LVCMOS25 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA

LVCMOS18 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a

LVCMOS15 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a

Figure 6: SSTL or HSTL SelectI/O-Ultra Standards

VCCO

OBUF

VREF

Clamp

Diode

PAD

VCCAUX = 3.3V

VCCINT = 1.5V

DS031_24_100900

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 6

Some input standards require a user-supplied threshold

voltage (VREF), and certain user-I/O pins are automatically

configured as VREF inputs. Approximately one in six of the

I/O pins in the bank assume this role.

VREF pins within a bank are interconnected internally, and

consequently only one VREF voltage can be used within

each bank. However, for correct operation, all VREF pins in

the bank must be connected to the external reference volt-

age source.

The VCCO and the VREF pins for each bank appear in the

device pinout tables. Within a given package, the number of

VREF and VCCO pins can vary depending on the size of

device. In larger devices, more I/O pins convert to VREF

pins. Since these are always a superset of the VREF pins

used for smaller devices, it is possible to design a PCB that

permits migration to a larger device if necessary.

All VREF pins for the largest device anticipated must be con-

nected to the VREF voltage and not used for I/O. In smaller

devices, some VCCO pins used in larger devices do not con-

nect within the package. These unconnected pins can be

left unconnected externally, or, if necessary, they can be

connected to VCCO to permit migration to a larger device.

Rules for Combining I/O Standards in the Same Bank

The following rules must be obeyed to combine different

input, output, and bi-directional standards in the same bank:

1. Combining output standards only. Output standards

with the same output VCCO requirement can be

combined in the same bank.

Compatible example:

SSTL2_I and LVDS_25_DCI outputs

Incompatible example:

SSTL2_I (output VCCO = 2.5V) and

LVCMOS33 (output VCCO = 3.3V) outputs

2. Combining input standards only. Input standards

with the same input VCCO and input VREF requirements

can be combined in the same bank.

Compatible example:

LVCMOS15 and HSTL_IV inputs

Incompatible example:

LVCMOS15 (input VCCO = 1.5V) and

LVCMOS18 (input VCCO = 1.8V) inputs

Incompatible example:

HSTL_I_DCI_18 (VREF = 0.9V) and

HSTL_IV_DCI_18 (VREF = 1.1V) inputs

3. Combining input standards and output standards.

Input standards and output standards with the same

input VCCO and output VCCO requirement can be

combined in the same bank.

Compatible example:

LVDS_25 output and HSTL_I input

Incompatible example:

LVDS_25 output (output VCCO = 2.5V) and

HSTL_I_DCI_18 input (input VCCO = 1.8V)

4. Combining bi-directional standards with input or

output standards. When combining bi-directional I/O

with other standards, make sure the bi-directional

standard can meet rules 1 through 3 above.

5. Additional rules for combining DCI I/O standards.

a. No more than one Single Termination type (input or

output) is allowed in the same bank.

Incompatible example:

HSTL_IV_DCI input and HSTL_III_DCI input

b. No more than one Split Termination type (input or

output) is allowed in the same bank.

Incompatible example:

HSTL_I_DCI input and HSTL_II_DCI input

The implementation tools will enforce these design rules.

Tabl e 5 summarizes all standards and voltage supplies.

Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond

Packages (CS/CSG, FG/FGG, & BG/BGG)

Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip

Packages (FF & BF)

ug002_c2_014_112900

Bank 0 Bank 1

Bank 5 Bank 4

Bank 7

Bank 6

Bank 2

Bank 3

ds031_66_112900

Bank 1 Bank 0

Bank 4 Bank 5

Bank 2

Bank 3

Bank 7

Bank 6

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 7

Table 5: Summary of Voltage Supply Requirements for

All Input and Output Standards

I/O Standard

VCCO VREF Termination Type

Output Input Input Output Input

LVDS_33

3.3

N/R

N/R(1) N/R N/R

LVDSEXT_33 N/R N/R N/R

LVPECL_33 N/R N/R N/R

SSTL3_I 1.5 N/R N/R

SSTL3_II 1.5 N/R N/R

AGP 1.32 N/R N/R

LVT T L

3.3

N/R N/R N/R

LVCMOS33 N/R N/R N/R

LVDCI_33 N/R Series N/R

LVDCI_DV2_33 N/R Series N/R

PCI33_3 N/R N/R N/R

PCI66_3 N/R N/R N/R

PCIX N/R N/R N/R

SSTL3_I_DCI 1.5 N/R Split

SSTL3_II_DCI 1.5 Split Split

LVDS_25

2.5

N/R

N/R N/R N/R

LVDSEXT_25 N/R N/R N/R

LDT_25 N/R N/R N/R

ULVDS_25 N/R N/R N/R

BLVDS_25 N/R N/R N/R

SSTL2_I 1.25 N/R N/R

SSTL2_II 1.25 N/R N/R

LVC M O S25

2.5

N/R N/R N/R

LVDCI_25 N/R Series N/R

LVDCI_DV2_25 N/R Series N/R

LVDS_25_DCI N/R N/R Split

LVDSEXT_25_DC

IN/R N/R Split

SSTL2_I_DCI 1.25 N/R Split

SSTL2_II_DCI 1.25 Split Split

HSTL_III_18

1.8

N/R

1.1 N/R N/R

HSTL_IV_18 1.1 N/R N/R

HSTL_I_18 0.9 N/R N/R

HSTL_II_18 0.9 N/R N/R

SSTL18_I 0.9 N/R N/R

SSTL18_II 0.9 N/R N/R

LVCM O S18

1.8

N/R N/R N/R

LVDCI_18 N/R Series N/R

LVDCI_DV2_18 N/R Series N/R

HSTL_III_DCI_18 1.1 N/R Single

HSTL_IV_DCI_18 1.1 Single Single

HSTL_I_DCI_18 0.9 N/R Split

HSTL_II_DCI_18 0.9 Split Split

SSTL18_I_DCI 0.9 N/R Split

SSTL18_II_DCI 0.9 Split Split

HSTL_III

1.5

N/R

0.9 N/R N/R

HSTL_IV 0.9 N/R N/R

HSTL_I 0.75 N/R N/R

HSTL_II 0.75 N/R N/R

LVCM O S15

1.5

N/R N/R N/R

LVDCI_15 N/R Series N/R

LVDCI_DV2_15 N/R Series N/R

GTLP_DCI 1 Single Single

HSTL_III_DCI 0.9 N/R Single

HSTL_IV_DCI 0.9 Single Single

HSTL_I_DCI 0.75 N/R Split

HSTL_II_DCI 0.75 Split Split

GTL_DCI 1.2 1.2 0.8 Single Single

GTLP

N/R N/R

1N/RN/R

GTL 0.8 N/R N/R

Notes:

1. N/R = no requirement.

Tabl e 5 : Summary of Voltage Supply Requirements for

All Input and Output Standards (Continued)

I/O Standard

VCCO VREF Termination Type

Output Input Input Output Input

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 8

Digitally Controlled Impedance (DCI)

Today’s chip output signals with fast edge rates require ter-

mination to prevent reflections and maintain signal integrity.

High pin count packages (especially ball grid arrays) can

not accommodate external termination resistors.

Virtex-II XCITE DCI provides controlled impedance drivers

and on-chip termination for single-ended and differential

I/Os. This eliminates the need for external resistors, and

improves signal integrity. The DCI feature can be used on

any IOB by selecting one of the DCI I/O standards.

When applied to inputs, DCI provides input parallel termina-

tion. When applied to outputs, DCI provides controlled

impedance drivers (series termination) or output parallel

termination.

DCI operates independently on each I/O bank. When a DCI

I/O standard is used in a particular I/O bank, external refer-

ence resistors must be connected to two dual-function pins

on the bank. These resistors, voltage reference of N transis-

tor (VRN) and the voltage reference of P transistor (VRP)

are shown in Figure 9.

When used with a terminated I/O standard, the value of

resistors are specified by the standard (typically 50Ω).

When used with a controlled impedance driver, the resistors

set the output impedance of the driver within the specified

range (25Ω to 100Ω). For all series and parallel termina-

tions listed in Ta bl e 6 and Ta bl e 7 , the reference resistors

must have the same value for any given bank. One percent

resistors are recommended.

The DCI system adjusts the I/O impedance to match the two

external reference resistors, or half of the reference resis-

tors, and compensates for impedance changes due to volt-

age and/or temperature fluctuations. The adjustment is

done by turning parallel transistors in the IOB on or off.

Controlled Impedance Drivers (Series Term.)

DCI can be used to provide a buffer with a controlled output

impedance. It is desirable for this output impedance to

match the transmission line impedance (Z0). Virtex-II input

buffers also support LVDCI and LVDCI_DV2 I/O standards.

Controlled Impedance Drivers (Parallel)

DCI also provides on-chip termination for SSTL3, SSTL2,

HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or

transmitters on bidirectional lines.

Ta b l e 7 and Ta bl e 8 list the on-chip parallel terminations avail-

able in Virtex-II devices. VCCO must be set according to

Ta b l e 3 . Note that there is a VCCO requirement for GTL_DCI

and GTLP_DCI, due to the on-chip termination resistor.

Figure 9: DCI in a Virtex-II Bank

DS031_50_101200

VCCO

GND

DCI

VRN

VRP

1 Bank

RREF (1%)

Figure 10: Internal Series Termination

Tabl e 6 : SelectI/O-Ultra Controlled Impedance Buffers

VCCO DCI DCI Half Impedance

3.3 V LVDCI_33 LVDCI_DV2_33

2.5 V LVDCI_25 LVDCI_DV2_25

1.8 V LVDCI_18 LVDCI_DV2_18

1.5 V LVDCI_15 LVDCI_DV2_15

Tabl e 7 : SelectI/O-Ultra Buffers With On-Chip Parallel

Termination

I/O Standard

Description

IOSTANDARD Attribute

External

Termination

On-Chip

Termination

SSTL3 Class I SSTL3_I SSTL3_I_DCI(1)

SSTL3 Class II SSTL3_II SSTL3_II_DCI(1)

SSTL2 Class I SSTL2_I SSTL2_I_DCI(1)

SSTL2 Class II SSTL2_II SSTL2_II_DCI(1)

HSTL Class I HSTL_I HSTL_I_DCI

HSTL Class II HSTL_II HSTL_II_DCI

HSTL Class III HSTL_III HSTL_III_DCI

HSTL Class IV HSTL_IV HSTL_IV_DCI

GTL GTL GTL_DCI

GTLP GTLP GTLP_DCI

Notes:

1. SSTL-compatible

IOB

Virtex-II DCI

DS031_51_110600

VCCO = 3.3 V, 2.5 V, 1.8 V or 1.5 V

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 9

Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O

standards. For a complete list, see the Virtex-II Platform FPGA User Guide.

Tabl e 8 : SelectI/O-Ultra Differential Buffers With On-Chip Termination

I/O Standard Description

IOSTANDARD Attribute

External Termination On-Chip Termination

LVDS 2.5V LVDS_25 LVDS_25_DCI

LVDS Extended 2.5V LVDSEXT_25 LVDSEXT_25_DCI

Figure 11: HSTL DCI Usage Examples

Virtex-II DCI

VCCO VCCO

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO/2 VCCO/2

Virtex-II DCI

VCCO VCCO/2

Virtex-II DCI

VCCO/2

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

DS031_65a_100201

Conventional

DCI Transmit

Conventional

Receive

Conventional

Transmit

DCI Receive

DCI Transmit

DCI Receive

Bidirectional

Reference

Resistor

Recommended

(1)

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

HSTL_I HSTL_II HSTL_III HSTL_IV

N/A N/A

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO/2

Virtex-II DCI

VCCO/2

Virtex-II DCI

VCCO

Virtex-II DCI Virtex-II DCI

VCCO

Z0Z0

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Note:

1. Z0 is the recommended PCB trace impedance.

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 10

Figure 12 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O

standards. For a complete list, see the Virtex-II Platform FPGA User Guide.

Figure 12: SSTL DCI Usage Examples

DS031_65b_112502

Conventional

DCI Transmit

Conventional

Receive

Conventional

Transmit

DCI Receive

DCI Transmit

DCI Receive

Bidirectional

Reference

Resistor

Recommended

(2)

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

VRN = VRP = R = Z0

50 Ω

SSTL2_I SSTL2_II SSTL3_I SSTL3_II

N/A N/A

Virtex-II DCI

CCO

R/2

VCCO/2 VCCO/2

R/2

VCCO/2 VCCO/2

R/2

CCO

R/2

VCCO/2

R/2

Virtex-II DCI

VCCO

VCCO/2

R/2

Virtex-II DCI

VCCO

R/2

Virtex-II DCI

VCCO

R/2

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO VCCO/2

Virtex-II DCI

VCCO VCCO/2

Virtex-II DCI

VCCO/2

Z0Z0Z0

Virtex-II DCI

CCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

25Ω

(1)

Notes:

1. The SSTL-compatible 25Ω series resistor is accounted for in the DCI buffer, and it is not DCI controlled.

2. Z0 is the recommended PCB trace impedance.

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 11

Figure 13 provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list,

see the Virtex-II Platform FPGA User Guide.

Figure 13: LVDS DCI Usage Examples

DS031_65c_022103

Conventional

Transmit

DCI Receive

Reference

Resistor

Recommended

VRN = VRP = R = Z0

50 Ω

LVDS_DCI and LVDSEXT_DCI Receiver

Virtex-II

LVDS DCI

VCCO

Virtex-II

LVDS

NOTE: Only LVDS25_DCI is supported (VCCO = 2.5V only)

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 12

Configurable Logic Blocks (CLBs)

The Virtex-II configurable logic blocks (CLB) are organized

in an array and are used to build combinatorial and synchro-

nous logic designs. Each CLB element is tied to a switch

matrix to access the general routing matrix, as shown in

Figure 14. A CLB element comprises 4 similar slices, with

fast local feedback within the CLB. The four slices are split

in two columns of two slices with two independent carry

logic chains and one common shift chain.

Slice Description

Each slice includes two 4-input function generators, carry

logic, arithmetic logic gates, wide function multiplexers and

two storage elements. As shown in Figure 15, each 4-input

function generator is programmable as a 4-input LUT, 16

bits of distributed SelectRAM memory, or a 16-bit vari-

able-tap shift register element.

The output from the function generator in each slice drives

both the slice output and the D input of the storage element.

Figure 16 shows a more detailed view of a single slice.

Configurations

Look-Up Table

Virtex-II function generators are implemented as 4-input

look-up tables (LUTs). Four independent inputs are pro-

vided to each of the two function generators in a slice (F and

G). These function generators are each capable of imple-

menting any arbitrarily defined boolean function of four

inputs. The propagation delay is therefore independent of

the function implemented. Signals from the function gener-

ators can exit the slice (X or Y output), can input the XOR

dedicated gate (see arithmetic logic), or input the carry-logic

multiplexer (see fast look-ahead carry logic), or feed the D

input of the storage element, or go to the MUXF5 (not

shown in Figure 16).

In addition to the basic LUTs, the Virtex-II slice contains

logic (MUXF5 and MUXFX multiplexers) that combines

function generators to provide any function of five, six,

seven, or eight inputs. The MUXFX are either MUXF6,

MUXF7 or MUXF8 according to the slice considered in the

CLB. Selected functions up to nine inputs (MUXF5 multi-

plexer) can be implemented in one slice. The MUXFX can

also be a MUXF6, MUXF7, or MUXF8 multiplexers to map

any functions of six, seven, or eight inputs and selected

wide logic functions.

The storage elements in a Virtex-II slice can be configured

either as edge-triggered D-type flip-flops or as level-sensi-

tive latches. The D input can be directly driven by the X or Y

output via the DX or DY input, or by the slice inputs bypass-

ing the function generators via the BX or BY input. The clock

enable signal (CE) is active High by default. If left uncon-

nected, the clock enable for that storage element defaults to

the active state.

In addition to clock (CK) and clock enable (CE) signals,

each slice has set and reset signals (SR and BY slice

inputs). SR forces the storage element into the state speci-

fied by the attribute SRHIGH or SRLOW. SRHIGH forces a

logic “1” when SR is asserted. SRLOW forces a logic “0”.

When SR is used, a second input (BY) forces the storage

element into the opposite state. The reset condition is pre-

dominant over the set condition. (See Figure 17.)

The initial state after configuration or global initial state is

defined by a separate INIT0 and INIT1 attribute. By default,

setting the SRLOW attribute sets INIT0, and setting the

SRHIGH attribute sets INIT1. For each slice, set and reset

can be set to be synchronous or asynchronous. Virtex-II

devices also have the ability to set INIT0 and INIT1 indepen-

dent of SRHIGH and SRLOW.

The control signals clock (CLK), clock enable (CE) and

set/reset (SR) are common to both storage elements in one

slice. All of the control signals have independent polarity. Any

inverter placed on a control input is automatically absorbed.

Figure 14: Virtex-II CLB Element

Figure 15: Virtex-II Slice Configuration

Slice

X1Y1

Slice

X1Y0

Slice

X0Y1

Slice

X0Y0

Fast

Connects

to neighbors

Switch

Matrix

DS031_32_101600

SHIFT

CIN

COUT

TBUF X0Y1 COUT

CIN

TBUF X0Y0

MUXF5

MUXFx

SRL16

RAM16

LUT

Arithmetic Logic

LUT

DS031_31_100900

SRL16

RAM16

ORCY

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 13

Figure 16: Virtex-II Slice (Top Half)

SOPIN

G3 A3

G2 A2

G1 A1

WG4 WG4

WG3 WG3

WG2 WG2

WG1

Dual-Port

LUT

LATCH

RAM

ROM

Shift-Reg

MC15

REV

PROD

CECE

CKCLK

MUXCY YB

DIG

MUXCY

SOPOUT

DYMUX

GYMUX

YBMUX

ORCY

WSG

WE[2:0]

SHIFTOUT

CYOG

XORG

CLK

WSF

ALTDIG

CLK

SLICEWE[2:0]

MULTAND

Shared between

x & y Registers

SHIFTIN COUT

CIN DS031_01_112502

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 14

The set and reset functionality of a register or a latch can be

configured as follows:

• No set or reset

• Synchronous set

• Synchronous reset

• Synchronous set and reset

• Asynchronous set (preset)

• Asynchronous reset (clear)

• Asynchronous set and reset (preset and clear)

The synchronous reset has precedence over a set, and an

asynchronous clear has precedence over a preset.

Distributed SelectRAM Memory

Each function generator (LUT) can implement a 16 x 1-bit

synchronous RAM resource called a distributed SelectRAM

element. The SelectRAM elements are configurable within

a CLB to implement the following:

• Single-Port 16 x 8 bit RAM

• Single-Port 32 x 4 bit RAM

• Single-Port 64 x 2 bit RAM

• Single-Port 128 x 1 bit RAM

• Dual-Port 16 x 4 bit RAM

• Dual-Port 32 x 2 bit RAM

• Dual-Port 64 x 1 bit RAM

Distributed SelectRAM memory modules are synchronous

(write) resources. The combinatorial read access time is

extremely fast, while the synchronous write simplifies

high-speed designs. A synchronous read can be imple-

mented with a storage element in the same slice. The dis-

tributed SelectRAM memory and the storage element share

the same clock input. A Write Enable (WE) input is active

High, and is driven by the SR input.

Tabl e 9 shows the number of LUTs (2 per slice) occupied by

each distributed SelectRAM configuration.

For single-port configurations, distributed SelectRAM mem-

ory has one address port for synchronous writes and asyn-

chronous reads.

For dual-port configurations, distributed SelectRAM mem-

ory has one port for synchronous writes and asynchronous

reads and another port for asynchronous reads. The func-

tion generator (LUT) has separated read address inputs

(A1, A2, A3, A4) and write address inputs (WG1/WF1,

WG2/WF2, WG3/WF3, WG4/WF4).

In single-port mode, read and write addresses share the

same address bus. In dual-port mode, one function genera-

tor (R/W port) is connected with shared read and write

addresses. The second function generator has the A inputs

(read) connected to the second read-only port address and

the W inputs (write) shared with the first read/write port

address.

Figure 17: Register / Latch Configuration in a Slice

FFY

LATCH

SR REV

FFX

LATCH

SR REV

CLK

Attribute

INIT1

INIT0

SRHIGH

SRLOW

Attribute

INIT1

INIT0

SRHIGH

SRLOW

Reset Type

SYNC

ASYNC

DS031_22_110600

Tabl e 9 : Distributed SelectRAM Configurations

RAM Number of LUTs

16 x 1S 1

16 x 1D 2

32 x 1S 2

32 x 1D 4

64 x 1S 4

64 x 1D 8

128 x 1S 8

Notes:

1. S = single-port configuration; D = dual-port configuration

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 15

Figure 18, Figure 19, and Figure 20 illustrate various exam-

ple configurations.

Similar to the RAM configuration, each function generator

(LUT) can implement a 16 x 1-bit ROM. Five configurations

are available: ROM16x1, ROM32x1, ROM64x1,

ROM128x1, and ROM256x1. The ROM elements are cas-

cadable to implement wider or/and deeper ROM. ROM con-

tents are loaded at configuration. Tabl e 1 0 shows the

number of LUTs occupied by each configuration.

Figure 18: Distributed SelectRAM (RAM16x1S)

Figure 19: Single-Port Distributed SelectRAM

(RAM32x1S)

A[3:0]

DIWS

WSG

WCLK

RAM 16x1S

RAM

A[4:1]

WG[4:1]

Output

Registered

Output

(optional)

(SR)

(BY)

DS031_02_100900

A[3:0]

WSG

F5MUX

WCLK

RAM 32x1S

WE0

WSF

DIWS

RAM

G[4:1]

A[4]

WG[4:1]

DIWS

RAM

F[4:1]

WF[4:1]

Output

Registered

Output

(optional)

(SR)

(BY)

(BX)

DS031_03_110100

Figure 20: Dual-Port Distributed SelectRAM

(RAM16x1D)

Table 10: ROM Configuration

ROM Number of LUTs

16 x 1 1

32 x 1 2

64 x 1 4

128 x 1 8 (1 CLB)

256 x 1 16 (2 CLBs)

A[3:0]

WSG

WCLK

RAM 16x1D

DIWS

RAM

G[4:1]

WG[4:1]

dual_port

RAM

dual_port

(BY)

DPRA[3:0]

SPO

A[3:0]

WSG

DIWS

G[4:1]

WG[4:1]

DPO

DS031_04_110100

(SR)

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 16

Shift Registers

Each function generator can also be configured as a 16-bit

shift register. The write operation is synchronous with a

clock input (CLK) and an optional clock enable, as shown in

Figure 21. A dynamic read access is performed through the

4-bit address bus, A[3:0]. The configurable 16-bit shift regis-

ter cannot be set or reset. The read is asynchronous, how-

ever the storage element or flip-flop is available to

implement a synchronous read. The storage element

should always be used with a constant address. For exam-

ple, when building an 8-bit shift register and configuring the

addresses to point to the 7th bit, the 8th bit can be the

flip-flop. The overall system performance is improved by

using the superior clock-to-out of the flip-flops.

An additional dedicated connection between shift registers

allows connecting the last bit of one shift register to the first

bit of the next, without using the ordinary LUT output. (See

Figure 22.) Longer shift registers can be built with dynamic

access to any bit in the chain. The shift register chaining

and the MUXF5, MUXF6, and MUXF7 multiplexers allow up

to a 128-bit shift register with addressable access to be

implemented in one CLB.

Figure 21: Shift Register Configurations

A[3:0]

SHIFTIN

SHIFTOUT

D(BY)

MC15

WSG

CE (SR)

CLK

SRLC16

SHIFT-REG

A[4:1] Output

Registered

Output

(optional)

DS031_05_110600

Figure 22: Cascadable Shift Register

SRLC16

MC15

SRLC16

SHIFTIN

CASCADABLE OUT

SLICE S0

SLICE S1

SLICE S2

SLICE S3

1 Shift Chain

in CLB

CLB

DS031_06_110200

SRLC16

MC15

SRLC16

SHIFTIN

SHIFTOUT

SRLC16

MC15

SRLC16

SHIFTIN

SHIFTOUT

SRLC16

MC15

SRLC16

SHIFTOUT

OUT

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 17

Multiplexers

Virtex-II function generators and associated multiplexers

can implement the following:

• 4:1 multiplexer in one slice

• 8:1 multiplexer in two slices

• 16:1 multiplexer in one CLB element (4 slices)

• 32:1 multiplexer in two CLB elements (8 slices)

Each Virtex-II slice has one MUXF5 multiplexer and one

MUXFX multiplexer. The MUXFX multiplexer implements

the MUXF6, MUXF7, or MUXF8, as shown in Figure 23.

Each CLB element has two MUXF6 multiplexers, one

MUXF7 multiplexer and one MUXF8 multiplexer. Examples

of multiplexers are shown in the Virtex-II Platform FPGA

User Guide. Any LUT can implement a 2:1 multiplexer.

Fast Lookahead Carry Logic

Dedicated carry logic provides fast arithmetic addition and

subtraction. The Virtex-II CLB has two separate carry

chains, as shown in the Figure 24.

The height of the carry chains is two bits per slice. The carry

chain in the Virtex-II device is running upward. The dedi-

cated carry path and carry multiplexer (MUXCY) can also

be used to cascade function generators for implementing

wide logic functions.

Arithmetic Logic

The arithmetic logic includes an XOR gate that allows a

2-bit full adder to be implemented within a slice. In addition,

a dedicated AND (MULT_AND) gate (shown in Figure 16)

improves the efficiency of multiplier implementation.

Figure 23: MUXF5 and MUXFX multiplexers

Slice S1

Slice S0

Slice S3

Slice S2

CLB

DS031_08_100201

MUXF8 combines

the two MUXF7 outputs

(Two CLBs)

MUXF6 combines the two MUXF5

outputs from slices S2 and S3

MUXF7 combines the two MUXF6

outputs from slices S0 and S2

MUXF6 combines the two MUXF5

outputs from slices S0 and S1

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 18

Figure 24: Fast Carry Logic Path

LUT

OI MUXCY

LUT

OI MUXCY

LUT

OI MUXCY

LUT

OI MUXCY

CIN

CIN CIN

COUT

LUT

OI MUXCY

LUT

OI MUXCY

LUT

OI MUXCY

LUT

OI MUXCY

CIN

COUT

to CIN of S2 of the next CLB

COUT

to S0 of the next CLB

(First Carry Chain)

(Second Carry Chain)

SLICE S1

SLICE S0

SLICE S3

SLICE S2

CLB

DS031_07_110200

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 19

Sum of Products

Each Virtex-II slice has a dedicated OR gate named ORCY,

ORing together outputs from the slices carryout and the ORCY

from an adjacent slice. The ORCY gate with the dedicated

Sum of Products (SOP) chain are designed for implementing

large, flexible SOP chains. One input of each ORCY is con-

nected through the fast SOP chain to the output of the previous

ORCY in the same slice row. The second input is connected to

the output of the top MUXCY in the same slice, as shown in

Figure 25.

LUTs and MUXCYs can implement large AND gates or

other combinatorial logic functions. Figure 26 illustrates

LUT and MUXCY resources configured as a 16-input AND

gate.

Figure 25: Horizontal Cascade Chain

MUXCY

Slice 1

ds031_64_110300

ORCY

LUT

MUXCY

Slice 0

VCC

LUT

MUXCY

Slice 3

ORCY

LUT

MUXCY

Slice 2

VCC

LUT

SOP

CLB

MUXCY

Slice 1

ORCY

LUT

MUXCY

Slice 0

VCC

LUT

MUXCY

Slice 3

ORCY

LUT

MUXCY

Slice 2

VCC

LUT

CLB

Figure 26: Wide-Input AND Gate (16 Inputs)

MUXCY

AND

MUXCY

“0”

MUXCY

Slice

OUT

Slice

LUT

DS031_41_110600

LUT

VCC

MUXCY

LUT

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 20

3-State Buffers

Introduction

Each Virtex-II CLB contains two 3-state drivers (TBUFs)

that can drive on-chip busses. Each 3-state buffer has its

own 3-state control pin and its own input pin.

Each of the four slices have access to the two 3-state buff-

ers through the switch matrix, as shown in Figure 27.

TBUFs in neighboring CLBs can access slice outputs by

direct connects. The outputs of the 3-state buffers drive hor-

izontal routing resources used to implement 3-state busses.

The 3-state buffer logic is implemented using AND-OR logic

rather than 3-state drivers, so that timing is more predict-

able and less load dependant especially with larger devices.

Locations / Organization

Four horizontal routing resources per CLB are provided for

on-chip 3-state busses. Each 3-state buffer has access

alternately to two horizontal lines, which can be partitioned

as shown in Figure 28. The switch matrices corresponding

to SelectRAM memory and multiplier or I/O blocks are

skipped.

Number of 3-State Buffers

Tabl e 1 1 shows the number of 3-state buffers available in

each Virtex-II device. The number of 3-state buffers is twice

the number of CLB elements.

CLB/Slice Configurations

Tabl e 1 2 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be

implemented in one of the configurations listed. Ta ble 1 3 shows the available resources in all CLBs.

Figure 27: Virtex-II 3-State Buffers

Slice

Switch

Matrix

DS031_37_060700

TBUF

Table 11: Virtex-II 3-State Buffers

Device

3-State Buffers

per Row

Total Number

of 3-State Buffers

XC2V40 16 128

XC2V80 16 256

XC2V250 32 768

XC2V500 48 1,536

XC2V1000 64 2,560

XC2V1500 80 3,840

XC2V2000 96 5,376

XC2V3000 112 7,168

XC2V4000 144 11,520

XC2V6000 176 16,896

XC2V8000 208 23,296

Figure 28: 3-State Buffer Connection to Horizontal Lines

Switch

matrix

CLB-II

Switch

matrix

CLB-II

DS031_09_032700

Programmable

connection

3 - state lines

Tabl e 1 2 : Logic Resources in One CLB

Slices LUTs Flip-Flops MULT_ANDs

Arithmetic &

Carry-Chains

SOP

Chains

Distributed

SelectRAM

Shift

Registers TBUF

4 8 8 8 2 2 128 bits 128 bits 2

Virtex-II Platform FPGAs: Functional Description

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Product Specification 21

18 Kbit Block SelectRAM Resources

Introduction

Virtex-II devices incorporate large amounts of 18 Kbit block

SelectRAM. These complement the distributed SelectRAM

resources that provide shallow RAM structures imple-

mented in CLBs. Each Virtex-II block SelectRAM is an 18

Kbit true dual-port RAM with two independently clocked and

independently controlled synchronous ports that access a

common storage area. Both ports are functionally identical.

CLK, EN, WE, and SSR polarities are defined through con-

figuration.

Each port has the following types of inputs: Clock and Clock

Enable, Write Enable, Set/Reset, and Address, as well as

separate Data/parity data inputs (for write) and Data/parity

data outputs (for read).

Operation is synchronous; the block SelectRAM behaves

like a register. Control, address and data inputs must (and

need only) be valid during the set-up time window prior to a

rising (or falling, a configuration option) clock edge. Data

outputs change as a result of the same clock edge.

Configuration

The Virtex-II block SelectRAM supports various configura-

tions, including single- and dual-port RAM and various

data/address aspect ratios. Supported memory configura-

tions for single- and dual-port modes are shown in Tab l e 1 4 .

Single-Port Configuration

As a single-port RAM, the block SelectRAM has access to

the 18 Kbit memory locations in any of the 2K x 9-bit,

1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit

memory locations in any of the 16K x 1-bit, 8K x 2-bit, or

4K x 4-bit configurations. The advantage of the 9-bit, 18-bit

and 36-bit widths is the ability to store a parity bit for each

eight bits. Parity bits must be generated or checked exter-

nally in user logic. In such cases, the width is viewed as 8 +

1, 16 + 2, or 32 + 4. These extra parity bits are stored and

behave exactly as the other bits, including the timing param-

eters. Video applications can use the 9-bit ratio of Virtex-II

block SelectRAM memory to advantage.

Each block SelectRAM cell is a fully synchronous memory

as illustrated in Figure 29. Input data bus and output data

bus widths are identical.

Tabl e 1 3 : Virtex-II Logic Resources Available in All CLBs

Device

CLB Array:

Row x

Column

Number

Slices

Number

LUTs

Max Distributed

SelectRAM or Shift

Number

Flip-Flops

Number

Carry-Chains(1)

Number

of SOP

Chains(1)

XC2V40 8 x 8 256 512 8,192 512 16 16

XC2V80 16 x 8 512 1,024 16,384 1,024 16 32

XC2V250 24 x 16 1,536 3,072 49,152 3,072 32 48

XC2V500 32 x 24 3,072 6,144 98,304 6,144 48 64

XC2V1000 40 x 32 5,120 10,240 163,840 10,240 64 80

XC2V1500 48 x 40 7,680 15,360 245,760 15,360 80 96

XC2V2000 56 x 48 10,752 21,504 344,064 21,504 96 112

XC2V3000 64 x 56 14,336 28,672 458,752 28,672 112 128

XC2V4000 80 x 72 23,040 46,080 737,280 46,080 144 160

XC2V6000 96 x 88 33,792 67,584 1,081,344 67,584 176 192

XC2V8000 112 x 104 46,592 93,184 1,490,944 93,184 208 224

Notes:

1. The carry-chains and SOP chains can be split or cascaded.

Table 14: Dual- and Single-Port Configurations

16K x 1 bit 2K x 9 bits

8K x 2 bits 1K x 18 bits

4K x 4 bits 512 x 36 bits

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 22

Dual-Port Configuration

As a dual-port RAM, each port of block SelectRAM has

access to a common 18 Kbit memory resource. These are

fully synchronous ports with independent control signals for

each port. The data widths of the two ports can be config-

ured independently, providing built-in bus-width conversion.

Tabl e 1 5 illustrates the different configurations available on

ports A and B.

If both ports are configured in either 2K x 9-bit, 1K x 18-bit,

or 512 x 36-bit configurations, the 18 Kbit block is accessi-

ble from port A or B. If both ports are configured in either

16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the

16 K-bit block is accessible from Port A or Port B. All other

configurations result in one port having access to an 18 Kbit

memory block and the other port having access to a 16 K-bit

subset of the memory block equal to 16 Kbits.

Figure 29: 18 Kbit Block SelectRAM Memory in

Single-Port Mode

DOP

DIP

ADDR

SSR

CLK

18 Kbit Block SelectRAM

DS031_10_071602

Tabl e 1 5 : Dual-Port Mode Configurations

Port A 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1

Port B 16K x 1 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36

Port A 8K x 2 8K x 2 8K x 2 8K x 2 8K x 2

Port B 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36

Port A 4K x 4 4K x 4 4K x 4 4K x 4

Port B 4K x 4 2K x 9 1K x 18 512 x 36

Port A 2K x 9 2K x 9 2K x 9

Port B 2K x 9 1K x 18 512 x 36

Port A 1K x 18 1K x 18

Port B 1K x 18 512 x 36

Port A 512 x 36

Port B 512 x 36

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 23

Each block SelectRAM cell is a fully synchronous memory,

as illustrated in Figure 30. The two ports have independent

inputs and outputs and are independently clocked.

Port Aspect Ratios

Ta bl e 1 6 shows the depth and the width aspect ratios for the

18 Kbit block SelectRAM. Virtex-II block SelectRAM also

includes dedicated routing resources to provide an efficient

interface with CLBs, block SelectRAM, and multipliers.

Read/Write Operations

The Virtex-II block SelectRAM read operation is fully syn-

chronous. An address is presented, and the read operation

is enabled by control signals WEA and WEB in addition to

ENA or ENB. Then, depending on clock polarity, a rising or

falling clock edge causes the stored data to be loaded into

output registers.

The write operation is also fully synchronous. Data and

address are presented, and the write operation is enabled

by control signals WEA or WEB in addition to ENA or ENB.

Then, again depending on the clock input mode, a rising or

falling clock edge causes the data to be loaded into the

memory cell addressed.

A write operation performs a simultaneous read operation.

Three different options are available, selected by configura-

tion:

1. “WRITE_FIRST”

The “WRITE_FIRST” option is a transparent mode. The

same clock edge that writes the data input (DI) into the

memory also transfers DI into the output registers DO

as shown in Figure 31.

2. “READ_FIRST”

The “READ_FIRST” option is a read-before-write mode.

The same clock edge that writes data input (DI) into the

memory also transfers the prior content of the memory

cell addressed into the data output registers DO, as

shown in Figure 32.

Figure 30: 18 Kbit Block SelectRAM in Dual-Port Mode

Tabl e 1 6 : 18 Kbit Block SelectRAM Port Aspect Ratio

Width Depth Address Bus Data Bus Parity Bus

1 16,384 ADDR[13:0] DATA[0] N/A

2 8,192 ADDR[12:0] DATA[1:0] N/A

4 4,096 ADDR[11:0] DATA[3:0] N/A

9 2,048 ADDR[10:0] DATA[7:0] Parity[0]

18 1,024 ADDR[9:0] DATA[15:0] Parity[1:0]

36 512 ADDR[8:0] DATA[31:0] Parity[3:0]

DOPA

DOPB

DIPA

ADDRA

WEA

ENA

SSRA

CLKA

DIPB

ADDRB

WEB

ENB

SSRB

CLKB

18 Kbit Block SelectRAM

DS031_11_071602

DOB

DOA

DIA

DIB

Figure 31: WRITE_FIRST Mode

Figure 32: READ_FIRST Mode

CLK

Data_in

New

Address

Internal

Memory DO Data_out = Data_in

Data_out

DS031_14_102000

New

RAM Contents New

Old

CLK

Data_in

New

Old

Address

Internal

Memory DO Prior stored data

Data_out

DS031_13_102000

RAM Contents New

Old

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 24

3. “NO_CHANGE”

The “NO_CHANGE” option maintains the content of the

output registers, regardless of the write operation. The

clock edge during the write mode has no effect on the

content of the data output register DO. When the port is

configured as “NO_CHANGE”, only a read operation

loads a new value in the output register DO, as shown in

Figure 33.

Control Pins and Attributes

Virtex-II SelectRAM memory has two independent ports

with the control signals described in Table 1 7 . All control

inputs including the clock have an optional inversion.

Initial memory content is determined by the INIT_xx

attributes. Separate attributes determine the output register

value after device configuration (INIT) and SSR is asserted

(SRVAL). Both attributes (INIT_B and SRVAL) are available

for each port when a block SelectRAM resource is config-

ured as dual-port RAM.

Locations

Virtex-II SelectRAM memory blocks are located in either

four or six columns. The number of blocks per column

depends of the device array size and is equivalent to the

number of CLBs in a column divided by four. Column loca-

tions are shown in Ta bl e 18 .

Figure 33: NO_CHANGE Mode

Tabl e 1 7 : Control Functions

Control Signal Function

CLK Read and Write Clock

EN Enable affects Read, Write, Set, Reset

WE Write Enable

SSR Set DO register to SRVAL (attribute)

CLK

Data_in

New

Last Read Cycle Content (no change)

Address

Internal

Memory DO No change during write

Data_out

DS031_12_102000

RAM Contents New

Old

Table 18: SelectRAM Memory Floor Plan

Device Columns

SelectRAM Blocks

Per Column Total

XC2V40 2 2 4

XC2V80 2 4 8

XC2V250 4 6 24

XC2V500 4 8 32

XC2V1000 4 10 40

XC2V1500 4 12 48

XC2V2000 4 14 56

XC2V3000 6 16 96

XC2V4000 6 20 120

XC2V6000 6 24 144

XC2V8000 6 28 168

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 25

Total Amount of SelectRAM Memory

Ta bl e 1 9 shows the amount of block SelectRAM memory

available for each Virtex-II device. The 18 Kbit SelectRAM

blocks are cascadable to implement deeper or wider single- or

dual-port memory resources.

18-Bit x 18-Bit Multipliers

Introduction

A Virtex-II multiplier block is an 18-bit by 18-bit 2’s comple-

ment signed multiplier. Virtex-II devices incorporate many

embedded multiplier blocks. These multipliers can be asso-

ciated with an 18 Kbit block SelectRAM resource or can be

used independently. They are optimized for high-speed

operations and have a lower power consumption compared

to an 18-bit x 18-bit multiplier in slices.

Figure 34: Block SelectRAM (2-column, 4-column, and 6-column)

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

SelectRAM Blocks

ds031_38_101000

2 CLB column

2 CLB columns

SelectRAM Blocks

2 CLB column

2 CLB columns

Tabl e 1 9 : Virtex-II SelectRAM Memory Available

Device

Total SelectRAM Memory

Blocks in Kbits in Bits

XC2V40 4 72 73,728

XC2V80 8 144 147,456

XC2V250 24 432 442,368

XC2V500 32 576 589,824

XC2V1000 40 720 737,280

XC2V1500 48 864 884,736

XC2V2000 56 1,008 1,032,192

XC2V3000 96 1,728 1,769,472

XC2V4000 120 2,160 2,211,840

XC2V6000 144 2,592 2,654,208

XC2V8000 168 3,024 3,096,576

Table 19: Virtex-II SelectRAM Memory Available

Device

Total SelectRAM Memory

Blocks in Kbits in Bits

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 26

Each SelectRAM memory and multiplier block is tied to four

switch matrices, as shown in Figure 35.

Association With Block SelectRAM Memory

The interconnect is designed to allow SelectRAM memory

and multiplier blocks to be used at the same time, but some

interconnect is shared between the SelectRAM and the

multiplier. Thus, SelectRAM memory can be used only up to

18 bits wide when the multiplier is used, because the multi-

plier shares inputs with the upper data bits of the

SelectRAM memory.

This sharing of the interconnect is optimized for an

18-bit-wide block SelectRAM resource feeding the multi-

plier. The use of SelectRAM memory and the multiplier with

an accumulator in LUTs allows for implementation of a digi-

tal signal processor (DSP) multiplier-accumulator (MAC)

function, which is commonly used in finite and infinite

impulse response (FIR and IIR) digital filters.

Configuration

The multiplier block is an 18-bit by 18-bit signed multiplier

(2's complement). Both A and B are 18-bit-wide inputs, and

the output is 36 bits. Figure 36 shows a multiplier block.

Locations / Organization

Multiplier organization is identical to the 18 Kbit SelectRAM

organization, because each multiplier is associated with an

18 Kbit block SelectRAM resource.

In addition to the built-in multiplier blocks, the CLB elements

have dedicated logic to implement efficient multipliers in

logic. (Refer to Configurable Logic Blocks (CLBs)).

Figure 35: SelectRAM and Multiplier Blocks

Switch

Matrix

Switch

Matrix

18-Kbit block

SelectRAM

18 x 18 Multiplier

Switch

Matrix

Switch

Matrix

DS031_33_101000

Figure 36: Multiplier Block

Table 20: Multiplier Floor Plan

Device Columns

Multipliers

Per Column Total

XC2V40 2 2 4

XC2V80 2 4 8

XC2V250 4 6 24

XC2V500 4 8 32

XC2V1000 4 10 40

XC2V1500 4 12 48

XC2V2000 4 14 56

XC2V3000 6 16 96

XC2V4000 6 20 120

XC2V6000 6 24 144

XC2V8000 6 28 168

MULT 18 x 18

A[17:0]

P[35:0]

B[17:0]

Multiplier Block

DS031_40_100400

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 27

Global Clock Multiplexer Buffers

Virtex-II devices have 16 clock input pins that can also be

used as regular user I/Os. Eight clock pads are on the top

edge of the device, in the middle of the array, and eight are

on the bottom edge, as illustrated in Figure 38.

The global clock multiplexer buffer represents the input to

dedicated low-skew clock tree distribution in Virtex-II

devices. Like the clock pads, eight global clock multiplexer

buffers are on the top edge of the device and eight are on

the bottom edge.

Each global clock buffer can either be driven by the clock

pad to distribute a clock directly to the device, or driven by

the Digital Clock Manager (DCM), discussed in Digital Clock

Manager (DCM), page 29. Each global clock buffer can also

be driven by local interconnects. The DCM has clock out-

put(s) that can be connected to global clock buffer inputs, as

shown in Figure 39.

Figure 37: Multipliers (2-column, 4-column, and 6-column)

DS031_39_101000

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

Multiplier Blocks

2 CLB column

2 CLB columns

Multiplier Blocks

2 CLB column

2 CLB columns

Figure 38: Virtex-II Clock Pads

8 clock pads

Virtex-II

Device

DS031_42_022305

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 28

Global clock buffers are used to distribute the clock to some

or all synchronous logic elements (such as registers in

CLBs and IOBs, and SelectRAM blocks.

Eight global clocks can be used in each quadrant of the

Virtex-II device. Designers should consider the clock distri-

bution detail of the device prior to pin-locking and floorplan-

ning (see the Virtex-II User Guide).

Figure 40 shows clock distribution in Virtex-II devices.

In each quadrant, up to eight clocks are organized in clock

rows. A clock row supports up to 16 CLB rows (eight up and

eight down). For the largest devices a new clock row is

added, as necessary.

To reduce power consumption, any unused clock branches

remain static.

Global clocks are driven by dedicated clock buffers (BUFG),

which can also be used to gate the clock (BUFGCE) or to mul-

tiplex between two independent clock inputs (BUFGMUX).

The most common configuration option of this element is as

a buffer. A BUFG function in this (global buffer) mode, is

shown in Figure 41.

The Virtex-II global clock buffer BUFG can also be config-

ured as a clock enable/disable circuit (Figure 42), as well as

a two-input clock multiplexer (Figure 43). A functional

description of these two options is provided below. Each of

them can be used in either of two modes, selected by con-

figuration: rising clock edge or falling clock edge.

This section describes the rising clock edge option. For the

opposite option, falling clock edge, just change all "rising"

references to "falling" and all "High" references to "Low",

except for the description of the CE or S levels. The rising

clock edge option uses the BUFGCE and BUFGMUX prim-

itives. The falling clock edge option uses the BUFGCE_1

and BUFGMUX_1 primitives.

BUFGCE

If the CE input is active (High) prior to the incoming rising

clock edge, this Low-to-High-to-Low clock pulse passes

through the clock buffer. Any level change of CE during the

incoming clock High time has no effect.

Figure 39: Virtex-II Clock Distribution Configurations

Clock

Pad

Clock

Buffer

Clock Distribution

Clock

Pad

Clock

Buffer

Clock Distribution

CLKIN

CLKOUT

DCM

DS031_43_101000

Figure 40: Virtex-II Clock Distribution

NW NE

SW SE

DS031_45_120200

8 BUFGMUX

8 max

8 BUFGMUX

16 Clocks 16 Clocks

Figure 41: Virtex-II BUFG Function

BUFG

DS031_61_101200

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 29

If the CE input is inactive (Low) prior to the incoming rising

clock edge, the following clock pulse does not pass through

the clock buffer, and the output stays Low. Any level change

of CE during the incoming clock High time has no effect. CE

must not change during a short setup window just prior to

the rising clock edge on the BUFGCE input I. Violating this

setup time requirement can result in an undefined runt

pulse output.

BUFGMUX

BUFGMUX can switch between two unrelated, even asyn-

chronous clocks. Basically, a Low on S selects the I0 input,

a High on S selects the I1 input. Switching from one clock to

the other is done in such a way that the output High and Low

time is never shorter than the shortest High or Low time of

either input clock. As long as the presently selected clock is

High, any level change of S has no effect .

If the presently selected clock is Low while S changes, or if

it goes Low after S has changed, the output is kept Low until

the other ("to-be-selected") clock has made a transition

from High to Low. At that instant, the new clock starts driv-

ing the output.

The two clock inputs can be asynchronous with regard to

each other, and the S input can change at any time, except

for a short setup time prior to the rising edge of the presently

selected clock (I0 or I1). Violating this setup time require-

ment can result in an undefined runt pulse output.

All Virtex-II devices have 16 global clock multiplexer buffers.

Figure 44 shows a switchover from I0 to I1.

• The current clock is CLK0.

• S is activated High.

• If CLK0 is currently High, the multiplexer waits for CLK0

to go Low.

• Once CLK0 is Low, the multiplexer output stays Low

until CLK1 transitions High to Low.

• When CLK1 transitions from High to Low, the output

switches to CLK1.

• No glitches or short pulses can appear on the output.

Local Clocking

In addition to global clocks, there are local clock resources

in the Virtex-II devices. There are more than 72 local clocks

in the Virtex-II family. These resources can be used for

many different applications, including but not limited to

memory interfaces. For example, even using only the left

and right I/O banks, Virtex-II FPGAs can support up to 50

local clocks for DDR SDRAM. These interfaces can operate

beyond 200 MHz on Virtex-II devices.

Digital Clock Manager (DCM)

The Virtex-II DCM offers a wide range of powerful clock

management features.

•Clock De-skew: The DCM generates new system

clocks (either internally or externally to the FPGA),

which are phase-aligned to the input clock, thus

eliminating clock distribution delays.

•Frequency Synthesis: The DCM generates a wide

range of output clock frequencies, performing very

flexible clock multiplication and division.

•Phase Shifting: The DCM provides both coarse phase

shifting and fine-grained phase shifting with dynamic

phase shift control.

The DCM utilizes fully digital delay lines allowing robust

high-precision control of clock phase and frequency. It also

utilizes fully digital feedback systems, operating dynamically

to compensate for temperature and voltage variations dur-

ing operation.

Up to four of the nine DCM clock outputs can drive inputs to

global clock buffers or global clock multiplexer buffers simul-

taneously (see Figure 45). All DCM clock outputs can simul-

taneously drive general routing resources, including routes

to output buffers.

Figure 42: Virtex-II BUFGCE Function

Figure 43: Virtex-II BUFGMUX Function

BUFGCE

DS031_62_101200

BUFGMUX

DS031_63_112900

Figure 44: Clock Multiplexer Waveform Diagram

OUT

Wait for Low

Switch

DS031_46_020604

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 30

The DCM can be configured to delay the completion of the

Virtex-II configuration process until after the DCM has

achieved lock. This guarantees that the chip does not begin

operating until after the system clocks generated by the

DCM have stabilized.

The DCM has the following general control signals:

• RST input pin: resets the entire DCM

• LOCKED output pin: asserted High when all enabled

DCM circuits have locked.

• STATUS output pins (active High): shown in Tabl e 21.

Clock De-Skew

The DCM de-skews the output clocks relative to the input

clock by automatically adjusting a digital delay line. Addi-

tional delay is introduced so that clock edges arrive at inter-

nal registers and block RAMs simultaneously with the clock

edges arriving at the input clock pad. Alternatively, external

clocks, which are also de-skewed relative to the input clock,

can be generated for board-level routing. All DCM output

clocks are phase-aligned to CLK0 and, therefore, are also

phase-aligned to the input clock.

To achieve clock de-skew, the CLKFB input must be con-

nected, and its source must be either CLK0 or CLK2X. Note

that CLKFB must always be connected, unless only the CLKFX

or CLKFX180 outputs are used and de-skew is not required.

Frequency Synthesis

The DCM provides flexible methods for generating new

clock frequencies. Each method has a different operating

frequency range and different AC characteristics. The

CLK2X and CLK2X180 outputs double the clock frequency.

The CLKDV output creates divided output clocks with divi-

sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,

8, 9, 10, 11, 12, 13, 14, 15, and 16.

The CLKFX and CLKFX180 outputs can be used to pro-

duce clocks at the following frequency:

FREQCLKFX = (M/D) * FREQCLKIN

where M and D are two integers. Specifications for M and D

are provided under DCM Timing Parameters in Module 3.

By default, M=4 and D=1, which results in a clock output fre-

quency four times faster than the clock input frequency

(CLKIN).

CLK2X180 is phase shifted 180 degrees relative to CLK2X.

CLKFX180 is phase shifted 180 degrees relative to CLKFX.

All frequency synthesis outputs automatically have 50/50

duty cycles (with the exception of the CLKDV output when

performing a non-integer divide in high-frequency mode).

Note that CLK2X and CLK2X180 are not available in

high-frequency mode.

Phase Shifting

The DCM provides additional control over clock skew

through either coarse or fine-grained phase shifting. The

CLK0, CLK90, CLK180, and CLK270 outputs are each

phase shifted by ¼ of the input clock period relative to each

other, providing coarse phase control. Note that CLK90 and

CLK270 are not available in high-frequency mode.

Fine-phase adjustment affects all nine DCM output clocks.

When activated, the phase shift between the rising edges of

CLKIN and CLKFB is a specified fraction of the input clock

period.

In variable mode, the PHASE_SHIFT value can also be

dynamically incremented or decremented as determined by

PSINCDEC synchronously to PSCLK, when the PSEN

input is active. Figure 46 illustrates the effects of fine-phase

shifting. For more information on DCM features, see the

Virtex-II User Guide.

Figure 45: Digital Clock Manager

Tabl e 2 1 : DCM Status Pins

Status Pin Function

0 Phase Shift Overflow

1 CLKIN Stopped

2 CLKFX Stopped

3N/A

4N/A

5N/A

6N/A

7N/A

CLKIN

CLKFB CLK180

CLK270

CLK0

CLK90

CLK2X

CLK2X180

CLKDV

DCM

DS031_67_112900

CLKFX

CLKFX180

LOCKED

STATUS[7:0]

PSDONE

RST

DSSEN

PSINCDEC

PSEN

PSCLK

clock signal

control signal

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 31

Tabl e 2 2 lists fine-phase shifting control pins, when used in

variable mode.

Two separate components of the phase shift range must be

understood:

•PHASE_SHIFT attribute range

•FINE_SHIFT_RANGE DCM timing parameter range

The PHASE_SHIFT attribute is the numerator in the following

equation:

Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN

The full range of this attribute is always -255 to +255, but its

practical range varies with CLKIN frequency, as constrained

by the FINE_SHIFT_RANGE component, which represents

the total delay achievable by the phase shift delay line. Total

delay is a function of the number of delay taps used in the

circuit. Across process, voltage, and temperature, this abso-

lute range is guaranteed to be as specified under DCM Tim-

ing Parameters in Module 3.

Absolute range (fixed mode) = ± FINE_SHIFT_RANGE

Absolute range (variable mode) = ± FINE_SHIFT_RANGE/2

The reason for the difference between fixed and variable

modes is as follows. For variable mode to allow symmetric,

dynamic sweeps from -255/256 to +255/256, the DCM sets

the "zero phase skew" point as the middle of the delay line,

thus dividing the total delay line range in half. In fixed mode,

since the PHASE_SHIFT value never changes after configu-

ration, the entire delay line is available for insertion into

either the CLKIN or CLKFB path (to create either positive or

negative skew).

Taking both of these components into consideration, the fol-

lowing are some usage examples:

• If PERIODCLKIN = 2 * FINE_SHIFT_RANGE, then

PHASE_SHIFT in fixed mode is limited to ± 128, and in

variable mode it is limited to ± 64.

• If PERIODCLKIN = FINE_SHIFT_RANGE, then

PHASE_SHIFT in fixed mode is limited to ± 255, and in

variable mode it is limited to ± 128.

• If PERIODCLKIN ≤ 0.5 * FINE_SHIFT_RANGE, then

PHASE_SHIFT is limited to ± 255 in either mode.

Operating Modes

The frequency ranges of DCM input and output clocks

depend on the operating mode specified, either

low-frequency mode or high-frequency mode, according to

Tabl e 2 3 . (For actual values, see Virtex-II Switching Charac-

teristics in Module 3). The CLK2X, CLK2X180, CLK90, and

CLK270 outputs are not available in high-frequency mode.

High or low-frequency mode is selected by an attribute.

Figure 46: Fine-Phase Shifting Effects

CLKOUT_PHASE_SHIFT

= FIXED

CLKOUT_PHASE_SHIFT

= VARIABLE

CLKOUT_PHASE_SHIFT

= NONE

CLKIN

CLKFB

(PS/256) x PERIODCLKIN

(PS negative)

(PS/256) x PERIODCLKIN

(PS positive)

(PS/256) x PERIODCLKIN

(PS negative)

(PS/256) x PERIODCLKIN

(PS positive) DS031_48_101201

CLKFB

Tabl e 2 2 : Fine-Phase Shifting Control Pins

Control Pin Direction Function

PSINCDEC in Increment or decrement

PSEN in Enable ± phase shift

PSCLK in Clock for phase shift

PSDONE out Active when completed

Tabl e 2 3 : DCM Frequency Ranges

Output Clock

Low-Frequency Mode High-Frequency Mode

CLKIN Input CLK Output CLKIN Input CLK Output

CLK0, CLK180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF

CLK90, CLK270 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF NA NA

CLK2X, CLK2X180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF NA NA

CLKDV CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF

CLKFX, CLKFX180 CLKIN_FREQ_FX_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF CLKOUT_FREQ_FX_HF

Virtex-II Platform FPGAs: Functional Description

DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 32

Routing

DCM Locations/Organization

Virtex-II DCMs are placed on the top and bottom of each

block RAM and multiplier column. The number of DCMs

depends on the device size, as shown in Ta bl e 2 4.

Active Interconnect Technology

Local and global Virtex-II routing resources are optimized

for speed and timing predictability, as well as to facilitate IP

cores implementation. Virtex-II Active Interconnect Technol-

ogy is a fully buffered programmable routing matrix. All rout-

ing resources are segmented to offer the advantages of a

hierarchical solution. Virtex-II logic features like CLBs,

IOBs, block RAM, multipliers, and DCMs are all connected

to an identical switch matrix for access to global routing

resources, as shown in Figure 47.

Each Virtex-II device can be represented as an array of

switch matrixes with logic blocks attached, as illustrated in

Figure 48.

Tabl e 2 4 : DCM Organization

Device Columns DCMs

XC2V40 2 4

XC2V80 2 4

XC2V250 4 8

XC2V500 4 8

XC2V1000 4 8

XC2V1500 4 8

XC2V2000 4 8

XC2V3000 6 12

XC2V4000 6 12

XC2V6000 6 12

XC2V8000 6 12

Figure 47: Active Interconnect Technology

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

CLB

18Kb

BRAM

MULT

18 x 18

Switch

Matrix IOB

Switch

Matrix DCM

DS031_55_022205

Figure 48: Routing Resources

Switch

Matrix IOB Switch

Matrix DCM Switch

Matrix

Switch

Matrix IOB Switch

Matrix CLB Switch

Matrix

Switch

Matrix

Switch

Matrix IOB Switch

Matrix CLB Switch

Matrix

Switch

Matrix

Switch

Matrix IOB Switch

Matrix CLB Switch

Matrix

Switch

Matrix

Switch

Matrix IOB Switch

Matrix CLB Switch

Matrix

Switch

Matrix

SelectRAM

Multiplier

DS031_34_022205

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DS031-2 (v3.5) November 5, 2007 www.xilinx.com Module 2 of 4

Product Specification 33

Place-and-route software takes advantage of this regular

array to deliver optimum system performance and fast com-

pile times. The segmented routing resources are essential

to guarantee IP cores portability and to efficiently handle an

incremental design flow that is based on modular imple-

mentations. Total design time is reduced due to fewer and

shorter design iterations.

Hierarchical Routing Resources

Most Virtex-II signals are routed using the global routing

resources, which are located in horizontal and vertical rout-

ing channels between each switch matrix.

As shown in Figure 49, Virtex-II has fully buffered program-

mable interconnections, with a number of resources

counted between any two adjacent switch matrix rows or

columns. Fanout has minimal impact on the performance of

each net.

• The long lines are bidirectional wires that distribute

signals across the device. Vertical and horizontal long

lines span the full height and width of the device.

• The hex lines route signals to every third or sixth block

away in all four directions. Organized in a staggered

pattern, hex lines can only be driven from one end.

Hex-line signals can be accessed either at the endpoints

or at the midpoint (three blocks from the source).

• The double lines route signals to every first or second

block away in all four directions. Organized in a

staggered pattern, double lines can be driven only at

their endpoints. Double-line signals can be accessed

either at the endpoints or at the midpoint (one block

from the source).

• The direct connect lines route signals to neighboring

blocks: vertically, horizontally, and diagonally.

• The fast connect lines are the internal CLB local

interconnections from LUT outputs to LUT inputs.

Dedicated Routing

In addition to the global and local routing resources, dedi-

cated signals are available.

• There are eight global clock nets per quadrant (see

Global Clock Multiplexer Buffers).

• Horizontal routing resources are provided for on-chip

3-state busses. Four partitionable bus lines are

provided per CLB row, permitting multiple busses

within a row. (See 3-State Buffers.)

• Two dedicated carry-chain resources per slice column

(two per CLB column) propagate carry-chain MUXCY

output signals vertically to the adjacent slice. (See

CLB/Slice Configurations.)

• One dedicated SOP chain per slice row (two per CLB

row) propagate ORCY output logic signals horizontally

to the adjacent slice. (See Sum of Products.)

• One dedicated shift-chain per CLB connects the output

of LUTs in shift-register mode to the input of the next

LUT in shift-register mode (vertically) inside the CLB.

(See Shift Registers, page 16.)

Figure 49: Hierarchical Routing Resources

24 Horizontal Long Lines

24 Vertical Long Lines

120 Horizontal Hex Lines

120 Vertical Hex Lines

40 Horizontal Double Lines

40 Vertical Double Lines

16 Direct Connections

(total in all four directions)

8 Fast Connects

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Product Specification 34

Creating a Design

Creating Virtex-II designs is easy with Xilinx Integrated Syn-

thesis Environment (ISE) development systems, which sup-

port advanced design capabilities, including ProActive

Timing Closure, integrated logic analysis, and the fastest

place and route runtimes in the industry. ISE solutions

enable designers to get the performance they need, quickly

and easily.

As a result of the ongoing cooperative development efforts

between Xilinx and EDA Alliance partners, designers can

take advantage of the benefits provided by EDA technolo-

gies in the programmable logic design process. Xilinx devel-

opment systems are available in a number of easy to use

configurations, collectively known as the ISE Series.

ISE Alliance

The ISE Alliance solution is designed to plug and play within

an existing design environment. Built using industry standard

data formats and netlists, these stable, flexible products

enable Alliance EDA partners to deliver their best design

automation capabilities to Xilinx customers, along with the

time to market benefits of ProActive Timing Closure.

ISE Foundation

The ISE Foundation solution delivers the benefits of true

HDL-based design in a seamlessly integrated design envi-

ronment. An intuitive project navigator, as well as powerful

HDL design and two HDL synthesis tools, ensure that

high-quality results are achieved quickly and easily. The ISE

Foundation product includes:

• State Diagram entry using Xilinx StateCAD

• Automatic HDL Testbench generation using Xilinx

HDLBencher

• HDL Simulation using ModelSim XE

Design Flow

Virtex-II design flow proceeds as follows:

•Design Entry

•Synthesis

• Implementation

• Verification

Most programmable logic designers iterate through these

steps several times in the process of completing a design.

Design Entry

All Xilinx ISE development systems support the mainstream

EDA design entry capabilities, ranging from schematic

design to advanced HDL design methodologies. Given the

high densities of the Virtex-II family, designs are created

most efficiently using HDLs. To further improve their time to

market, many Xilinx customers employ incremental, modu-

lar, and Intellectual Property (IP) design techniques. When

properly used, these techniques further accelerate the logic

design process.

To enable designers to leverage existing investments in

EDA tools, and to ensure high performance design flows,

Xilinx jointly develops tools with leading EDA vendors,

including:

•Aldec

• Cadence®

•Exemplar

• Mentor Graphics®

• Model Technology®

• Synopsys®

• Synplicity®

Complete information on Alliance Series partners and their

associated design flows is available at www.xilinx.com on

the Xilinx Alliance Series web page.

The ISE Foundation product offers schematic entry and

HDL design capabilities as part of an integrated design

solution - enabling one-stop shopping. These capabilities

are powerful, easy to use, and they support the full portfolio

of Xilinx programmable logic devices. HDL design capabil-

ities include a color-coded HDL editor with integrated lan-

guage templates, state diagram entry, and Core generation

capabilities.

Synthesis

The ISE Alliance product is engineered to support

advanced design flows with the industry's best synthesis

tools. Advanced design methodologies include:

• Physical Synthesis

• Incremental synthesis

• RTL floorplanning

• Direct physical mapping

The ISE Foundation product seamlessly integrates synthesis

capabilities purchased directly from Exemplar, Synopsys, and

Synplicity. In addition, it includes the capabilities of Xilinx

Synthesis Technology.

A benefit of having two seamlessly integrated synthesis

engines within an ISE design flow is the ability to apply alter-

native sets of optimization techniques on designs, helping to

ensure that designers can meet even the toughest timing

requirements.

Design Implementation

The ISE Series development systems include Xilinx tim-

ing-driven implementation tools, frequently called “place

and route” or “fitting” software. This robust suite of tools

enables the creation of an intuitive, flexible, tightly inte-

grated design flow that efficiently bridges “logical” and

“physical” design domains. This simplifies the task of defin-

ing a design, including its behavior, timing requirements,

and optional layout (or floorplanning), as well as simplifying

the task of analyzing reports generated during the imple-

mentation process.

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Product Specification 35

The Virtex-II implementation process is comprised of Syn-

thesis, translation, mapping, place and route, and configu-

ration file generation. While the tools can be run individually,

many designers choose to run the entire implementation

process with the click of a button. To assist those who prefer

to script their design flows, Xilinx provides Xflow, an auto-

mated single command line process.

Design Verification

In addition to conventional design verification using static

timing analysis or simulation techniques, Xilinx offers pow-

erful in-circuit debugging techniques using ChipScope ILA

(Integrated Logic Analysis). The reconfigurable nature of

Xilinx FPGAs means that designs can be verified in real

time without the need for extensive sets of software simula-

tion vectors.

For simulation, the system extracts post-layout timing infor-

mation from the design database, and back-annotates this

information into the netlist for use by the simulator. The back

annotation features a variety of patented Xilinx techniques,

resulting in the industry’s most powerful simulation flows.

Alternatively, timing-critical portions of a design can be ver-

ified using the Xilinx static timing analyzer or a third party

static timing analysis tool like Synopsys Prime Time™, by

exporting timing data in the STAMP data format.

For in-circuit debugging, ChipScope ILA enables designers

to analyze the real-time behavior of a device while operating

at full system speeds. Logic analysis commands and cap-

tured data are transferred between the ChipScope software

and ILA cores within the Virtex-II FPGA, using industry

standard JTAG protocols. These JTAG transactions are

driven over an optional download cable (MultiLINX or

JTAG), connecting the Virtex device in the target system to

a PC or workstation.

ChipScope ILA was designed to look and feel like a logic

analyzer, making it easy to begin debugging a design imme-

diately. Modifications to the desired logic analysis can be

downloaded directly into the system in a matter of minutes.

Other Unique Features of Virtex-II Design Flow

Xilinx design flows feature a number of unique capabilities.

Among these are efficient incremental HDL design flows; a

robust capability that is enabled by Xilinx exclusive hierar-

chical floorplanning capabilities. Another powerful design

capability only available in the Xilinx design flow is “Modular

Design”, part of the Xilinx suite of team design tools, which

enables autonomous design, implementation, and verifica-

tion of design modules.

Incremental Synthesis

Xilinx unique hierarchical floorplanning capabilities enable

designers to create a programmable logic design by isolating

design changes within one hierarchical “logic block”, and

perform synthesis, verification and implementation pro-

cesses on that specific logic block. By preserving the logic in

unchanged portions of a design, Xilinx incremental design

makes the high-density design process more efficient.

Xilinx hierarchical floorplanning capabilities can be speci-

fied using the high-level floorplanner or a preferred RTL

floorplanner (see the Xilinx web site for a list of supported

EDA partners). When used in conjunction with one of the

EDA partners’ floorplanners, higher performance results

can be achieved, as many synthesis tools use this more

predictable detailed physical implementation information to

establish more aggressive and accurate timing estimates

when performing their logic optimizations.

Modular Design

Xilinx innovative modular design capabilities take the incre-

mental design process one step further by enabling the

designer to delegate responsibility for completing the

design, synthesis, verification, and implementation of a hier-

archical “logic block” to an arbitrary number of designers -

assigning a specific region within the target FPGA for exclu-

sive use by each of the team members.

This team design capability enables an autonomous

approach to design modules, changing the hand-off point to

the lead designer or integrator from “my module works in

simulation” to “my module works in the FPGA”. This unique

design methodology also leverages the Xilinx hierarchical

floorplanning capabilities and enables the Xilinx (or EDA

partner) floorplanner to manage the efficient implementa-

tion of very high-density FPGAs.

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Product Specification 36

Configuration

Virtex-II devices are configured by loading application spe-

cific configuration data into the internal configuration mem-

ory. Configuration is carried out using a subset of the device

pins, some of which are dedicated, while others can be

re-used as general purpose inputs and outputs once config-

uration is complete.

Depending on the system design, several configuration

modes are supported, selectable via mode pins. The mode

pins M2, M1 and M0 are dedicated pins. The M2, M1, and

M0 mode pins should be set at a constant DC voltage level,

either through pull-up or pull-down resistors, or tied directly

to ground or VCCAUX. The mode pins should not be toggled

during and after configuration.

An additional pin, HSWAP_EN is used in conjunction with

the mode pins to select whether user I/O pins have pull-ups

during configuration. By default, HSWAP_EN is tied High

(internal pull-up) which shuts off the pull-ups on the user I/O

pins during configuration. When HSWAP_EN is tied Low,

user I/Os have pull-ups during configuration. Other dedi-

cated pins are CCLK (the configuration clock pin), DONE,

PROG_B, and the Boundary-Scan pins: TDI, TDO, TMS,

and TCK. Depending on the configuration mode chosen,

CCLK can be an output generated by the FPGA, or an input

accepting an externally generated clock. The configuration

pins and Boundary-Scan pins are independent of the VCCO.

The auxiliary power supply (VCCAUX) of 3.3V is used for

these pins. All configuration pins are LVTTL 12 mA. (See

Virtex-II DC Characteristics in Module 3.)

A persist option is available which can be used to force the

configuration pins to retain their configuration function even

after device configuration is complete. If the persist option is

not selected then the configuration pins with the exception

of CCLK, PROG_B, and DONE can be used as user I/O in

normal operation. The persist option does not apply to the

Boundary-Scan related pins. The persist feature is valuable

in applications which employ partial reconfiguration or

reconfiguration on the fly.

Configuration Modes

Virtex-II supports the following five configuration modes:

•Slave-Serial Mode

•Master-Serial Mode

•Slave SelectMAP Mode

•Master SelectMAP Mode

•Boundary-Scan (JTAG, IEEE 1532) Mode

A detailed description of configuration modes is provided in

the Virtex-II User Guide.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other serial source

of configuration data. The CCLK pin on the FPGA is an

input in this mode. The serial bitstream must be setup at the

DIN input pin a short time before each rising edge of the

externally generated CCLK.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the next device is routed internally to the

DOUT pin. The data on the DOUT pin changes on the falling

edge of CCLK.

Slave-serial mode is selected by applying <111> to the

mode pins (M2, M1, M0). A weak pull-up on the mode pins

makes slave serial the default mode if the pins are left

unconnected.

Master-Serial Mode

In master-serial mode, the CCLK pin is an output pin. It is

the Virtex-II FPGA device that drives the configuration clock

on the CCLK pin to a Xilinx Serial PROM which in turn feeds

bit-serial data to the DIN input. The FPGA accepts this data

on each rising CCLK edge. After the FPGA has been

loaded, the data for the next device in a daisy-chain is pre-

sented on the DOUT pin after the falling CCLK edge.

The interface is identical to slave serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration.

Slave SelectMAP Mode

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the Virtex-II FPGA device with

a BUSY flag controlling the flow of data. An external data

source provides a byte stream, CCLK, an active Low Chip

Select (CS_B) signal and a Write signal (RDWR_B). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low. Data can also be read using the

SelectMAP mode. If RDWR_B is asserted, configuration

data is read out of the FPGA as part of a readback opera-

tion.

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback using the per-

sist option.

Multiple Virtex-II FPGAs can be configured using the

SelectMAP mode, and be made to start-up simultaneously.

To configure multiple devices in this way, wire the individual

CCLK, Data, RDWR_B, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

deasserting the CS_B pin of each device in turn and writing

the appropriate data.

Master SelectMAP Mode

This mode is a master version of the SelectMAP mode. The

device is configured byte-wide on a CCLK supplied by the

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Product Specification 37

Virtex-II FPGA device. Timing is similar to the Slave Serial-

MAP mode except that CCLK is supplied by the Virtex-II

FPGA.

Boundary-Scan (JTAG, IEEE 1532) Mode

In Boundary-Scan mode, dedicated pins are used for con-

figuring the Virtex-II device. The configuration is done

entirely through the IEEE 1149.1 Test Access Port (TAP).

Virtex-II device configuration using Boundary-Scan is com-

patible with the IEEE 1149.1-1993 standard and the new

IEEE 1532 standard for In-System Configurable (ISC)

devices. The IEEE 1532 standard is backward compliant

with the IEEE 1149.1-1993 TAP and state machine. The

IEEE Standard 1532 for In-System Configurable (ISC)

devices is intended to be programmed, reprogrammed, or

tested on the board via a physical and logical protocol.

Configuration through the Boundary-Scan port is always

available, independent of the mode selection. Selecting the

Boundary-Scan mode simply turns off the other modes.

Tabl e 2 6 lists the total number of bits required to configure

each device.

Configuration Sequence

The configuration of Virtex-II devices is a three-phase pro-

cess after Power On Reset or POR. POR occurs when

VCCINT is greater than 1.2V, VCCAUX is greater than 2.5V,

and VCCO (bank 4) is greater than 1.5V. Once the POR volt-

ages have been reached, the three-phase process begins.

First, the configuration memory is cleared. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process.

Configuration is automatically initiated on power-up unless

it is delayed by the user. The INIT_B pin can be held Low

using an open-drain driver. An open-drain is required since

INIT_B is a bidirectional open-drain pin that is held Low by a

Virtex-II FPGA device while the configuration memory is

being cleared. Extending the time that the pin is Low causes

the configuration sequencer to wait. Thus, configuration is

delayed by preventing entry into the phase where data is

loaded.

The configuration process can also be initiated by asserting

the PROG_B pin. The end of the memory-clearing phase is

signaled by the INIT_B pin going High, and the completion

of the entire process is signaled by the DONE pin going

High. The Global Set/Reset (GSR) signal is pulsed after the

last frame of configuration data is written but before the

start-up sequence. The GSR signal resets all flip-flops on

the device.

The default start-up sequence is that one CCLK cycle after

DONE goes High, the global 3-state signal (GTS) is

released. This permits device outputs to turn on as neces-

sary. One CCLK cycle later, the Global Write Enable (GWE)

signal is released. This permits the internal storage ele-

Tabl e 2 5 : Virtex-II Configuration Mode Pin Settings

Configuration Mode(1) M2 M1 M0 CCLK Direction Data Width Serial DOUT(2)

Master Serial 0 0 0 Out 1 Yes

Slave Serial 1 1 1 In 1 Yes

Master SelectMAP 0 1 1 Out 8 No

Slave SelectMAP 1 1 0 In 8 No

Boundary-Scan 1 0 1 N/A 1 No

Notes:

1. The HSWAP_EN pin controls the pull-ups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin

controls whether or not the pull-ups are used.

2. Daisy chaining is possible only in modes where Serial DOUT is used. For example, in SelectMAP modes, the first device does NOT

support daisy chaining of downstream devices.

Tabl e 2 6 : Virtex-II Bitstream Lengths

Device # of Configuration Bits

XC2V40 338,976

XC2V80 598,816

XC2V250 1,593,632

XC2V500 2,560,544

XC2V1000 4,082,592

XC2V1500 5,170,208

XC2V2000 6,812,960

XC2V3000 10,494,368

XC2V4000 15,659,936

XC2V6000 21,849,504

XC2V8000 26,194,208

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Product Specification 38

ments to begin changing state in response to the logic and

the user clock.

The relative timing of these events can be changed via con-

figuration options in software. In addition, the GTS and

GWE events can be made dependent on the DONE pins of

multiple devices all going High, forcing the devices to start

synchronously. The sequence can also be paused at any

stage, until lock has been achieved on any or all DCMs, as

well as the DCI.

Readback

In this mode, configuration data from the Virtex-II FPGA

device can be read back. Readback is supported only in the

SelectMAP (master and slave) and Boundary-Scan mode.

Along with the configuration data, it is possible to read back

the contents of all registers, distributed SelectRAM, and

block RAM resources. This capability is used for real-time

debugging. For more detailed configuration information, see

the Virtex-II Platform FPGA User Guide.

Bitstream Encryption

Virtex-II devices have an on-chip decryptor using one or two

sets of three keys for triple-key Data Encryption Standard

(DES) operation. Xilinx software tools offer an optional

encryption of the configuration data (bitstream) with a tri-

ple-key DES determined by the designer.

The keys are stored in the FPGA by JTAG instruction and

retained by a battery connected to the VBATT pin, when the

device is not powered. Virtex-II devices can be configured

with the corresponding encrypted bitstream, using any of

the configuration modes described previously.

A detailed description of how to use bitstream encryption is

provided in the Virtex-II Platform FPGA User Guide. For

devices that support this feature, please contact your sales

representative for specific ordering part number.

Partial Reconfiguration

Partial reconfiguration of Virtex-II devices can be accom-

plished in either Slave SelectMAP mode or Boundary-Scan

mode. Instead of resetting the chip and doing a full configu-

ration, new data is loaded into a specified area of the chip,

while the rest of the chip remains in operation. Data is

loaded on a column basis, with the smallest load unit being

a configuration “frame” of the bitstream (device size depen-

dent).

Partial reconfiguration is useful for applications that require

different designs to be loaded into the same area of a chip,

or that require the ability to change portions of a design

without having to reset or reconfigure the entire chip.

Revision History

This section records the change history for this module of the data sheet.

Date Version Revision

11/07/00 1.0 Early access draft.

12/06/00 1.1 Initial release.

01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II

Switching Characteristics sections.

01/25/01 1.3 The data sheet was divided into four modules (per the current style standard). A note was

added to Ta bl e 1 .

04/02/01 1.5

• Under Input/Output Individual Options, the range of values for optional pull-up and

pull-down resistors was changed to 10 - 60 KΩ from 50 - 100 KΩ.

• Skipped v1.4 to sync up modules. Reverted to traditional double-column format.

07/30/01 1.6

• Added Table 6.

• Changed definition of multiply and divide integer ranges under Digital Clock Manager

(DCM).

• Made numerous minor edits throughout this module.

10/02/01 1.7 • Updated descriptions under Digitally Controlled Impedance (DCI), Global Clock

Multiplexer Buffers, Digital Clock Manager (DCM), and Creating a Design.

10/12/01 1.8 • Made clarifying edits under Digital Clock Manager (DCM).

11/29/01 1.9 • Changed bitstream lengths for each device in Ta bl e 2 6 .

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Product Specification 39

07/16/02 2.0 • Updated compatible input standards listed in Table 6.

09/26/02 2.1 • Changed number of resources available to the XC2V40 device in Ta b le 1 3 .

• Clarified Power On Reset information under Configuration Sequence.

12/06/02 2.1.1 • Cosmetic edits.

05/07/03 2.1.2

• Added qualification note to Figure 13, page 11.

• Corrected sentence in section Input/Output Individual Options, page 4, to read “The

optional weak-keeper circuit is connected to each user I/O pad.”

• Corrected typographical errors in Tabl e 3 for names of HSTL_[x]_DCI_18 standards.

06/19/03 2.2

• Removed Compatible Output Standards and Compatible Input Standards tables.

• Added new Tabl e 5 , Summary of Voltage Supply Requirements for All Input and

Output Standards. This table replaces deleted I/O standards tables.

• Added section Rules for Combining I/O Standards in the Same Bank, page 6.

08/01/03 3.0 All Virtex-II devices and speed grades now Production. See Table 13, Module 3.

10/14/03 3.1 • Added section Local Clocking, page 29.

•Table 1, page 1:

- Added SSTL18_I and SSTL18_II.

- Corrected names of 1.8V HSTL_I-IV standards to “HSTL_I-IV_18”.

- Corrected Input VREF for HSTL_III-IV_18 from 1.08V to 1.1V.

- Changed “N/A” to “N/R” (no requirement).

•Table 2, page 2:

- Changed “N/A” to “N/R” (no requirement).

•Table 3, page 2:

- Added SSTL18_I_DCI, SSTL18_II_DCI, LVDS_33_DCI, LVDSEXT_33_DCI,

LVDS_25_DCI, and LVDSEXT_25_DCI.

- Corrected Input VREF for HSTL_III-IV_18 from 1.08V to 1.1V.

• Sections Slave-Serial Mode and Master-Serial Mode, page 36: Changed "rising" to

"falling" edge with respect to DOUT.

• Added verbiage to section Bitstream Encryption, page 38: “For devices that support

this feature, please contact your sales representative for specific ordering part

number.”

03/29/04 3.2 • Table 2, page 2, and Table 5, page 7: Removed LVDS_33_DCI and

LVDSEXT_33_DCI from tables.

•Table 26, page 37: Updated bitstream lengths.

• Section BUFGMUX, page 29: Corrected the definition of the "presently selected clock"

to be I0 or I1. Corrected signal names in Figure 44 and associated text from CLK0 and

CLK1 to I0 and I1.

• Recompiled for backward compatibility with Acrobat 4 and above.

06/24/04 3.3 • Table 1, page 1: Added example to Footnote (1) regarding VCCO rules for GTL and

GTLP.

• Added reference to Pb-free package types in Figure 7, page 6.

03/01/05 3.4 • Reassigned heading hierarchies for better agreement with content.

•Tabl e 2 : Corrected VOD output voltages.

•Tabl e 2 6 : Updated bitstream lengths.

11/05/07 3.5 • Updated copyright statement and legal disclaimer.

•Boundary-Scan (JTAG, IEEE 1532) Mode, page 37: Updated IEEE 1149.1 compliance

statement.

Date Version Revision

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Product Specification 40