PIC16(L)F1934/1936/1937 PIC16(L)F1934/1936/1937 Family Silicon Errata and Data Sheet Clarification The PIC16(L)F1934/1936/1937 family devices that you have received conform functionally to the current Device Data Sheet (DS41364E), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC16(L)F1934/1936/1937 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A7). For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 3 or PICkitTM 3: 1. 2. 3. 4. Using the appropriate interface, connect the device to the MPLAB ICD 3 programmer/ debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: Data Sheet clarifications and corrections start on page 10, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC16(L)F1934/ 1936/1937 silicon revisions are shown in Table 1. SILICON DEVREV VALUES DEVICE ID<13:0>(1),(2) Part Number DEV<8:0> Revision ID for Silicon Revision A2 A3 A5 A6 A7 PIC16F1934 10 0011 010 0 0010 0 0011 0 0101 0 0110 0 0111 PIC16LF1934 10 0100 010 0 0010 0 0011 0 0101 0 0110 0 0111 PIC16F1936 10 0011 011 0 0010 0 0011 0 0101 0 0110 0 0111 PIC16LF1936 10 0100 011 0 0010 0 0011 0 0101 0 0110 0 0111 PIC16F1937 10 0011 100 0 0010 0 0011 0 0101 0 0110 0 0111 PIC16LF1937 10 0100 100 0 0010 0 0011 0 0101 0 0110 0 0111 Note 1: 2: The Device ID is located in the configuration memory at address 8006h. Refer to the "PIC16F193X/LF193X and PIC16F194X/LF194X Memory Programming Specification" (DS41397) for detailed information on Device and Revision IDs for your specific device. 2009-2012 Microchip Technology Inc. DS80479H-page 1 PIC16(L)F1934/1936/1937 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A2 A3 A5 A6 A7 X X Data EE Memory Memory Endurance 1.1 Erase/Write Endurance limited. X X X Data EE Memory Writes 1.2 Min. VDD for writes. X X X Program Flash Memory (PFM) Endurance 2.1 Erase/Write Endurance limited. X X X Program Flash Memory (PFM) Writes 2.2 Min. VDD for writes. X X X X X Capture Compare PWM (CCP) PWM Dead-Band Delay 3.1 Unpredictable waveforms. X X X X X Capture Compare PWM (CCP) ECCP2 Switching 3.2 PWM outputs. X X X X X Capture Compare PWM (CCP) ECCP2 Changing Direction 3.3 Outputs will improperly go active. X X X X X Capture Compare PWM (CCP) Capture mode 3.4 Capture will be triggered. X X X X X Capture Compare PWM (CCP) ECCPx Dead-Time Delay 3.5 Dead-band delay. X X X X X Capture Compare PWM (CCP) PWM with Pulse Steering 3.6 PWM output. X X X X X Capture Compare PWM (CCP) Capture mode 3.7 Capture will be triggered. X X X X X Brown-Out Reset (BOR) Threshold 4.1 Voltage level. X ADC ADC Conversion 5.1 ADC conversion may not complete. X X X Oscillator HS Oscillator 6.1 HS oscillator min. VDD. X X X Oscillator HFINTOSC Ready/ Stable bit 6.2 Bits remained set to `1' after initial trigger. X X X X X Oscillator Clock Switching 6.3 Clock switching can cause a single corrupted instruction. X X X X X Oscillator Oscillator Start-up Timer (OST) bit 6.4 OST bit remains set. X X X X X Enhanced Capture Compare PWM (ECCP) Enhanced PWM 7.1 PWM 0% duty-cycle direction change. X X X X X Enhanced Capture Compare PWM (ECCP) Enhanced PWM 7.2 PWM 0% duty-cycle port steering. X X X X X Timer1 Timer0 Gate Source 8.1 Toggle mode works improperly. X X X X X Timer1 Timer1 Gate Toggle mode 8.2 T1 gate flip-flop does not clear. X X X X X LDO Minimum VDD above 85C 9.1 Minimum operating VDD for the PIC16F193X devices at TA > 85C. X X X X X Enhanced Universal Synchronous Asynchronous Receiver (EUSART) Auto-Baud Detect 10.1 Auto-Baud Detect may store incorrect count value in the SPBRG registers. X X X X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80479H-page 2 2009-2012 Microchip Technology Inc. PIC16(L)F1934/1936/1937 Silicon Errata Issues Note: 2.2 Program Flash Memory Writes at Min. VDD This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A7). 1. Module: Data EE Memory 1.1 Data EE Memory Endurance The typical write/erase endurance of the data EE memory is limited to 10k cycles. Work around Use error correction method that stores data in multiple locations. Affected Silicon Revisions A2 A3 A5 X X X A6 A7 1.2 Data EE Write at Min. VDD The minimum voltage required for a data EE write operation is 2.0 volts. Work around None. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 2. Module: Program Flash Memory (PFM) 2.1 Program Flash Memory Endurance The typical write/erase endurance of the PFM is limited to 1k cycles when VDD is above 3.0 volts. Endurance degrades when VDD is below 3V. Work around Use an error correction method that stores data in multiple locations. Affected Silicon Revisions A2 A3 A5 X X X A6 A7 The minimum voltage required for a PFM write operation is 2.0V. Work around None. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 3. Module: Capture Compare PWM (CCP) 3.1 Dead-Band Delay With the ECCP configured for PWM Half-Bridge mode and a dead-band delay greater than or equal to the PWM duty cycle; unpredictable waveforms will result. Work around Make sure the dead-band delay is always less than the PWM duty cycle. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 3.2 ECCP2 Switching Between Single, HalfBridge and Full-Bridge PWM modes Switching PWM mode during the current PWM cycle by modifying the P2M<1:0> bits in the CCP2CON register will cause the PWM outputs to switch immediately and not on the start of the next PWM cycle. Work around None. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 3.3 ECCP2 Changing Direction in Full-Bridge PWM modes When changing direction, the active and modulated outputs will improperly go active at the same time and the dead time does not occur, which can lead to large shoot-through currents. Work around None. Affected Silicon Revisions 2009-2012 Microchip Technology Inc. A2 A3 A5 A6 A7 X X X X X DS80479H-page 3 PIC16(L)F1934/1936/1937 3.4 Capture mode Selected while CCPx Pin is Held High If the module is configured to capture on the first rising edge and the CCPx pin is high at this time, a capture will be triggered. 4. Module: Brown-Out Reset (BOR) 4.1 Brown-Out Threshold Configuring the BOR for 2.5V operation, the Reset will typically occur at 2.7V. Work around Work around Clear the CCP interrupt flag (CCPxIF = 0) immediately after configuring the module for a capture event. None. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X Affected Silicon Revisions A2 A3 A5 A6 A7 X 3.5 ECCPx Dead-Time Delay in Half-Bridge mode In Half-Bridge mode, the dead-band delay is 1 TOSC longer than calculated for the first PWM cycle and 1.5 TOSC for following cycles. Work around None. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 3.6 PWM with Pulse Steering Disabling a PWM output during a PWM cycle will cause the output to end 1 TOSC time earlier than expected. Work around None. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 3.7 Capture mode Selected while CCPx Pin is Held Low If the module is configured to capture on the first falling edge and the CCPx pin is low at this time, a capture will be triggered. Work around Clear the CCP interrupt flag (CCPxIF = 0) immediately after configuring the module for a capture event. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X DS80479H-page 4 2009-2012 Microchip Technology Inc. PIC16(L)F1934/1936/1937 5. Module: ADC 5.1 Analog-to-Digital Conversion An ADC conversion may not complete under these conditions: 1. 2. When FOSC is greater than 8 MHz and it is the clock source used for the ADC converter. The ADC is operating from its dedicated internal FRC oscillator and the device is not in Sleep mode (any FOSC frequency). When this occurs, the ADC Interrupt Flag (ADIF) does not get set, the GO/DONE bit does not get cleared, and the conversion result does not get loaded into the ADRESH and ADRESL result registers. Work around Method 1: Select the system clock, FOSC, as the ADC clock source and reduce the FOSC frequency to 8 MHz or less when performing ADC conversions. Method 3: This method is provided if the application cannot use Sleep mode and requires continuous operation at frequencies above 8 MHz. This method requires early termination of an ADC conversion. Provide a fixed time delay in software to stop the A-to-D conversion manually, after all 10 bits are converted, but before the conversion would complete automatically. The conversion is stopped by clearing the GO/ DONE bit in software. The GO/ DONE bit must be cleared during the last 1/2 TAD cycle, before the conversion would have completed automatically. Refer to Figure 1 for details. Method 2: Select the dedicated FRC oscillator as the ADC conversion clock source and perform all conversions with the device in Sleep. FIGURE 1: INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE FOSC = 32 MHz TCY = 4/32 MHz = 125 nsec TAD = 1 sec, ADCS = FOSC/32 88 TCY 8 TCY 84 TCY } 4 TCY 11 TAD Stop the A/D conversion between 10.5 and 11 TAD cycles. See the Analog-to-Digital Conversion Timing diagram in the Analog-to-Digital Converter chapter of the device data sheet. 1 TAD See the ADC Clock Period (TAD) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter chapter of the device data sheet. In Figure 1, 88 instruction cycles (TCY) will be required to complete the full conversion. Each TAD cycle consists of 8 TCY periods. A fixed delay is provided to stop the A/D conversion after 86 instruction cycles and terminate the conversion at the correct time as shown in the figure above. 2009-2012 Microchip Technology Inc. DS80479H-page 5 PIC16(L)F1934/1936/1937 6. Module: Oscillator Note: The exact delay time will depend on the TAD divisor (ADCS) selection. The TCY counts shown in the timing diagram above apply to this example only. Refer to Table 3 for the required delay counts for other configurations. EXAMPLE 1: CODE EXAMPLE OF INSTRUCTION CYCLE DELAY BSF ADCON0, ADGO BCF ADCON0, ADGO MOVF ADRESH, W ; Start ADC conversion ; Provide 86 instruction cycle delay here ; Terminate the conversion manually ; Read conversion result For other combinations of FOSC, TAD values and Instruction cycle delay counts, refer to Table 3. 6.1 HS Oscillator The HS oscillator requires a minimum voltage of 3.0 volts (at 65C or less) to operate at 20 MHz. Work around None. Affected Silicon Revisions A2 A3 A5 X X X A6 A7 6.2 OSCSTAT bits: HFIOFR and HFIOFS When HFINTOSC is selected, the HFIOFR and HFIOFS bits will become set when the oscillator becomes ready and stable. Once these bits are set, they become "stuck", indicating that HFINTOSC is always ready and stable. If the HFINTOSC is disabled, the bits fail to be cleared. Work around None. TABLE 3: INSTRUCTION CYCLE DELAY COUNTS BY TAD SELECTION Affected Silicon Revisions Instruction Cycle Delay Counts A2 A3 A5 A6 A7 FOSC/64 172 X X X X X FOSC/32 86 FOSC/16 43 TAD Affected Silicon Revisions A2 A3 A5 X X X A6 A7 6.3 Clock Switching When switching clock sources between INTOSC clock source and an external clock source, one corrupted instruction may be executed after the switch occurs. This issue does not affect Two-Speed Start-up or the Fail-Safe Clock Monitor operation. Work around When switching from an external oscillator clock source, first switch to 16 MHz HFINTOSC. Once running at 16 MHz HFINTOSC, configure IRCF to run at desired internal oscillator frequency. When switching from an internal oscillator (INTOSC) to an external oscillator clock source, first switch to HFINTOSC High-Power mode (8 MHz or 16 MHz). Once running from HFINTOSC, switch to the external oscillator clock source. Affected Silicon Revisions DS80479H-page 6 A2 A3 A5 A6 A7 X X X X X 2009-2012 Microchip Technology Inc. PIC16(L)F1934/1936/1937 6.4 Oscillator Start-up Timer (OST) bit During the Two-Speed Start-up sequence, the OST is enabled to count 1024 clock cycles. After the count is reached, the OSTS bit is set, the system clock is held low until the next falling edge of the external crystal (LP, XT or HS mode), before switching to the external clock source. When an external oscillator is configured as the primary clock and Fail-Safe Clock mode is enabled (FCMEN = 1), any of the following conditions will result in the Oscillator Start-up Timer (OST) failing to restart: * MCLR Reset * Wake from Sleep * Clock change from INTOSC to Primary Clock This anomaly will manifest itself as a clock failure condition for external oscillators which take longer than the clock failure time-out period to start. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 7. Module: Enhanced Capture Compare PWM (ECCP) 7.1 Enhanced PWM When the PWM is configured for Full-Bridge mode and the duty cycle is set to 0%, writing the PxM<1:0> bits to change the direction has no effect on PxA and PxC outputs. Work around Increase the duty cycle to a value greater than 0% before changing directions. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 7.2 Enhanced PWM 8. Module: Timer1 8.1 Timer1 Gate Toggle mode with Timer0 as Gate Source Timer1 Gate Toggle mode provides unexpected results when Timer0 overflow is selected as the Timer1 gate source. We do not recommend using Timer0 overflow as the Timer1 gate source while in Timer1 Gate Toggle mode or when Toggle mode is used in conjunction with Timer1 Gate Single-Pulse mode. Work around None. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 8.2 Timer1 Gate Toggle mode When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal. To perform this function, the Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the gate signal. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When working properly, clearing either the T1GTM bit or the TMR1ON bit would also clear the output value of this flip-flop, and hold it clear. This is done in order to control which edge is being measured. The issue that exists is that clearing the TMR1ON bit does not clear the output value of the flip-flop and hold it clear. Work around Clear the T1GTM bit in the T1GCON register to clear and hold clear the output value of the flipflop. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X In PWM mode, when the duty cycle is set to 0% and the STRxSYNC bit is set, writing the STRxA, STRxB, STRxC and the STRxD bits to enable/ disable steering to port pins has no effect on the outputs. Work around Increase the duty cycle to a value greater than 0% before enabling/disabling steering to port pins. Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 2009-2012 Microchip Technology Inc. DS80479H-page 7 PIC16(L)F1934/1936/1937 9. Module: LDO 9.1 Minimum VDD above 85C The minimum voltage required for the PIC16F193X devices is 3.5 volts for temperatures above 85C. Note: 10. Module: Enhanced Universal Synchronous Asynchronous Receiver (EUSART) 10.1 Auto-Baud Detect When using automatic baud detection (ABDEN), on occasion, an incorrect count value can be stored at the end of auto-baud detection in the SPBRGH:SPBRGL (SPBRG) registers. The SPBRG value may be off by several counts. This condition happens sporadically when the device clock frequency drifts to a frequency where the SPBRG value oscillates between two different values. The issue is present regardless of the baud rate Configuration bit settings. This issue only applies to the PIC16F193X devices operating in the Extended temperature range. The PIC16LF193X devices are not affected. Work around None. Affected Silicon Revisions A2 A3 A5 A6 A7 Work around X X X X X When using auto-baud, it is a good practice to always verify the obtained value of SPBRG, to ensure it remains within the application specifications. Two recommended methods are shown below. For additional auto-baud information, see Technical Brief TB3069, "Use of Auto-Baud for Reception of LIN Serial Communications Devices: Mid-Range and Enhanced Mid-Range". EXAMPLE 2: METHOD 1 - EUSART AUTO-BAUD DETECT WORK AROUND In firmware, define default, minimum and maximum auto-baud (SPBRG) values according to the application requirements. For example, if the application runs at 9600 baud at 16 MHz then, the default SPBRG value would be (assuming 16-bit/ Asynchronous mode) 0x67. The minimum and maximum allowed values can be calculated based on the application. In this example, a +/-5% tolerance is required, so tolerance is 0x67 * 5% = 0x05. #define SPBRG_16BIT const const const const * * * ABDEN while int int int int *((*int)&SPBRG; DEFAULT_BAUD = 0x0067; TOL = 0x05; MIN_BAUD = DEFAULT_BAUD - TOL; MAX_BAUD = DEFAULT_BAUD + TOL; = 1; (ABDEN); // define location for 16-bit SPBRG value // // // // Default Auto-Baud value Baud Rate % tolerance Minimum Auto-Baud Limit Maximum Auto-Baud Limit // Start Auto-Baud // Wait until Auto-Baud completes if((SPBRG_16BIT > MAX_BAUD)||(SPBRG_16BIT < MIN_BAUD)) { // Compare if value is within limits SPBRG_16BIT = DEFAULT_BAUD); // if out of spec, use DEFAULT_BAUD } * // if in spec, continue using the * // Auto-Baud value in SPBRG * DS80479H-page 8 2009-2012 Microchip Technology Inc. PIC16(L)F1934/1936/1937 EXAMPLE 3: METHOD 2 - EUSART AUTO-BAUD DETECT WORK AROUND Similar to Method 1, define default, minimum and maximum auto-baud (SPBRG) values. In firmware, compute a running average of SPBRG. If the new SPBRG value falls outside the minimum or maximum limits, then use the current running average value (Average_Baud), otherwise use the auto-baud SPBRG value and calculate a new running average. For example, if the application runs at 9600 baud at 16 MHz then, the default SPBRG value would be (assuming 16-bit/ Asynchronous mode) 0x67. The minimum and maximum allowed values can be calculated based on the application. In this example, a +/-5% tolerance is required, so tolerance is 0x67 * 5% = 0x05. #define SPBRG_16BIT const const const const int int int int *((*int)&SPBRG; DEFAULT_BAUD = 0x0067; TOL = 0x05; MIN_BAUD = DEFAULT_BAUD - TOL; MAX_BAUD = DEFAULT_BAUD + TOL; int Average_Baud; int Integrator; * * * Average_Baud = DEFAULT_BAUD; Integrator = DEFAULT_BAUD*15; * * * ABDEN = 1; while (ABDEN); // define location for 16-bit SPBRG value // // // // Default Auto-Baud value Baud Rate % tolerance Minimum Auto-Baud Limit Maximum Auto-Baud Limit // Define Average_Baud variable // Define Integrator variable // Set initial average Baud rate // The running 16 count average // Start Auto-Baud // Wait until Auto-Baud completes Integrator+ = SPBRG_16BIT; Average_Baud = Integrator/16; if((SPBRG_16BIT > MAX_BAUD)||(SPBRG_16BIT < MIN_BAUD)) { // Check if value is within limits SPBRG_16BIT = Average_Baud; // If out of spec, use previous average } else // If in spec, calculate the running { // average but continue using the Integrator+ = SPBRG_16BIT; // Auto-Baud value in SPBRG Average_Baud = Integrator/16; Integrator- = Average_Baud; } * * * Affected Silicon Revisions A2 A3 A5 A6 A7 X X X X X 2009-2012 Microchip Technology Inc. DS80479H-page 9 PIC16(L)F1934/1936/1937 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41364E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Oscillator 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware. DS80479H-page 10 2009-2012 Microchip Technology Inc. PIC16(L)F1934/1936/1937 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (9/2009) Initial release of this document. Rev B Document (1/2010) Added silicon revision A5. Rev C Document (5/2010) Added Modules 5, 6, 7 and 8. Data Sheet Clarifications: Added Modules 1 and 2. Rev D Document (6/2010) Added Silicon Revision A6. Rev E Document (7/2010) Revised Module 5.1; Added Module 8.2; Other minor corrections. Rev F Document (9/2010) Added Module 9, LDO. Rev G Document (9/2011) Added Silicon Revision A7. Data Sheet Clarifications: Removed Modules 1 and 2. Rev H Document (2/2012) Updated Table 1; Added Module 6.2, 6.3 and 6.4; Added Module 10, EUSART; Other minor corrections. Data Sheet Clarifications: Added Module 1, Oscillator. 2009-2012 Microchip Technology Inc. DS80479H-page 11 PIC16(L)F1934/1936/1937 NOTES: DS80479H-page 12 2009-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. 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Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620760598 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2009-2012 Microchip Technology Inc. DS80479H-page 13 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS80479H-page 14 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 11/29/11 2009-2012 Microchip Technology Inc.