1. General description
The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel
converter). Each shift register has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input
(MR). Information present on D is shifted to the first register position, and all the data in
the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A
HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.
The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise
and fall times.
It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C.
Complies with JEDEC standard JESD 13-B
3. Applications
Serial-to-parallel converter
Buffer stores
General purpose register
4. Ordering information
HEF4015B
Dual 4-bit static shift register
Rev. 8 — 21 November 2011 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +85
C.
Type number Package
Name Description Version
HEF4015BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4015BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 2 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
5. Functional diagram
Fig 1. Functional di agram
Fig 2. Logic diagram for one register
001aae560
1D
SHIFT
REGISTER
4 BITS
SHIFT
REGISTER
4 BITS
7
910
3
5
4
1CP
1Q0
1Q1
1Q2
1Q3
6 1MR
2D15
12
11
13
12
2CP
2Q0
2Q1
2Q2
2Q3
14 2MR
001aae562
CP
MR
D
FF 1
Q0
DQ
CP
CD
FF 2
Q1
DQ
CP
CD
FF 3
Q2
DQ
CP
CD
FF 4
Q3
DQ
CP
CD
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 3 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Dn = either HIGH or LOW;
= positive-going transition; = negative-going transition.
Fig 3. Pin configuratio n
HEF4015B
2CP VDD
2Q3 2D
1Q2 2MR
1Q1 2Q0
1Q0 2Q1
1MR 2Q2
1D 1Q3
VSS 1CP
001aae561
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
1Q0 to 1Q3 5, 4, 3, 10 parallel output
2Q0 to 2Q3; 13, 12, 11, 2 parallel output
1MR, 2MR 6, 14 master reset input (active HIGH)
1D, 2D 7, 15 serial data input
VSS 8 ground supply voltage
1CP, 2CP 9, 1 clock input (LOW-to-HIGH edge-triggered)
VDD 16 supply voltage
Table 3. Function table [1]
number of clock
pulse transitions Input Output
CP DMR Q0 Q1 Q2 Q3
1 D1LD1XXX
2 D2 L D2 D1 X X
3 D3L D3D2D1X
4 D4L D4D3D2D1
X L no change no change no change no change
XXHLLLL
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 4 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping current VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation Tamb = 40 C to +85 C
DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
P power dissipation per output - 100 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VIinput voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5 V --3.75s/V
VDD = 10 V --0.5s/V
VDD = 15 V --0.08s/V
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 5 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
10. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit
Min Max Min Max Min Max
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.3 6 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
IIinput leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0 A 5 V - 20 - 20 - 150 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A
CIinput capacitance - - - - 7.5 - - pF
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 6 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
11. Dynamic characteristics
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 7. Dynamic characteristics
VSS = 0 V; CL = 50 pF; Tamb = 25
C.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW
propagation delay nCP to Qn;
see Figure 4 5 V 103 ns + (0.55 ns/pF)CL- 130 260 ns
10 V 44 ns + (0.23 ns/pF)CL- 55 110 ns
15 V 32 ns + (0.16 ns/pF)CL- 4080ns
nMR to Qn;
see Figure 6 5 V 78 ns + (0.55 ns/pF)C L- 105 210 ns
10 V 34 ns + (0.23 ns/pF)CL- 4590ns
15 V 27 ns + (0.16 ns/pF)CL- 3570ns
tPLH LOW to HIGH
propagation delay nCP to Qn
see Figure 4 5 V 93 ns + (0.55 ns/pF)C L- 120 240 ns
10 V 44 ns + (0.23 ns/pF)CL- 55 110 ns
15 V 32 ns + (0.16 ns/pF)CL- 4080ns
tttransition time see Figure 4 5 V 10 ns + (1.00 ns/pF)CL-60120ns
10 V 9 ns + (0.42 ns/pF)CL- 3060ns
15 V 6 ns + (0.28 ns/pF)CL- 2040ns
tsu set-up time nD to nCP;
see Figure 5 5 V +25 15 - ns
10 V +25 10 - ns
15 V +20 5- ns
thhold time nD to nCP;
see Figure 5 5 V 40 20 - ns
10 V 20 10 - ns
15 V 15 8 - ns
tWpulse width nCP LOW;
minimum width;
see Figure 5
5 V 60 30 - ns
10 V 30 15 - ns
15 V 20 10 - ns
nMR HIGH;
minimum width;
see Figure 6
5 V 80 40 - ns
10 V 30 15 - ns
15 V 24 12 - ns
trec recovery time pin nMR;
see Figure 6 5 V 50 20 - ns
10 V 30 10 - ns
15 V 20 5 - ns
fmax maximum frequency see Figure 5 5 V 7 15 - MHz
10 V 15 30 - MHz
15 V 22 44 - MHz
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 7 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
12. Waveforms
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula for PD (W) where:
PDdynamic power
dissipation 5V P
D = 1500 fi + (fo CL) VDD2fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
10 V PD = 6300 fi + (fo CL) VDD2
15 V PD = 17000 fi + (fo CL) VDD2
Measurement points are given in Table 9.
Fig 4. Waveforms showing nCP p ropagation delays and n Qn transition times
001aaj464
tPHL
tttt
nCP input
nQn output
VI
VSS
VM
VOH
VOL
VM
90 %
10 %
tPLH
The shaded area indicates where the input is permitted to change for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values;
Measurement points are given in Table 9.
Fig 5. Waveforms showing set-up times, hold times, and minimum clock pulse width
nCP input
nD input
001aae563
tW
th
VMVM
VMVM
tsu tsu
th
1/fmax
VM
VM
VI
VM
VSS
VI
VSS
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 8 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
Measurement points are given in Table 9.
Fig 6. Waveforms showing MR recover y time, propagation delay and minimum p ulse width
tW
tPHL
trec
VM
VI
VM
VM
001aae564
nMR input
nCP input
nQn output VM
VSS
VI
VSS
VOH
VOL
Table 9. Measurement points
Supply voltage Input Output
VDD VMVM
5 V to 15 V 0.5VDD 0.5VDD
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 9 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
a. Input waveforms
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test;
CL= load capacitance including jig and probe capacitance;
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 7. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
VDD
VIVO
001aag182
DUT
CL
RT
G
Table 10. Test data
Supply voltage Input Load
VDD VItr, tfCL
5 V to 15 V VSS or VDD 20 ns 50 pF
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 10 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
13. Package outline
Fig 8. Package outline SOT38-4 (DIP16)
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 11 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
Fig 9. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 12 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
14. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4015B v.8 2011112 1 Product data sheet - HEF4015B v.7
Modifications: •Legal pages updated.
•Changes in “General description” and “Features and benefits”.
HEF4015B v.7 20110914 Product data sheet - HEF4015B v.6
HEF4015B v.6 20091103 Product data sheet - HEF4015B v.5
HEF4015B v.5 20090624 Product data sheet - HEF4015B v.4
HEF4015B v.4 20090127 Product data sheet - HEF4015B_CNV v.3
HEF4015B_CNV v.3 19950101 Product specification - HEF4015B_CNV v.2
HEF4015B_CNV v.2 19950101 Product specification - -
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 13 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe propert y or environment al
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Pro duction This document contains the product specification.
HEF4015B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 14 of 15
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed produ ct claims result ing from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4015B
Dual 4-bit static shift register
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 21 Novem ber 2011
Document iden tifier: HE F4015B
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16 Contact information. . . . . . . . . . . . . . . . . . . . . 14
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15