MIC4605
85V Half-Bridge MOSFET Drivers
with Adaptive Dead Time and
Shoot-Through Protection
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
November 11, 2013
Revision 1.0
General Description
The MIC4605 is an 85V half-bridge MOSFET driver that
features adaptive-dead-time and shoot-through protection.
The adapt ive-dead-tim e circuitr y activel y monitors the half-
bridge out puts to m inimize the tim e between high-si de and
low-side MOSFET transitions, thus maximizing power
eff iciency. Anti-shoot-through cir cuitry pre vents errone ous
inputs and noise from turning both MOSFETS on at the
same time.
The MIC4605 also offers a wide 5.5V to 16V operating
suppl y range to m ax imize system eff icienc y. The low 5.5V
operating voltage allows longer run times in battery-
powered applications. Additionally, the MIC4605’s
adjustable gate drive sets the gate drive voltage to VDD
for optimal MOSFET RDS(ON), which minimizes power loss
due to the MOSFET’s RDS(ON).
The MIC4605 is availab le in an 8-pin SOIC p ackage and a
tiny 10-pin 2.5mm × 2.5mm TDFN package. Both
pack ages have an op erati ng junc tion tem perature r an ge of
–40°C to +125°C.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
• 5.5V to 16V gate drive supply voltage range
• Advanced adaptive-dead-time
• Intelligent shoot-thr ou gh prot ecti on
− MIC4605-1: Dual TTL inputs
− MIC4605-2: Single PWM input
• Enable input for on/off control
• On-chip bootstrap diode
• Fast 35ns propagation times
• Drives 1000pF load with 20ns rise and fall times
• Low power consumption: 135µA quiescent current
• Separate high- and low-side undervoltage protection
• –40°C to +125°C junction temperature range
Applications
• Fans
• Power invert ers
• High-voltage step-down regulators
• Half-, full-, and three-phase bridge motor drives
• Appliances
• E-bikes
MIC4605 Door Lock/Unlock Module
Micrel, Inc.
MIC4605
November 11, 2013
2 Revision 1.0
Ordering Information
Part Number Part Marking Input Junction Temperature Range Package
MIC4605-1YMT 165 Dual TTL Inputs –40°C to +125°C 10-pin 2.5mm × 2.5mm TDFN
MIC4605-2YMT 265 Single PWM TTL Input –40°C to +125°C 10-pin 2.5mm × 2.5mm TDFN
MIC4605-1YM 4605-1YM Dual TTL Inputs –40°C to +125°C 8-pin SOIC-8
MIC4605-2YM 4605-2YM Single PWM TTL Input –40°C to +125°C 8-pin SOIC-8
Pin Configurations
MIC4605-1YMT
10-Pin 2.5mm × 2.5mm TDFN (MT)
(Top View)
MIC4605-2YMT
10-Pin 2.5mm × 2.5mm TDFN (MT)
(Top View)
MIC4605-1YM
8-Pin SOIC (M)
(Top View)
MIC4605-2YM
8-Pin SOIC (M)
(Top View)
Micrel, Inc.
MIC4605
November 11, 2013
3 Revision 1.0
Pin Description
MIC4605-1
TDFN
Pin
Number
MIC4605-2
TDFN
Pin
Number
MIC4605-1
SOIC-8
Pin
Number
MIC4605-2
SOIC-8
Pin
Number
Pin
Name Pin Function
1 1 — — EN Enable Input. Logic high on the enable pin results in
normal operation, conversely, the device enters shutdown
mode with a logic l ow applied to enable.
2 2 1 1 VDD Input Supply for Gate Drivers. Decouple this pin to VSS
with a >0.1µF cap ac itor.
3 3 2 2 HB
High-Side Bootstrap Supply. An external bootstrap
capacitor is required. Connect the bootstrap capac itor
across this pin and HS. An on-board bootstrap diode is
connected from VDD to HB.
4 4 3 3 HO High-Side Drive Output. Connect to the gat e of the
external high-side pow er MOSFET .
5 5 4 4 HS High-Side Drive Reference Connection. Connect to
source of the external high-side power MOSFET. Connect
the bottom of bootstrap capacitor to this pin.
6 — 5 — HI High-Side Drive Input
— 6 — 5 PWM Single PWM Input. Drives both the high- and low-side
outputs out of phase
7 — 6 — LI Low-Side Drive Input.
— 7 — 6 NC No Connect. This pin is not connected internally.
8 8 7 7 VSS Driver Reference Supply Input. Generally connected to
the power ground of ex ternal c ircu itr y .
9 9 8 8 LO Low-Side Drive Output. Connect to the gate of the
external low-side pow er M O SFET .
10 10 — — NC No Connect. This pin is not connected internally.
EP EP — — ePad Exposed Pad. Connect to VSS.
Micrel, Inc.
MIC4605
November 11, 2013
4 Revision 1.0
Absolute Maximum Ratings(1)
Supply Voltage (VDD, VHB – VHS) .................... −0.3V to 18V
Input Voltages (VLI, VHI, VEN) ............... −0.3V to VDD + 0.3V
Voltage on LO (VLO) ............................ −0.3V to VDD + 0.3V
Voltage on HO (VHO) ..................... VHS − 0.3V to VHB + 0.3V
Voltage on HS (continuous) ............................... −1V to 90V
Voltage on HB .............................................................. 108V
Average Current in VDD to HB Diode ....................... 100mA
Storage Temperature (TS) ......................... −60°C to +150°C
ESD Rating(3)
HBM ......................................................................... 1kV
MM ......................................................................... 200V
Operating Ratings(2)
Supply Voltage (VDD) [decreasing VDD]........ 5.25V to 16V
Supply Voltage (VDD) [increasing VDD] ........... 5.5V to 16V
Voltage on HS .................................................... −1V to 85V
Voltage on HS (repetitive transient) ................... −5V to 90V
HS Slew Rate ............................................................ 50V/ns
Voltage on HB ..................................................... VHS + VDD
and/or ...................................... VDD − 1V to VDD + 85V
Junction Temperature (TJ) ........................ –40°C to +125°C
Junction Thermal Resistance
2.5mm × 2.5mm TDFN-10L (θJA) .................... 71.4°C/W
SOIC-8L (θJA) ..................................................... 99°C/W
Electrical Characteristics(4)
VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless otherwise noted.
Bold values indicate –40°C ≤ TJ ≤ +125°C.
Symbol Parameter Condition Min. Typ. Max. Units
Supply Current
IDD VDD Quiescent Current LI = HI = 0V
100
250
µA
IDDSH VDD Shutdown Current EN = 0V with HS = floating 2.2 10 µA
EN = 0V 25 50
IDDO VDD Operating Current f = 20kHz 170 500 µA
IHB Total HB Quiescent Current LI = HI = 0V or LI = 0V and HI =5V 35 75 µA
IHBO Total HB Operating Current f = 20kHz 50 400 µA
IHBS HB to VSS Current, Quiescent VHS = VHB = 90V 0.05 5 µA
IHBSO HB t o VSS Current, Operating f = 20kHz 30 300 µA
Input (TTL: LI, HI, EN)
(5)
VIL Low-Level Input Voltage 0.8 V
VIH High-Level Input Voltage 2.2 V
VHYS Input Voltage Hysteresis 0.1 V
RI Input Pull-Down Resistance LI and HI 100 300 500 kΩ
PWM
50
130
250
Undervoltage Protection
VDDR VDD Falling Threshold 4.0 4.4 4.9 V
VDDH VDD Threshold Hysteresis 0.25 V
VHBR HB Falling Threshold 4.0 4.4 4.9 V
VHBH HB Threshold Hysteresis 0.25 V
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to functi on outside its operat i ng ratings.
3. Devices are ESD sensitive. Handling precauti ons are recommended.
4. Specific at i on for packaged product only.
5. VIL (MAX) = maxim um positi ve voltage applied to the input which will be accepted by the device as a logic low. VIH (MIN) = minimum positive voltage
applied to the input which will be accepted by the device as a logic high.
Micrel, Inc.
MIC4605
November 11, 2013
5 Revision 1.0
Electrical Characteristics(4) (Continued)
VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless otherwise noted.
Bold values indicate –40°C ≤ TJ ≤ +125°C.
Symbol Parameter Condition Min. Typ. Max. Units
Bootstrap Diode
VDL Low-Current Forward Voltage IVDD-HB = 100µA 0.4 0.70 V
VDH High-Current Forward Voltage IVDD-HB = 50mA 0.7 1.0 V
RD Dynamic Resistance IVDD-HB = 50mA 2.0 5.0 Ω
LO Gate Driver
VOLL Low-Level Output Voltage ILO = 50mA 0.3 0.6 V
VOHL High-Level Output Voltage ILO = −50mA, VOHL = VDD − VLO 0.5 1.0 V
IOHL Peak Sink Current VLO = 0V 1 A
IOLL Peak Source Current VLO = 12V 1 A
HO Gate Driver
VOLH Low-Level Output Voltage IHO = 5 0mA 0.3 0.6 V
VOHH High-Level Output Voltage IHO = −50mA, VOHH = VHB – VHO 0.5 1.0 V
IOHH Peak Sink Current VHO = 0V 1 A
IOLH Peak Source Current VHO = 12V 1 A
Switching Specifications
(LI/HI mode with inputs non-overlapping, assumes HS low before LI goes high and LO low before HI goes high)
tLPHL Lower Turn-Off Propagation Delay
(LI Falling to LO Falling) 35 75 ns
tHPHL Upper Turn-Off Propagation Delay
(HI Falling to HO Falling) 35 75 ns
tLPLH Lower Turn-On Propagation Delay
(LI Rising to LO Rising) 35 75 ns
tHPLH Upper Turn-On Propagation Delay
(HI Rising to HO Rising) 35 75 ns
tRC/FC Output Rise/Fall Time CL = 1000pF 20 ns
tR/F Output Rise/Fall Time (3V to 9V) CL = 0.1µF 0.8 µs
tPW Minimum Input Pulse Width that Changes the
Output(5) 50 ns
Switching Specifications PWM Mode (MIC4605-2) or LI/HI Mode (MIC4605-1) with Ov erlapping LI/HI Inputs
tLOOFF Delay from PWM Going High / LI Low, to LO
Going Low 35 75 ns
VLOOFF LO Output Voltage Threshold for LO FET to be
Considered Off 1.9 V
tHOON Delay from LO off to HO Going High 35 75 ns
tHOOFF Delay from PWM Going Low / HI Low, to HO
Going Low 35 75 ns
VSWTH Switch Node Voltage Threshold Signaling HO is
Off 1 2.2 4 V
Micrel, Inc.
MIC4605
November 11, 2013
6 Revision 1.0
Electrical Characteristics(4) (Continued)
VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless otherwise noted.
Bold values indicate –40°C ≤ TJ ≤ +125°C.
Symbol Parameter Condition Min. Typ. Max. Units
Switching Specifications PWM Mode (MIC4605-2) or LI/HI Mode (MIC4605-1) with Ov erlapping LI/HI Inputs
tLOON Delay Between HO FET Being Considered Off to
LO Turning On 35 75 ns
tLOONHI For HS Low/LI High, Delay from PWM/HI Low to
LO going HI 80 150 ns
tSWTO Force LO On if VSWTH is Not Detected 100 250 500 ns
Micrel, Inc.
MIC4605
November 11, 2013
7 Revision 1.0
Timing Diagrams
In LI/HI input mode, external LI/HI inputs are delayed to
the point that HS is low before LI is pulled high and
similarly LO is low before HI goes high
HO goes high with a hig h signal on HI af ter a t ypical dela y
of 35ns (tHPLH). HI going low drives HO low also with
typical delay of 35ns (tHPHL).
Likewise, LI going high forces LO high after typical delay of
35ns (tLPLH) a nd LO follows low transition of LI after typic al
delay of 35ns (tLPHL).
HO and LO output rise and fall times (tR/tF) are typically
20ns driving 1000pF capacitive loads.
Note: All propagation delays are measured from the 50%
voltage level.
Figure 1. Separate Non-Overlapping LI/HI Input Mode (MIC4605-1)
Micrel, Inc.
MIC4605
November 11, 2013
8 Revision 1.0
Timing Diagrams (Continued)
When LI/HI input on conditions overlap, LO/HO output
states are dominated by the first output to be turned on.
That is, if LI goes high (on), while HO is high, HO stays
high until HI goes lo w at which point, after a dela y of t HOOFF
and when HS < 2.2V, LO goes high with a delay of tLOON.
Should HS never trip the aforementioned internal
comparator reference (2.2V), a falling HI edge delayed by
250ns will set “HS latch” allowing LO to go high.
If HS falls very fast, LO will be held low by a 35ns delay
gated by HI going low. Conversely, HI going high (on)
when LO is high has no effect on outputs until LI is pulled
low (off ) and LO falls t o < 1.9V. Delay fr om LI going low to
LO falling is tLOOFF and delay from LO < 1.9V to HO being
on is tHOON.
Figure 2. Separate Overlapping LI/HI Input Mode (MIC4605-1)
Micrel, Inc.
MIC4605
November 11, 2013
9 Revision 1.0
Timing Diagrams (Continued)
PWM signal applied to the MIC4605-2 going low causes
HO to go low typically 35ns (tHOOFF) after the PWM input
goes low, at which point the switch node HS falls (1 − 2).
When HS reaches 2.2V (VSWTH), the external high-side
MOSFET is deem ed off and LO goes high, t ypically within
35ns (tLOON). HS falling below 1.9V sets a latch that can
only be reset by PWM going high. This design prevents
ringing on HS from causing an indeterminate LO state.
Should HS never trip the aforementioned internal
comparator reference (2.2V), a falling PWM edge delayed
by 250ns will set “HS latch” allowing LO to go high. An
80ns delay gated by PWM going low may determine the
time to LO going high for fast falling HS designs (3 − 4).
PWM goes high forcing LO low in typically 35ns (tLOOFF)
(5 − 6).
When LO reaches 1.9V (VLOOFF), the low-side MOSFET is
deemed off and HO is allowed to go high. The delay
between these two points is typically 35ns (tLOON). HO
goes high with a high signal on HI after a typical delay of
35ns (tHPLH). HI going low drives HO low also with a typical
delay of 35ns (tHPHL) (7 − 8).
HO and LO output rise and fall times (tR/tF) are typically
20ns driving 1000pF capacitive loads.
Note: All propagation delays are measured from the 50%
voltage level.
Figure 3. PWM Mode (MIC4605-2)
Micrel, Inc.
MIC4605
November 11, 2013
10 Revision 1.0
Block Diagram
For HO to be high, HI must be high and LO must be low.
HO going high is delayed by LO falling below 1.9V. The HI
and LI inputs must not rise at the same time to prevent a
glitch f rom occ urring on the output. A m inim um 50ns dela y
between both inputs is recommended.
LO is turned off very quickly on the LI falling edge. LO
going high is delayed by the longer of 35ns delay of HO
control signal going “off” or the RS latch being set.
The latch is set by the quicker of either the falling edge of
HS or LI gated delay of 240ns. The latch is present to
lockout LO bounce due to ringing on HS. If HS never
adequately falls du e to th e abs ence of or the pres enc e of a
very weak external pull-down on HS, the gated delay of
240ns at LI will set the lat ch allowin g LO to transition high.
This in turn allows the LI startup pulse to charge the
bootstrap capacitor if the load inductor current is very low
and HS is uncontrolled. The latch is reset by the LI falling
edge.
MIC4605 Top Level Block Diagram
MIC4605-1 Cross-Conduction Lockout/PWM Input Logic Block Diagram
Micrel, Inc.
MIC4605
November 11, 2013
11 Revision 1.0
Typical Characteris tics
40
60
80
100
120
140
46810 12 14 16
QUIESCENT CURRENT (µA)
INPUT VOLTAGE (V)
Quiescent Current
vs. Input Voltage
HS = 0V
T = 125°C
T = -40°C
T = 25°C
0
50
100
150
200
250
300
46810 12 14 16
VDD OPERATING CURRENT (µA)
INPUT VOLTAGE (V)
VDD Operating Current
vs. Input Voltage
FREQ = 20kHz
HS = 0V
VHB = VDD
T = 125°C
T = -40°C
T = 25°C
0
20
40
60
80
4 6 8 10 12 14 16
VHB OPERATING CURRENT (µA)
INPUT VOLTAGE (V)
VHB Operating Current
vs. Input Voltage
FREQ = 20kHz
HS = 0V
VHB = VDD
T = -40°C
T = 125°C
T = 25°C
20
35
50
65
80
46810 12 14 16
DELAY (ns)
INPUT VOLTAGE (V)
Propagation Delay
vs. Input Voltage
T
AMB
= 25°C
HS = 0V
t
HPLH
t
HPHL
t
LPLH
t
LPHL
40
60
80
100
120
140
-50 -25 025 50 75 100 125
QUIESCENT CURRENT (µA)
TEMPERATURE (°C)
Quiescent Current
vs. Temper at ure
HS = 0V
VDD = 16V
VDD = 12V
VDD = 5.5V
50
100
150
200
250
300
-50 -25 025 50 75 100 125
VDD OPERATING CURRENT (µA)
TEMPERATURE (°C)
VDD Operating Current
vs. Temper at ure
FREQ = 20kHz
HS = 0V
VHB = VDD
VDD = 16V
VDD = 12V
VDD = 5.5V
0
10
20
30
40
50
60
70
80
-50 -25 025 50 75 100 125
VHB OPERATING CURRENT (µA)
TEMPERATURE (°C)
VHB Operating Current
vs. Temper at ure
FREQ = 20kHz
HS = 0V
VHB = VDD
VHB = 16V
VHB = 12V
VHB = 5.5V
0
100
200
300
400
500
-50 -25 025 50 75 100 125
VOLL , VOLH (mV)
TEMPERATURE (°C)
Low-Level Output V oltage
vs. Temper at ure
HS = 0V
I
LO
, I
HO
= 50mA
VDD = 16V
VDD = 12V
VDD = 5.5V
0
100
200
300
400
500
-50 -25 025 50 75 100 125
VOHL , VOHH (mV)
TEMPERATURE (°C)
High-Level Output Voltage
vs. Temper at ure
VDD = 16V
VDD = 12V
VDD = 5.5V
HS = 0V
I
LO
, I
HO
= -50mA
Micrel, Inc.
MIC4605
November 11, 2013
12 Revision 1.0
Typical Characteris tics (Continued)
20.0
30.0
40.0
50.0
60.0
-50 -25 025 50 75 100 125
DELAY (ns)
TEMPERATURE (°C)
Propagation Delay
vs. Temper at ure
VDD = VHB = 12V
HS = 0V
t
HPLH
t
HPHL
t
LPLH
t
LPHL
4.2
4.3
4.4
4.5
4.6
4.7
4.8
-50 -25 025 50 75 100 125
THRESHOLDS (V)
TEMPERATURE (°C)
UVLO Thresholds
vs. Temper at ure
HS = 0V
VHB RISING
VDD RISING
VDD FALLING
VHB FALLING
0.16
0.18
0.2
0.22
0.24
0.26
0.28
-50 -25 025 50 75 100 125
HYSTERESIS (V)
TEMPERATURE (°C)
UVLO Hysteresis
vs. Temper at ure
HS = 0V
VDD HYSTERESIS
VHB HYSTERESIS
0
2
4
6
8
0200 400 600 800 1000
VDD OPERATING (m A)
FREQUENCY (kHz)
VDD Operating Current
vs. Frequency
HS = 0V
VHB = VDD =12V
T = 125°C
T = -40°C
T = 25°C
0
0.4
0.8
1.2
1.6
2
0200 400 600 800 1000
VHB OPERATING CURRENT (mA)
FREQUENCY (kHz)
VHB Operating Current
vs. Frequency
HS = 0V
VHB = VDD = 12V
T = -40°C
T = 125°C
T = 25°C
0.1
1
10
100
1000
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FORWARD CURRENT (m A)
FORWARD VOLTAGE (V)
Bootstrap Diode I-V
Characteristics
HS = 0V
T = 125°C
T = -40°C
T = 25°C
0.0001
0.001
0.01
0.1
1
10
100
010 20 30 40 50 60 70 80 90 100
REVERSE CURRENT (µA)
REVERSE VOLTAGE (V)
Bootstrap Diode Reverse Current
T = 125°C
T = 25°C
T = 85°C
HS = 0V
Micrel, Inc.
MIC4605
November 11, 2013
13 Revision 1.0
Functional Description
The MIC4605 is a non-inverting, 85V half-bridge
MOSFET driver designed to independently drive both
high-side and low-side N-Channel MOSFETs. The
MIC4605 offers a wide 5.5V to 16V operating supply
range with either dual T T L inputs (MI C46 05-1) or a single
PWM input (MIC4605-2). Refer to the MIC4605 Top
Level Block Diagram.
Both drivers contain an input buffer with hysteresis, a
UVLO circuit, and an output buffer. The high-side output
buffer includes a high-speed level-shifting circuit that is
referenced to the HS pin. An internal diode is used as
part of a bootstrap circuit to provide the drive voltage for
the high-s ide out put.
Startup and UVLO
The UVLO circuit forces the driver output low until the
supply voltage exceeds the UVLO threshold. The low-
side UVLO circuit monitors the voltage between the VDD
and VSS pins. The high-side UVLO circuit monitors the
voltage between the HB and HS pins. Hysteresis in the
UVLO circuit prevents noise and finite circuit impedance
from causing chatter during turn-on.
Enable Input
The 10-pin 2.5mm × 2.5mm TDFN package features an
enable pin for on/off control of the device. Logic high on
the enable pin (EN) allows for startup and normal
operation to occur. Conversely, when a logic low is
applied on the enable pin, the device enters shutdown
mode.
Input Stage
Both the H I/LI pi ns of the M IC460 5-1 a nd t h e sin gl e PWM
input of the MIC4605-2 are referenced to the VSS pin.
The voltage state of the input signal(s) does not change
the quiescent current draw of the driver.
The MIC4605 has a TTL-compatible input range and can
be used with input signals with amplitude less than the
supply voltage. The threshold level is independent of the
VDD suppl y vo ltage and ther e is no dep end enc e bet ween
IVDD and the input signal amplitude with the MIC4605.
This feature makes the MIC4605 an excellent level
translator that will drive high-threshold MOSFETs from a
low-voltage PWM IC.
Low-Side Driver
A block diagram of the low-side driver is shown in Figure
4. The lo w-side dr iver is de signe d to dr ive a grou nd (V SS
pin) referenced N-c han ne l MO SFET .
Low driv er impedanc es allow the ex ternal MO SFET to be
turned on and off quickly. The rail-to-rail drive capability
of the output ensures a low RDSON from the external
MOSFET.
A high level applied to LI pin causes the upper driver
MOSFET to turn on and VDD voltage is applied to the
gate of the external MOSFET. A low level on the LI pin
turns of f the upper driver and tur ns on the low sid e driver
to ground the gate of the external MOSFET.
Figure 4. Low-Side Driver Block Diagram
High-Side Driver a n d Bootstrap Circuit
A block diagram of the high-side driver and bootstrap
circuit is shown in Figure 5. This driver is designed to
drive a floating N-channel MOSFET, whose source
terminal is referenced to the HS pin.
Figure 5. High-Side Driver and Bootstrap Circuit
Block Diagram
Micrel, Inc.
MIC4605
November 11, 2013
14 Revision 1.0
A low-po wer, high-spe ed, level-shif ting c ircuit isola tes t he
low side (VS S pin) referenced circ uitry from the high-side
(HS pin) referenced driver. Power to the high-side driver
and UVLO c irc u it is s u ppl ie d b y the bootstrap c irc u it whil e
the voltage level of the HS pin is shifted hi gh.
The bootstrap circuit consists of an internal diode and
external capacitor, CB. In a typical application, such as
the synchronous buck converter shown in Figure 6, the
HS pin is at grou nd potential wh ile the lo w-side MOSFET
is on. T he inter nal d iode all ows c apacitor CB to ch arge up
to VDD-VF during this time (where VF is the forward
voltage drop of the internal diode). After the low-side
MOSFET is turned off and the HO pin turns on, the
voltage across capacitor CB is applied to the gate of the
upper external MOSFET. As the upper MOSFET turns
on, voltage on the HS pin rises with the source of the
high-side MOSFET until it reaches VIN. As the HS and
HB pin rise, the internal diode is reverse biased
preventing capacitor CB from discharging.
Figure 6. MIC4605 Driving a Synchronous Buck Converter
Programmable Gate Drive
The MIC4605 offers programmable gate drive, which
means the MOSFET gate drive (gate to source voltage)
equals the VDD voltage. This feature offers designers
flexibility in driving the MOSFETs. Different MOSFETs
require different VGS characteristics for optimum RDSON
perform ance. T ypica lly, the hig her the gate v oltage (u p to
16V), the lower the RDSON achieved. For example, a
NTMSF4899NF MOSFET can be driven to the ON state
at 4.5V gate voltage but RDSON is 7.5mΩ. If driven to 10V
gate volta ge, RDSON is 4.5mΩ. In low-current ap plicatio ns,
the losses due to RDSON are minimal, but in high-current
applications such as power hand tools, the difference in
RDSON can cut into the efficiency budget.
In portable hand tools and other battery-powered
applications, the MIC4605 offers the ability to drive
motors at a lower voltage compared to the traditional
MOSFET drivers because of the wide VDD range (5.5V
to 16V). Traditional MOSFET drivers typically require a
VDD greater than 9V. The MIC4605 dr ives a motor us ing
only two Li-ion batteries (total 7.2V) compared to
traditional MOSFET drivers which will require at least
three cells (total of 10.8V) to exceed the minimal VDD
range. As an additional benefit, the low 5.5V gate drive
capability allows a longer run time. This is because the
Li-ion battery can run down to 5.5V, which is just above
its 4.8V minimum recommended discharge voltage. This
is also a benefit i n hig her c ur rent po wer to ols that us e f ive
or six cells. The driver can be operated up to 16V to
minim ize the RDSON of the MOSFETs and use as m uch of
the discharge battery pack as possible for a longer run
time. For example, an 18V battery pack can be used to
the lowest operating discharge voltage of 13.5V.
Micrel, Inc.
MIC4605
November 11, 2013
15 Revision 1.0
Application Information
Adaptive Dead Time
The MIC4605 Door Lock/Unlock Module diagram
illustrates how the MIC4605 drives the power stage of a
DC motor. It is important that only one of the two
MOSFETs is on at any given time. If both MOSFETs on
the same side of the half bridge are simultaneously on,
VIN will short to ground. The high current from the
shorted VIN supply will then “shoot through” the
MOSFETs into ground. Excessive shoot-through causes
higher po wer dissipati on in the MOSF ETs, voltage s pikes
and ringing in the circuit. The high current and voltage
ringing generate conducted and radiated EMI. Table 1
illustrates truth tables for both the MIC4605-1 (dual TTL
inputs) and MIC4605-2 (single PWM input) that details
the “first on” priority as well as the failsafe delay.
Table 1. MIC4605-1 and MIC4605-2 Truth Tables
LI HI LO HO Comments
0 0 0 0 Both outputs off.
0 1 0 1 HO will not go high until LO
falls below 1.9V.
1 0 1 0 LO will be delayed an extra
240ns if HS never falls below
2.2V.
1 1 X X First ON stays on until input of
same goes low.
PWM LO HO Comments
0 1 0 LO will be delayed an extra
240ns if HS never falls below
2.2V.
1 0 1 HO will not go high until LO
falls below 1.9V.
Minimizing shoot-through can be done passivel y, activel y
or through a c ombination o f both. Pass ive shoot-through
protection can be achieved by implementing delays
between the high and low gate drivers to prevent both
MOSFETs from being on at the sam e tim e. Thes e delays
can be adjusted for different applications. Although
sim ple, the disad va nta ge of this approac h is requir es lo ng
delays to account for process and temperature variations
in the MOSFET and MOSFET driver.
Adaptive dead time monitors voltages on the gate drive
outputs an d switch node t o determ ine when to switc h the
MOSFETs on and off. This active approach adjusts the
delays to account for some of the variations, but it too
has its disadvantages. High currents and fast switching
voltages in the gate drive and return paths can cause
parasitic ringi ng to tur n t he MOSF ET s bac k on even whil e
the gate dri ver ou tput is l o w. An oth er disa dv ant age is that
the driver cannot monitor the gate voltage inside the
MOSFET. Figure 7 shows an equivalent circuit of the
gate driver section, including parasitics.
Figure 7. MIC4605 Driving an External MOSFET
The internal gate resistance (RG_FET) and any external
damping resistor (RG) isolate the MOSFET’s gate from
the driver output. There is a delay between when the
driver output goes low and the MOSFET turns off. This
turn-off delay is usually specified in the MOSFET data
sheet. This delay increases when an external damping
resistor is used.
The MIC4605 uses a combination of active sensing and
passive del a y to ensur e tha t both MO SF ETs are not on at
the same time, minimizing shoot-through current. Figure
8 illustrates how the adaptive dead time circuitry works.
Figure 8. Adaptive Dead Time Logic Diagram (PWM)
Figure 9 shows the dead time (<20ns) between the gate
drive output transitions as the low-side driver transitions
from on-to-off while the high-side driver transitions from
off-to-on.
Micrel, Inc.
MIC4605
November 11, 2013
16 Revision 1.0
Figure 9. Adaptive Dead Time LO (Low) to HO (High)
A high level o n the PWM pin c aus es the LO p in to g o l o w.
The MIC4605 monitors the LO pin voltage and prevents
the HO pin fr om tur ning on until the voltag e on the LO pin
reaches the VLOOFF threshold. After a short delay, the
MIC4605 drives the HO pin high. Monitoring the LO
voltage eliminates any excessive delay due to the
MOSFET drivers turn-off time and the short delay
accounts for the MOSF ET turn-of f delay as well as lett ing
the LO pin voltage settle out. An external resistor
between the LO output and the MOSFET may affect the
performance of the LO pin monitoring circuit and is not
recommended.
A low on the PW M pin ca uses the HO pin to go low a fter
a short delay (THOOFF). Before the LO pin can go high,
the voltage on the switching node (HS pin) must have
dropped to 2.2V. Monitor ing the switch voltage instea d of
the HO pin voltage eliminates timing variations and
excessive delays due to the high side MOSFET turn-off.
The LO driver turns o n after a short delay (T LOON). Once
the LO driver is turned on, it is latched on until the PW M
signal go es high. T his prevents any ringi ng or oscill ations
on the switch node or HS pin from turning off the LO
driver. If the PWM pin goes low and the voltage on the
HS pin does not cross the VSWTH threshold, the LO pin will
be forc ed high af ter a s hort delay (T SWTO) , insuring pr oper
operation.
Fast propagation delay between the input and output
drive waveform is desirable. It improves overcurrent
protection by decreasing the response time between the
control signal and the MOSFET gate drive. Minimizing
propagation delay also minimizes phase shift errors in
power supplies with wide bandwidth control loops.
Care must be taken to ensure that the input signal pulse
width is greater than the minimum specified pulse width.
An input s ignal that is l ess than the m inimum pulse width
may result in no output pulse or an output pulse whose
width is significantly less than the input.
The maximum duty cycle (ratio of high side on-time to
switching period) is determined by the time required for
the CB capacitor to charge during the off-time. Adequate
time must be allowed for the CB capacitor to charge up
before the hi gh-side driver is turned back on.
Although the adaptive dead time circuit in the MIC4605
prevents th e driver f rom turning both MOSFETs on at the
same tim e, other fact ors outs ide of the anti-shoot-through
circuit’s control can cause shoot-through. Other factors
include ringing on the gate drive node and capacitive
coupling of the switching node voltage on the gate of the
low-side MOSFET.
Power Dissipation Considerations
Power dissipation in the driver can be separated into
three areas:
• Internal diode dissipation in the bootstrap circuit
• Internal driver dissipation
Quiescent current dissipation used to supply the internal
logic and control functions.
Bootstrap Circuit Power Diss ipation
Power diss ipati on of the int ernal boo tstr ap diode pr im arily
comes from the average charging current of the CB
capacitor multiplied by the forward voltage drop of the
diode. Secondary sources of diode power dissipation are
the reverse leakage current and reverse recover y effects
of the diode.
The average current drawn by repeated charging of the
high-side MOSFET is calculated by Equati on 1:
S
GATE)AVE
(F
fQ
I×=
Eq. 1
Where:
QGATE = Total gate charge at VHB – VHS
fS = gate drive switching frequency
Micrel, Inc.
MIC4605
November 11, 2013
17 Revision 1.0
The average power dissipated by the forward voltage
drop of the diode equals, as illustrated in Equation 2:
F)AVE
(
F
FWD
DIODE
V
IP ×
=
Eq. 2
Where:
VF = Diode forward voltage drop
The value of VF should be taken at the peak current
through the diode; however, this current is difficult to
calculate because of differences in source impedances.
The peak current can either be measured or the value of
VF at the average current can be used, which will yield a
good approximation of diode power dissipation.
The reverse leakage current of the internal bootstrap
diode is typically 3µA at a reverse voltage of 85V at
125°C. Power dissipation due to reverse leakage is
typically much less than 1mW and can be ignored.
Reverse recovery time is the time required for the
injected minority carriers to be swept away from the
depletion region during turn-off of the diode. Power
dissipation due to reverse recovery can be calculated by
computing the average reverse current due to reverse
recovery charge times the reverse voltage across the
diode. The average reverse current and power
dissipation due to reverse recovery can be estimated by
Equation 3:
REV)AVE(RR
RR
DIODE
SRRRRM)AVE(RR
VIP
ftI5.0I
×=
×××=
Eq. 3
Where:
IRRM = Peak reverse recovery current
tRR = Reverse recovery time
The total diode power dissipation is noted in Eq uat ion 4:
RR
DIODE
FWD
DIODE
TOTAL
DIODE PPP +=
Eq. 4
Figure 10 illustrates an optional external bootstrap diode
may be used instead of the internal diode.
Figure 10. Optional Bootstrap Diode
An external diode may be useful if high gate charge
MOSFETs are being driven and the power dissipation of
the internal diode is contributing to excessive die
temperatures. The voltage drop of the external diode
must be less than the internal diode for this option to
work. The reverse voltage across the diode will be equal
to the input voltage minus the VDD supply voltage. The
above equations can be used to calculate power
dissipation in the external diode; however, if the external
diode has significant reverse leakage current, the power
dissipated in that diode due to reverse leakage can be
calculated as in Equation 5:
)D1(VIP
REVR
REV
DIODE
−××=
Eq. 5
Where:
IR = Reverse current flow at VREV and TJ
VREV = Diode reverse voltage
D = Duty cycle = tON × fS
The on-time is the time the high-side switch is
conducting. In most topologies, the diode is reverse
biased during the switching cycle off-time.
Micrel, Inc.
MIC4605
November 11, 2013
18 Revision 1.0
Gate Driver Power Dissipation
Power dissipation in the output driver stage is mainly
caused by charging and discharging the gate to source
and gate to drain capacitance of the external MOSFET.
Figure 11 shows a simplified equivalent circuit of the
MIC4605 driving an external high-s ide MOSF ET.
Figure 11. MIC4605 Driving an External MOSFET
Dissip ation during the External MOSFET Turn-On
Energy from capacitor CB is used to charge up the input
capacitance of the MOSFET (CGD and CGS). The energy
delivered to the MOSFET is dissipated in the three
resistive components, RON, RG and RG_FET. RON is the on
resistance of the upper driver MOSFET in the MIC4605.
RG is the seri es res istor (if an y) b et ween t he dr i ver IC and
the MOSFET. RG_FET is the gate resistance of the
MOSFET. RG_FET is usuall y listed in the power MO SFET ’s
specifications. The ESR of capacitor CB and the
resistance of the connecting etch can be ignored since
they are much less than RON and RG_FET.
The effective capacitances of CGD and CGS are dif ficult to
calculate bec ause the y vary non-linearl y with Id, VGS, and
VDS. Fortunately, most power MOSFET specifications
include a typical graph of total gate charge vs. VGS.
Figure 12 shows a typical gate charge curve for an
arbitrary power MOSFET. This chart shows that for a
gate volta ge of 10V, the MOSFET requires about 23. 5nC
of charge. The energy dissipated by the resistive
components of the gate drive circuit during turn-on is
calculated as not ed in Eq u atio n 6:
GSG
2
GSISS
VQ
2
1
E
so ,VCQ
but
,VC
2
1
E
××=
×=
××=
Eq. 6
Where:
CISS = Total gate capacitance of the MOSFET
Figure 12. Typical Gate Charge vs. VGS
The same energy is dissipated by ROFF, RG, and RG_FET
when the dri ver IC turns the MOSFET off. Assum ing Ron
is approximately equal to ROFF, the total energy and
power dissipated by the resistive drive elements is
illustrated in Equation 7:
SGSGDRIVER
GSGDRIVER
fVQP
and VQE
××=
×=
Eq. 7
Where:
EDRIVER = Energy dissipated per switching cycle
PDRIVER = Power dissipated per switching cycle
QG = Total gate charge at VGS
VGS = Gate to source voltage on the MOSFET
fS = Switching frequency of the gate drive circuit
Micrel, Inc.
MIC4605
November 11, 2013
19 Revision 1.0
The power dissipated inside the MIC4605 is equal to the
ratio of RON and R OFF to the ex ternal res is ti ve los ses in R G
and RG_FET. Letting RON = ROFF, the power dissipated in
the MIC4605 due to driving the external MOSFET is
illustrated in Equation 8:
FET_GGON
ON
DRIVER
DRIVER
DISS RRR R
PP ++
=
Eq. 8
Supply Cu rrent Power Dissipati o n
Power is dissipated in the MIC4605 even if nothing is
being driven. The supply current is drawn by the bias for
the interna l circuitry, the le vel shif ting cir cuitr y, and sho ot-
through current in the output drivers. The supply current
is proportional to operating frequency and the VDD and
VHB voltages. The typical characteristic graphs show
how supply current varies with switching frequency and
suppl y voltage.
The power dissipated by the MIC4605 due to supply
current is illustrated in Equation 9:
IHBVHBIDDVDDP
SUPPLY
DISS
×+×=
Eq. 9
Total Power Dissipation and Therma l Considerations
Total power dissipation in the MIC4605 is equal to the
power dissipation caused by driving the external
MOSFETs, the supply current and the internal bootstrap
diode, as in Equation 10:
TOTAL
DIODE
DRIVE
DISS
SUPPLY
DISS
TOTAL
DISS P
PPP +
+=
Eq. 10
The die temperature can be calculated after the total
power dissipation is known, as in Equation 11:
JA
TOTAL
DISSAJ P
TT θ×
+
=
Eq. 11
Where:
TA = Maximum ambient temperature
TJ = Junction temperature (°C)
TOTAL
DISS
P
= Power diss ip ati on of the MIC4605
θJA = Thermal resistance from junction to ambient air
Other Timing Considerations
Make s ure the i nput s igna l pulse width is gr eater than the
minimum specified pulse width. An input signal that is
less than the minimum pulse width may result in no
output pulse or an output pulse whose width is
significantly less than the input.
The maximum duty cycle (ratio of high side on-time to
switching period) is controlled by the minimum pulse
width of the low side and by the time required for the CB
capacitor to charge during the off-time. Adequate time
must be a llowed for the CB capacitor to charge u p before
the high-side driver is turned on.
Decoupling and Bootstrap Capacitor Selection
Decoupling capacitors are required for both the low side
(VDD) and high side (HB) supply pins. These capacitors
supply the charge necessary to drive the external
MOSFETs and also minimize the voltage ripple on these
pins. The capacitor from HB to HS has two functions: it
provides decoupling for the high-side circuitry and also
provides current to the high-side circuit while the high-
side external MOSFET is on. Ceramic capacitors are
recom mended becaus e of t heir low impedance and s mall
size. Z5U type ceramic capacitor dielectrics are not
recommended because of the large change in
capacitance over temperature and voltage. A minimum
value of 0.1µF is required for each of the capacitors,
regardless of the MOSFETs being driven. Larger
MOSFETs may require larger capacitance values for
proper operation. The voltage rating of the capacitors
depends o n the su pply volt age, am bient tem perature and
the voltag e derating us ed for reliab ility. 25V rated X 5R or
X7R ceramic capacitors are recommended for most
applications. The minimum capacitance value should be
increased if low voltage capacitors are used because
even good qualit y dielectric capacitors, such as X5R, will
lose 40% to 70% of their capacitance value at the rated
voltage.
Micrel, Inc.
MIC4605
November 11, 2013
20 Revision 1.0
Placement of the decoupling capacitors is critical. The
bypass capacitor for VDD should be placed as close as
possible between the VDD and VSS pins. The bypass
capacitor (CB) for the HB supply pin must be located as
close as possible between the HB and HS p ins. The e tch
connecti ons m ust be s hort, wide, and direc t. The us e of a
ground plane to minimize connection impedance is
recommended (refer to the Grounding, Component
Placement, and Circuit Layout section for more
information).
The voltage on the bo otstrap c apacitor drops each time it
delivers char ge t o tur n on t he MOSFET . The voltag e d rop
depends on the gate charge required by the MOSFET.
Most MOSFET specifications specify gate charge versus
VGS voltage. Based on this information and a
recommended ΔVHB of less than 0.1V, the minimum
value of bootstrap capacitance is calculated as:
HB
GATE
B
V
Q
C∆
≥
Eq. 12
Where:
QGATE = Total gate charge at VHB
∆VHB = Voltage drop at the HB pin
The decoupling capacitor for the VDD input may be
calculated in with the same formula; however, the two
capacitors are usually equal in value.
DC Motor Ap p lications
MIC4605 MOSFET drivers are widely used in DC motor
applications. They address brushed motors in both half-
bridge and full-bridge motor topologies as well as three-
phase brushless motors. As shown in Figure 13, Figure
14, and Figure 15, the drivers switch the MOSFETs at
variable duty cycles that modulate the voltage to control
motor speed. In the half-bridge topology, the motor turns
in one direction only. The full-bridge topology allows for
bidirectional control. Three-phase motors are more
efficient compared to the brushed motors but require
three half-bridge switches and additional circuitry to
sense the position of the rotor.
The MIC4605 85V operating voltage offers the engineer
margin to protect against back electrom otive force (EMF)
which is a voltage spike caused by the rotation of the
rotor. The back EMF voltage amplitude depends on the
speed of the rotation. It is good practice to have at least
twice the H V vo ltage of the m otor s upply. 85V is pl enty of
margin for 12V, 24V, and 40V motors.
Figure 13. Half-Bridge DC Motor
Figure 14. Full-Bridge DC Motor
Micrel, Inc.
MIC4605
November 11, 2013
21 Revision 1.0
Figure 15. Three-Phase Brushless DC
Motor Driver
−
24V Block Diagram
The MIC46 05 is of f er ed in a small 2.5mm × 2.5mm TDFN
package for applications that are space constrained and
an SOIC-8 pac kage for ease of manuf ac tur ing. T he m otor
trend is to put the motor control circuit inside the motor
casing, which requires small packaging because of the
size of the motor.
The MIC4605 offers low UVLO threshold and
programmable gate drive, which allows for longer
operation time in battery operated motors such as power
hand tools.
Cross conduction across the half bridge can cause
catastrophic failure in a motor application. Engineers
typically add dead time between states that switch
between high input and low input to ensure that the low-
side MOSFET completely turns off before the high-side
MOSFET turns on and vice versa. The dead time
depends on the MOSFET used in the application, but
200ns is typical for most motor applications.
Power Inverter
Power inverters are used to supply AC loads from a DC
operated ba ttery s ystem , mainl y durin g po wer f ailure. The
battery voltage can be 12VDC, 24VDC, or up to 36VDC,
depending on th e power re quir ements. There t wo p op ular
conversion methods, Type I and T ype II, that convert the
battery energy to AC line voltage (110VAC or 230VAC).
Figure 16. Type I Inverter Topology
As shown in Figure 16, Type I is a dual-stage topology
where line voltage is converted to DC through a
transformer to charge the storage batteries. When a
power failure is detected, the stored DC energy is
converted to AC through a nother transform er to drive the
AC loads c o nnected to the in verter o utp ut. This method is
simplest to design but tends to be bulky and expensive
because it uses two transformers.
Type II is a single-stage topology that uses only one
transformer to charge the bank of batteries to store the
energy. During a power outage, the same transformer is
used to power the line voltage. The T ype II switches at a
higher frequency compared to the Type I topology to
maintain a small transformer size.
Both types require a half bridge or full bridge topology to
boost the DC to AC. This application can use two
MIC4605s. The 85V operating voltage offers enough
margin to address all of the available banks of batteries
commonly used in inverter applications. The 85V
operating voltage allows designers to increase the bank
of batteries up to 72V, if desired. The MIC4605 can sink
as m uch as 1A, w hich is e nough current to o vercome t he
MOSFET’s i npu t c ap acita n c e and switch th e MOSFET up
to 50kHz. This makes the MIC4605 an ideal solution for
inverter applications.
As with all half bridge and full bridge topologies, cross
conduction is a concern to inverter manufactures
because it can cause catastrophic failure. This can be
remedied by adding the appropriate dead time between
transitioning from the high-side MOSFET to the low-side
MOSFET and vice versa.
Grounding, Co m p o n ent Placement, and Circuit
Layout
Nanoseco nd switch ing spe eds and am pere peak c urrents
in and around the MIC4605 drivers require proper
placement and trace routing of all components. Im proper
placement may cause degraded noise immunity, false
switching, excessive ringing, or circuit latch-up.
Micrel, Inc.
MIC4605
November 11, 2013
22 Revision 1.0
Figure 17 sh ows the critica l c urrent pa ths when the dr i ver
outputs go high and turn on the external MOSFETs. It
also helps demonstrate the need for a low impedance
ground plane. Charge needed to turn-on the MOSFET
gates comes from the decoupling capacitors CVDD and
CB. Current in the low-side gate driver flows from CVDD
through the internal driver, into the MOSFET gate, and
out the source. The return connection back to the
decoupling capacitor is made through the ground plane.
Any inductance or resistance in the ground return path
causes a vo lta ge spik e or r i ngi ng to app ear on the s ou r ce
of the MOSFET. This voltage works against the gate
drive voltage and can either slow down or turn off the
MOSFET during the period when it should be turned on.
Current in the high-side driver is sourced from capacitor
CB and flows int o the HB pin and out the HO p in, into the
gate of the high side MOSFET. The return path for the
current is from the source of the MOSFET and back to
capacitor CB. The high-side circuit return path usually
does not have a l ow-im pedanc e ground pl ane so the e tch
connections in this critical path should be short and wide
to minimize parasitic inductance. As with the low-side
circuit, impedance between the MOSFET source and the
decoupling capacitor causes negative voltage feedback
that fights the turn-on of the MOSFET.
It is important to note that capacitor CB must be placed
close to the HB and HS pins. This capacitor not only
provides all the energy for turn-on but it must also keep
HB pin noise and ripple low for proper operation of the
high-side drive circuitry.
Figure 17. Turn-On Current Paths
Figure 18 sh ows the critica l c urrent pa ths when the dr i ver
outputs go lo w an d t urn of f the external MO SF ETs. Sh ort,
low-impedance connections are important during turn-off
for the same reasons given in the turn-on explanation.
Current flowing through the internal diode replenishes
charge in the bootstrap capacitor, CB.
Figure 18. Turn-Off Current Paths
Use the following layout guidelines for optimum circuit
performance:
• Use a ground plane to minimize parasitic inductance
and impedance of the return paths. The MIC4605 is
capable of greater than 1A peak currents and any
impedance between the MIC4605, the decoupling
capacitors, and the external MOSFET will degrade the
performance of the driver.
• A typical layout of a synchronous buck converter power
stage is shown in Figure 19.
The high-side MOSFET drain connects to the input
supply voltage (drain) and the source connects to the
switching node. The low-side MOSF ET drain connects to
the switch in g no de and its sour c e is c onn ec ted t o ground.
The buck converter output inductor (not sho wn) conne cts
to the switching node. The high-side drive trace, HO, is
routed on top of its return trace, HS, to minimize loop
area and parasitic inductance. The low-side drive trace
LO is routed over the ground plane to minimize the
impedance of that current path. The decoupling
capacitors, CB and CVDD, are placed to minimize etch
length between the capacitors and their respective pins.
This close placement is necessary to efficiently charge
capacitor CB when the HS node is low. All traces are
0.025in wide or gre ater to r educe im pedance. CIN is u sed
to decouple the high current path through the MOSFETs.
Micrel, Inc.
MIC4605
November 11, 2013
23 Revision 1.0
Top Side
Bottom Side
Figure 19. Typical Layout of a S ynchronous Buck Converter Power Stage
Micrel, Inc.
MIC4605
November 11, 2013
25 Revision 1.0
Package Information(6) and Recommended Layout Pattern (Continued)
2.5mm × 2.5mm 10-Pin TDF N (MT)
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