P r o du c t B r i e f IGLOOTM Low Power Flash FPGAs with Flash*FreezeTM Technology Features and Benefits * * * * * * * 5 W Power Consumption in Flash*Freeze Mode 1.2 V or 1.5 V Core Voltage for Low Power Supports Single-Voltage System Operation Low Power Active Capability Enables Active FPGA Operation with Ultra-Low Power (from 25 W) Flash*Freeze Technology Enables Ultra-Low Power Consumption While Maintaining FPGA Content Quick and Easy Way to Enter and Exit Flash*Freeze Mode Using Flash*Freeze Pin * * * * High Capacity * * * 30 k to 1 Million System Gates Up to 144 kbits of True Dual-Port SRAM Up to 300 User I/Os * * * Reprogrammable Flash Technology * * * * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live At Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off In-System Programming (ISP) and Security * * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except AGL030 and ARM(R)enabled IGLOO devices) via JTAG (IEEE 1532compliant) FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy * Segmented, Hierarchical Routing and Clock Structure * High-Performance, Low-Skew Global Network Table 1 * IGLOO Product Family IGLOO Devices ARM-Enabled IGLOO Devices System Gates VersaTiles (D-Flip-Flops) Quiescent Current (typical) Flash*Freeze Mode (A) RAM kbits (1,024 bits) 4,608 Bit Blocks FlashROM Bits Secure (AES) ISP1 Integrated PLL in CCCs VersaNet Globals2 I/O Banks Maximum User I/Os Package Pins CS QFN VQFP FBGA in Architecture Supports Ultra-High Utilization Advanced I/O Low Power * * * * (R) 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above) 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages--Up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/ 2.5 V/1.8 V/1.5 V, 3.3 V PCI/ 3.3 V PCI-X (except AGL030), and LVCMOS 2.5 V/5.0 V Input Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS (AGL250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold Sparing I/Os (AGL030 only) Programmable Output Slew Rate (except AGL030) and Drive Strength Weak Pull-Up/Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages Across the IGLOO Family Clock Conditioning Circuit (CCC) and PLL (except AGL030) * * * Six CCC Blocks, One with an Integrated PLL Flexible Phase-Shift, Multiply/Divide, and Delay Capabilities Wide Input Frequency Range (1.5 MHz to 200 MHz) Embedded Memory * * * 1 kbit of FlashROM User Nonvolatile Memory SRAMs and FIFOs with Variable-Aspect Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations available) True Dual-Port SRAM (except x18) Soft ARM7TM Core Support in M7 IGLOO Devices AGL030 AGL060 AGL125 125 k 3,072 AGL250 M7AGL250 250 k 6,144 AGL600 M7AGL600 600 k 13,824 AGL1000 M7AGL1000 1M 24,576 30 k 768 60 k 1,536 4 8 14 28 60 102 - - 1k - - 6 2 81 18 4 1k Yes 1 18 2 96 36 8 1k Yes 1 18 2 133 36 8 1k Yes 1 18 4 143 108 24 1k Yes 1 18 4 227 144 32 1k Yes 1 18 4 300 QN132 VQ100 CS196 QN132 VQ100 FG144 CS196 QN132 VQ100 FG144 CS1963 QN1323 VQ100 FG144 FG144, FG256, FG484 FG144, FG256, FG484 Notes: 1. AES is not available for ARM-enabled IGLOO devices. 2. Six chip (main) and three quadrant global networks are available for AGL060 and above. 3. The M7AGL250 device does not support this package. 4. For higher densities and support of additional features, refer to the IGLOOe Flash FPGAs datasheet. August 2006 (c) 2006 Actel Corporation 1 See the Actel website for the latest version of the datasheet. IGLOO Low Power Flash FPGAs with Flash*Freeze Technology I/Os Per Package1 IGLOO Devices AGL030 AGL060 AGL250 2 AGL600 AGL1000 M7AGL250 2, 3 M7AGL600 M7AGL1000 AGL125 ARM-Enabled IGLOO Devices Single-Ended I/O Single-Ended I/O Single-Ended I/O2 Differential I/O Pairs Differential I/O Pairs Single-Ended I/O2 Differential I/O Pairs VQ100 (14x14) 79 71 71 68 13 - - - QN132 (8x8) 81 80 84 87 19 - - - CS196 (8x8) - 96 133 143 30 - - - FG144 (13x13) - 96 97 97 24 97 24 97 25 FG256 (17x17) - - - - - 179 45 177 44 FG484 (27x27) - - - - - 227 56 300 74 Single-Ended I/O2 Package (Dimensions mm) Single-Ended I/O I/O Type Notes: 1. 2. 3. 4. 5. Each used differential I/O pair reduces the number of single-ended I/Os available by two. For AGL250 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. The M7AGL250 device does not support the QN132 and CS196 packages. FG256 and FG484 are footprint-compatible packages. When the Flash*Freeze pin is used to enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by 1. 6. "G" indicates RoHS compliant packages. Refer to the "IGLOO Ordering Information" on page 3 for the location of the "G" in the part number. 2 P ro du ct B ri e f IGLOO Low Power Flash FPGAs with Flash*Freeze Technology IGLOO Ordering Information AGL1000 _ FG G 144 I Application (Ambient Temperature Range) Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS Compliant Packaging Package Type CS = Chip Scale Package (0.5 mm pitch) QN = Quad Flat Pack No Leads (0.5 mm pitch) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade F = 20% Slower than Standard* Blank = Standard Part Number IGLOO Devices AGL030 = 30,000 System Gates AGL060 = 60,000 System Gates AGL125 = 125,000 System Gates AGL250 = 250,000 System Gates AGL600 = 600,000 System Gates AGL1000 = 1,000,000 System Gates ARM-Enabled IGLOO Devices M7AGL250 = 250,000 System Gates M7AGL600 = 600,000 System Gates M7AGL1000 = 1,000,000 System Gates Note: *The characteristics provided for -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in commercial temperature range. P ro du c t B ri ef 3 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Temperature Grade Offerings AGL030 AGL060 AGL125 Package AGL250 M7AGL250 1 AGL600 AGL1000 M7AGL600 M7AGL1000 VQ100 C, I C, I C, I C, I - - QN132 C, I C, I C, I C, I - - CS196 - C, I C, I C, I - - FG144 - C, I C, I C, I C, I C, I FG256 - - - - C, I C, I FG484 - - - - C, I C, I Notes: 1. The QN132 and CS196 packages are not supported for the M7AGL250 device. 2. C = Commercial temperature range: 0C to 70C ambient 3. I = Industrial temperature range: -40C to 85C ambient Speed Grade and Temperature Grade Matrix -F 1 Std. 2 3 - Temperature Grade C I Notes: 1. The characteristics provided for -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in commercial temperature range. 2. C = Commercial temperature range: 0C to 70C ambient 3. I = Industrial temperature range: -40C to 85C ambient Datasheet references made to IGLOO devices also apply to ARM-enabled IGLOO devices. The ARM-enabled part numbers start with M7. Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html). 4 P ro du ct B ri e f IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Introduction and Overview General Description The IGLOO family of Flash FPGAs, based on a 130-nm Flash process, offers the lowest power FPGA, a singlechip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Low Power Active capability (static idle) allows for ultra-low power consumption (from 25 W) while the IGLOO device is completely functional in the system by maintaining I/O, SRAM, registers, and logic functions. This allows the IGLOO device to control the system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. The Flash*Freeze technology used in IGLOO devices allows entering and exiting an ultra-low power mode that consumes as little as 5 W while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. Nonvolatile Flash technology gives IGLOO devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time to market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM memory storage as well as clock conditioning circuitry based on an integrated phaselocked loop (PLL). The AGL030 device has no PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM, and up to 288 user I/Os. IGLOO devices support the ARM7 soft IP core in devices with at least 250 k system gates. The ARM-enabled devices have Actel ordering numbers that begin with M7AGL and do not support AES decryption. Flash*Freeze Technology The IGLOO device offers unique Flash*Freeze technology that allows the IGLOO device to enter and exit an ultralow power mode. IGLOO devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. The Flash*Freeze technology is combined with in-system programmability, which allows users to quickly and easily upgrade and update the design in the final stages of manufacturing or in the field. The ability of IGLOO to support 1.2 V core voltage allows further reduction of power consumption, thus achieving the lowest total system power. Flash*Freeze technology allows the user to keep all power supplies, I/Os, and clocks connected to the device in normal operation. When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. This low power feature, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high pin-count packages, makes IGLOO devices the best fit for portable electronics. Flash Advantages Low Power Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current surge and no highcurrent transition period, both of which occur on many FPGAs. IGLOO devices also have low dynamic power consumption to further maximize power savings, which is also reduced by the use of 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, makes the IGLOO device the lowest total system power offered by any FPGA. Security The nonvolatile, Flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile Flash programming can offer. IGLOO devices utilize a 128-bit Flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in the IGLOO devices can be encrypted P ro du c t B ri ef 5 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000, and replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption engine and a Flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO device cannot be read back, although secure design verification is possible. ARM-enabled IGLOO devices do not support usercontrolled AES security mechanisms. Since the ARM core must be protected at all times, the AES encryption is always on for the core logic, so bitstreams are always encrypted. There is no user access to encryption for the FlashROM programming data. Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The Flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOO device provides the most impenetrable security for programmable logic designs. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/ communications, computing, and avionics markets. Firm Errors Single Chip Flash-based FPGAs store the configuration information in on-chip Flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, Flash-based IGLOO FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load the device configuration data. This reduces bill-of-materials costs and printed circuit board (PCB) area, and increases security and system reliability. Live at Power-Up The Actel Flash-based IGLOO devices support Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of Flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often eliminating the need for complex programmable logic devices (CPLDs) and clock generation PLLs that are used 6 for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the IGLOO device's Flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO devices simplify total system design, and reduce cost and design risk, while increasing system reliability and improving system initialization time. Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO Flashbased FPGAs. Once it is programmed, the Flash cell configuration element of IGLOO FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO family offers many benefits, including nonvolatility and reprogrammability through an advanced Flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The P ro du ct B ri e f IGLOO Low Power Flash FPGAs with Flash*Freeze Technology combination of fine granularity, enhanced flexible routing resources, and abundant Flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The IGLOO device consists of five distinct and programmable architectural features (Figure 1 and Figure 2 on page 8): * Flash*Freeze technology * FPGA VersaTiles * Dedicated FlashROM memory * Dedicated SRAM/FIFO memory1 * Extensive clock conditioning circuitry (CCC) and PLLs1 * Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function or as a D-flip-flop (with or without enable), or as a latch, by programming the appropriate Flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC(R) families of third generation architecture Flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of the IGLOO devices via an IEEE 1532 JTAG interface. Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* User Nonvolatile FlashROM Bank 0 Bank 1 VersaTile Charge Pumps Bank 1 Note: *Not supported by AGL030 Figure 1 * Device Architecture Overview with Two I/O Banks (AGL030, AGL060, and AGL125) 1. The AGL030 does not support PLL and SRAM. P ro du c t B ri ef 7 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os Bank 1 Bank 3 VersaTile ISP AES Decryption User Nonvolatile FlashROM Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (AGL600 and AGL1000) Bank 2 Figure 2 * Device Architecture Overview with Four I/O Banks (AGL250, AGL600, and AGL1000) Flash*Freeze Technology The IGLOO device has an ultra-low power static mode that retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology allows the user to quickly enter and exit Flash*Freeze mode within 1 s by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and states. No power is consumed by the I/Os, clocks, JTAG pins, or PLL, and the device consumes as little as 5 W in this mode. Flash*Freeze Mode Control Flash*Freeze Pin Figure 3 * IGLOO Flash*Freeze Mode Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active high) can be routed internally to the core to allow the user's logic to decide if it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if the Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power static (as low as 25 W) and dynamic capabilities of the IGLOO device. Refer to Figure 3 for an illustration of entering/ exiting Flash*Freeze mode. For more information on how to use the Flash*Freeze mode, refer to the Low Power Modes in Actel IGLOO FPGAs application note. 8 Actel IGLOO FPGA P ro du ct B ri e f IGLOO Low Power Flash FPGAs with Flash*Freeze Technology VersaTiles The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The IGLOO VersaTile supports the following: * All three-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 4 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Y Enable D-Flip-Flop with Clear or Set Data CLK D-FF Y D-FF Enable CLR Figure 4 * VersaTile Configurations User Nonvolatile FlashROM Actel IGLOO devices have 1 kbit of on-chip, useraccessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and onchip AES decryption can be used selectively to securely load data over public networks (except in the AGL030 device), such as security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface, and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOO development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM memory. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOO devices (except in the AGL030 device) have embedded SRAM blocks along the north and south sides of the device. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in the AGL030 device). P ro du c t B ri ef 9 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and Clock Conditioning Circuitry (CCC) IGLOO devices provide designers with very flexible clock conditioning capabilities. Each member of the IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The AGL030 does not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several I/O inputs located near the CCC that have dedicated connections to the CCC block. Global Clocking IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets. I/Os with Advanced I/O Standards The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOO FPGAs support many different I/O standards--single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-Data-Rate applications * Double-Data-Rate applications--DDR LVDS, BLVDS, and M-LVDS I/Os for point-to-point communications The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz to 200 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz to 200 MHz * Two programmable delay types for clock skew minimization * Clock frequency synthesis (for PLL only) IGLOO banks for the AGL250 device and above support LVPECL, LVDS, BLVDS and M-LVDS. BLVDS and M-LVDS can support up to 20 loads. Additional CCC specifications: 10 * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). * Output duty cycle = 50% 1.5% or better (for PLL only) * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) * Maximum acquisition time = 200 s (for PLL only) * Exceptional tolerance to input period jitter-- allowable input jitter is up to 1.5 ns (for PLL only) * Four precise phases; maximum misalignment between adjacent phases of 40 ps x (200 MHz / fOUT_CCC) (for PLL only) P r o d u ct B r i e f IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Quiescent Supply Current Table 2 * Quiescent Supply Current (IDD), Flash*Freeze Mode Typical (25C) Note: Core Voltage AGL030 AGL060 AGL125 AGL250 AGL600 AGL1000 Units 1.2 V 4 8 14 28 60 102 A 1.5 V 6 10 18 34 72 127 A IDD includes VCC, VPUMP, VCCI, VMV, and I/O static currents in worst case conditions. Table 3 * Quiescent Supply Current (IDD), Sleep Mode (VCC = 0 V) AGL030 AGL060 AGL125 AGL250 AGL600 AGL1000 Units VCCI = 1.5 V (all banks) Typical (25C) 5 5 5 9 9 9 A VCCI = 1.8 V (all banks) Typical (25C) 5 5 5 11 11 11 A VCCI = 2.5 V (all banks) Typical (25C) 8 8 8 15 15 15 A VCCI = 3.3 V (all banks) Typical (25C) 10 10 10 20 20 20 A Note: IDD includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution. Table 4 * Quiescent Supply Current (IDD), Shutdown Mode (VCC, VCCI = 0 V) Core Voltage AGL030 Units 1.2 V / 1.5 V 0 A Typical (25C) Note: I DD Table 5 * includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution. Quiescent Supply Current, No Flash*Freeze Mode1 Core Voltage AGL030 AGL060 AGL125 AGL250 AGL600 AGL1000 Units 1.2V 14 18 24 38 70 112 A 1.5V 16 20 28 44 82 137 A 3.3 V Typical (25C) 1.2 V / 1.5 V 5 5 5 5 5 5 A 2.5 V Typical (25C) 1.2 V / 1.5 V 4 4 4 4 4 4 A 1.8 V Typical (25C) 1.2 V / 1.5 V 3 3 3 3 3 3 A 1.5 V Typical (25C) 1.2 V / 1.5 V 2 2 2 2 2 2 A ICCA Current2 Typical (25C) ICCI or IJTAG Current3, 4 Notes: 1. 2. 3. 4. To calculate total device IDD, multiply the number of banks used in ICCI and add ICCA contribution. Includes VCC and VPUMP currents Per VCCI or VJTAG bank Values do not include I/O static contribution. P ro du c t B ri ef 11 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Web-only." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. Unmarked (production) This datasheet version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation Actel Europe Ltd. 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