Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.6
FUJITSU SEMICONDUCTOR
DATA SHEET DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
32-bit ARMTM CortexTM-M3 based Microcontroller
MB9B110R Series
MB9BF112N/R, MB9BF114N/R,
MB9BF115N/R, MB9BF116N/R
DESCRIPTION
The MB9B110R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers
with high-performance and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has
peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces ( UART, CSIO,
I2C, LIN).
The products which are described in this data sheet are placed into TYPE4 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
FEATURES
32-bit ARM Cortex-M3 Core
・ Processor version: r2p1
・ Up to 144MHz Frequency Operation
・ Memory Protection Unit (MPU): improves the reliability of an embedded system
・ Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
・ 24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash memories.
・ MainFlash
・ Up to 512Kbyte
・ Built-in Flash Accelerator System with 16Kbyte trace buffer memory
・ The read access to Flash memory can be achieved without wait cycle up to operation frequency of
72MHz. Even at the operation frequency more than 72MHz, an equivalent access to Flash memory
can be obtained by Flash Accelerator System.
・ Security function for code protection
・ WorkFlash
・ 32Kbyte
・ Read cycle
・ 4wait-cycle: the operation frequency more than 72MHz
・ 2wait-cycle: the operation frequency more than 40MHz, and to 72MHz
・ 0wait-cycle: the operation frequency to 40MHz
・ Security function is shared with code protection
[SRAM]
This Series contain a total of up to 64Kbyte on-chip SRAM memories. This is composed of two
independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3
core. SRAM1 is connected to System bus.
・ SRAM0: Up to 32 Kbyte
・ SRAM1: Up to 32 Kbyte
External Bus Interface
・ Supports SRAM, NOR and NAND Flash device
・ Up to 8 chip selects
・ 8/16-bit Data width
・ Up to 25-bit Address bit
・ Supports Address/Data multiplex
・ Supports external RDY input
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MB9B110R Series
Multi-function Serial Interface (Max 8channels)
・ 4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
・ Operation mode is selectable from the followings for each channel.
・ UART
・ CSIO
・ LIN
・ I2C
[UART]
・ Full-duplex double buffer
・ Selection with or without parity supported
・ Built-in dedicated baud rate generator
・ External clock available as a serial clock
・ Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
・ Full-duplex double buffer
・ Built-in dedicated baud rate generator
・ Overrun error detect function available
[LIN]
・ LIN protocol Rev.2.1 supported
・ Full-duplex double buffer
・ Master/Slave mode supported
・ LIN break field generate (can be changed 13 to 16-bit length)
・ LIN break delimiter generate (can be changed 1 to 4-bit length)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
[I2C]
Standard mode (Max 100kbps) / High-speed mode (Max 400kbps) supported
DMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・ 8 independently configured and operated channels
・ Transfer can be started by software or request from the built-in peripherals
・ Transfer address area: 32bit (4Gbyte)
・ Transfer mode: Block transfer/Burst transfer/Demand transfer
・ Transfer data type: byte/half-word/word
・ Transfer block count: 1 to 16
・ Number of transfers: 1 to 65536
A/D Converter (Max 16channels)
[12-bit A/D Converter]
・ Successive Approximation Register type
・ Built-in 3unit
・ Conversion time: 1.0μs@5V
・ Priority conversion available (priority at 2levels)
・ Scanning conversion mode
・ Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
Base Timer (Max 8channels)
Operation mode is selectable from the followings for each channel.
・ 16-bit PWM timer
・ 16-bit PPG timer
・ 16/32-bit reload timer
・ 16/32-bit PWC timer
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.
・ Capable of pull-up control per pin
・ Capable of reading pin level directly
・ Built-in the port relocate function
・ Up 103 fast general purpose I/O Ports@120pin Package
・ Some pin is 5V tolerant I/O.
See "PIN DESCRIPTION" to confirm the corresponding pins.
Multi-function Timer (Max 3units)
The Multi-function timer is composed of the following blocks.
・ 16-bit free-run timer × 3ch./unit
・ Input capture × 4ch./unit
・ Output compare × 6ch./unit
・ A/D activating compare × 3ch./unit
・ Waveform generator × 3ch./unit
・ 16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.
・ PWM signal output function
・ DC chopper waveform output function
・ Dead time function
・ Input capture function
・ A/D convertor activate function
・ DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
・ Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the
week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
・ Timer interrupt function after set time or each set time.
・ Capable of rewriting the time with continuing the time count.
・ Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC) (Max 3channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
・ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
・ 16-bit position counter
・ 16-bit revolution counter
・ Two 16-bit compare registers
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・ Free-running
・ Periodic (=Reload)
・ One-shot
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MB9B110R Series
Watch Counter
The Watch counter is used for wake up from power saving mode.
Interval timer: up to 64s (Max) @ Sub Clock : 32.768kHz
External Interrupt Controller Unit
・ Up to 16 external interrupt input pin
・ Include one non-maskable interrupt (NMI)
Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware"
watchdog is active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・ CCITT CRC16 Generator Polynomial: 0x1021
・ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
・ Main Clock : 4MHz to 48MHz
・ Sub Clock : 32.768kHz
・ High-speed internal CR Clock : 4MHz
・ Low-speed internal CR Clock : 100kHz
・ Main PLL Clock
[Resets]
・ Reset requests from INITX pin
・ Power on reset
・ Software reset
・ Watchdog timers reset
・ Low-voltage detector reset
・ Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
・ External OSC clock failure (clock stop) is detected, reset is asserted.
・ External OSC frequency anomaly is detected, interrupt or reset is asserted.
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage has been set, Low-Voltage Detector generates an interrupt or reset.
・ LVD1: error reporting via interrupt
・ LVD2: auto-reset operation
Low-Power Mode
Three power saving modes supported.
・ SLEEP
・ TIMER
・ STOP
Debug
・ Serial Wire JTAG Debug Port (SWJ-DP)
・ Embedded T race Macrocells (ETM) provide comprehensive debug and trace facilities.
Power Supply
Wide range voltage : VCC = 2.7V to 5.5V
6
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
PRODUCT LINEUP
Memory size
Product name MB9BF112N/R MB9BF114N/R MB9BF115N/R MB9BF116R
MainFlash 128Kbyte 256Kbyte 384Kbyte 512Kbyte
WorkFlash 32Kbyte 32Kbyte 32Kbyte 32Kbyte
On-chip RAM 16Kbyte 32Kbyte 48Kbyte 64Kbyte
SRAM0 8Kbyte 16Kbyte 24Kbyte 32Kbyte
SRAM1 8Kbyte 16Kbyte 24Kbyte 32Kbyte
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Function
Product name
MB9BF112N
MB9BF114N
MB9BF115N
MB9BF116N
MB9BF112R
MB9BF114R
MB9BF115R
MB9BF116R
Pin count 100/112 120
Cortex-M3
CPU Freq. 144MHz
Power supply voltage range VCC: 2.7V to 5.5V
DMAC 8ch.
External Bus Interface
Addr: 25-bit (Max)
R/Wdata: 8/16-bit (Max)
CS: 8 (Max)
Support: SRAM, NOR Flash
Addr: 25-bit (Max)
R/Wdata: 8/16-bit (Max)
CS: 8 (Max)
Support: SRAM, NOR & NAND Flash
MF Serial Interface
(UART/CSIO/LIN/I2C) 8ch. (Max)
Base T imer
(PWC/Reload timer/PWM/PPG) 8ch. (Max)
A/D
activation
compare 3ch.
Input
capture 4ch.
Free-run
timer 3ch.
Output
compare 6ch.
Waveform
generator 3ch.
MF-
Timer
PPG 3ch.
3 units (Max)
QPRC 3ch. (Max)
Dual T imer 1 unit
Real-Time Clock 1 unit
Watch Counter 1 unit
CRC Accelerator Yes
Watchdog timer 1ch. (SW) + 1ch. (HW)
External Interrupts 16pins (Max) + NMI × 1
I/O ports 83pins (Max) 103pins (Max)
12-bit A/D converter 16ch. (3 units)
CSV (Clock Super Visor) Yes
LVD (Low-Voltage Detector) 2ch.
High-speed 4MHz (± 2%) Internal
OSC Low-speed 100kHz (Typ)
Debug Function SWJ-DP/ETM
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
PACKAGES
Product name
Package
MB9BF112N
MB9BF114N
MB9BF115N
MB9BF116N
MB9BF112R
MB9BF114R
MB9BF115R
MB9BF116R
QFP: FPT-100P-M36 (0.65mm pitch) -
LQFP: FPT-100P-M20*/M23 (0.5mm pitch) -
LQFP: FPT-120P-M21*/M37 (0.5mm pitch) -
BGA: BGA-112P-M04 (0.8mm pitch) -
: Supported
*: ES product only
Note : See "PACKAGE DIMENSIONS" for detailed information on each package.
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
PIN ASSIGNMENT
・ FPT-100P-M20/M23
(TOP VIEW)
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_0
P63/INT03_0/SIN5_1/MWEX_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VCC 1 75 VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0 2 74 P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0 3 73 P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0 4 72 P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0 5 71 P23/SCK0_0/TIOA7_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0 6 70 P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0 7 69 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P56/INT 08_2/DT T I1X_0/M ADATA06_0 8 68 P1D/AN13/CTS4_1/IC03_1/MAD21_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0 9 67 P1C/AN12/SCK4_1/IC02_1/MAD20_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0 10 66 P1B/AN11/SOT4_1/IC01_1/MAD19_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0 11 65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0 12 64 P19/AN09/SCK2_2/MAD17_0
P34/FRCK0_0/TIOB4_1/MADATA11_0 13 63 P18/AN08/SOT2_2/MAD16_0
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_0 14 62 AVSS
P36/IC02_0/SIN5_2/INT09_1/MADATA13_0 15 61 AVRH
P37/IC01_0/SOT5_2/INT10_1/MADATA14_0 16 60 AVCC
P38/IC00_0/SCK5_2/INT11_1/MADATA15_0 17 59 P17/AN07/SIN2_2/INT04_1/MAD15_0
P39/DTTI0X_0/ADTG_2 18 58 P16/AN06/SCK0_1/MAD14_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 19 57 P15/AN05/SOT0_1/IC03_2/MAD13_0
P3B/RTO01_0/TIOA1_1 20 56 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3C/RTO02_0/TIOA2_1 21 55 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3D/RTO03_0/TIOA3_1 22 54 P12/AN02/SOT1_1/IC00_2/MAD10_0
P3E/RTO04_0/TIOA4_1 23 53 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_0
P3F/RTO05_0/TIOA5_1 24 52 P10/AN00
VSS 25 51 VCC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1
P43/TIOA3_0/RTO13_1/ADTG_7
P44/TIOA4_0/RTO14_1/MAD00_0
P45/TIOA5_0/RTO15_1/MAD01_0
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_
0
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_
0
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ FPT-120P-M21/M37
(TOP VIEW)
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_0
P63/INT03_0/SIN5_1/RTO20_0/MWEX_0
P64/TIOA7_0/SOT5_1/INT10_2/FRCK2_1/RTO21_0
P65/TIOB7_0/SCK5_1/IC23_1/RTO22_0
P66/SIN3_0/ADTG_8/INT11_2/IC22_1/RTO23_0
P67/SOT3_0/TIOA7_2/IC21_1/RTO24_0
P68/SCK3_0/TIOB7_2/INT12_2/IC20_1/RTO25_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
VCC 1 90 VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0 2 89 P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0 3 88 P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0 4 87 P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0 5 86 P23/SCK0_0/TIOA7_1/RTO00_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0 6 85 P24/SIN2_1/INT01_2/RTO01_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0 7 84 P25/SOT2_1/RTO02_1
P56/SIN1_0/INT08_2/DTTI1X_0/MADATA06_0 8 83 P26/SCK2_1/RTO03_1
P57/SOT1_0/MADATA07_0 9 82 P27/TIOA6_2/INT02_2/RTO04_1
P58/SCK1_0/AIN2_0/MADATA08_0 10 81 P28/TIOB6_2/ADTG_4/RTO05_1
P59/SIN7_0/INT09_2/BIN2_0/MADATA09_0 11 80 P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P5A/SOT7_0/ZIN2_0/MADATA10_0 12 79 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P5B/SCK7_0/MADATA11_0 13 78 P1D/AN13/CTS4_1/IC03_1/MAD21_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA12_0 14 77 P1C/AN12/SCK4_1/IC02_1/MAD20_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA13_0 15 76 P1B/AN11/SOT4_1/IC01_1/MAD19_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA14_0 16 75 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA15_0 17 74 P19/AN09/SCK2_2/MAD17_0
P34/FRCK0_0/TIOB4_1/MNALE_0 18 73 P18/AN08/SOT2_2/MAD16_0
P35/IC03_0/TIOB5_1/INT08_1/MNCLE_0 19 72 AVSS
P36/IC02_0/SIN5_2/INT09_1/MNWEX_0 20 71 AVRH
P37/IC01_0/SOT5_2/INT10_1/MNREX_0 21 70 AVCC
P38/IC00_0/SCK5_2/INT11_1 22 69 P17/AN07/SIN2_2/INT04_1/MAD15_0
P39/DTTI0X_0/ADTG_2 23 68 P16/AN06/SCK0_1/MAD14_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 24 67 P15/AN05/SOT0_1/IC03_2/MAD13_0
P3B/RTO01_0/TIOA1_1 25 66 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3C/RTO02_0/TIOA2_1 26 65 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3D/RTO03_0/TIOA3_1 27 64 P12/AN02/SOT1_1/IC00_2/MAD10_0
P3E/RTO04_0/TIOA4_1 28 63 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_0
P3F/RTO05_0/TIOA5_1 29 62 P10/AN00
VSS 30 61 VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1
P43/TIOA3_0/RTO13_1/ADTG_7
P44/TIOA4_0/RTO14_1/MAD00_0
P45/TIOA5_0/RTO15_1/MAD01_0
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_
0
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_
0
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
P70/TIOA4_2
P71/INT13_2/TIOB4_2
P72/SIN2_0/INT14_2/TIOA6_0
P73/SOT2_0/INT15_2/TIOB6_0
P74/SCK2_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 120
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS706-00028-2v0-E
11
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ FPT-100P-M36
(TOP VIEW)
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0
VCC
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_0
P63/INT03_0/SIN5_1/MWEX_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
VSS
P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P21/SIN0_0/INT06_1/BIN1_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0 81 50 P22/SOT0_0/TIOB7_1/ZIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0 82 49 P23/SCK0_0/TIOA7_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0 83 48 P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0 84 47 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0 85 46 P1D/AN13/CTS4_1/IC03_1/MAD21_0
P56/INT08_2/DTTI1X_0/MADATA06_0 86 45 P1C/AN12/SCK4_1/IC02_1/MAD20_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0 87 44 P1B/AN11/SOT4_1/IC01_1/MAD19_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0 88 43 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0 89 42 P19/AN09/SCK2_2/MAD17_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0 90 41 P18/AN08/SOT2_2/MAD16_0
P34/FRCK0_0/TIOB4_1/MADATA11_0 91 40 AVSS
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_0 92 39 AVRH
P36/IC02_0/SIN5_2/INT09_1/MADATA13_0 93 38 AVCC
P37/IC01_0/SOT5_2/INT10_1/MADATA14_0 94 37 P17/AN07/SIN2_2/INT04_1/MAD15_0
P38/IC00_0/SCK5_2/INT11_1/MADATA15_0 95 36 P16/AN06/SCK0_1/MAD14_0
P39/DTTI0X_0/ADTG_2 96 35 P15/AN05/SOT0_1/IC03_2/MAD13_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 97 34 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3B/RTO01_0/TIOA1_1 98 33 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3C/RTO02_0/TIOA2_1 99 32 P12/AN02/SOT1_1/IC00_2/MAD10_0
P3D/RTO03_0/TIOA3_1 100 31 P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3E/RTO04_0/TIOA4_1
P3F/RTO05_0/TIOA5_1
VSS
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1
P43/TIOA3_0/RTO13_1/ADTG_7
P44/TIOA4_0/RTO14_1/MAD00_0
P45/TIOA5_0/RTO15_1/MAD01_0
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_
0
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_
0
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
P10/AN00
QFP - 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ BGA-112P-M04
(TOP VIEW)
H
J
11
A
B
C
67
K
L
D
E
F
G
891034512
VSS
VCC
P50
P53
VSS
P54
VSS X1A INITXVCC P4BP42 P48
VCC
VSS
P20
P23
AN12
AN09
AN01VCC P3F
AN07
AN04
VSS
AN06
AN03
P4E MD1
P4C
P07
P30
P34
P37
P3B
P35
VSS P40
P81 P80 VCC P0E
P44
VSS
AN14
AN10
AN05 VSS
P09
P0A
AN13
P0C P08
VSS
P22
P56
TRSTXP0B
P3D
P55
P32
P36
TMS/
SWDIO
AN08
P52 P61 P0F
X1VSS
VSS
P33
P39
P38
P3C P3E
P63
Index
VCC
VSS
C X0A VSS P41 P45 P4A
P43 P49
MD0 X0
VSS
VSS
TDI
P21
AN15
AN11
AVRH
AVSS
AN00
P31
P60 P62 P0DP51
VSS
P3A
P4D AN02
TCK/
SWCLK
VSS
P06
TDO/
SWO
P05
AVCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
DS706-00028-2v0-E
13
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
PIN DESCRIPTION
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
1 B1 1 79 VCC -
P50
INT00_0
AIN0_2
SIN3_1
RTO10_0
(PPG10_0)
2 C1 2 80
MADATA00_0
E H
P51
INT01_0
BIN0_2
SOT3_1
(SDA3_1)
RTO11_0
(PPG10_0)
3 C2 3 81
MADATA01_0
E H
P52
INT02_0
ZIN0_2
SCK3_1
(SCL3_1)
RTO12_0
(PPG12_0)
4 B3 4 82
MADATA02_0
E H
P53
SIN6_0
TIOA1_2
INT07_2
RTO13_0
(PPG12_0)
5 D1 5 83
MADATA03_0
E H
P54
SOT6_0
(SDA6_0)
TIOB1_2
RTO14_0
(PPG14_0)
6 D2 6 84
MADATA04_0
E I
14
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P55
SCK6_0
(SCL6_0)
ADTG_1
RTO15_0
(PPG14_0)
7 D3 7 85
MADATA05_0
E I
P56
INT08_2
DTTI1X_0
8 D5 86
MADATA06_0
- -
8
- SIN1_0
(120pin only)
E H
P57
SOT1_0
(SDA1_0)
- - 9 -
MADATA07_0
E I
P58
SCK1_0
(SCL1_0)
AIN2_0
- - 10 -
MADATA08_0
E I
P59
SIN7_0
INT09_2
BIN2_0
- - 11 -
MADATA09_0
E H
P5A
SOT7_0
(SDA7_0)
ZIN2_0
- - 12 -
MADATA10_0
E I
P5B
SCK7_0
(SCL7_0)
- - 13 -
MADATA11_0
E I
DS706-00028-2v0-E
15
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P30
AIN0_0
TIOB0_1
14
INT03_2
9 E1
-
87
MADATA07_0
(100pin only)
- -
14 - MADATA12_0
(120pin only)
E H
P31
BIN0_0
TIOB1_1
SCK6_1
(SCL6_1)
15
INT04_2
10 E2
-
88
MADATA08_0
(100pin only)
- - 15 -
MADATA13_0
(120pin only)
E H
P32
ZIN0_0
TIOB2_1
SOT6_1
(SDA6_1)
16
INT05_2
11 E3
-
89
MADATA09_0
(100pin only)
- - 16 -
MADATA14_0
(120pin only)
E H
P33
INT04_0
TIOB3_1
SIN6_1
17
ADTG_6
12 E4
-
90
MADATA10_0
(100pin only)
- - 17 -
MADATA15_0
(120pin only)
E H
P34
FRCK0_0
18
TIOB4_1
13 F1
-
91
MADATA11_0
(100pin only)
- - 18 -
MNALE_0
(120pin only)
E I
16
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P35
IC03_0
TIOB5_1
19
INT08_1
14 F2
-
92
MADATA12_0
(100pin only)
- - 19 -
MNCLE_0
(120pin only)
E H
P36
IC02_0
SIN5_2
20
INT09_1
15 F3
-
93
MADATA13_0
(100pin only)
- - 20 -
MNWEX_0
(120pin only)
E H
P37
IC01_0
SOT5_2
(SDA5_2)
21
INT10_1
16 G1
-
94
MADATA14_0
(100pin only)
- - 21 -
MNREX_0
(120pin only)
E H
P38
IC00_0
SCK5_2
(SCL5_2)
22
INT11_1
17 G2
-
95
MADATA15_0
(100pin only)
E H
P39
DTTI0X_0
18 F4 23 96
ADTG_2
E I
P3A
RTO00_0
(PPG00_0)
TIOA0_1
RTCCO_2
19 G3 24 97
SUBOUT_2
G I
- B2 - - VSS -
DS706-00028-2v0-E
17
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P3B
RTO01_0
(PPG00_0)
20 H1 25 98
TIOA1_1
G I
P3C
RTO02_0
(PPG02_0)
21 H2 26 99
TIOA2_1
G I
P3D
RTO03_0
(PPG02_0)
22 G4 27 100
TIOA3_1
G I
P3E
RTO04_0
(PPG04_0)
23 H3 28 1
TIOA4_1
G I
P3F
RTO05_0
(PPG04_0)
24 J2 29 2
TIOA5_1
G I
25 L1 30 3 VSS -
26 J1 31 4 VCC -
P40
TIOA0_0
RTO10_1
(PPG10_1)
27 J4 32 5
INT12_1
G H
P41
TIOA1_0
RTO11_1
(PPG10_1)
28 L5 33 6
INT13_1
G H
P42
TIOA2_0
29 K5 34 7 RTO12_1
(PPG12_1)
G I
P43
TIOA3_0
RTO13_1
(PPG12_1)
30 J5 35 8
ADTG_7
G I
- K2 - - VSS -
- J3 - - VSS -
- H4 - - VSS -
18
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P44
TIOA4_0
RTO14_1
(PPG14_1)
31 H5 36 9
MAD00_0
G I
P45
TIOA5_0
RTO15_1
(PPG14_1)
32 L6 37 10
MAD01_0
G I
33 L2 38 11 C -
34 L4 39 12 VSS -
35 K1 40 13 VCC -
P46
36 L3 41 14 X0A D M
P47
37 K3 42 15 X1A D N
38 K4 43 16 INITX B C
P48
DTTI1X_1
INT14_1
SIN3_2
39 K6 44 17
MAD02_0
E H
P49
TIOB0_0
IC10_1
AIN0_1
SOT3_2
(SDA3_2)
40 J6 45 18
MAD03_0
E I
P4A
TIOB1_0
IC11_1
BIN0_1
SCK3_2
(SCL3_2)
41 L7 46 19
MAD04_0
E I
P4B
TIOB2_0
IC12_1
ZIN0_1
42 K7 47 20
MAD05_0
E I
DS706-00028-2v0-E
19
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P4C
TIOB3_0
IC13_1
SCK7_1
(SCL7_1)
AIN1_2
43 H6 48 21
MAD06_0
I* I
P4D
TIOB4_0
FRCK1_1
SOT7_1
(SDA7_1)
BIN1_2
44 J7 49 22
MAD07_0
I* I
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
45 K8 50 23
MAD08_0
I* H
P70
- - 51 -
TIOA4_2 E I
P71
INT13_2
- - 52 -
TIOB4_2
E H
P72
SIN2_0
INT14_2
- - 53 -
TIOA6_0
E H
P73
SOT2_0
(SDA2_0)
INT15_2
- - 54 -
TIOB6_0
E H
P74
- - 55 -
SCK2_0
(SCL2_0) E I
PE0
46 K9 56 24 MD1 C P
47 L8 57 25 MD0 P D
20
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
PE2
48 L9 58 26 X0 A A
PE3
49 L10 59 27 X1 A B
50 L11 60 28 VSS -
51 K11 61 29 VCC -
P10
52 J11 62 30 AN00 F K
P11
AN01
SIN1_1
INT02_1
FRCK0_2
53 J10 63 31
MAD09_0
F L
- K10 - - VSS -
- J9 - - VSS -
P12
AN02
SOT1_1
(SDA1_1)
IC00_2
54 J8 64 32
MAD10_0
F K
P13
AN03
SCK1_1
(SCL1_1)
RTCCO_1
SUBOUT_1
IC01_2
55 H10 65 33
MAD11_0
F K
DS706-00028-2v0-E
21
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P14
AN04
SIN0_1
INT03_1
IC02_2
56 H9 66 34
MAD12_0
F L
P15
AN05
SOT0_1
(SDA0_1)
IC03_2
57 H7 67 35
MAD13_0
F K
P16
AN06
SCK0_1
(SCL0_1)
58 G10 68 36
MAD14_0
F K
P17
AN07
SIN2_2
INT04_1
59 G9 69 37
MAD15_0
F L
60 H11 70 38 AVCC -
61 F11 71 39 AVRH -
62 G11 72 40 AVSS -
P18
AN08
SOT2_2
(SDA2_2)
63 G8 73 41
MAD16_0
F K
P19
AN09
SCK2_2
(SCL2_2)
64 F10 74 42
MAD17_0
F K
P1A
AN10
SIN4_1
INT05_1
IC00_1
65 F9 75 43
MAD18_0
F L
- H8 - - VSS -
22
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P1B
AN11
SOT4_1
(SDA4_1)
IC01_1
66 E11 76 44
MAD19_0
F K
P1C
AN12
SCK4_1
(SCL4_1)
IC02_1
67 E10 77 45
MAD20_0
F K
P1D
AN13
CTS4_1
IC03_1
68 F8 78 46
MAD21_0
F K
P1E
AN14
RTS4_1
DTTI0X_1
69 E9 79 47
MAD22_0
F K
P1F
AN15
ADTG_5
FRCK0_1
70 D11 80 48
MAD23_0
F K
P28
TIOB6_2
ADTG_4
- - 81 -
RTO05_1
(PPG04_1)
E I
P27
TIOA6_2
INT02_2
- - 82 -
RTO04_1
(PPG04_1)
E H
P26
SCK2_1
(SCL2_1)
- - 83 -
RTO03_1
(PPG02_1)
E I
DS706-00028-2v0-E
23
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P25
SOT2_1
(SDA2_1)
- - 84 -
RTO02_1
(PPG02_1)
E I
- B10 - - VSS -
- C9 - - VSS -
P24
SIN2_1
INT01_2
- - 85 -
RTO01_1
(PPG00_1)
E H
P23
SCK0_0
(SCL0_0)
71 D10 49
TIOA7_1
- -
86
- RTO00_1
(PPG00_1)
E I
P22
SOT0_0
(SDA0_0)
TIOB7_1
72 E8 87 50
ZIN1_1
E I
P21
SIN0_0
INT06_1
73 C11 88 51
BIN1_1
E H
P20
INT05_0
CROUT_0
AIN1_1
74 C10 89 52
MAD24_0
E H
75 A11 90 53 VSS -
76 A10 91 54 VCC -
P00
TRSTX
77 A9 92 55
MCSX7_0
E E
P01
TCK
78 B9 93 56
SWCLK
E E
24
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P02
TDI
79 B11 94 57
MCSX6_0
E E
P03
TMS
80 A8 95 58
SWDIO
E E
P04
TDO
81 B8 96 59
SWO
E E
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
82 C8 97 60
MCSX5_0
E F
- D8 - - VSS -
P06
TRACED1
TIOB5_2
SOT4_2
(SDA4_2)
INT01_1
AIN2_1
83 D9 98 61
MCSX4_0
E F
P07
TRACED2
ADTG_0
SCK4_2
(SCL4_2)
BIN2_1
84 A7 99 62
MCLKOUT_0
E G
P08
TRACED3
TIOA0_2
CTS4_2
ZIN2_1
85 B7 100 63
MCSX3_0
E G
P09
TRACECLK
TIOB0_2
RTS4_2
RTO20_1
(PPG20_1)
86 C7 101 64
MCSX2_0
E G
DS706-00028-2v0-E
25
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P0A
SIN4_0
INT00_2
FRCK1_0
FRCK2_0
RTO21_1
(PPG20_1)
87 D7 102 65
MCSX1_0
I* H
P0B
SOT4_0
(SDA4_0)
TIOB6_1
IC10_0
IC20_0
RTO22_1
(PPG22_1)
88 A6 103 66
MCSX0_0
I* I
P0C
SCK4_0
(SCL4_0)
TIOA6_1
IC11_0
IC21_0
RTO23_1
89 B6 104 67
MALE_0
I* I
P0D
RTS4_0
TIOA3_2
IC12_0
IC22_0
RTO24_1
(PPG24_1)
90 C6 105 68
MDQM0_0
E I
P0E
CTS4_0
TIOB3_2
IC13_0
IC23_0
RTO25_1
(PPG24_1)
91 A5 106 69
MDQM1_0
E I
- D4 - - VSS -
- C3 - - VSS -
26
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
DTTI2X_0
92 B5 107 70
DTTI2X_1
E J
P68
SCK3_0
(SCL3_0)
TIOB7_2
INT12_2
IC20_1
- - 108 -
RTO25_0
(PPG24_0)
E H
P67
SOT3_0
(SDA3_0)
TIOA7_2
IC21_1
- - 109 -
RTO24_0
(PPG24_0)
E I
P66
SIN3_0
ADTG_8
INT11_2
IC22_1
- - 110 -
RTO23_0
(PPG22_0)
E H
P65
TIOB7_0
SCK5_1
(SCL5_1)
IC23_1
- - 111 -
RTO22_0
(PPG22_0)
E I
P64
TIOA7_0
SOT5_1
(SDA5_1)
INT10_2
FRCK2_1
- - 112 -
RTO21_0
(PPG20_0)
E H
DS706-00028-2v0-E
27
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
LQFP-100 BGA-112 LQFP-120 QFP-100 Pin Name I/O circuit
type Pin state
type
P63
INT03_0
SIN5_1
93 D6 71
MWEX_0
- -
113
- RTO20_0
(PPG20_0)
E H
P62
SCK5_0
(SCL5_0)
ADTG_3
94 C5 114 72
MOEX_0
E I
P61
SOT5_0
(SDA5_0)
95 B4 115 73
TIOB2_2
E I
P60
SIN5_0
TIOA2_2
INT15_1
96 C4 116 74
MRDY_0
I* H
97 A4 117 75 VCC -
98 A3 118 76 P80 H O
99 A2 119 77 P81 H O
100 A1 120 78 VSS -
*: 5V tolerant I/O
28
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
SIGNAL DESCRIPTION Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
ADTG_0 84 A7 99 62
ADTG_1 7 D3 7 85
ADTG_2 18 F4 23 96
ADTG_3 94 C5 114 72
ADTG_4 - - 81 -
ADTG_5 70 D11 80 48
ADTG_6 12 E4 17 90
ADTG_7 30 J5 35 8
ADTG_8
A/D converter external trigger input pin
- - 110 -
AN00 52 J11 62 30
AN01 53 J10 63 31
AN02 54 J8 64 32
AN03 55 H10 65 33
AN04 56 H9 66 34
AN05 57 H7 67 35
AN06 58 G10 68 36
AN07 59 G9 69 37
AN08 63 G8 73 41
AN09 64 F10 74 42
AN10 65 F9 75 43
AN11 66 E11 76 44
AN12 67 E10 77 45
AN13 68 F8 78 46
AN14 69 E9 79 47
ADC
AN15
A/D converter analog input pin.
ANxx describes ADC ch.xx.
70 D11 80 48
TIOA0_0 27 J4 32 5
TIOA0_1 19 G3 24 97
TIOA0_2
Base timer ch.0 TIOA pin
85 B7 100 63
TIOB0_0 40 J6 45 18
TIOB0_1 9 E1 14 87
Base T imer
0
TIOB0_2
Base timer ch.0 TIOB pin
86 C7 101 64
TIOA1_0 28 L5 33 6
TIOA1_1 20 H1 25 98
TIOA1_2
Base timer ch.1 TIOA pin
5 D1 5 83
TIOB1_0 41 L7 46 19
TIOB1_1 10 E2 15 88
Base T imer
1
TIOB1_2
Base timer ch.1 TIOB pin
6 D2 6 84
TIOA2_0 29 K5 34 7
TIOA2_1 21 H2 26 99
TIOA2_2
Base timer ch.2 TIOA pin
96 C4 116 74
TIOB2_0 42 K7 47 20
TIOB2_1 11 E3 16 89
Base T imer
2
TIOB2_2
Base timer ch.2 TIOB pin
95 B4 115 73
DS706-00028-2v0-E
29
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
TIOA3_0 30 J5 35 8
TIOA3_1 22 G4 27 100
TIOA3_2 Base timer ch.3 TIOA pin 90 C6 105 68
TIOB3_0 43 H6 48 21
TIOB3_1 12 E4 17 90
Base T imer
3
TIOB3_2 Base timer ch.3 TIOB pin 91 A5 106 69
TIOA4_0 31 H5 36 9
TIOA4_1 23 H3 28 1
TIOA4_2 Base timer ch.4 TIOA pin - - 51 -
TIOB4_0 44 J7 49 22
TIOB4_1 13 F1 18 91
Base T imer
4
TIOB4_2 Base timer ch.4 TIOB pin - - 52 -
TIOA5_0 32 L6 37 10
TIOA5_1 24 J2 29 2
TIOA5_2 Base timer ch.5 TIOA pin 82 C8 97 60
TIOB5_0 45 K8 50 23
TIOB5_1 14 F2 19 92
Base T imer
5
TIOB5_2 Base timer ch.5 TIOB pin 83 D9 98 61
TIOA6_0 - - 53 -
TIOA6_1 89 B6 104 67
TIOA6_2 Base timer ch.6 TIOA pin - - 82 -
TIOB6_0 - - 54 -
TIOB6_1 88 A6 103 66
Base T imer
6
TIOB6_2 Base timer ch.6 TIOB pin - - 81 -
TIOA7_0 - - 112 -
TIOA7_1 71 D10 86 49
TIOA7_2 Base timer ch.7 TIOA pin - - 109 -
TIOB7_0 - - 111 -
TIOB7_1 72 E8 87 50
Base T imer
7
TIOB7_2 Base timer ch.7 TIOB pin - - 108 -
30
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
SWCLK Serial wire debug interface clock input pin 78 B9 93 56
SWDIO Serial wire debug interface data input /
output pin 80 A8 95 58
SWO Serial wire viewer output pin 81 B8 96 59
TCK J-TAG test clock input pin 78 B9 93 56
TDI J-TAG test data input pin 79 B11 94 57
TDO J-TAG debug data output pin 81 B8 96 59
TMS J-TAG test mode state input/output pin 80 A8 95 58
TRACECLK Trace CLK output pin of ETM 86 C7 101 64
TRACED0 82 C8 97 60
TRACED1 83 D9 98 61
TRACED2 84 A7 99 62
TRACED3
Trace data output pin of ETM
85 B7 100 63
Debugger
TRSTX J-TAG test reset input pin 77 A9 92 55
MAD00_0 31 H5 36 9
MAD01_0 32 L6 37 10
MAD02_0 39 K6 44 17
MAD03_0 40 J6 45 18
MAD04_0 41 L7 46 19
MAD05_0 42 K7 47 20
MAD06_0 43 H6 48 21
MAD07_0 44 J7 49 22
MAD08_0 45 K8 50 23
MAD09_0 53 J10 63 31
MAD10_0 54 J8 64 32
MAD11_0 55 H10 65 33
MAD12_0 56 H9 66 34
MAD13_0 57 H7 67 35
MAD14_0 58 G10 68 36
MAD15_0 59 G9 69 37
MAD16_0 63 G8 73 41
MAD17_0 64 F10 74 42
MAD18_0 65 F9 75 43
MAD19_0 66 E11 76 44
MAD20_0 67 E10 77 45
MAD21_0 68 F8 78 46
MAD22_0 69 E9 79 47
MAD23_0 70 D11 80 48
MAD24_0
External bus interface address bus
74 C10 89 52
MCSX0_0 88 A6 103 66
MCSX1_0 87 D7 102 65
MCSX2_0 86 C7 101 64
MCSX3_0 85 B7 100 63
MCSX4_0 83 D9 98 61
MCSX5_0 82 C8 97 60
MCSX6_0 79 B11 94 57
External
Bus
MCSX7_0
External bus interface chip select output pin
77 A9 92 55
DS706-00028-2v0-E
31
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
MADATA0_0 2 C1 2 80
MADATA1_0 3 C2 3 81
MADATA2_0 4 B3 4 82
MADATA3_0 5 D1 5 83
MADATA4_0 6 D2 6 84
MADATA5_0 7 D3 7 85
MADATA6_0 8 D5 8 86
MADATA7_0 9 E1 9 87
MADATA8_0 10 E2 10 88
MADATA9_0 11 E3 11 89
MADATA10_0 12 E4 12 90
MADATA11_0 13 F1 13 91
MADATA12_0 14 F2 14 92
MADATA13_0 15 F3 15 93
MADATA14_0 16 G1 16 94
MADATA15_0
External bus interface data bus
(Address / data multiplex bus)
17 G2 17 95
MDQM0_0 90 C6 105 68
MDQM1_0 External bus interface byte mask signal
output pin 91 A5 106 69
MALE_0 External bus interface Address Latch
enable output signal for multiplex 89 B6 104 67
MRDY_0 External bus interface external RDY input
signal 96 C4 116 74
MCLKOUT_0 External bus interface external clock
output pin 84 A7 99 62
MNALE_0 External bus interface ALE signal to
control NAND Flash output pin - - 18 -
MNCLE_0 External bus interface CLE signal to
control NAND Flash output pin - - 19 -
MNREX_0 External bus interface read enable signal to
control NAND Flash - - 21 -
MNWEX_0 External bus interface write enable signal
to control NAND Flash - - 20 -
MOEX_0 External bus interface read enable signal
for SRAM 94 C5 114 72
External
Bus
MWEX_0 External bus interface write enable signal
for SRAM 93 D6 113 71
32
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
INT00_0 2 C1 2 80
INT00_1 82 C8 97 60
INT00_2 External interrupt request 00 input pin 87 D7 102 65
INT01_0 3 C2 3 81
INT01_1 83 D9 98 61
INT01_2 External interrupt request 01 input pin - - 85 -
INT02_0 4 B3 4 82
INT02_1 53 J10 63 31
INT02_2 External interrupt request 02 input pin - - 82 -
INT03_0 93 D6 113 71
INT03_1 56 H9 66 34
INT03_2 External interrupt request 03 input pin 9 E1 14 87
INT04_0 12 E4 17 90
INT04_1 59 G9 69 37
INT04_2 External interrupt request 04 input pin 10 E2 15 88
INT05_0 74 C10 89 52
INT05_1 65 F9 75 43
INT05_2 External interrupt request 05 input pin 11 E3 16 89
INT06_1 73 C11 88 51
INT06_2 External interrupt request 06 input pin 45 K8 50 23
INT07_2 External interrupt request 07 input pin 5 D1 5 83
INT08_1 14 F2 19 92
INT08_2 External interrupt request 08 input pin 8 D5 8 86
INT09_1 15 F3 20 93
INT09_2 External interrupt request 09 input pin - - 11 -
INT10_1 16 G1 21 94
INT10_2 External interrupt request 10 input pin - - 112 -
INT11_1 17 G2 22 95
INT11_2 External interrupt request 11 input pin - - 110 -
INT12_1 27 J4 32 5
INT12_2 External interrupt request 12 input pin - - 108 -
INT13_1 28 L5 33 6
INT13_2 External interrupt request 13 input pin - - 52 -
INT14_1 39 K6 44 17
INT14_2 External interrupt request 14 input pin - - 53 -
INT15_1 96 C4 116 74
INT15_2 External interrupt request 15 input pin - - 54 -
External
Interrupt
NMIX Non-Maskable Interrupt input pin 92 B5 107 70
DS706-00028-2v0-E
33
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
P00 77 A9 92 55
P01 78 B9 93 56
P02 79 B11 94 57
P03 80 A8 95 58
P04 81 B8 96 59
P05 82 C8 97 60
P06 83 D9 98 61
P07 84 A7 99 62
P08 85 B7 100 63
P09 86 C7 101 64
P0A 87 D7 102 65
P0B 88 A6 103 66
P0C 89 B6 104 67
P0D 90 C6 105 68
P0E 91 A5 106 69
P0F
General-purpose I/O port 0
92 B5 107 70
P10 52 J11 62 30
P11 53 J10 63 31
P12 54 J8 64 32
P13 55 H10 65 33
P14 56 H9 66 34
P15 57 H7 67 35
P16 58 G10 68 36
P17 59 G9 69 37
P18 63 G8 73 41
P19 64 F10 74 42
P1A 65 F9 75 43
P1B 66 E11 76 44
P1C 67 E10 77 45
P1D 68 F8 78 46
P1E 69 E9 79 47
P1F
General-purpose I/O port 1
70 D11 80 48
P20 74 C10 89 52
P21 73 C11 88 51
P22 72 E8 87 50
P23 71 D10 86 49
P24 - - 85 -
P25 - - 84 -
P26 - - 83 -
P27 - - 82 -
GPIO
P28
General-purpose I/O port 2
- - 81 -
34
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
P30 9 E1 14 87
P31 10 E2 15 88
P32 11 E3 16 89
P33 12 E4 17 90
P34 13 F1 18 91
P35 14 F2 19 92
P36 15 F3 20 93
P37 16 G1 21 94
P38 17 G2 22 95
P39 18 F4 23 96
P3A 19 G3 24 97
P3B 20 H1 25 98
P3C 21 H2 26 99
P3D 22 G4 27 100
P3E 23 H3 28 1
P3F
General-purpose I/O port 3
24 J2 29 2
P40 27 J4 32 5
P41 28 L5 33 6
P42 29 K5 34 7
P43 30 J5 35 8
P44 31 H5 36 9
P45 32 L6 37 10
P46 36 L3 41 14
P47 37 K3 42 15
P48 39 K6 44 17
P49 40 J6 45 18
P4A 41 L7 46 19
P4B 42 K7 47 20
P4C 43 H6 48 21
P4D 44 J7 49 22
P4E
General-purpose I/O port 4
45 K8 50 23
P50 2 C1 2 80
P51 3 C2 3 81
P52 4 B3 4 82
P53 5 D1 5 83
P54 6 D2 6 84
P55 7 D3 7 85
P56 8 D5 8 86
P57 - - 9 -
P58 - - 10 -
P59 - - 11 -
P5A - - 12 -
GPIO
P5B
General-purpose I/O port 5
- - 13 -
DS706-00028-2v0-E
35
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
P60 96 C4 116 74
P61 95 B4 115 73
P62 94 C5 114 72
P63 93 D6 113 71
P64 - - 112 -
P65 - - 111 -
P66 - - 110 -
P67 - - 109 -
P68
General-purpose I/O port 6
- - 108 -
P70 - - 51 -
P71 - - 52 -
P72 - - 53 -
P73 - - 54 -
P74
General-purpose I/O port 7
- - 55 -
P80 98 A3 118 76
P81 General-purpose I/O port 8 99 A2 119 77
PE0 46 K9 56 24
PE2 48 L9 58 26
GPIO
PE3 General-purpose I/O port E 49 L10 59 27
SIN0_0 73 C11 88 51
SIN0_1 Multi-function serial interface ch.0 input pin 56 H9 66 34
SOT0_0
(SDA0_0) 72 E8 87 50
SOT0_1
(SDA0_1)
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA0 when it is used in an I2C
(operation mode 4). 57 H7 67 35
SCK0_0
(SCL0_0) 71 D10 86 49
Multi-
function
Serial
0
SCK0_1
(SCL0_1)
Multi-function serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SCL0 when it is used in an I2C
(operation mode 4). 58 G10 68 36
SIN1_0 - - 8 -
SIN1_1 Multi-function serial interface ch.1 input pin 53 J10 63 31
SOT1_0
(SDA1_0) - - 9 -
SOT1_1
(SDA1_1)
Multi-function serial interface ch.1 output
pin.
This pin operates as SOT1 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA1 when it is used in an I2C
(operation mode 4). 54 J8 64 32
SCK1_0
(SCL1_0) - - 10 -
Multi-
function
Serial
1
SCK1_1
(SCL1_1)
Multi-function serial interface ch.1 clock I/O
pin.
This pin operates as SCK1 when it is used in
a CSIO (operation modes 4) and as SCL1
when it is used in an I2C (operation mode 4). 55 H10 65 33
36
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No.
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
SIN2_0 - - 53 -
SIN2_1 - - 85 -
SIN2_2 Multi-function serial interface ch.2 input pin 59 G9 69 37
SOT2_0
(SDA2_0) - - 54 -
SOT2_1
(SDA2_1) - - 84 -
SOT2_2
(SDA2_2)
Multi-function serial interface ch.2 output
pin.
This pin operates as SOT2 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA2 when it is used in an I2C
(operation mode 4). 63 G8 73 41
SCK2_0
(SCL2_0) - - 55 -
SCK2_1
(SCL2_1) - - 83 -
Multi-
function
Serial
2
SCK2_2
(SCL2_2)
Multi-function serial interface ch.2 clock I/O
pin.
This pin operates as SCK2 when it is used in
a CSIO (operation modes 2) and as SCL2
when it is used in an I2C (operation mode 4). 64 F10 74 42
SIN3_0 - - 110 -
SIN3_1 2 C1 2 80
SIN3_2
Multi-function serial interface ch.3 input pin
39 K6 44 17
SOT3_0
(SDA3_0) - - 109 -
SOT3_1
(SDA3_1) 3 C2 3 81
SOT3_2
(SDA3_2)
Multi-function serial interface ch.3 output
pin.
This pin operates as SOT3 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA3 when it is used in an I2C
(operation mode 4). 40 J6 45 18
SCK3_0
(SCL3_0) - - 108 -
SCK3_1
(SCL3_1) 4 B3 4 82
Multi-
function
Serial
3
SCK3_2
(SCL3_2)
Multi-function serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in
a CSIO (operation modes 2) and as SCL3
when it is used in an I2C (operation mode 4). 41 L7 46 19
DS706-00028-2v0-E
37
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
SIN4_0 87 D7 102 65
SIN4_1 65 F9 75 43
SIN4_2 Multi-function serial interface ch.4 input pin 82 C8 97 60
SOT4_0
(SDA4_0) 88 A6 103 66
SOT4_1
(SDA4_1) 66 E11 76 44
SOT4_2
(SDA4_2)
Multi-function serial interface ch.4 output
pin.
This pin operates as SOT4 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA4 when it is used in an I2C
(operation mode 4). 83 D9 98 61
SCK4_0
(SCL4_0) 89 B6 104 67
SCK4_1
(SCL4_1) 67 E10 77 45
SCK4_2
(SCL4_2)
Multi-function serial interface ch.4 clock I/O
pin.
This pin operates as SCK4 when it is used in
a CSIO (operation modes 2) and as SCL4
when it is used in an I2C (operation mode 4). 84 A7 99 62
RTS4_0 90 C6 105 68
RTS4_1 69 E9 79 47
RTS4_2
Multi-function serial interface ch.4 RTS
output pin 86 C7 101 64
CTS4_0 91 A5 106 69
CTS4_1 68 F8 78 46
Multi-
function
Serial
4
CTS4_2
Multi-function serial interface ch.4 CTS
input pin 85 B7 100 63
SIN5_0 96 C4 116 74
SIN5_1 93 D6 113 93
SIN5_2 Multi-function serial interface ch.5 input pin 15 F3 20 93
SOT5_0
(SDA5_0) 95 B4 115 73
SOT5_1
(SDA5_1) - - 112 -
SOT5_2
(SDA5_2)
Multi-function serial interface ch.5 output
pin.
This pin operates as SOT5 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA5 when it is used in an I2C
(operation mode 4). 16 G1 21 94
SCK5_0
(SCL5_0) 94 C5 114 72
SCK5_1
(SCL5_1) - - 111 -
Multi-
function
Serial
5
SCK5_2
(SCL5_2)
Multi-function serial interface ch.5 clock I/O
pin.
This pin operates as SCK5 when it is used in
a CSIO (operation modes 2) and as SCL5
when it is used in an I2C (operation mode 4). 17 G2 22 95
38
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
SIN6_0 5 D1 5 83
SIN6_1 Multi-function serial interface ch.6 input pin 12 E4 17 90
SOT6_0
(SDA6_0) 6 D2 6 84
SOT6_1
(SDA6_1)
Multi-function serial interface ch.6 output
pin.
This pin operates as SOT6 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA6 when it is used in an I2C
(operation mode 4).
11 E3 16 89
SCK6_0
(SCL6_0) 7 D3 7 85
Multi-
function
Serial
6
SCK6_1
(SCL6_1)
Multi-function serial interface ch.6 clock I/O
pin.
This pin operates as SCK6 when it is used in
a CSIO (operation modes 2) and as SCL6
when it is used in an I2C (operation mode 4). 10 E2 15 88
SIN7_0 - - 11 -
SIN7_1 Multi-function serial interface ch.7 input pin 45 K8 50 23
SOT7_0
(SDA7_0) - - 12 -
SOT7_1
(SDA7_1)
Multi-function serial interface ch.7 output
pin.
This pin operates as SOT7 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA7 when it is used in an I2C
(operation mode 4). 44 J7 49 22
SCK7_0
(SCL7_0) - - 13 -
Multi-
function
Serial
7
SCK7_1
(SCL7_1)
Multi-function serial interface ch.7 clock I/O
pin.
This pin operates as SCK7 when it is used in
a CSIO (operation modes 2) and as SCL7
when it is used in an I2C (operation mode 4). 43 H6 48 21
DS706-00028-2v0-E
39
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
DTTI0X_0 18 F4 23 96
DTTI0X_1
Input signal controlling wave form generator
outputs RTO00 to RTO05 of Multi-function
timer 0. 69 E9 79 47
FRCK0_0 13 F1 18 91
FRCK0_1 70 D11 80 48
FRCK0_2
16-bit free-run timer ch.0 external clock
input pin 53 J10 63 31
IC00_0 17 G2 22 95
IC00_1 65 F9 75 43
IC00_2 54 J8 64 32
IC01_0 16 G1 21 94
IC01_1 66 E11 76 44
IC01_2 55 H10 65 33
IC02_0 15 F3 20 93
IC02_1 67 E10 77 45
IC02_2 56 H9 66 34
IC03_0 14 F2 19 92
IC03_1 68 F8 78 46
IC03_2
16-bit input capture ch.0 input pin of
Multi-function timer 0.
ICxx describes channel number.
57 H7 67 35
RTO00_0
(PPG00_0) 19 G3 24 97
RTO00_1
(PPG00_1)
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes. - - 86 -
RTO01_0
(PPG00_0) 20 H1 25 98
RTO01_1
(PPG00_1)
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes. - - 85 -
RTO02_0
(PPG02_0) 21 H2 26 99
RTO02_1
(PPG02_1)
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes. - - 84 -
RTO03_0
(PPG02_0) 22 G4 27 100
RTO03_1
(PPG02_1)
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes. - - 83 -
RTO04_0
(PPG04_0) 23 H3 28 1
RTO04_1
(PPG04_1)
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes. - - 82 -
RTO05_0
(PPG04_0) 24 J2 29 2
Multi-
function
Timer
0
RTO05_1
(PPG04_1)
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes. - - 81 -
40
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
DTTI1X_0 8 D5 8 86
DTTI1X_1
Input signal controlling wave form generator
outputs RTO10 to RTO15 of Multi-function
timer 1. 39 K6 44 17
FRCK1_0 87 D7 102 65
FRCK1_1 16-bit free-run timer ch.1 external clock
input pin 44 J7 49 22
IC10_0 88 A6 103 66
IC10_1 40 J6 45 18
IC11_0 89 B6 104 67
IC11_1 41 L7 46 19
IC12_0 90 C6 105 68
IC12_1 42 K7 47 20
IC13_0 91 A5 106 69
IC13_1
16-bit input capture ch.1 input pin of
Multi-function timer 1.
ICxx describes channel number.
43 H6 48 21
RTO10_0
(PPG10_0) 2 C1 2 80
RTO10_1
(PPG10_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes. 27 J4 32 5
RTO11_0
(PPG10_0) 3 C2 3 81
RTO11_1
(PPG10_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes. 28 L5 33 6
RTO12_0
(PPG12_0) 4 B3 4 82
RTO12_1
(PPG12_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes. 29 K5 34 7
RTO13_0
(PPG12_0) 5 D1 5 83
RTO13_1
(PPG12_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes. 30 J5 35 8
RTO14_0
(PPG14_0) 6 D2 6 84
RTO14_1
(PPG14_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes. 31 H5 36 9
RTO15_0
(PPG14_0) 7 D3 7 85
Multi-
function
Timer
1
RTO15_1
(PPG14_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes. 32 L6 37 10
DS706-00028-2v0-E
41
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
DTTI2X_0 92 B5 107 70
DTTI2X_1
Input signal controlling wave form generator
outputs RTO20 to RTO25 of Multi-function
timer 2. 92 B5 107 70
FRCK2_0 87 D7 102 65
FRCK2_1 16-bit free-run timer ch.2 external clock input
pin - - 112 -
IC20_0 88 A6 103 66
IC20_1 - - 108 -
IC21_0 89 B6 104 67
IC21_1 - - 109 -
IC22_0 90 C6 105 68
IC22_1 - - 110 -
IC23_0 91 A5 106 69
IC23_1
16-bit input capture ch.2 input pin of
Multi-function timer 2.
ICxx describes channel number.
- - 111 -
RTO20_0
(PPG20_0) - - 113 -
RTO20_1
(PPG20_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes. 86 C7 101 64
RTO21_0
(PPG20_0) - - 112 -
RTO21_1
(PPG20_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes. 87 D7 102 65
RTO22_0
(PPG22_0) - - 111 -
RTO22_1
(PPG22_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes. 88 A6 103 66
RTO23_0
(PPG22_0) - - 110 -
RTO23_1
(PPG22_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes. 89 B6 104 67
RTO24_0
(PPG24_0) - - 109 -
RTO24_1
(PPG24_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes. 90 C6 105 68
RTO25_0
(PPG24_0) - - 108 -
Multi-
function
Timer
2
RTO25_1
(PPG24_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes. 91 A5 106 69
42
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
AIN0_0 9 E1 14 87
AIN0_1 40 J6 45 18
AIN0_2
QPRC ch.0 AIN input pin
2 C1 2 80
BIN0_0 10 E2 15 88
BIN0_1 41 L7 46 19
BIN0_2
QPRC ch.0 BIN input pin
3 C2 3 81
ZIN0_0 11 E3 16 89
ZIN0_1 42 K7 47 20
Quadrature
Position/
Revolution
Counter
0
ZIN0_2
QPRC ch.0 ZIN input pin
4 B3 4 82
AIN1_1 74 C10 89 52
AIN1_2 QPRC ch.1 AIN input pin 43 H6 48 21
BIN1_1 73 C11 88 51
BIN1_2 QPRC ch.1 BIN input pin 44 J7 49 22
ZIN1_1 72 E8 87 50
Quadrature
Position/
Revolution
Counter
1
ZIN1_2 QPRC ch.1 ZIN input pin 45 K8 50 23
AIN2_0 - - 10 -
AIN2_1 QPRC ch.2 AIN input pin 83 D9 98 61
BIN2_0 - - 11 -
BIN2_1 QPRC ch.2 BIN input pin 84 A7 99 62
ZIN2_0 - - 12 -
Quadrature
Position/
Revolution
Counter
2
ZIN2_1 QPRC ch.2 ZIN input pin 85 B7 100 63
RTCCO_0 92 B5 107 70
RTCCO_1 55 H10 65 33
RTCCO_2
0.5 seconds pulse output pin of Real-time
clock 19 G3 24 97
SUBOUT_0 92 B5 107 70
SUBOUT_1 55 H10 65 33
Real-time
clock
SUBOUT_2
Sub clock output pin
19 G3 24 97
DS706-00028-2v0-E
43
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Pin No
Module Pin name Function LQFP-
100 BGA-
112 LQFP-
120 QFP-
100
RESET INITX External Reset Input pin.
A reset is valid when INITX="L". 38 K4 43 16
MD0
Mode 0 pin.
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
47 L8 57 25
Mode
MD1 Mode 1 pin.
During serial programming to Flash memory,
MD1="L" must be input. 46 K9 56 24
VCC Power supply Pin 1 B1 1 79
VCC Power supply Pin 26 J1 31 4
VCC Power supply Pin 35 K1 40 13
VCC Power supply Pin 51 K11 61 29
VCC Power supply Pin 76 A10 91 54
POWER
VCC Power supply Pin 97 A4 117 75
VSS GND Pin - B2 -
VSS GND Pin 25 L1 30 3
VSS GND Pin - K2 -
VSS GND Pin - J3 -
VSS GND Pin - H4 -
VSS GND Pin 34 L4 39 12
VSS GND Pin 50 L11 60 28
VSS GND Pin - K10 -
VSS GND Pin - J9 -
VSS GND Pin - H8 -
VSS GND Pin - B10 -
VSS GND Pin - C9 -
VSS GND Pin 75 A11 90 53
VSS GND Pin - D8 -
VSS GND Pin - D4 -
VSS GND Pin - C3 -
GND
VSS GND Pin 100 A1 120 78
X0 Main clock (oscillation) input pin 48 L9 58 26
X0A Sub clock (oscillation) input pin 36 L3 41 14
X1 Main clock (oscillation) I/O pin 49 L10 59 27
X1A Sub clock (oscillation) I/O pin 37 K3 42 15
CROUT_0 74 C10 89 52
CLOCK
CROUT_1 High-speed CR-osc clock output port 92 B5 107 70
AVCC A/D converter analog power pin 60 H11 70 38 ADC
POWER AVRH A/D converter analog reference voltage input
pin 61 F11 71 39
ADC
GND AVSS A/D converter GND pin 62 G11 72 40
C pin C Power stabilization capacity pin 33 L2 38 11
44
DS706-00028-2v0-E
MB9B110R Series
I/O CIRCUIT TYPE
Type Circuit Remarks
A
P-chP-ch
N-ch
R
R
P-chP-ch
N-ch
X0
X1
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
・ Oscillation feedback
resistor
: Approximately 1MΩ
・ With Standby mode control
When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL = 4mA
B
・ CMOS level hysteresis
input
・ Pull-up resistor
: Approximately 50kΩ
Di
g
ital output
Di
g
ital output
Pull-up resistor control
Di
g
ital input
Standb
y
mode Control
Clock input
Standb
y
mode Control
Di
g
ital input
Standb
y
mode Control
Di
g
ital output
Di
g
ital output
Pull-up resistor control
Di
g
ital input
Pull-up resisto
r
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
DS706-00028-2v0-E
45
MB9B110R Series
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
Type Circuit Remarks
C
N-ch
・ Open drain output
・ CMOS level hysteresis
input
D
P-chP-ch
N-ch
R
R
P-chP-ch
N-ch
X0A
X1A
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is
selected.
・ Oscillation feedback
resistor
: Approximately 5MΩ
・ With Standby mode control
When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL= 4mA
Di
g
ital input
Di
g
ital output
Di
g
ital output
Di
g
ital output
Pull-up resistor control
Di
g
ital input
Standb
y
mode Control
Clock input
Standb
y
mode Control
Di
g
ital input
Standb
y
mode Control
Di
g
ital output
Di
g
ital output
Pull-up resistor control
46
DS706-00028-2v0-E
MB9B110R Series
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
Type Circuit Remarks
E
P-chP-ch
N-ch
R
・ CMOS level output
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL = 4mA
F
P-chP-ch
N-ch
X1A
R
・ CMOS level output
・ CMOS level hysteresis
input
・ With input control
・ Analog input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH = -4mA, IOL = 4mA
Di
g
ital output
Di
g
ital output
Pull-up resistor control
Di
g
ital input
Standb
y
mode Control
Di
g
ital output
Di
g
ital output
Pull-up resistor control
Di
g
ital input
Standb
y
mode Control
A
nalo
g
input
Input control
DS706-00028-2v0-E
47
MB9B110R Series
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
Type Circuit Remarks
G
P-chP-ch
N-ch
R
・ CMOS level output
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50kΩ
・ IOH= -12mA, IOL= 12mA
H
P-ch
N-ch
R
・ CMOS level output
・ CMOS level hysteresis
input
・ With standby mode control
Di
g
ital output
Di
g
ital output
Pull-up resistor control
Di
g
ital input
Standb
y
mode Control
Di
g
ital output
Di
g
ital output
Di
g
ital input
Standb
y
mode Control
48
DS706-00028-2v0-E
MB9B110R Series
Type Circuit Remarks
I
P-chP-ch
N-ch
R
・ CMOS level output
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ 5V tolerant
・ With standby mode control
・ IOH = -4mA, IOL = 4mA
・ Available to control of PZR
registers.
J
CMOS level hysteresis input
Di
g
ital output
Di
g
ital output
Pull-up resistor control
Di
g
ital input
Standb
y
mode Control
Mode input
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
DS706-00028-2v0-E
49
MB9B110R Series
HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your FUJITSU SEMICONDUCTOR semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
・Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
・Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
・Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
・Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-1Ea
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
50
DS706-00028-2v0-E
MB9B110R Series
・Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
・Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
・Precautions Related to Usage of Devices
FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications
(computers, office automation and other office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under FUJITSU SEMICONDUCTOR's recommended conditions.
For detailed information about mount conditions, contact your sales representative.
・Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended
mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
・Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder
reflow method, and has established a ranking of mounting conditions for each product. Users are advised to
mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions.
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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・Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
・Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly
moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in
their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
・Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.
Condition: 125°C/24 h
・Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU SEMICONDUCTOR products in other special
environmental conditions should consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://edevice.fujitsu.com/fj/handling-e.pdf
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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HANDLING DEVICES
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between VCC and VSS near this device.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Using an external clock
When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A
pin should be kept open.
Example of Using an External Clock Device
X0(X0A)
X1(X1A)Open
Handling when using Multi function serial pin as I2C pin
If it is using multi function serial pin as I2C pins, P-ch transistor of digital output is always disable.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C
bus system with power OFF.
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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C Pin
As this series includes an internal regulator, always connect a bypass capacitor of approximately 4.7 µF to
the C pin for use by the regulator.
GND
4.7μF
VSS
C
Device
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
BLOCK DIAGRAM
MainFlash I/F
Cortex-M3 Core
144MHz(Max)
Clock Reset
Generator
Dual-Timer
Watchdog Timer
(Hardware) DMAC
8ch.
Multi-function Timer x 3
Multi-function Serial I/F
8ch.
(with FIFO ch.4-ch.7)
HW flow control(ch.4)
16-bit Free-run Timer
3ch.
16-bit Output
Compare
6ch.
16-bit Input Capture
4ch.
Waveform Generator
3ch.
A/D Activation
Compare
3ch.
16-bit PPG
3ch.
Watch Counter
12-bit A/D Converter
GPIO
CSV
Main
Osc PLL
External Interrupt
Controller
16-pin + NMI
TPIU ROM
Table
ETM SRAM0
8/16/24/32Kbyte
SWJ-DP
Multi-layer AHB (Max 144MHz)
AHB-APB Bridge : APB1 (Max 72MHz)
SRAM1
8/16/24/32Kbyte
AHB-APB Bridge:
APB0(Max 72MHz)
I
D
Sys
CLK RST
AHB-APB Bridge : APB2 (Max 72MHz)
Base Timer
16-bit 8ch./
32-bit 4ch.
NVIC
Watchdog Timer
(Software)
Security
Sub
Osc CR
4MHz
A/D Converter ×3
12-bit A/D Converter
12-bit A/D Converter
TRSTX,TCK,
TDI,TMS
TRACED[3:0],
TRACECLK
X0
AVCC,
AVSS, AVRH
AN[15:00]
TIOA[7:0]
TIOB[7:0]
IC0[3:0]
DTTI[2:0]X
RTO0[5:0]
FRCK[2:0]
TDO
X1
X0A
X1A
SCK[7:0]
SIN[7:0]
SOT[7:0]
INT[15:00]
NMIX
P0[F:0],
P1[F:0],
.
.
.
Px[x:0]
INITX
MODE-Ctrl
IRQ-Monitor
PIN-Function-Ctrl
MD[1:0]
CR
100kHz
QPRC
3ch.
AIN[2:0]
BIN[2:0]
ZIN[2:0]
LVD Ctrl
CRC
Accelerator
IC1[3:0]
ADTG[8:0]
RTS4
CTS4
External Bus I/F
MAD[24:00]
MADATA[15:00]
MCSX[7:0],
MALE,
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
RTO1[5:0]
MPU Trace Buffer
(16Kbyte)
IC2[3:0]
RTO2[5:0]
MainFlash
128Kbyte/
256Kbyte/
384Kbyte/
512Kbyte
LVD
Power On
Reset
Regulator C
WorkFlash
32Kbyte
WorkFlash I/F
AHB-AHB
Bridge
Real-Time Clock RTCCO
SUBOUT
MRDY
MEMORY SIZE
See "PRODUCT LINEUP" of " Memory size" to confirm the memory size.
56
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MEMORY MAP
Memory Map (1)
0xFFFF_FFFF
0xE010_0000
Reserved
0xE000_0000 Cortex-M3 Private
Peripherals
0x6000_0000
External Device
Area
0x4400_0000 Reserved
0x4200_0000 32Mbyte
Bit band alias
0x4000_0000 Peripherals
0x2400_0000
Reserved
0x2200_0000
32Mbyte
Bit band alias
0x200E_1000 Reserved
0x200E_0000 WorkFlash I/F
0x200C_0000 WorkFlash
0x2008_0000 Reserved
0x2000_0000 SRAM1
0x1FFF_0000 SRAM0
0x0010_2000 Reserved
0x0010_0000
Security/CR T rim
See the next page
"Memory Map (2), (3)"
for the memory size
details.
0x0000_0000
MainFlash
Peripherals Area
0x41FF_FFFF
0x4006_1000
Reserved
0x4006_0000 DMAC
0x4004_0000
Reserved
0x4003_F000 EXT-bus I/F
0x4003_C000 Reserved
0x4003_B000 RTC
0x4003_A000 Watch Counter
0x4003_9000 CRC
0x4003_8000 MFS
0x4003_6000 Reserved
0x4003_5000 LVD Ctrl
0x4003_4000 Reserved
0x4003_3000 GPIO
0x4003_2000 Reserved
0x4003_1000 Int-Req. Read
0x4003_0000 EXTI
0x4002_F000 Reserved
0x4002_E000 CR Trim
0x4002_8000 Reserved
0x4002_7000 A/DC
0x4002_6000 QPRC
0x4002_5000 Base Timer
0x4002_4000 PPG
0x4002_3000 Reserved
0x4002_2000 MFT unit2
0x4002_1000 MFT unit1
0x4002_0000 MFT unit0
0x4001_6000 Reserved
0x4001_5000 Dual Timer
0x4001_3000 Reserved
0x4001_2000 SW WDT
0x4001_1000 HW WDT
0x4001_0000 Clock/Reset
0x4000_1000 Reserved
0x4000_0000 MainFlash I/F
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
Memory Map (2)
MB9BF116N/R
0x200E_0000
0x200C_8000
Reserved
0x200C_0000
WorkFlash
32Kbyte
0x2000_8000 Reserved
0x2000_0000
SRAM1
32Kbyte
0x1FFF_8000
SRAM0
32Kbyte
0x0010_2000
Reserved
0x0010_1000 CR trimming
0x0010_0000 Security
0x0008_0000
Reserved
0x0000_0000
MainFlash
512Kbyte
MB9BF115N/R
0x200E_0000
0x200C_8000
Reserved
0x200C_0000
WorkFlash
32Kbyte
0x2000_6000
Reserved
0x2000_0000
SRAM1
24Kbyte
0x1FFF_A000
SRAM0
24Kbyte
0x0010_2000
Reserved
0x0010_1000 CR trimming
0x0010_0000 Security
0x0006_0000
Reserved
0x0000_0000
MainFlash
384Kbyte
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MB9B110R Series
Memory Map (3)
MB9BF114N/R
0x200E_0000
0x200C_8000
Reserved
0x200C_0000
WorkFlash
32Kbyte
0x2000_4000
Reserved
0x2000_0000
SRAM1
16Kbyte
0x1FFF_C000
SRAM0
16Kbyte
0x0010_2000
Reserved
0x0010_1000 CR trimming
0x0010_0000 Security
0x0004_0000
Reserved
0x0000_0000
MainFlash
256Kbyte
MB9BF112N/R
0x200E_0000
0x200C_8000
Reserved
0x200C_0000
WorkFlash
32Kbyte
0x2000_2000
Reserved
0x2000_0000 SRAM1
8Kbyte
0x1FFF_E000
SRAM0
8Kbyte
0x0010_2000
Reserved
0x0010_1000 CR trimming
0x0010_0000 Security
0x0002_0000
Reserved
0x0000_0000
MainFlash
128Kbyte
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
Peripheral Address Map
Start address End address Bus Peripherals
0x4000_0000 0x4000_0FFF MainFlash I/F register
0x4000_1000 0x4000_FFFF
AHB Reserved
0x4001_0000 0x4001_0FFF Clock/Reset Control
0x4001_1000 0x4001_1FFF Hardware Watchdog timer
0x4001_2000 0x4001_2FFF Software Watchdog timer
0x4001_3000 0x4001_4FFF Reserved
0x4001_5000 0x4001_5FFF Dual-Timer
0x4001_6000 0x4001_FFFF
APB0
Reserved
0x4002_0000 0x4002_0FFF Multi-function timer unit0
0x4002_1000 0x4002_1FFF Multi-function timer unit1
0x4002_2000 0x4002_3FFF Multi-function timer unit2
0x4002_4000 0x4002_4FFF PPG
0x4002_5000 0x4002_5FFF Base Timer
0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter
0x4002_7000 0x4002_7FFF A/D Converter
0x4002_8000 0x4002_DFFF Reserved
0x4002_E000 0x4002_EFFF Internal CR trimming
0x4002_F000 0x4002_FFFF
APB1
Reserved
0x4003_0000 0x4003_0FFF External Interrupt Controller
0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function
0x4003_2000 0x4003_2FFF Reserved
0x4003_3000 0x4003_3FFF GPIO
0x4003_4000 0x4003_4FFF Reserved
0x4003_5000 0x4003_5FFF Low-Voltage Detector
0x4003_6000 0x4003_6FFF Reserved
0x4003_7000 0x4003_7FFF CAN prescaler
0x4003_8000 0x4003_8FFF Multi-function serial Interface
0x4003_9000 0x4003_9FFF CRC
0x4003_A000 0x4003_AFFF Watch Counter
0x4003_B000 0x4003_BFFF Real-time clock
0x4003_C000 0x4003_EFFF Reserved
0x4003_F000 0x4003_FFFF
APB2
External Memory interface
0x4004_0000 0x4005_FFFF Reserved
0x4006_0000 0x4006_0FFF DMAC register
0x4006_1000 0x41FF_FFFF Reserved
0x200E_0000 0x200E_FFFF
AHB
WorkFlash I/F register
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PIN STATUS IN EACH CPU STATE
The terms used for pin status have the following meanings.
・ INITX=0
This is the period when the INITX pin is the "L" level.
・ INITX=1
This is the period when the INITX pin is the "H" level.
・ SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "0".
・ SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "1".
・ Input enabled
Indicates that the input function can be used.
・ Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
・ Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
・ Setting disabled
Indicates that the setting is disabled.
・ Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
・ Analog input is enabled
Indicates that the analog input is enabled.
・ Trace output
Indicates that the trace function can be used.
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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List of Pin Status Power-on reset
or low-voltage
detection state
INITX input
state
Device
internal reset
state
Run mode or
sleep mode
state
Timer mode or sleep mode
state
Power supply
unstable Power supply stable Power supply
stable Power supply stable
- INITX=0 INITX=1 INITX=1 INITX=1
Pin
status
type Function group
- - - - SPL=0 SPL=1
GPIO selected Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
A Main crystal
oscillator input
pin
Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled
GPIO selected Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
B Main crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enable
Hi-Z/
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state/ Hi-Z
at oscillation
stop*1/
Internal
input fixed
at "0"
Maintain
previous
state/ Hi-Z
at oscillation
stop*1/
Internal
input fixed
at "0"
C INITX input pin Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
Pull-up/
Input
enabled
D Mode input pin Input enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled
JTAG
selected Hi-Z Pull-up/
Input
enabled
Pull-up/
Input
enabled
Maintain
previous
state
E GPIO
selected Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state Hi-Z/
Internal
input fixed
at "0"
Trace selected Trace output
External interrupt
enabled selected
Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
F GPIO
selected, or other
than above
resource selected
Hi-Z Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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Power-on reset
or low-voltage
detection state
INITX input
state
Device
internal reset
state
Run mode or
sleep mode
state
Timer mode or sleep mode
state
Power supply
unstable Power supply stable Power supply
stable Power supply stable
- INITX=0 INITX=1 INITX=1 INITX=1
Pin
status
type Function group
- - - - SPL=0 SPL=1
Trace selected Setting
disabled Setting
disabled Setting
disabled Trace output
G GPIO selected,
or other than
above resource
selected
Hi-Z Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state Hi-Z/
Internal
input fixed
at "0"
External interrupt
enabled selected Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
H GPIO selected,
or other than
above resource
selected
Hi-Z Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state Hi-Z/
Internal
input fixed
at "0"
I
GPIO selected,
resource selected Hi-Z Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
NMIX selected Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
J GPIO selected,
or other than
above resource
selected
Hi-Z Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous
state Hi-Z/
Internal
input fixed
at "0"
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
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MB9B110R Series
Power-on reset
or low-voltage
detection state
INITX input
state
Device
internal reset
state
Run mode or
sleep mode
state
Timer mode or sleep mode
state
Power supply
unstable Power supply stable Power supply
stable Power supply stable
- INITX=0 INITX=1 INITX=1 INITX=1
Pin
status
type Function group
- - - - SPL=0 SPL=1
Analog input
selected Hi-Z Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
K
GPIO selected,
or other than
above resource
selected
Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
External interrupt
enabled selected Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Analog input
selected Hi-Z Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
L
GPIO selected,
or other than
above resource
selected
Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
GPIO selected Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
M
Sub crystal
oscillator input
pin
Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled
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MB9B110R Series
Power-on reset
or low-voltage
detection state
INITX input
state
Device
internal reset
state
Run mode
or sleep mode
state
Timer mode or sleep mode
state
Power supply
unstable Power supply stable Power supply
stable Power supply stable
- INITX=0 INITX=1 INITX=1 INITX=1
Pin
status
type Function group
- - - - SPL=0 SPL=1
GPIO selected Setting
disabled Setting
disabled Setting
disabled Maintain
previous
state
Maintain
previous state Hi-Z/
Internal
input fixed
at "0"
N
Sub crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enable
Hi-Z/
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
p
revious state/
Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
Maintain
previous
state/ Hi-Z
at
oscillation
stop*2/
Internal
input fixed
at "0"
O
GPIO selected Hi-Z Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Maintain
previous state Hi-Z/
Internal
input fixed
at "0"
Mode input pin Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled
P
GPIO selected Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Input
enabled
*1 : Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, and STOP mode.
*2 : Oscillation is stopped at STOP mode.
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MB9B110R Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter Symbol Min Max
Unit Remarks
Power supply voltage*1, *2 Vcc Vss - 0.5 Vss + 6.5 V
Analog power su ppl y vol t age*1, *3 AVcc Vss - 0.5 Vss + 6.5 V
Analog reference voltage*1, *3 AVRH Vss - 0.5 Vss + 6.5 V
Vss - 0.5 Vcc + 0.5
(≤ 6.5V) V
Input voltage*1 V
I Vss - 0.5 Vss + 6.5 V 5V tolerant
Analog pin input voltage*1 V
IA Vss - 0.5 AVcc + 0.5
(≤ 6.5V) V
Output vol t a ge*1 V
O Vss - 0.5 Vcc + 0.5
(≤ 6.5V) V
10 mA 4mA type
"L" level maximum output current*4 I
OL - 20 mA 12mA type
4 mA 4mA type
"L" level average output current*6 I
OLAV - 12 mA 12mA type
"L" level total maximum output curren t ∑IOL - 100 mA
"L" level total average output current* 6 ∑IOLAV - 50 mA
- 10 mA 4mA type
"H" level maximum output current*4 I
OH - - 20 mA 12mA type
- 4 mA 4mA type
"H" level average output current*5 I
OHAV - - 12 mA 12mA type
"H" level total maximum output current ∑IOH - - 100 mA
"H" level total average output current*6 ∑IOHAV - - 50 mA
Power consumption PD - 1000 mW
Storage temperature TSTG - 55 + 150 °C
*1 : These parameters are based on the condition that VSS = AVSS = 0.0V.
*2 : Vcc must not drop below VSS - 0.5V.
*3 : Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output is the average current for a single pin over a period of 100 ms.
*6 : The total average output current is the average current for all pins over a period of 100 ms.
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB9B110R Series
2. Recommended Operating Conditions
(Vss = AVss = 0.0V)
Value
Parameter Symbol Conditions Min Max
Unit Remarks
Power supply voltage Vcc - 2.7 5.5 V
Analog power su ppl y vol t age AVcc - 2.7 5.5 V AVcc = Vcc
Analog reference voltage AVRH - AVss AVcc V
FPT-100P-M20/M23
FPT-120P-M21/M37 Ta
When
mounted on
four-layer
PCB
- 40 + 85 °C
Operating
temperature FPT-100P-M36
BGA-112P-M04 Ta - - 40 + 85 °C
<WARNING>
The recommended operating conditions are required in order to ensure the no rmal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact th eir representatives beforehand.
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MB9B110R Series
3. DC Characteristics
(1) Current Rating (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin
name Conditions Min Typ Max Unit Remarks
- 85 117 mA
CPU : 144MHz,
Peripheral : 72MHz,
Main Flash 2Wait
TraceBuffer : ON
FRWTR.RWT = 10
FSYNDN.SD = 000
FBFCR.BE = 1
*1
Normal operation
(PLL)
- 52 70 mA
CPU : 72MHz,
Peripheral : 72MHz,
Main Flash 0Wait
TraceBuffer : OFF
FRWTR.RWT = 00
FSYNDN.SD = 000
FBFCR.BE = 0
*1
Normal operation
(high-speed internal
CR) - 5 17 mA
CPU/ Peripheral : 4MHz*2
Main Flash 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*1
Normal operation
(sub oscillation) - 1.3 14 mA
CPU/ Peripheral : 32kHz
Main Flash 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*1
Icc
Normal operation
(low-speed
internal CR) - 1.3 14 mA
CPU/ Peripheral : 100kH z
Main Flash 0Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*1
SLEEP operation
(PLL) - 28 43 mA
Peripheral : 72MHz
*1
SLEEP operation
(high-speed internal
CR) - 3 16 mA
Peripheral : 4MHz*2
*1
SLEEP operation
(sub oscillation) - 1 14 mA
Peripheral : 32kHz
*1
Power
supply
current
Iccs
VCC
SLEEP operation
(low-speed internal
CR) - 1 14 mA
Peripheral : 100kHz
*1
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MB9B110R Series
Value
Parameter Symbol Pin
name Conditions Min Typ Max Unit Remarks
- 0.8 3 mA
Ta = + 25°C,
When LVD is of f
*1
ICCH STOP mode
- - 12 mA
Ta = + 85°C,
When LVD is of f
*1
- 0.9 3 mA
Ta = + 25°C,
When LVD is of f
*1
Power
supply
current
ICCT TIMER mode
(sub oscillation) - - 12 mA
Ta = + 85°C,
When LVD is of f
*1
Low-voltage
detection
circuit (LVD)
power supply
current
ICCLVD
VCC
At operation - 4 7 mA For occurrence of
interrupt
*1: When all ports are fixed.
*2: When setting it to 4MHz by trimming.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(2) Pin Characteristic s (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter SymbolPin name Conditions Min Typ Max Unit Remarks
CMOS
hysteresis
input pin,
MD0, MD1
- Vcc × 0.8 - Vcc + 0.3 V
"H" level
input
voltage
(hysteresis
input)
VIHS
5V tolerant
input pin - Vcc × 0.8 - Vss + 5.5 V
CMOS
hysteresis
input pin,
MD0, MD1
- Vss - 0.3 - Vcc × 0.2 V
"L" level
input
voltage
(hysteresis
input)
VILS
5V tolerant
input pin - Vss - 0.3 - Vcc × 0.2 V
Vcc ≥ 4.5 V
IOH = - 4mA
4mA type Vcc < 4.5 V
IOH = - 2mA
Vcc - 0.5 - Vcc V
Vcc ≥ 4.5 V
IOH = - 12mA
"H" level
output vol t a ge VOH
12mA type Vcc < 4.5 V
IOH = - 8mA
Vcc - 0.5 - Vcc V
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MB9B110R Series
Value
Parameter Symbol Pin
name Conditions Min Typ Max
Unit Remarks
Vcc ≥ 4.5 V
IOL = 4mA
4mA type Vcc < 4.5 V
IOL = 2mA
Vss - 0.4 V
Vcc ≥ 4.5 V
IOL = 12mA
"L" level
output vol t a ge VOL
12mA type Vcc < 4.5 V
IOL = 8mA
Vss - 0.4 V
Input leak
current IIL - - - 5 - +5 μA
Vcc ≥ 4.5 V 25 50 100
Pull-up
resistance
value RPU Pull-up pin Vcc < 4.5 V 30 80 200 kΩ
Input
capacitance CIN
Other than
VCC,
VSS,
AVCC,
AVSS,
AVRH
- - 5 15 pF
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
4. AC Characteristics
(1) Main Clock Input Chara cteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol
Pin
name Conditions Min Max
Unit Remarks
Vcc ≥ 4.5V 4 48
Vcc < 4.5V 4 20 MHz When crystal oscillator
is connected
Vcc ≥ 4.5V 4 48
Input frequency FCH
Vcc < 4.5V 4 20 MHz When using external
clock
Vcc ≥ 4.5V 20.83 250
Input clock cycle tCYLH Vcc < 4.5V 50 250 ns When using external
clock
Input clock pulse
width - PWH/tCYLH
PWL/tCYLH 45 55 %
When using external
clock
Input clock rise
time and fall time tCF,
tCR
X0
X1
- - 5 ns
When using external
clock
FCC - - - 144 MHz Base clock
(HCLK/FCLK)
FCP0 - - - 72 MHz APB0 bus clock*2
FCP1 - - - 72 MHz APB1 bus clock*2
Internal ope rati ng
clock*1 frequency
FCP2 - - - 72 MHz APB2 bus clock*2
tCYCC - - 6.94 - ns
Base clock
(HCLK/FCLK)
tCYCP0 - - 13.8 - ns APB0 bus clock*2
tCYCP1 - - 13.8 - ns APB1 bus clock*2
Internal ope rati ng
clock*1 cycle time
tCYCP2 - - 13.8 - ns APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter:Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data
sheet.
0.8 × Vcc
tCYLH
0.8 × Vcc
0.2 × Vcc 0.2 × Vcc
0.8 × Vcc
PWLPWH tCF tCR
X0
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(2) Sub Clock Input Charac teristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol
Pin
name Conditions Min Typ Max Unit Remarks
- - 32.768 - kHz
When cr ystal
oscillator is
connected
Input frequency 1/ tCYLL
- 32 - 100 kHz
When using
external clock
Input clock cycle tCYLL - 10 - 31.25 μs When using
external clock
Input clock pulse
width -
X0A
X1A
PWH/tCYLL
PWL/tCYLL 45 - 55 %
When using
external clock
0.8 × Vcc
t
CYLL
0.8 × Vcc
0.2 × Vcc 0.2 × Vcc
0.8 × Vcc
P
WL
P
WH
(3) Internal CR Oscillation Characteristics
・ High-speed Internal CR (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Conditions Min Typ Max Unit Remarks
Ta = + 25°C 3.96 4 4.04
Ta =
0°C to + 70°C 3.84 4 4.16
Ta =
- 40°C to + 85°C 3.8 4 4.2
When trimming*
Clock frequency FCRH
Ta =
- 40°C to + 85°C 3 4 5
MHz
When not trimming
*: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
・ Low-speed Internal CR (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Conditions Min Typ Max Unit Remarks
Clock frequency FCRL - 50 100 150 kHz
X0
A
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Min Typ Max Unit Remarks
PLL oscillation stabilization wait time*
(LOCK UP time) tLOCK 100 - - μs
PLL input clock frequency FPLLI 4 - 16 MHz
PLL multiple rate - 13 - 75 multiple
PLL macro oscillation clock frequency FPLLO 200 - 300 MHz
*: Time from when the PLL starts operating until th e oscillation stabilizes.
(4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Min Typ Max Unit Remarks
PLL oscillation stabilization wait time*
(LOCK UP time) tLOCK 100 - - μs
PLL input clock frequency FPLLI 3.8 4 4.2 MHz
PLL multiple rate - 50 - 71 multiple
PLL macro oscillation clock frequency FPLLO 190 - 300 MHz
*: Time from when the PLL starts operating until th e oscillation stabilizes.
Note:It needs to input to PLL by internal CR trimmin g frequency.
(5) Reset Input Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol
Pin
name Conditions Min Max Unit Remarks
Reset input time tINITX INITX - 500 - ns
(6) Power-on Reset Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin
name Min Max
Unit Remarks
Power supply rising time Tr 0 - ms
Power supply shut down time Toff VCC 1 - ms
0.2V
2.7V
Tr
V
cc
Toff
0.2V 0.2V
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(7) External Bus Timing
・ External bus clock output characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions
Min Max Unit
Vcc ≥ 4.5 V - 50*2 MHz
Output frequency tCYCLE MCLKOUT*1 Vcc < 4.5 V - 32*3 MHz
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "Chapter:External Bus Interface" in "FM3 Family
PERIPHERAL MANUAL".
*2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more
than 4.
*3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more
than 4.
0.8 × Vcc0.8 × Vcc
t
CYCLE
・ External bus signal input/output characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter Symbol Conditions Value Unit Remarks
VIH 0.8 × VCC V
Signal input characteristics VIL 0.2 × VCC V
VOH 0.8 × VCC V
Signal output characteristics VOL
-
0.2 × VCC V
VIH
VIL VIL
VIH
VOH
VOL VOL
VOH
MCLK
Input signal
Output signal
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ Separate Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit
Vcc ≥ 4.5V MOEX
Min pulse width tOEW MOEX
Vcc < 4.5V MCLK×n-3 - ns
Vcc ≥ 4.5V -9 +9
MCSX ↓ → Address
output delay time tCSL – AV MCSX[7:0]
MAD[24:0] Vcc < 4.5V -12 +12
ns
Vcc ≥ 4.5V MCLK×m+9
MOEX ↑ →
Address hold time tOEH - AX MOEX
MAD[24:0] Vcc < 4.5V 0 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9
MCSX ↓ →
MOEX ↓ delay time tCSL - OEL Vcc < 4.5V MCLK×m-12 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×m+9
MOEX ↑ →
MCSX ↑ time tOEH - CSH
MOEX
MCSX[7:0] Vcc < 4.5V 0 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9
MCSX ↓ →
MDQM ↓ delay time tCSL - RDQML MCSX
MDQM[1:0] Vcc < 4.5V MCLK×m-12 MCLK×m+12 ns
Vcc ≥ 4.5V 20 -
Data set up →
MOEX ↑ time tDS - OE MOEX
MADATA[15:0] Vcc < 4.5V 38 -
ns
Vcc ≥ 4.5V MOEX ↑ →
Data hold time tDH - OE MOEX
MADATA[15:0] Vcc < 4.5V 0 -
ns
Vcc ≥ 4.5V MWEX
Min pulse width tWEW MWEX
Vcc < 4.5V MCLK×n-3 - ns
Vcc ≥ 4.5V MCLK×m+9
MWEX ↑ → Address
output delay time tWEH - AX MWEX
MAD[24:0] Vcc < 4.5V 0 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×n-9 MCLK×n+9
MCSX ↓ →
MWEX ↓ delay time tCSL - WEL Vcc < 4.5V MCLK×n-12 MCLK×n+12 ns
Vcc ≥ 4.5V MCLK×m+9
MWEX ↑ →
MCSX ↑ delay time tWEH - CSH
MWEX
MCSX[7:0] Vcc < 4.5V 0 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×n-9 MCLK×n+9
MCSX ↓→
MDQM ↓ delay time tCSL-WDQML MCSX
MDQM[1:0] Vcc < 4.5V MCLK×n-12 MCLK×n+12 ns
Vcc ≥ 4.5V - 9 +9
MWEX ↓→
Data output time tWEL - DV Vcc < 4.5V -12 +12
ns
Vcc ≥ 4.5V MCLK×m+9
MWEX ↑ →
Data hold time tWEH - DX
MWEX
MADATA[15:0] Vcc < 4.5V 0 MCLK×m+12 ns
Note: When the external load capacitance = 30pF. (m = 0 to 15, n = 1 to 16)
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Address
RD WD
Address
t
CYCLE
t
OEH - CSH
t
OEH -AX
t
CS L - AV
t
WEH -AX
t
WEH - CSH
t
CS L - AV
t
CS L - O EL
t
OEW
t
DS - OE
t
DH - OE
t
WEL -DV
t
WEW
t
CSL -W EL
t
CSL -W DQML
t
WEH -DX
t
CSL - RDQML
MCLK
MCSX[7:0]
MAD[24:0]
MDQM[1:0]
MWEX
MADATA[15:0]
MOEX
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ Separate Bus Access Synchronous SR AM M ode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit
Vcc ≥ 4.5V 9
Address delay time tAV MCLK
MAD[24:0] Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9
tCSL Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9
MCSX delay time tCSH
MCLK
MCSX[7:0] Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9
tREL Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9
MOEX delay time tREH
MCLK
MOEX Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 19 Data set up →
MCLK ↑ time tDS MCLK
MADATA[15:0] Vcc < 4.5V 37 - ns
Vcc ≥ 4.5V MCLK ↑ →
Data hold time tDH MCLK
MADATA[15:0] Vcc < 4.5V 0 - ns
Vcc ≥ 4.5V 9
tWEL Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9
MWEX delay time tWEH
MCLK
MWEX Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9
tDQML Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9
MDQM[1:0]
delay time tDQMH
MCLK
MDQM[1:0] Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 18 MCLK ↑ →
Data output time tOD MCLK
MADATA[15:0] Vcc < 4.5V 1 24 ns
Note: When the external load capacitance = 30pF.
t
CYCLE
AddressAddress
RD WD
t
CSL
t
AV
t
REL
t
DQML
t
REH
t
AV
t
CSH
t
DQMH
t
DS
t
DH
t
OD
t
OD
t
WEL
t
WEH
t
DQML
t
DQMH
MCLK
MCSX[7:0]
MAD[24:0]
MDQM[1:0]
MWEX
MADATA[15:0]
MOEX
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit
Vcc ≥ 4.5V 10 Multiplexed
address delay time tALE-CHMADV Vcc < 4.5V 0 20 ns
Vcc ≥ 4.5V MCLK×n+0 MCLK×n+10Multiplexed
address hold time tCHMADH
MALE
MADATA[15:0] Vcc < 4.5V MCLK×n+0 MCLK×n+20 ns
Note: When the external load capacitance = 30pF. (m = 0 to 15, n = 1 to 16)
AddressAddress
RD
tCHMADH
tALE - CHMADV
tALE - CHMADV
tCYCLE
Address Address WD
MCLK
MCSX[7:0]
MALE
MOEX
MWEX
MADATA[15:0]
MAD [24:0]
MDQM [1:0]
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit Remarks
Vcc ≥ 4.5V 9 ns
tCHAL Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V 9 ns
MALE delay time tCHAH
MCLK
ALE Vcc < 4.5V 1 12 ns
Vcc ≥ 4.5V
MCLK ↑ →
Multiplexed
Address delay time tCHMADV Vcc < 4.5V 1 tOD ns
Vcc ≥ 4.5V
MCLK ↑ →
Multiplexed
Data output time tCHMADX
MCLK
MADATA[15:0]
Vcc < 4.5V 1 tOD ns
Note: When the external load capacitance = 30pF.
Address
Address Address
RD WD
Address
tCYCLE
tCHAH tCHAL
tCHMADX
tCHMADVtCHMADV
MCLK
MCSX[7:0]
MALE
MOEX
MWEX
MADATA[15:0]
MAD [24:0]
MDQM [1:0]
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ NAND Flash Mode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = -40°C to +85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit
Vcc ≥ 4.5VMNREX
Min pulse width tNREW MNREX
Vcc < 4.5V MCLK×n-3 - ns
Vcc ≥ 4.5V 20 -
Data setup →
MNREX ↑ time tDS – NRE MNREX
MADATA[15:0] Vcc < 4.5V 38 -
ns
Vcc ≥ 4.5VMNREX ↑ →
Data hold time tDH – NRE MNREX
MADATA[15:0] Vcc < 4.5V 0 -
ns
Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9
MNALE ↑ →
MNWEX delay time tALEH - NWEL MNALE
MNWEX Vcc < 4.5V MCLK×m-12 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9
MNALE ↓ →
MNWEX delay time tALEL - NWEL MNALE
MNWEX Vcc < 4.5V MCLK×m-12 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9
MNCLE ↑ →
MNWEX delay time tCLEH - NWEL MNCLE
MNWEX Vcc < 4.5V MCLK×m-12 MCLK×m+12 ns
Vcc ≥ 4.5V MCLK×m+9
MNWEX ↑ →
MNCLE delay time tNWEH - CLEL MNCLE
MNWEX Vcc < 4.5V 0 MCLK×m+12 ns
Vcc ≥ 4.5VMNWEX
Min pulse width tNWEW MNWEX
Vcc < 4.5V MCLK×n-3 - ns
Vcc ≥ 4.5V - 9 + 9
MNWEX ↓ →
Data delay time tNWEL – DV MNWEX
MADATA[15:0] Vcc < 4.5V -12 +12
ns
Vcc ≥ 4.5V MCLK×m+9
MNWEX ↑ →
Data hold time tNWEH – DX MNWEX
MADATA[15:0] Vcc < 4.5V 0 MCLK×m+12 ns
Note: When the external load capacitance = 30pF. (m=0 to 15, n=1 to 16)
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
NAND Flash Read
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
t
CYCLE
t
NREW
t
DS-NRE
t
DH-NRE
MCLK
MNREX
MADATA[15:0] Read
82
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
NAND Flash Address Write
VOL
VOL
VOH
VOH
VOH VOL
VOH
VOH
VOH
tCYCLE
tALEH-NWEL
tNWEW
tNWEH-DX
tNWEL-DV
NAND Flash Command W rite
V
OL
V
OH
V
OL
V
OL
V
OL
V
OH
V
OH
V
OL
V
OH
V
OH
V
OH
t
CYCLE
t
ALEL-NWEL
t
NWEW
t
NWEH-CLEL
t
CLEH-NWEL
t
NWEH-DX
t
NWEL-DV
MCLK
MNALE
MNCLE
MADATA[15:0]
MNWEX
Write
MCLK
MNALE
MNCLE
MADATA[15:0]
MNWEX
Write
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ External Ready Input Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit Remarks
Vcc ≥ 4.5V 19
MCLK ↑
MRDY input
setup time tRDYI MCLK
MRDY Vcc < 4.5V 37 - ns
・ When RDY is input
···
Over 2cycle
t
RDYI
・ When RDY is released
··· ···
2 cycle
t
RDYI
0.5×VCC
MCLK
Original
MOEX
MWEX
MRDY
MCLK
Extended
MOEX
MWEX
MRDY
84
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(8) Base Timer Input Timing
・ Timer input timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit Remarks
Input pulse width tTIWH
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN) - 2tCYCP - ns
t
TIWH
V
IHS
V
IHS
V
ILS
V
ILS
t
TIWL
・ Trigger input timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max
Unit Remarks
Input pulse width tTRGH
tTRGL
TIOAn/TIOBn
(when using as
TGIN) - 2tCYCP - ns
t
TRGH
V
IHS
V
IHS
V
ILS
V
ILS
t
TRGL
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see "BLOCK DIAGRAM" in this data
sheet.
ECK
TIN
TGIN
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(9) UART Timing
・ Synchronous serial (SPI = 0, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Vcc < 4.5V Vcc ≥ 4.5V
Parameter Symbol
Pin
name Conditions Min Max Min Max
Unit
Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns
SCK ↓ → SOT delay time tSLOVI SCKx
SOTx -30 +30 - 20 + 20 ns
SIN → SCK ↑ setup time tIVSHI SCKx
SINx 50 - 30 - ns
SCK ↑ → SIN hold time tSHIXI SCKx
SINx
Internal shift
clock
operation
0 - 0 - ns
Serial clock "L" pulse width tSLSH SCKx 2tcycp -
10 - 2tcycp -
10 - ns
Serial clock "H" pulse width tSHSL SCKx tcycp +
10 - tcycp +
10 - ns
SCK ↓ → SOT delay time tSLOVE SCKx
SOTx - 50 - 30 ns
SIN → SCK ↑ setup time tIVSHE SCKx
SINx 10 - 10 - ns
SCK ↑ → SIN hold time tSHIXE SCKx
SINx 20 - 20 - ns
SCK fall time tF SCKx - 5 - 5 ns
SCK rise time tR SCKx
External shift
clock
operation
- 5 - 5 ns
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "■BLOCK DIAGRAM" in this data
sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30pF.
86
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
t
SCYC
V
OH
V
OH
V
OL
V
OL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SLOVI
t
IVSHI
t
SHIXI
MS bit = 0
t
SLSH
t
SHSL
V
IH
t
F
tR
V
IH
V
OH
V
IH
V
IL
V
IL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SLOVE
t
IVSHE
t
SHIXE
MS bit = 1
SCK
SOT
SIN
SCK
SOT
SIN
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ Synchronous serial (SPI = 0, SCINV = 1) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Vcc < 4.5V Vcc ≥ 4.5V
Parameter Symbol
Pin
name Conditions Min Max Min Max
Unit
Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns
SCK ↑ → SOT delay time tSHOVI SCKx
SOTx -30 +30 - 20 + 20 ns
SIN → SCK ↓ setup time tIVSLI SCKx
SINx 50 - 30 - ns
SCK ↓ → SIN hold time tSLIXI SCKx
SINx
Internal shift
clock
operation
0 - 0 - ns
Serial clock "L" pulse width tSLSH SCKx 2tcycp -
10 - 2tcycp -
10 - ns
Serial clock "H" pulse width tSHSL SCKx tcycp +
10 - tcycp +
10 - ns
SCK ↑ → SOT delay time tSHOVE SCKx
SOTx - 50 - 30 ns
SIN → SCK ↓ setup time tIVSLE SCKx
SINx 10 - 10 - ns
SCK ↓ → SIN hold time tSLIXE SCKx
SINx 20 - 20 - ns
SCK fall time tF SCKx - 5 - 5 ns
SCK rise time tR SCKx
External shift
clock
operation
- 5 - 5 ns
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "■BLOCK DIAGRAM" in this data
sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30pF.
88
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
t
SCYC
V
OH
V
OH
V
OH
V
OL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SHOVI
t
IVSLI
t
SLIXI
MS bit = 0
tSHSL tSLSH
VIH
tF
tR
VIH
VOH
VIL
VIL VIL
VOL
VIH
VIL VIH
VIL
t
SHOVE
tIVSLE tSLIXE
MS bit = 1
SCK
SOT
SIN
SCK
SOT
SIN
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ Synchronous serial (SPI = 1, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Vcc < 4.5V Vcc ≥ 4.5V
Parameter Symbol
Pin
name Conditions Min Max Min Max
Unit
Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns
SCK ↑ → SOT delay time tSHOVI SCKx
SOTx -30 +30 - 20 + 20 ns
SIN → SCK ↓ setup time tIVSLI SCKx
SINx 50 - 30 - ns
SCK ↓→ SIN hold time tSLIXI SCKx
SINx 0 - 0 - ns
SOT → SCK ↓ delay time tSOVLI SCKx
SOTx
Internal shift
clock
operation
2tcycp -
30 - 2tcycp -
30 - ns
Serial clock "L" pulse width tSLSH SCKx 2tcycp -
10 - 2tcycp -
10 - ns
Serial clock "H" pulse width tSHSL SCKx tcycp +
10 - tcycp +
10 - ns
SCK ↑ → SOT delay time tSHOVE SCKx
SOTx - 50 - 30 ns
SIN → SCK ↓ setup time tIVSLE SCKx
SINx 10 - 10 - ns
SCK ↓→ SIN hold time tSLIXE SCKx
SINx 20 - 20 - ns
SCK fall time tF SCKx - 5 - 5 ns
SCK rise time tR SCKx
External shift
clock
operation
- 5 - 5 ns
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "■BLOCK DIAGRAM" in this data
sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30pF.
90
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
t
SOVLI
t
SCYC
t
SHOVI
V
OL
V
OL
V
OH
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSLI
t
SLIXI
MS bit = 0
tF tR
t
SLSH
t
SHSL
t
SHOVE
V
IL
V
IL
V
IH
V
IH
V
IH
V
OH
*
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSLE
t
SLIXE
MS bit = 1
*: Changes when writing to TDR register
SCK
SOT
SIN
SCK
SOT
SIN
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・ Synchronous serial (SPI = 1, SCINV = 1) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Vcc < 4.5V Vcc ≥ 4.5V
Parameter Symbol
Pin
name Conditions Min Max Min Max
Unit
Serial clock cycle time tSCYC SCKx 4tcycp - 4tcycp - ns
SCK ↓ → SOT delay time tSLOVI SCKx
SOTx -30 +30 - 20 + 20 ns
SIN → SCK ↑ setup time tIVSHI SCKx
SINx 50 - 30 - ns
SCK ↑ → SIN hold time tSHIXI SCKx
SINx 0 - 0 - ns
SOT → SCK ↑ delay time tSOVHI SCKx
SOTx
Internal shift
clock
operation
2tcycp -
30 - 2tcycp -
30 - ns
Serial clock "L" pulse width tSLSH SCKx 2tcycp -
10 - 2tcycp -
10 - ns
Serial clock "H" pulse width tSHSL SCKx tcycp +
10 - tcycp +
10 - ns
SCK ↓ → SOT delay time tSLOVE SCKx
SOTx - 50 - 30 ns
SIN → SCK ↑ setup time tIVSHE SCKx
SINx 10 - 10 - ns
SCK ↑ → SIN hold time tSHIXE SCKx
SINx 20 - 20 - ns
SCK fall time tF SCKx - 5 - 5 ns
SCK rise time tR SCKx
External shift
clock
operation
- 5 - 5 ns
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see "■BLOCK DIAGRAM" in this data
sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30pF.
92
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
t
SCYC
t
SLOVI
V
OL
V
OH
V
OH
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSHI
t
SHIXI
t
SOVHI
MS bit = 0
t
SHSL
tR t
SLSH
tF
t
SLOVE
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSHE
t
SHIXE
MS bit = 1
・ External clock (EXT = 1) : asynchronous only (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Conditions Min Max
Unit Remarks
Serial clock "L" pulse width tSLSH tcycp + 10 - ns
Serial clock "H" pulse width tSHSL tcycp + 10 - ns
SCK fall time tF - 5 ns
SCK rise time tR
CL = 30pF
- 5 ns
t
SHSL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
tR tF
t
SLSH
SCK
SOT
SIN
SCK
SOT
SIN
SCK
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(10) External Input Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max Unit Remarks
ADTG A/D converter
trigger input
FRCKx Free-run timer input
clock
ICxx
- 2tCYCP*1 - ns
Input capture
DTTIxX - 2tCYCP*1 - ns
Wave form
generator
- 2tCYCP + 100*1- ns
Input pulse width tINH,
tINL
INT00 to IN T15,
NMIX 500*2 - ns
External interrup t
NMI
*1 : tCYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode.
About the APB bus number which A/D converter, Multi-function Timer, Ex ternal interrupt is connected to,
see "BLOCK DIAGRAM" in this data sheet.
*2 : When in stop mode, in timer mode.
tINH tINL
VILS VILS VIHS VIHS
94
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(11) Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Conditions Min Max
Unit
AIN pin "H" width tAHL -
AIN pin "L" width tALL -
BIN pin "H" width tBHL -
BIN pin "L" width tBLL -
BIN rise time from
AIN pin "H" level tAUBU PC_Mo de2 or
PC_Mode3
AIN fall time from
BIN pin "H" level tBUAD PC_M o de2 or
PC_Mode3
BIN fall time from
AIN pin "L" level tADBD PC_Mode 2 or
PC_Mode3
AIN rise time from
BIN pin "L" level tBDAU PC_Mode 2 or
PC_Mode3
AIN rise time from
BIN pin "H" level tBUAU PC_M o de2 or
PC_Mode3
BIN fall time from
AIN pin "H" level tAUBD PC_M o de2 or
PC_Mode3
AIN fall time from
BIN pin "L" level tBDAD PC_Mode 2 or
PC_Mode3
BIN rise time from
AIN pin "L" level tADBU PC_Mode 2 or
PC_Mode3
ZIN pin "H" width tZHL QCR:CGSC="0"
ZIN pin "L" width tZLL QCR:CGSC="0"
AIN/BIN rise and fall time
from determined ZIN level tZABE QCR:CGSC="1"
Determined ZIN level from
AIN/BIN rise and fall time tABEZ QCR:CGSC="1"
2tCYCP* - ns
*: tCYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "BLOCK
DIAGRAM" in this data sheet.
t
AHL
t
BHL
t
BLL
t
ALL
t
AUBU
t
BUAD
t
ADBD
t
BDAU
AIN
BIN
DS706-00028-2v0-E
95
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
tBHL
tAHL
tALL
tBLL
tBUAU tAUBD tBDAD tADBU
tZHL
tZLL
t
ZABE
t
ABEZ
BIN
AIN
ZIN
ZIN
AIN/BIN
96
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(12) I2C T imin g (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Typical mode High-speed
mode
Parameter Symbol Conditions
Min Max Min Max
Unit Remarks
SCL clock frequency fSCL 0 100 0 400 kHz
(Repeated) START condition
hold time
SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs
SCLclock "L" width tLOW 4.7 - 1.3 - μs
SCLclock "H" width tHIGH 4.0 - 0.6 - μs
(Repeated) START setup time
SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs
Data hold time
SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*20 0.9*3 μs
Data setup time
SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns
STOP co ndition setup time
SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs
Bus free time between
"STOP condition" and
"START condition" tBUF
CL = 30pF,
R = (Vp/IOL)*1
4.7 - 1.3 - μs
8MHz ≤
tCYCP ≤ 40MHz 2 tCYCP*4- 2 tCYCP*4 - ns *5
40MHz <
tCYCP ≤ 60MHz 3 tCYCP*4- 3 tCYCP*4 - ns *5
Noise filter tSP
60MHz <
tCYCP ≤ 72MHz 4 tCYCP*4- 4 tCYCP*4 - ns *5
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3 : A high-speed m ode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "BLOCK DIAGRAM" in this data sheet.
To use I2C, set the peripheral bus clock at 8 MHz or more.
*5 : The number of the steps of the noise filter can be changed by register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
t
LOW
t
HDSTA
t
HDDAT
t
HIGH
t
SUDAT
t
SUSTA
t
HDSTA
t
SP
t
SUSTO
t
BUF
SDA
SCL
98
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(13) ETM Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions Min Max Unit Remarks
Vcc ≥ 4.5V 2 9
Data hold tETMH TRACECLK
TRACED[3:0] Vcc < 4.5V 2 15 ns
Vcc ≥ 4.5V - 50 MHz
TRACECLK
frequency 1/ tTRACE Vcc < 4.5V - 32 MHz
Vcc ≥ 4.5V 20 - ns
TRACECLK
cycle time tTRACE
TRACECLK
Vcc < 4.5V 31.25 - ns
Note: When the external load capacitance = 30pF.
tCYC
tETMH
tTRACE
tETMH
VOH
VOH VOH
VOH
VOH
VOL
VOL VOH
VOL
HCLK
TRACECLK
TRACED[3:0]
DS706-00028-2v0-E
99
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
(14) JTAG Timing (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Symbol Pin name Conditions
Min Max Unit Remarks
Vcc ≥ 4.5V
TMS, TDI setup
time tJTAGS TCK,
TMS, TDI Vcc < 4.5V 15 - ns
Vcc ≥ 4.5V
TMS, TDI hold time tJTAGH TCK,
TMS, TDI Vcc < 4.5V 15 - ns
Vcc ≥ 4.5V - 25
TDO delay time tJTAGD TCK,
TDO Vcc < 4.5V - 45 ns
Note: When the external load capacitance = 30pF.
V
OH
V
OH
V
OL
V
OL
V
OH
V
OL
V
OH
V
OL
t
JTAGS
t
JTAGD
t
JTAGH
TCK
TMS/TDI
TDO
100
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
5. 12-bit A/D Converter
・Electrical Characteristi cs for the A/D Converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)
Value
Parameter Pin
name Min Typ Max
Unit Remarks
Resolution - - - 12 bit
Linearity error - - 4.5 - + 4.5 LSB
Differential linearity error - - 2.5 - + 2.5 LSB
Zero transition voltage AN0 to
AN15 - 20 - + 20 mV
Full-scale transition
voltage AN0 to
AN15 AVRH - 20 - AVRH + 20 mV
AVRH = 2.7V to 5.5V
Conversion time - 1.0*1 - - μs AVcc ≥ 4.5V
*2 - - AVcc ≥ 4.5V
Sampling time Ts *2 - -
ns AVcc < 4.5V
AVcc ≥ 4.5V
Compare clock cycle*3 Tcck 50 - 2000 ns
AVcc < 4.5V
State transition time to
operation perm i ssi on Tstt 1.0 - - μs
- 0. 47 0.62 mA A/D 1unit opera t i on Power supply curren t
(analog + digital) AVCC - 0.06 25 μA When A/ D stop
- 1.1 1.96 mA A/D 1unit operation
AVRH=5.5V
Reference power supply
current
(between AVRH to AVSS) AVRH - 0.06 4 μA When A/D stop
Analog input capacity Cin - - 12.9 pF
2 AVcc ≥ 4.5V
Analog input resistance Rin - - 3.8 kΩAVcc < 4.5V
Interchannel di sparity - - - 4 LSB
Analog port input current AN0 to
AN15 - - 5 μA
Analog input voltage AN0 to
AN15 AVSS - AVRH V
Reference voltage AVRH AVSS - AVCC V
*1: Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 300ns, the value of
sampling time: 700ns (AVcc ≥ 4.5V).
Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck).
For setting*4 of sampling time and compare clock cycle, see "Chapter:12-bit A/D Converter" in "FM3
Family PERIPHERAL MANUAL Analog Macro Part ".
A/D Converter register is set at APB bus clock timing. Sampling and compare clock is set at Base clock
(HCLK).
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling ti me to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock.
Sampling clock and compare clock are set in base clock (HCLK).
About the APB bus number which A/D Converter is connected to, see "BLOCK DIAGRAM" in this data
sheet.
DS706-00028-2v0-E
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
Rext Rin
Cin
(Equation 1) Ts ≥ ( Rin + Rext ) × Cin × 9
Ts : Samplin g time
Rin : input resistance of A/D = 2kΩ at 4.5 < AVCC < 5.5
input resistance of A/D = 3.8kΩ at 2.7 < AVCC < 4.5
Cin : input capacity of A/D = 12.9pF at 2.7 < AVCC < 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
Analog
signal source
AN0 to AN15
Analog input pin Comparator
102
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
・Definition of 12-bit A/D Converter Terms
・ Resolution : Analog variation that is recognized by an A/D converter.
・ Linearity error : Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual co nversion
characteristics.
・ Differential linearity error : Deviation from the ideal value of the inpu t voltage that is required to change
the output code by 1 LSB.
VNT - {1LSB × (N - 1) + VOT}
Linearity error of digital output N = 1LSB [LSB]
V(N + 1) T - VNT
Differe ntial linearity error of digital output N = 1LSB - 1 [LSB]
VFST - VOT
1LSB = 4094
N : A/D converter digital output value.
VOT : Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Linearity error Differential linearity error
Digital output
Digital output
A
ctual conversion
characteristics Actual conversion
characteristics
Ideal characteristics
(Actually-
measured
value)
A
ctual conversion
characteristics
A
ctual conversion characteristi cs
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics (Actually-measured
value)
Analog input Analog input
(Actually-measured
value)
0x001
0x002
0x003
0x004
0xFFD
0xFFE
0xFFF
A
Vss
A
VRH
A
Vss
A
VRH
0x(N-2)
0x(N-1)
0x(N+1)
0xN
{1 LSB(N-1) + VOT}
VNT
VFST
VOT
VNT
V(N+1)T
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
6. Low-Voltage Detection Characteristics
(1) Low-Voltage Dete ction Reset (Ta = - 40°C to + 85°C)
Value
Parameter Symbol Conditions Min Typ Max Unit Remarks
Detected volta ge VD L - 2.25 2.45 2.65 V When voltage drops
Released voltage VDH - 2.30 2.50 2.70 V When voltage rises
(2) Interrupt of Low-Voltage Detection (Ta = - 40°C to + 85°C)
Value
Parameter Symbol Conditions Min Typ Max Unit Remarks
Detected volta ge VDL 2.58 2.8 3.02 V When voltage drops
Released voltage VDH SVHI = 0000 2.67 2.9 3.13 V When voltage rises
Detected volta ge VDL 2.76 3.0 3.24 V When voltage drops
Released voltage VDH SVHI = 0001 2.85 3.1 3.34 V When voltage rises
Detected volta ge VDL 2.94 3.2 3.45 V When voltage drops
Released voltage VDH SVHI = 0010 3.04 3.3 3.56 V When voltage rises
Detected volta ge VDL 3.31 3.6 3.88 V When voltage drops
Released voltage VDH SVHI = 0011 3.40 3.7 3.99 V When voltage rises
Detected volta ge VDL 3.40 3.7 3.99 V When voltage drops
Released voltage VDH SVHI = 0100 3.50 3.8 4.10 V When voltage rises
Detected volta ge VDL 3.68 4.0 4.32 V When voltage drops
Released voltage VDH SVHI = 0 111 3.77 4.1 4.42 V When voltage ri ses
Detected volta ge VDL 3.77 4.1 4.42 V When voltage drops
Released voltage VDH SVHI = 1000 3.86 4.2 4.53 V When voltage rises
Detected volta ge VDL 3.86 4.2 4.53 V When voltage drops
Released voltage VDH SVHI = 1001 3.96 4.3 4.64 V When voltage rises
LVD stabilizatio n
wait time TLVDW - - -
2240 ×
tcycp*μs
*: tCYCP indicates the APB2 bus clock cycle time.
104
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
7. MainFlash Memory Write/Erase Characteristics
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Value
Parameter Min Typ Max Unit Remarks
Large Sector 0.7 3.7
Sector erase
time Small Sector - 0.3 1.1 s Includes write time prior to internal
erase
Half word (16-bit)
write time - 12 384 μs Not including system-level overhead
time
Chip erase time - 8 38.4 s Includes write time prior to internal
erase
Erase/write cycles and data hold time
Erase/write cycles (cycle) Data hold time (year) Remarks
1,000 20*
10,000 10*
100,000 5*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C) .
8. WorkFlash Memory Write/Erase Characteristics
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Value
Parameter Min Typ Max Unit Remarks
Large Sector 0.7 3.7
Sector erase
time Small Sector - 0.3 1.1 s Includes write time prior to internal
erase
Half word (16-bit)
write time - 12 384 μs Not including system-level overhead
time
Chip erase time - 1.2 6 s Includes write time prior to internal
erase
Erase/write cycles and data hold time
Erase/write cycles (cycle) Data hold time (year) Remarks
1,000 20*
10,000 10*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C) .
DS706-00028-2v0-E
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MB9B110R Series
ORDERING INFORMATION
Part number Package
MB9BF112NPQC
MB9BF114NPQC
MB9BF115NPQC
MB9BF116NPQC
Plastic QFP 100-pin
(0.65mm pitch), (FPT-100P-M36)
MB9BF112NPMC
MB9BF114NPMC
MB9BF115NPMC
MB9BF116NPMC
Plastic LQFP 100-pin
(0.5mm pitch), (FPT-100P-M20*/M23)
MB9BF112RPMC
MB9BF114RPMC
MB9BF115RPMC
MB9BF116RPMC
Plastic LQFP 120-pin
(0.5mm pitch), (FPT-120P-M21*/M37)
MB9BF112NBGL
MB9BF114NBGL
MB9BF115NBGL
MB9BF116NBGL
Plastic PFBGA 112-pin
(0.8mm pitch), (BGA-112P-M04)
* : ES product only
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
106
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
PACKAGE DIMENSIONS
100-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 14.0 mm × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm Max
Weight 0.65 g
Code
(Reference) P-LFQFP100-14×14-0.50
100-pin plastic LQFP
(FPT-100P-M20)
(FPT-100P-M20)
C2005 -2010 F UJIT S U SEMICONDUCTOR LI MITE D F100 031S-c -3-5
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020) 0.20±0.05
(.008±.002) M
0.08(.003) 0.145±0.055
(.006±.002)
0.08(.003)
"A"
INDEX .059–.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0°~8°
0.50±0.20
(.020±.008)
(.024±.006)
0.60±0.15
0.25(.010)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
*14.00±0.10(.551±.004)SQ
Dimensio ns in mm (in ches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00028-2v0-E
107
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
100-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 14.00 mm × 14.00 mm
Lead shape Gullwing
Lead bend
direction Normal bend
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Weight 0.65 g
100-pin plastic LQFP
(FPT-100P-M23)
(FPT-100P-M23)
C2009-2010 F UJI TS U SEMICONDUCTO R LIMIT ED F1000 34S-c -3-4
16.00±0.20(.630±.008)SQ
125
51
76
75
100
0.50(.020) 0.22±0.05 M
0.08(.003)
*14.00±0.10(.551±.004)SQ
26
50
0.145±0.055
(.006±.002)
0.08(.003)
"A"
INDEX
0°~8°
0.50±0.20 0.10±0.10
(Stand off)
+.008
+0.20
(Mounting height)
-0.10
1.50
.059-.004
()
0.60±0.15 0.25(.010)
Dimensio ns in mm (in ches).
Note:The values inparenthesesare reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Details of " A" par t
(.004±.004)
(.009±.002)
(.020±.008)
(.024±.006)
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
108
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
120-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 16.0 × 16.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.88 g
Code
(Reference) P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
(FPT-120P-M21)
C2002-2010 F UJIT SU SEMI CONDUCTOR LIMIT ED F12 0033S-c -4-7
130
60
31
90 61
120
91
SQ
18.00±0.20(.709±.008)SQ
0.50(.020) 0.22±0.05
(.009±.002) M
0.08(.003)
INDEX
.006–.001
+.002
–0.03
+0.05
0.145
"A"
0.08(.003)
LEAD No.
.059 –.004
+.008
–0.10
+0.20
1.50
Details of " A" par t
(Mounting height)
0.60±0.15
(.024±.006) 0.25(.010)
(.004±.002)
0.10±0.05
(Stand off)
0~8°
*.630 –.004
+.016
–0.10
+0.40
16.00
Dimensio ns in mm (in ches).
Note: The values inparenthesesare reference values.
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00028-2v0-E
109
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
120-pin plastic LQFP Lead pitch 0.50 mm
P ackage width ×
package length 16.0 mm × 16.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm Max
Weight 0.88 g
Code
(Reference) P-LFQFP120-16 × 16-0.50
120-pin plastic LQFP
(FPT-120P-M37)
(FPT-120P-M37)
C2010 FUJ IT SU SEM ICONDUCTO R LIMIT ED F 120037S c(1 )-1-1
16.00 ± 0.10(.630 ± .004) SQ
18.00 ± 0.20(.709 ± .008) SQ
130
31
61
91 60
90
120
0.50(.020) 0.22± 0.05
(.0 09± .00 2) M
0.08(.003) ()
0.08(.003)
"A"
INDEX
.059–.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0˚~8˚
(.0 24± .00 6)
0.60± 0.15
0.25(.010)
0.10± 0.05
(.004± .002)
Details of "A" part
(Stand off)
*
LEAD No. –0.03
+0.05
0.145
–.001
+.002
.006
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
110
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
100-pin plastic QFP Lead pitch 0.65 mm
P ackage width ×
package length 14.00 mm × 20.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 3.35 mm MAX
Code
(Reference) P-QFP100-14 × 20-0.65
100-pin plastic QFP
(FPT-100P-M36)
(FPT-100P-M36)
2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1
C
130
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
(.551±.008)
17.90± 0.40
(.705±.016)
INDEX
0.65(.026) 0.32 ± 0.05
(.013±.002) M
0.13(.005)
"A"
0.17 ± 0.06
(.007 ±. 002)
0.10(.004)
Details of "A" part
(.035 ±. 006)
0.88 ± 0.15
(.031 ±. 008)
0.80 ± 0.20
0.25(.010)
3.00+0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25 ± 0.20
(.010 ±. 008)
(Stand off)
0~8°
*
*14.00±0.20
Dimensions in mm (inches).
Note: The valuesin parentheses are referencevalues.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS706-00028-2v0-E
111
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
112-ball plastic PFBGA Ball pitch 0.80 mm
Package width ×
package length 10.00 × 10.00 mm
Lead shape Soldering ball
Sealing method Plastic mold
Ball siz e Ф 0.45 mm
Mounting height 1.45 mm Max.
Weight 0.22 g
112-ball plastic PFBGA
(BGA-112P-M04)
(BGA-112P-M04)
C2003-2010 F UJ IT S U SE MICONDUCTO R LI MIT ED B11 2004S -c -2-3
10.00±0.10(.394±.004)
(.049±.008)
1.25±0.20
(Seated height)
6
F
INDEX
(INDEX AREA)
10.00±0.10
(.394±.004)
(112-Ф0.18±.004)
112-Ф0.45±010
0.35±0.10
(.014±.004)
(Stand off)
0.10(.004) S
B
A
GHJKLEDCBA
7
8
9
10
11
5
4
3
2
1
0.80(.031)
REF
REF
0.80(.031)
Ф0.08(.003) BAS
M
0.20(.008) S B
S
AS0.20(.008)
Dimensio ns in mm (in ches).
Note: The values inparenthesesare reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
112
DS706-00028-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB9B110R Series
MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page Section Change Results
5 FEATURES
External Interrupt Controller Unit Corrected the external interrupt input pin.
101
ELECTRICAL CHARACTERISTICS
5. 12-bit A/D Converter
Electrical Characteristics for the A/D
Converter
Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
106 ORDERING INFORMATION Corrected the part number.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL r3.0
114
DS706-00028-2v0-E
MB9B110R Series
FUJITSU SEMICONDUCTOR CONFIDENTIAL r3.0
DS706-00028-2v0-E
115
MB9B110R Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road,
Pudong District, Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of
any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR
assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would
result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
FUJITSU SEMICONDUCTOR CONFIDENTIAL r3.0
