NXP Semiconductors Data Sheet: Technical Data Kinetis K26 Sub-Family 180 MHz ARM(R) Cortex(R)-M4F Microcontroller. The K26 sub-family members provide greater performance, memory options up to 2 MB total flash and 256 KB of SRAM, as well as higher peripheral integration with features such as Dual USB. These devices maintain hardware and software compatibility with the existing Kinetis family. This product also offers: * Integration of a High Speed USB Physical Transceiver * Greater performance flexibility with a High Speed Run mode * Smarter peripherals with operation in Stop modes K26P169M180SF5 Rev. 4, 04/2017 MK26FN2M0VMD18 MK26FN2M0VMI18 MK26FN2M0VLQ18 MK26FN2M0CAC18R 144 MAPBGA (MD) 144 LQFP (LQ) 13 mm x 13 mm Pitch 1 20 mm x 20 mm Pitch mm 0.5 mm 169 MAPBGA (MI) 9 mm x 9 mm Pitch 0.65 mm Performance * Up to 180 MHz ARM Cortex-M4 based core with DSP instructions and Single Precision Floating Point unit 169 WLCSP (AC) 5.6 mm x 5.5 mm Pitch 0.4 mm System and Clocks * Multiple low-power modes to provide power optimization based on application requirements * Memory protection unit with multi-master protection Memories and memory expansion * 3 to 32 MHz main crystal oscillator * Up to 2 MB program flash memory on non-FlexMemory * 32 kHz low power crystal oscillator devices with 256 KB RAM * 48 MHz internal reference * Up to 1 MB program flash memory and 256 KB of Security FlexNVM on FlexMemory devices * 4 KB FlexRAM on FlexMemory devices * Hardware random-number generator * FlexBus external bus interface and SDRAM controller * Supports DES, AES, SHA accelerator (CAU) * Multiple levels of embedded flash security Analog modules Timers * Two 16-bit SAR ADCs and two 12-bit DAC * Four analog comparators (CMP) containing a 6-bit * Four Periodic interrupt timers DAC and programmable reference input * 16-bit low-power timer * Voltage reference 1.2V * Two 16-bit low-power timer PWM modules * Two 8-channel motor control/general purpose/PWM Communication interfaces timers * USB high-/full-/low-speed On-the-Go with on-chip high * Two 2-ch quad decoder/general purpose timers speed transceiver * Real-time clock * USB full-/low-speed OTG with on-chip transceiver Operating Characteristics * Two CAN, three SPI and four I2C modules * Low Power Universal Asynchronous Receiver/ * Voltage/Flash write voltage range:1.71 to 3.6 V Transmitter 0 (LPUART0) and five standard UARTs * V-Temperature range (ambient): -40 to 105C * Secure Digital Host Controller (SDHC) * C-Temperature range (ambient): -40 to 85C * I2S module Human-machine interface * Low-power hardware touch sensor interface (TSI) * General-purpose input/output NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Ordering Information 1 Part Number Memory Maximum number of I\O's Flash SRAM MK26FN2M0VMD18 2 MB 256 KB 100 MK26FN2M0VLQ18 2 MB 256 KB 100 MK26FN2M0CAC18R 2 MB 256 KB 116 MK26FN2M0VMI18 2 MB 256 KB 116 1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K26P169M180SF5RM Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document. Chip Errata The chip mask set Errata provides additional or corrective information for Kinetis_K_0N65N 1 a particular device mask set. Package drawing Package dimensions are provided in package drawings. MAPBGA 144-pin : 98ASA00222D1 QFP 144-pin: 98ASS23177W1 MAPBGA 169-pin : 98ASA00628D1 WLCSP 169-pin: 98ASA00222D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Kinetis K26 Sub-Family ARM (R) Cortex(R) -M4 Core System Memories and Memory Interfaces Clocks Internal and external watchdogs Program flash RAM Phaselocked loop Debug interfaces DSP Memory protection FlexMemory Cache Frequencylocked loop Interrupt controller Floatingpoint unit DMA Serial programming interface External bus Low/high frequency oscillators Low-leakage wakeup SDRAM controller Internal reference clocks Human-Machine Interface (HMI) Communication Interfaces Security Analog Timers CRC 16-bit ADC x2 Timers x4 (20ch) I C x4 I S x1 GPIO Random number generator Analog comparator x4 Carrier modulator transmitter UART x5 Secure Digital Xtrinsic touch-sensing interface Hardware encryption 6-bit DAC x4 Programmable delay block SPI x3 12-bit DAC x2 Periodic interrupt timers CAN x2 USB LS/FS OTG controller with transceiver Voltage reference Low power timer LPUART and Integrity 2 Independent real-time clock Low power TPM x 2 (4ch) 2 USB LS/FS/HS OTG controller with transceiver USB DCD/ USBHSDCD USB voltage regulator Figure 1. K26 Block Diagram Kinetis K26 Sub-Family, Rev. 4, 04/2017 3 NXP Semiconductors Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current operating ratings............................. 6 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................7 2.2.1 Voltage and current operating requirements.....7 2.2.2 LVD and POR operating requirements............. 8 2.2.3 Voltage and current operating behaviors.......... 9 2.2.4 Power mode transition operating behaviors......10 2.2.5 Power consumption operating behaviors.......... 12 2.2.6 EMC radiated emissions operating behaviors...17 2.2.7 Designing with radiated emissions in mind....... 18 2.2.8 Capacitance attributes...................................... 18 2.3 Switching specifications...................................................18 2.3.1 Device clock specifications............................... 18 2.3.2 General switching specifications....................... 19 2.4 Thermal specifications..................................................... 20 2.4.1 Thermal operating requirements....................... 20 2.4.2 Thermal attributes............................................. 20 3 Peripheral operating requirements and behaviors.................. 22 3.1 Core modules.................................................................. 22 3.1.1 Debug trace timing specifications..................... 22 3.1.2 JTAG electricals................................................ 23 3.2 System modules.............................................................. 26 3.3 Clock modules................................................................. 26 3.3.1 MCG specifications........................................... 26 3.3.2 IRC48M specifications...................................... 29 3.3.3 Oscillator electrical specifications..................... 30 3.3.4 32 kHz oscillator electrical characteristics.........32 3.4 Memories and memory interfaces................................... 33 3.4.1 Flash (FTFE) electrical specifications............... 33 3.4.2 EzPort switching specifications......................... 38 3.4.3 Flexbus switching specifications....................... 38 3.4.4 SDRAM controller specifications.......................41 3.5 Analog............................................................................. 44 3.5.1 ADC electrical specifications.............................44 3.5.2 CMP and 6-bit DAC electrical specifications.....48 3.5.3 12-bit DAC electrical characteristics................. 51 3.5.4 Voltage reference electrical specifications........ 54 4 NXP Semiconductors 4 5 6 7 3.6 Timers..............................................................................55 3.7 Communication interfaces............................................... 55 3.7.1 USB Voltage Regulator Electrical Specifications.................................................... 56 3.7.2 USB Full Speed Transceiver and High Speed PHY specifications............................................ 57 3.7.3 USB DCD electrical specifications.................... 57 3.7.4 CAN switching specifications............................ 58 3.7.5 DSPI switching specifications (limited voltage range)................................................................58 3.7.6 DSPI switching specifications (full voltage range)................................................................60 3.7.7 Inter-Integrated Circuit Interface (I2C) timing....61 3.7.8 UART switching specifications.......................... 63 3.7.9 Low Power UART switching specifications....... 63 3.7.10 SDHC specifications......................................... 63 3.7.11 I2S switching specifications.............................. 65 3.8 Human-machine interfaces (HMI)....................................71 3.8.1 TSI electrical specifications...............................71 Dimensions............................................................................. 71 4.1 Obtaining package dimensions....................................... 71 Pinout...................................................................................... 72 5.1 MK26 Signal Multiplexing and Pin Assignments..............72 5.2 Recommended connection for unused analog and digital pins........................................................................81 5.3 MK26 Pinouts.................................................................. 82 Ordering parts......................................................................... 86 6.1 Determining valid orderable parts....................................86 Part identification.....................................................................87 7.1 Description.......................................................................87 7.2 Format............................................................................. 87 7.3 Fields............................................................................... 87 7.4 Example...........................................................................88 8 Terminology and guidelines.................................................... 88 8.1 Definitions........................................................................ 88 8.2 Examples......................................................................... 89 8.3 Typical-value conditions.................................................. 89 8.4 Relationship between ratings and operating requirements....................................................................90 8.5 Guidelines for ratings and operating requirements..........90 9 Revision History...................................................................... 90 Kinetis K26 Sub-Family, Rev. 4, 04/2017 Ratings 1 Ratings 1.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. -- Max. * For Ctemp varian t: 1 * For Vtemp varian t :3 Unit Notes -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. Kinetis K26 Sub-Family, Rev. 4, 04/2017 5 NXP Semiconductors General 1.4 Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage -0.3 3.8 V IDD Digital supply current -- 300 mA VDIO Digital1 input voltage,including RESET_b -0.3 VDD + 0.3 V VAIO Analog1 input voltage, including EXTAL32 and XTAL32 -0.3 VDD + 0.3 V Maximum current single pin limit (digital output pins) -25 25 mA VDD - 0.3 VDD + 0.3 V ID VDDA Analog supply voltage VUSB0_DP USB0_DP input voltage -0.3 3.63 V VUSB1_DP USB1_DP input voltage -0.3 3.63 V VUSB0_DM USB0_DM input voltage -0.3 3.63 V VUSB1_DM USB1_DM input voltage -0.3 3.63 V VUSB1_VBUS USB1_VBUS detect voltage -0.3 6.0 V VREG_IN0, VREG_IN1 USB regulator input -0.3 6.0 V RTC battery supply voltage -0.3 3.8 V VBAT 1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general purpose I/O port. 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 6 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 General Input Signal High Low VIH 80% 50% 20% Midpoint1 VIL Fall Time Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V 1.71 3.6 V * 2.7 V VDD 3.6 V 0.7 x VDD -- V * 1.71 V VDD 2.7 V 0.75 x VDD -- V * 2.7 V VDD 3.6 V -- 0.35 x VDD V * 1.71 V VDD 2.7 V -- 0.3 x VDD V 0.06 x VDD -- V -5 -- mA VBAT VIH VIL RTC battery supply voltage Notes Input high voltage Input low voltage VHYS Input hysteresis IICDIO Digital1 input pin negative DC injection current (except RTC_WAKEUP pins) -- single pin 2 * VIN < VSS-0.3V IICAIO Analog1 input pin DC injection current -- single pin * VIN < VSS-0.3V (Negative current injection) IICcont Contiguous pin DC injection current --regional limit, includes sum of negative injection currents of 16 contiguous pin 2 mA -5 -- -25 -- mA Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 7 NXP Semiconductors General Table 1. Voltage and current operating requirements (continued) Symbol Description Min. Max. Unit Notes VDD VDD V 3 1.2 -- V VPOR_VBAT -- V * Negative current injection VODPU Pseudo Open drain pullup voltage level VRAM VDD voltage required to retain RAM VRFVBAT VBAT voltage required to retain the VBAT register file 1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general purpose I/O port. 2. All digital and analog I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VSS-0.3V, a current limiting resistor is required. The minimum negative DC injection current limiting resistor value is calculated as R=(-0.3-VIN)/|IICDIO| or R=(-0.3-VIN)/|IICAIO|. The actual resistor should be an order of magnitude higher to tolerate transient voltages. 3. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold -- high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds -- high range 1 VLVW1H * Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H * Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV=11) 2.92 3.00 3.08 V -- 80 -- mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range 1 VLVW1L * Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L * Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L * Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L * Level 4 falling (LVWV=11) 2.04 2.10 2.16 V -- 60 -- mV VHYSL Low-voltage inhibit reset/recover hysteresis -- low range VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s 8 NXP Semiconductors Notes Kinetis K26 Sub-Family, Rev. 4, 04/2017 General 1. Rising threshold is the sum of falling threshold and hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes 2.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Typ. Max. Unit * 2.7 V VDD 3.6 V, IOH = -10mA VDD - 0.5 -- -- V * 1.71 V VDD 2.7 V, IOH = -5mA VDD - 0.5 -- -- V * 2.7 V VDD 3.6 V, IOH = -20mA VDD - 0.5 -- -- V * 1.71 V VDD 2.7 V, IOH = -10mA VDD - 0.5 -- -- V -- -- 100 mA VBAT - 0.5 -- VBAT - 0.5 -- -- -- 100 mA -- -- 0.5 V -- -- 0.5 V -- -- 0.5 V -- -- 0.5 V -- -- 100 mA Notes Output high voltage -- normal drive pad Output high voltage -- High drive pad IOHT Output high current total for all ports VOH_RTC_WAKEUP Output high voltage-- normal drive pad * 2.7 V VBAT 3.6 V, IOH = -5 mA * 1.71 V VBAT 2.7 V, IOH = -2.5 mA IOH_RTC_WAKEUP Output high current total for RTC_WAKEUP pins VOL Output low voltage -- normal drive pad * 2.7 V VDD 3.6 V, IOL = 10 mA V V * 1.71 V VDD 2.7 V, IOL = 5 mA Output low voltage -- high drive pad * 2.7 V VDD 3.6 V, IOL = 20 mA * 1.71 V VDD 2.7 V, IOL = 10 mA IOLT Output low current total for all ports VOL_RTC_WAKEUP Output low voltage-- normal drive pad -- 0.5 * 2.7 V VBAT 3.6 V, IOL = 5 mA -- 0.5 V V * 1.71 V VBAT 2.7 V, IOL = 2.5mA IOL_RTC_WAKEUP Output low current total for RTC_WAKEUPpins IIN Input leakage current, analog and digital pins -- -- 100 mA -- 0.002 0.5 A 1 Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 9 NXP Semiconductors General Table 4. Voltage and current operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- -- 0.25 A Notes * VSS VIN VDD IOZ_RTC_WAKEUP Hi-Z (off-state) leakage current (per RTC_WAKEUP pin) RPU Internal pullup resistors 20 -- 50 k 2 RPD Internal pulldown resistors 20 -- 50 k 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD 2.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx -> RUN recovery times in the following table assume this clock configuration: * * * * * CPU and system clocks = 100MHz Bus clock = 50MHz FlexBus clock = 50 MHz Flash clock = 25 MHz MCG mode=FEI Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. * VLLS0 -> RUN * VLLS1 -> RUN * VLLS2 -> RUN * VLLS3 -> RUN * LLS2 -> RUN * LLS3 -> RUN * VLPS -> RUN * STOP -> RUN 10 NXP Semiconductors Min. Max. Unit -- 300 s -- 172 s -- 172 s -- 94 s -- 94 s -- 5.8 s -- 5.8 s -- 5.4 s -- 5.4 s Notes Kinetis K26 Sub-Family, Rev. 4, 04/2017 General Table 6. Low power mode peripheral adders -- typical value Symbol Description Temperature (C) Unit -40 25 50 70 85 1051 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 A IIREFSTEN32KH 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the z 32 kHz IRC enabled. 52 52 52 52 52 52 A IEREFSTEN4MH External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode z with the crystal enabled. 206 228 237 245 251 258 uA IEREFSTEN32K External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and Hz EREFSTEN] bits. Measured by entering all modes with the crystal enabled. nA VLLS1 440 490 540 560 570 580 VLLS3 440 490 540 560 570 580 LLS2 490 490 540 560 570 680 LLS3 490 490 540 560 570 680 VLPS 510 560 560 560 610 680 STOP 510 560 560 560 610 680 48MHz IRC 511 520 545 556 563 576 A ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 A IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. I48MIRC A 66 66 66 66 66 66 OSCERCLK (4 MHz external crystal) 214 234 246 254 260 268 IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 A IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing 366 366 366 366 366 366 A MCGIRCLK (4 MHz internal reference clock) Kinetis K26 Sub-Family, Rev. 4, 04/2017 11 NXP Semiconductors General Table 6. Low power mode peripheral adders -- typical value Symbol Description Temperature (C) -40 25 50 70 Unit 1051 85 the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 1. Applicable to LQFP and BGA packages only 2.2.5 Power consumption operating behaviors NOTE The maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma) Table 7. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Typ. Max. Unit Notes -- -- See note mA 1 Run mode current -- all peripheral clocks disabled, code executing from flash * @ 1.8V * @ 3.0V IDD_RUN Min. 2 -- 32.3 71.03 mA -- 32.4 71.81 mA Run mode current -- all peripheral clocks enabled, code executing from flash * @ 1.8V * @ 3.0V * @ 25C * @ 85C * @ 105C IDD_RUNC Run mode current in compute operation - 120 MHz core / 24 MHz flash / bus clock disabled, O code of while(1) loop executing from flash 3, 4 -- 50.5 89.58 mA -- 50.6 55.95 mA -- 60.5 79.20 mA -- 69.7 99.85 mA -- 28.5 67.74 mA 5 * at 3.0 V IDD_HSRUN Run mode current -- all peripheral clocks disabled, code executing from flash * @ 1.8V * @ 3.0V 6 -- 47.2 91.25 mA -- 47.3 91.62 mA IDD_HSRUN Run mode current -- all peripheral clocks enabled, code executing from flash 7, 4 -- 71.4 103.58 mA Table continues on the next page... 12 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 General Table 7. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit 71.5 79.13 mA 84.5 106.75 mA 93.3 115.08 mA Notes * @ 1.8V -- * @ 3.0V * @ 25C -- * @ 85C * @ 105C -- IDD_HSRUN HSRun mode current in compute operation - 168 MHz core/ 28 MHz flash / bus clock disabled, CO code of while(1) loop executing from flash at 3.0V -- 42.9 91.97 mA 5 IDD_WAIT Wait mode high frequency current at 3.0 V -- all peripheral clocks disabled -- 16.9 45.2 mA 8 IDD_WAIT Wait mode reduced frequency current at 3.0 V -- all peripheral clocks enabled -- 35 62.81 mA 8 IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks disabled -- 1.1 9.56 mA 9 IDD_VLPR Very-low-power run mode current at 3.0 V -- all peripheral clocks enabled -- 2 9.88 mA 10 -- 986 9.47 A IDD_VLPW Very-low-power wait mode current at 3.0 V -- all peripheral clocks disabled -- 0.690 9.25 mA IDD_VLPW Very-low-power wait mode current at 3.0 V -- all peripheral clocks enabled -- 1.5 10.00 mA * @ -40 to 25C -- 0.791 2.39 mA * @ 70C -- 3.8 6.91 mA * @ 85C * @ 105C -- 6.8 11.44 mA -- 13.2 18.91 mA -- 202 353.77 A -- 1400 2464.54 A -- 2700 4642.45 A -- 5100 8949.06 A -- 9.0 16.5 A -- 76.3 88.63 A -- 169.1 181.46 A -- 402 656.08 A IDD_VLPRC Very-low-power run mode current in compute operation - 4 MHz core / 1 MHz flash / bus clock O disabled, LPTMR running with 4 MHz internal reference clock * at 3.0 V 11 12 IDD_STOP Stop mode current at 3.0 V IDD_VLPS Very-low-power stop mode current at 3.0 V * @ -40 to 25C * @ 70C * @ 85C * @ 105C IDD_LLS3 Low leakage stop mode current at 3.0 V * @ -40 to 25C * @ 70C * @ 85C * @ 105C Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 13 NXP Semiconductors General Table 7. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- 5.7 9.7 A -- 41.3 55.80 -- 92.4 120.01 A -- 229 276.81 A * @ -40 to 25C -- 5.5 7.31 A * @ 70C -- 46.3 58.33 A * @ 85C * @ 105C -- 104 196.02 A -- 249 380.77 A * @ -40 to 25C -- 2.7 3.24 A * @ 70C -- 13.1 18.72 A * @ 85C * @ 105C -- 29.6 37.49 A -- 76.6 84.77 A * @ -40 to 25C -- 0.847 1.48 A * @ 70C -- 6.5 11.31 A * @ 85C * @ 105C -- 16.2 28.31 A -- 46.7 81.78 A -- 0.551 .65 A -- 6.3 7.12 A -- 17.1 20.02 A -- 49.6 53.68 A -- 0.254 0.445 A -- 6.3 10.99 A -- 15.8 27.58 A -- 48.7 85.27 A * @ -40 to 25C -- 0.19 0.22 A * @ 70C -- 0.49 0.64 A * @ 85C * @ 105C -- 1.11 1.4 A -- 2.2 3.2 A IDD_LLS2 Low leakage stop mode current at 3.0 V * @ -40 to 25C Notes A * @ 70C * @ 85C * @ 105C IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled * @ -40 to 25C * @ 70C * @ 85C * @ 105C IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled * @ -40 to 25C * @ 70C * @ 85C * @ 105C IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V Table continues on the next page... 14 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 General Table 7. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit IDD_VBAT Average current when CPU is not accessing RTC registers Notes 13 * @ 1.8V * @ -40 to 25C * @ 70C * @ 105C * @ 3.0V * @ -40 to 25C * @ 70C * @ 85C * @ 105C -- 0.68 0.8 -- 1.2 1.56 -- 3.6 5.3 A A A -- 0.81 0.96 -- 1.45 1.89 -- 2.5 3.46 -- 4.3 6.33 A A A A 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. MCG configured for PEE mode. 6. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 7. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 8. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode. 9. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 11. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for balanced. 12. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 13. Includes 32kHz oscillator current and RTC operation. 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * * * * USB regulator disabled No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFE Kinetis K26 Sub-Family, Rev. 4, 04/2017 15 NXP Semiconductors General Figure 3. Run mode supply current vs. core frequency 16 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 General Figure 4. VLPR mode supply current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 8. EMC radiated emissions operating behaviors Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15-50 23 dBV VRE2 Radiated emissions voltage, band 2 50-150 27 dBV VRE3 Radiated emissions voltage, band 3 150-500 28 dBV VRE4 Radiated emissions voltage, band 4 500-1000 14 dBV IEC level 0.15-1000 K -- VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic Kinetis K26 Sub-Family, Rev. 4, 04/2017 17 NXP Semiconductors General application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 C, fOSC = 12 MHz (crystal), fSYS = MHz, fBUS = MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. Go to nxp.com 2. Perform a keyword search for "EMC design." 2.2.8 Capacitance attributes Table 9. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins -- 7 pF CIN_D Input capacitance: digital pins -- 7 pF 2.3 Switching specifications 2.3.1 Device clock specifications Table 10. Device clock specifications Symbol Description Min. Max. Unit -- 180 MHz Notes High Speed run mode fSYS System and core clock Normal run mode (and High Speed run mode unless otherwise specified above) fSYS fSYS_USBHS fBUS FB_CLK fFLASH System and core clock -- 120 MHz System and core clock when Full Speed USB in operation 20 -- MHz System and core clock when High Speed USB in operation 100 -- MHz Bus clock -- 60 MHz FlexBus clock -- 60 MHz Flash clock -- 28 MHz Table continues on the next page... 18 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 General Table 10. Device clock specifications (continued) Symbol Description fLPTMR LPTMR clock VLPR Min. Max. Unit -- 25 MHz mode1 fSYS System and core clock -- 4 MHz fBUS Bus clock -- 4 MHz FlexBus clock -- 4 MHz fFLASH Flash clock -- 1 MHz fERCLK External reference clock -- 16 MHz LPTMR clock -- 25 MHz -- 8 MHz FB_CLK fLPTMR_pin Notes fFlexCAN_ERCLK FlexCAN external reference clock fI2S_MCLK I2S master clock -- 12.5 MHz fI2S_BCLK I2S bit clock -- 4 MHz 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, timers, and I2C signals. Table 11. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) -- Asynchronous path 100 -- ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) -- Asynchronous path 50 -- ns 3 External reset pulse width (digital glitch filter disabled) 100 -- ns 3 Mode select (EZP_CS) hold time after reset deassertion 2 -- Bus clock cycles Port rise and fall time (high drive strength) 4 * Slew enabled * 1.71 VDD 2.7V -- 25 ns * 2.7 VDD 3.6V -- 15 ns * Slew disabled Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 19 NXP Semiconductors General Table 11. General switching specifications (continued) Symbol Description Min. Max. Unit * 1.71 VDD 2.7V -- 7 ns * 2.7 VDD 3.6V -- 7 ns Port rise and fall time (low drive strength) Notes 5 * Slew enabled * 1.71 VDD 2.7V -- 25 ns * 2.7 VDD 3.6V -- 15 ns * 1.71 VDD 2.7V -- 7 ns * 2.7 VDD 3.6V -- 7 ns * Slew disabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 12. Thermal operating requirements Symbol Description Min. Max. TJ Die junction temperature * For BGA and LQFP package -40 125 TJ Die junction temperature * For CSP package -40 95 TA Ambient temperature * For BGA and LQFP package -40 105 TA Ambient temperature * For CSP package -40 85 Unit Notes C C C 1 C 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + RJA x chip power dissipation. 20 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 General 2.4.2 Thermal attributes Board type Symbol Descripti 144 LQFP 144 169 on MAPBGA MAPBGA 169 WLCSP Unit Notes Singlelayer (1s) RJA Thermal 45 resistance, junction to ambient (natural convection) 48 38 48.3 C/W 1 Four-layer (2s2p) RJA Thermal 36 resistance, junction to ambient (natural convection) 29 21.9 24 C/W 1 Singlelayer (1s) RJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 36 38 30 39.8 C/W 1 Four-layer (2s2p) RJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 30 25 18.6 19.5 C/W 1 -- RJB Thermal resistance, junction to board 24 16 14.4 21.4 C/W 2 -- RJC Thermal resistance, junction to case 9 9 8.2 0.1 C/W 3 -- JT Thermal 2 characteriz ation parameter, junction to package top outside center (natural convection) 2 0.2 0.2 C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. Kinetis K26 Sub-Family, Rev. 4, 04/2017 21 NXP Semiconductors Peripheral operating requirements and behaviors 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 Debug trace timing specifications Table 13. Debug trace operating behaviors Symbol Description Min. Max. Unit Tcyc Clock period Frequency dependent MHz Twl Low pulse width 2 -- ns Twh High pulse width 2 -- ns Tr Clock and data rise time -- 3 ns Tf Clock and data fall time -- 3 ns Ts Data setup 1.5 -- ns Th Data hold 1.0 -- ns TRACECLK Tr Tf Twh Twl Tcyc Figure 5. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 6. Trace data specifications 22 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 3.1.2 JTAG electricals Table 14. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 25 * Serial Wire Debug 0 50 1/J1 -- ns * Boundary Scan 50 -- ns * JTAG and CJTAG 20 -- ns * Serial Wire Debug 10 -- ns J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 2.0 -- ns J7 TCLK low to boundary scan output data valid -- 28 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1 -- ns J11 TCLK low to TDO data valid -- 19 ns J12 TCLK low to TDO high-Z -- 17 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns Unit J2 TCLK cycle period J3 TCLK clock pulse width Table 15. JTAG full voltage range electricals Symbol J1 Description Min. Max. Operating voltage 1.71 3.6 TCLK frequency of operation V MHz * Boundary Scan 0 10 * JTAG and CJTAG 0 20 * Serial Wire Debug 0 40 1/J1 -- ns 50 -- ns J2 TCLK cycle period J3 TCLK clock pulse width * Boundary Scan Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 23 NXP Semiconductors Peripheral operating requirements and behaviors Table 15. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit * JTAG and CJTAG 25 -- ns * Serial Wire Debug 12.5 -- ns J4 TCLK rise and fall times -- 3 ns J5 Boundary scan input data setup time to TCLK rise 20 -- ns J6 Boundary scan input data hold time after TCLK rise 2.0 -- ns J7 TCLK low to boundary scan output data valid -- 30.6 ns J8 TCLK low to boundary scan output high-Z -- 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 -- ns J10 TMS, TDI input data hold time after TCLK rise 1.0 -- ns J11 TCLK low to TDO data valid -- 19.0 ns J12 TCLK low to TDO high-Z -- 17.0 ns J13 TRST assert time 100 -- ns J14 TRST setup time (negation) to TCLK high 8 -- ns J2 J3 J3 TCLK (input) J4 J4 Figure 7. Test clock input timing 24 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 8. Boundary scan (JTAG) timing TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing Kinetis K26 Sub-Family, Rev. 4, 04/2017 25 NXP Semiconductors Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 10. TRST timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 16. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C -- 32.768 -- kHz fints_t Internal reference frequency (slow clock) -- user trimmed 31.25 -- 39.0625 kHz -- 20 -- A fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM and SCFTRIM -- 0.3 0.6 %fdco 1 fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using SCTRIM only -- 0.2 0.5 %fdco 1 Iints Internal reference (slow clock) current fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature -- 0.5 2 %fdco 1 fdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70C -- 0.3 1.5 %fdco 1 fintf_ft Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25C -- 4 -- MHz fintf_t Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz Internal reference (fast clock) current -- 25 -- A Iintf Table continues on the next page... 26 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 16. MCG specifications (continued) Symbol floc_low Description Loss of external clock minimum frequency -- RANGE = 00 Min. Typ. Max. Unit (3/5) x fints_t -- -- kHz (16/5) x fints_t -- -- kHz Notes ext clk freq: above (3/5)fint never reset ext clk freq: between (2/5)fint and (3/5)fint maybe reset (phase dependency) ext clk freq: below (2/5)fint always reset floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 ext clk freq: above (16/5)fint never reset ext clk freq: between (15/5)fint and (16/5)fint maybe reset (phase dependency) ext clk freq: below (15/5)fint always reset FLL ffll_ref FLL reference frequency range 31.25 -- 39.0625 kHz fdco_ut DCO output frequency range -- untrimmed 16.0 23.04 26.66 MHz 32.0 46.08 53.32 48.0 69.12 79.99 64.0 92.16 106.65 18.3 26.35 30.50 36.6 52.70 60.99 54.93 79.09 91.53 73.23 105.44 122.02 Low range 2 (DRS=00, DMX32=0) 640 x fints_ut Mid range (DRS=01, DMX32=0) 1280 x fints_ut Mid-high range (DRS=10, DMX32=0) 1920 x fints_ut High range (DRS=11, DMX32=0) 2560 x fints_ut Low range (DRS=00, DMX32=1) 732 x fints_ut Mid range (DRS=01, DMX32=1) 1464 x fints_ut Mid-high range (DRS=10, DMX32=1) 2197 x fints_ut High range (DRS=11, DMX32=1) 2929 x fints_ut Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 27 NXP Semiconductors Peripheral operating requirements and behaviors Table 16. MCG specifications (continued) Symbol fdco Description DCO output frequency range Low range (DRS=00) Min. Typ. Max. Unit Notes 20 20.97 25 MHz 3, 4 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz -- 23.99 -- MHz -- 47.97 -- MHz -- 71.99 -- MHz -- 95.98 -- MHz -- 180 -- -- 150 -- -- -- 1 ms 8 -- 16 MHz 640 x ffll_ref Mid range (DRS=01) 1280 x ffll_ref Mid-high range (DRS=10) 1920 x ffll_ref High range (DRS=11) 2560 x ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 5, 6 732 x ffll_ref Mid range (DRS=01) 1464 x ffll_ref Mid-high range (DRS=10) 2197 x ffll_ref High range (DRS=11) 2929 x ffll_ref Jcyc_fll FLL period jitter * fDCO = 48 MHz * fDCO = 98 MHz tfll_acquire FLL target frequency acquisition time ps 7 PLL fpll_ref PLL reference frequency range fvcoclk_2x VCO output frequency fvcoclk PLL output frequency fvcoclk_90 180 90 PLL quadrature output frequency Ipll PLL operating current * VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 23) Ipll PLL operating current * VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) Jcyc_pll Jacc_pll 90 -- -- -- 360 180 180 MHz MHz MHz -- 2.8 -- mA -- 3.6 -- mA PLL period jitter (RMS) 8 8 9 * fvco = 180 MHz -- 100 -- ps * fvco = 360 MHz -- 75 -- ps PLL accumulated jitter over 1s (RMS) 9 * fvco = 180 MHz -- 600 -- ps * fvco = 360 MHz -- 300 -- ps Table continues on the next page... 28 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 16. MCG specifications (continued) Symbol Dunl tpll_lock Description Lock exit frequency tolerance Min. Typ. Max. Unit 4.47 -- 5.97 % Lock detector detection time -- 10-6 -- 150 x + 1075(1/ fpll_ref) s Notes 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 IRC48M specifications Table 17. IRC48M specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDD48M Supply current -- 520 -- A firc48m Internal reference frequency -- 48 -- MHz firc48m_ol_lv Open loop total deviation of IRC48M frequency at low voltage (VDD=1.71V-1.89V) over full temperature * Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]= 0) * Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]= 1) firc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over 0--70C * Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]= 1) firc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over full temperature Notes 1 -- 0.4 1.0 -- 0.5 1.5 %firc48m 1 -- 0.2 0.5 %firc48m 1 -- 0.4 1.0 %firc48m Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 29 NXP Semiconductors Peripheral operating requirements and behaviors Table 17. IRC48M specifications (continued) Symbol Description Min. Typ. Max. Unit Notes 2 * Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]= 1) firc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature -- -- 0.1 %fhost Jcyc_irc48m Period Jitter (RMS) -- 35 150 ps Startup time -- 2 3 s tirc48mst 3 1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard deviation (mean 3 sigma) 2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings: * USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or * MCG_C7[OSCSEL]=10, or * SIM_SOPT2[PLLFLLSEL]=11 3.3.3 Oscillator electrical specifications 3.3.3.1 Oscillator DC electrical specifications Table 18. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC IDDOSC Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 600 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Supply current -- high gain mode (HGO=1) 1 * 32 kHz -- 7.5 -- A * 4 MHz -- 500 -- A * 8 MHz (RANGE=01) -- 650 -- A * 16 MHz -- 2.5 -- mA -- 3.25 -- mA Table continues on the next page... 30 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 18. Oscillator DC electrical specifications (continued) Symbol Description * 24 MHz Min. Typ. Max. Unit -- 4 -- mA Notes * 32 MHz Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) 5 Vpp 1. 2. 3. 4. 5. VDD=3.3 V, Temperature =25 C, Internal capacitance = 20 pf See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. Kinetis K26 Sub-Family, Rev. 4, 04/2017 31 NXP Semiconductors Peripheral operating requirements and behaviors 3.3.3.2 Symbol Oscillator frequency specifications Table 19. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency -- lowfrequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- highfrequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- 750 -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- 250 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.3.4 32 kHz oscillator electrical characteristics 3.3.4.1 32 kHz oscillator DC electrical specifications Table 20. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 -- 3.6 V -- 100 -- M RF Internal feedback resistor Table continues on the next page... 32 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 20. 32kHz oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Cpara Parasitical capacitance of EXTAL32 and XTAL32 -- 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation -- 0.6 -- V 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.4.2 Symbol 32 kHz oscillator frequency specifications Table 21. 32 kHz oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal -- 32.768 -- kHz Crystal start-up time -- 1000 -- ms 1 fec_extal32 Externally provided input clock frequency -- 32.768 -- kHz 2 vec_extal32 Externally provided input clock amplitude 700 -- VBAT mV 2, 3 fosc_lo tstart Description Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 3.4 Memories and memory interfaces 3.4.1 Flash (FTFE) electrical specifications This section describes the electrical characteristics of the FTFE module. 3.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 22. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm8 thversscr Program Phrase high-voltage time -- 7.5 18 s Erase Flash Sector high-voltage time -- 13 113 ms 1 thversblk256k Erase Flash Block high-voltage time for 256 KB -- 208 1808 ms 1 thversblk512k Erase Flash Block high-voltage time for 512 KB -- 416 3616 ms 1 Kinetis K26 Sub-Family, Rev. 4, 04/2017 Notes 33 NXP Semiconductors Peripheral operating requirements and behaviors 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Symbol Flash timing specifications -- commands Table 23. Flash command timing specifications Description Min. Typ. Max. Unit Notes Read 1s Block execution time trd1blk256k * 256 KB data flash -- -- 1.0 ms trd1blk512k * 512 KB program flash -- -- 1.8 ms trd1sec4k Read 1s Section execution time (4 KB flash) -- -- 100 s 1 tpgmchk Program Check execution time -- -- 95 s 1 trdrsrc Read Resource execution time -- -- 40 s 1 tpgm8 Program Phrase execution time -- 90 150 s Erase Flash Block execution time 2 tersblk256k * 256 KB data flash -- 220 1850 ms tersblk512k * 512 KB program flash -- 435 3700 ms Erase Flash Sector execution time -- 15 115 ms Program Section execution time (1 KB flash) -- 5 -- ms tersscr tpgmsec1k 2 Read 1s All Blocks execution time trd1allx * FlexNVM devices -- -- 5.9 ms trd1alln * Program flash only devices -- -- 6.7 ms Read Once execution time -- -- 30 s trdonce tpgmonce 1 Program Once execution time -- 90 -- s tersall Erase All Blocks execution time -- 1750 14,800 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 Swap Control execution time tswapx01 * control code 0x01 -- 200 -- s tswapx02 * control code 0x02 -- 90 150 s tswapx04 * control code 0x04 -- 90 150 s tswapx08 * control code 0x08 -- -- 30 s tswapx10 * control code 0x10 -- 90 150 s Program Partition for EEPROM execution time tpgmpart32k * 32 KB EEPROM backup -- 70 -- ms tpgmpart256k * 256 KB EEPROM backup -- 78 -- ms * Control Code 0xFF -- 70 -- s tsetram32k * 32 KB EEPROM backup -- 0.8 1.2 ms tsetram64k * 64 KB EEPROM backup -- 1.3 1.9 ms Set FlexRAM Function execution time: tsetramff Table continues on the next page... 34 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 23. Flash command timing specifications (continued) Min. Typ. Max. Unit tsetram128k Symbol Description * 128 KB EEPROM backup -- 2.4 3.1 ms tsetram256k * 256 KB EEPROM backup -- 4.5 5.5 ms Notes Byte-write to FlexRAM execution time: teewr8b32k * 32 KB EEPROM backup -- 385 1700 s teewr8b64k * 64 KB EEPROM backup -- 475 2000 s teewr8b128k * 128 KB EEPROM backup -- 650 2350 s teewr8b256k * 256 KB EEPROM backup -- 1000 3250 s 16-bit write to FlexRAM execution time: teewr16b32k * 32 KB EEPROM backup -- 385 1700 s teewr16b64k * 64 KB EEPROM backup -- 475 2000 s teewr16b128k * 128 KB EEPROM backup -- 650 2350 s teewr16b256k * 256 KB EEPROM backup -- 1000 3250 s -- 360 1500 s teewr32bers 32-bit write to erased FlexRAM location execution time 32-bit write to FlexRAM execution time: teewr32b32k * 32 KB EEPROM backup -- 630 2000 s teewr32b64k * 64 KB EEPROM backup -- 810 2250 s teewr32b128k * 128 KB EEPROM backup -- 1200 2650 s teewr32b256k * 256 KB EEPROM backup -- 1900 3500 s 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 24. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation -- 3.5 7.5 mA Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Reliability specifications Table 25. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 35 NXP Semiconductors Peripheral operating requirements and behaviors Table 25. NVM reliability specifications (continued) Min. Typ.1 Max. Unit tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years nnvmcycp Cycling endurance 10 K 50 K -- cycles tnvmretd10k Data retention after up to 10 K cycles 5 50 -- years tnvmretd1k Data retention after up to 1 K cycles 20 100 -- years nnvmcycd Cycling endurance 10 K 50 K -- cycles Symbol Description Notes 2 Data Flash 2 FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance 5 50 -- years tnvmretee10 Data retention up to 10% of write endurance 20 100 -- years 20 K 50 K -- cycles nnvmcycee Cycling endurance for EEPROM backup Write endurance 2 3 nnvmwree16 * EEPROM backup to FlexRAM ratio = 16 140 K 400 K -- writes nnvmwree128 * EEPROM backup to FlexRAM ratio = 128 1.26 M 3.2 M -- writes nnvmwree512 * EEPROM backup to FlexRAM ratio = 512 5M 12.8 M -- writes nnvmwree2k * EEPROM backup to FlexRAM ratio = 2,048 20 M 50 M -- writes nnvmwree8k * EEPROM backup to FlexRAM ratio = 8,192 80 M 200 M -- writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40C Tj 125C. 3. Write endurance represents the number of writes to each FlexRAM location at -40C Tj 125C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance. 3.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFE to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. 36 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Writes_subsystem = EEPROM - 2 x EEESPLIT x EEESIZE EEESPLIT x EEESIZE x Write_efficiency x n nvmcycee where Average Writes per FlexRAM Location * Writes_subsystem -- minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) * EEPROM -- allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command * EEESPLIT -- FlexRAM split factor for subsystem; entered with the Program Partition command * EEESIZE -- allocated FlexRAM based on DEPART; entered with the Program Partition command * Write_efficiency -- * 0.25 for 8-bit writes to FlexRAM * 0.50 for 16-bit or 32-bit writes to FlexRAM * nnvmcycee -- EEPROM-backup cycling endurance 16/32-bit 8-bit Ratio of EEPROM Backup to FlexRAM Figure 11. EEPROM backup writes to FlexRAM Kinetis K26 Sub-Family, Rev. 4, 04/2017 37 NXP Semiconductors Peripheral operating requirements and behaviors 3.4.2 EzPort switching specifications Table 26. EzPort full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V EP1 EZP_CK frequency of operation (all commands except READ) -- fSYS/2 MHz EP1a EZP_CK frequency of operation (READ command) -- fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK -- ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 -- ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 -- ns EP5 EZP_D input valid to EZP_CK high (setup) 2 -- ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 -- ns EP7 EZP_CK low to EZP_Q output valid -- 14 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 -- ns EP9 EZP_CS negation to EZP_Q tri-state -- 12 ns EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 12. EzPort Timing Diagram 38 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 3.4.3 Flexbus switching specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 27. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- FB_CLK MHz 1/FB_CLK -- ns FB1 Clock period FB2 Address, data, and control output valid -- 11.8 ns FB3 Address, data, and control output hold 1.0 -- ns FB4 Data and FB_TA input setup 11.9 -- ns FB5 Data and FB_TA input hold 0.0 -- ns Notes 1 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 28. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V -- FB_CLK MHz 1/FB_CLK -- ns Frequency of operation FB1 Clock period FB2 Address, data, and control output valid -- 12.6 ns FB3 Address, data, and control output hold 1.0 -- ns FB4 Data and FB_TA input setup 12.5 -- ns FB5 Data and FB_TA input hold 0 -- ns Notes 1 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Kinetis K26 Sub-Family, Rev. 4, 04/2017 39 NXP Semiconductors Peripheral operating requirements and behaviors Read Timing Parameters S0 S1 S2 S3 S0 FB1 FB_CLK FB5 FB_A[Y] Address FB4 FB2 FB_D[X] FB3 Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn electricals_read.svg FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ S0 S1 S2 S3 S0 Figure 13. FlexBus read timing diagram 40 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Write Timing Parameters FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 electricals_write.svg FB4 TSIZ Figure 14. FlexBus write timing diagram 3.4.4 SDRAM controller specifications Following figure shows SDRAM read cycle. Kinetis K26 Sub-Family, Rev. 4, 04/2017 41 NXP Semiconductors Peripheral operating requirements and behaviors 0 1 D0 2 3 4 5 6 7 8 9 10 11 12 13 CLKOUT D3 D1 Row A[23:0] Column D4 SRAS D2 SCAS1 D4 DRAMW D5 D[31:0]2 D6 SDRAM_CS[1:0] D4 BS[3:0] ACTV NOP READ NOP PRE DACR[CASL] = 2 D[31:16] for 144-pin packages 1 2 Figure 15. SDRAM read timing diagram Table 29. SDRAM Timing (Full voltage range) NUM Characteristic 1 Symbol MIn Max Operating voltage 1.71 3.6 V -- CLKOUT MHz 1/CLKOUT -- ns 2 - 11.2 ns 11.1 ns 1.0 - ns Frequency of operation Unit D0 Clock period D1 CLKOUT high to SDRAM address valid tCHDAV D2 CLKOUT high to SDRAM control valid tCHDCV D3 CLKOUT high to SDRAM address invalid tCHDAI D4 CLKOUT high to SDRAM control invalid tCHDCI 1.0 - ns D5 SDRAM data valid to CLKOUT high tDDVCH 12.0 - ns D6 CLKOUT high to SDRAM data invalid tCHDDI 1.0 - ns D73 CLKOUT high to SDRAM data valid tCHDDVW - 12.0 ns D83 CLKOUT high to SDRAM data invalid tCHDDIW 1.0 - ns 1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins. 42 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz 3. D7 and D8 are for write cycles only. Table 30. SDRAM Timing (Limited voltage range) NUM Characteristic 1 Symbol MIn Max Operating voltage 2.7 3.6 V Frequency of operation -- CLKOUT MHz 1/CLKOUT -- ns 2 - 11.1 ns 11.1 ns Unit D0 Clock period D1 CLKOUT high to SDRAM address valid tCHDAV D2 CLKOUT high to SDRAM control valid tCHDCV D3 CLKOUT high to SDRAM address invalid tCHDAI 1.0 - ns D4 CLKOUT high to SDRAM control invalid tCHDCI 1.0 - ns D5 SDRAM data valid to CLKOUT high tDDVCH 11.3 - ns D6 CLKOUT high to SDRAM data invalid tCHDDI 1.0 - ns D73 CLKOUT high to SDRAM data valid tCHDDVW - 11.1 ns D83 CLKOUT high to SDRAM data invalid tCHDDIW 1.0 - ns 1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins. 2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz 3. D7 and D8 are for write cycles only. Following figure shows an SDRAM write cycle. Kinetis K26 Sub-Family, Rev. 4, 04/2017 43 NXP Semiconductors Peripheral operating requirements and behaviors 0 D0 1 2 3 4 5 6 7 8 9 10 11 12 CLKOUT D3 D1 Row A[23:0] Column SRAS D2 SCAS1 D4 DRAMW D7 D[31:0]2 D8 SDRAM_CS[1:0] D2 D4 D4 BS[3:0] D4 ACTV NOP WRITE NOP PALL DACR[CASL]=2 D[31:16] for 144-pin packages 1 2 Figure 16. SDRAM write timing diagram 3.5 Analog 3.5.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 31 and Table 32 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 44 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 3.5.1.1 16-bit ADC operating conditions Table 31. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 -- 3.6 V -- VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage * 16-bit differential mode VREFL -- 31/32 * VREFH V -- * All other modes VREFL -- * 16-bit mode -- 8 10 pF -- * 8-bit / 10-bit / 12-bit modes -- 4 5 -- 2 5 k -- -- -- 5 k 3 CADIN RADIN RAS Input capacitance Input series resistance Analog source resistance (external) 13-bit / 12-bit modes VREFH fADCK < 4 MHz fADCK ADC conversion 13-bit mode clock frequency 1.0 -- 24 MHz 4 fADCK ADC conversion 16-bit mode clock frequency 2.0 -- 12.0 MHz 4 Crate ADC conversion 13-bit modes rate No ADC hardware averaging 20.000 -- 1200 kS/s 37.037 -- 461.467 kS/s 5 Continuous conversions enabled, subsequent conversion time Crate ADC conversion 16-bit mode rate No ADC hardware averaging 5 Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Kinetis K26 Sub-Family, Rev. 4, 04/2017 45 NXP Semiconductors Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 17. ADC input impedance equivalency diagram 3.5.1.2 16-bit ADC electrical characteristics Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description Conditions1 IDDA_ADC Supply current ADC asynchronous clock source fADACK Sample Time TUE DNL INL Min. Typ.2 Max. Notes 0.215 -- 1.7 mA 3 * ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz * ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK * ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz * ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 Differential nonlinearity * 12-bit modes -- 0.7 -1.1 to +1.9 * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 Integral non-linearity Unit -0.3 to 0.5 -2.7 to +1.9 Table continues on the next page... 46 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1 Min. Typ.2 Max. -- 0.5 -0.7 to +0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 * 16-bit modes -- -1 to 0 -- * 13-bit modes -- -- 0.5 * <12-bit modes EFS EQ ENOB Full-scale error Quantization error Effective number of bits Unit Notes LSB4 VADIN = VDDA5 LSB4 16-bit differential mode 6 * Avg = 32 12.8 14.5 * Avg = 4 11.9 13.8 -- -- bits bits 16-bit single-ended mode * Avg = 32 * Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode * Avg = 32 12.2 13.9 11.4 13.1 -- -- 6.02 x ENOB + 1.76 bits bits dB dB -- -94 7 -- dB 16-bit single-ended mode * Avg = 32 SFDR Spurious free dynamic range -- -85 82 95 16-bit differential mode * Avg = 32 16-bit single-ended mode 78 -- -- dB -- dB 7 90 * Avg = 32 EIL Input leakage error IIn x RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device VTEMP25 Temp sensor voltage 25 C 1.55 1.62 1.69 mV/C 8 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. Kinetis K26 Sub-Family, Rev. 4, 04/2017 47 NXP Semiconductors Peripheral operating requirements and behaviors 4. 5. 6. 7. 8. 1 LSB = (VREFH - VREFL)/2N ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 18. Typical ENOB vs. ADC_CLK for 16-bit differential mode Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 ENOB 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 Averaging of 4 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 19. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 48 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 3.5.2 CMP and 6-bit DAC electrical specifications Table 33. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VH Analog comparator hysteresis1 VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns -- -- 40 s -- 7 -- A Analog comparator initialization IDAC6b delay2 6-bit DAC current adder (enabled) INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Kinetis K26 Sub-Family, Rev. 4, 04/2017 49 NXP Semiconductors Peripheral operating requirements and behaviors 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 50 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.5.3 12-bit DAC electrical characteristics 3.5.3.1 Symbol 12-bit DAC operating requirements Table 34. 12-bit DAC operating requirements Desciption VDDA Supply voltage VDACR Reference voltage Min. Max. Unit 3.6 V 1.13 3.6 V 1 2 CL Output load capacitance -- 100 pF IL Output load current -- 1 mA Notes 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. Kinetis K26 Sub-Family, Rev. 4, 04/2017 51 NXP Semiconductors Peripheral operating requirements and behaviors 3.5.3.2 Symbol 12-bit DAC operating behaviors Table 35. 12-bit DAC operating behaviors Description IDDA_DACL Supply current -- low-power mode Min. Typ. Max. Unit -- -- 150 A -- -- 700 A Notes P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode -- 100 200 s 1 tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode -- 15 30 s 1 tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and high-speed mode -- 0.7 1 s 1 Vdacoutl DAC output voltage range low -- highspeed mode, no load, DAC set to 0x000 -- -- 100 mV Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF VDACR -100 -- VDACR mV INL Integral non-linearity error -- high speed mode -- -- 8 LSB 2 DNL Differential non-linearity error -- VDACR > 2 V -- -- 1 LSB 3 DNL Differential non-linearity error -- VDACR = VREF_OUT -- -- 1 LSB 4 -- 0.4 0.8 %FSR 5 Gain error -- 0.1 0.6 %FSR 5 Power supply rejection ratio, VDDA 2.4 V 60 -- 90 dB TCO Temperature coefficient offset voltage -- 3.7 -- V/C TGE Temperature coefficient gain error -- 0.000421 -- %FSR/C AC Offset aging coefficient -- -- 100 V/yr Rop Output resistance (load = 3 k) -- -- 250 SR Slew rate -80h F7Fh 80h VOFFSET Offset error EG PSRR 1. 2. 3. 4. 5. V/s * High power (SPHP) 1.2 1.7 -- * Low power (SPLP) 0.05 0.12 -- -- -- -80 CT Channel to channel cross talk BW 3dB bandwidth 6 dB kHz * High power (SPHP) 550 -- -- * Low power (SPLP) 40 -- -- Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV 52 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 22. Typical INL error vs. digital code Kinetis K26 Sub-Family, Rev. 4, 04/2017 53 NXP Semiconductors Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 25 -40 55 85 105 125 Temperature C Figure 23. Offset at half scale vs. temperature 3.5.4 Voltage reference electrical specifications Table 36. VREF full-range operating requirements Symbol Description VDDA Supply voltage TA Temperature CL Output load capacitance Min. Max. Unit 3.6 V Operating temperature range of the device C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. 54 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 37. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.190 1.195 1.200 V 1 Vout Voltage reference output -- factory trim 1.1584 -- 1.2376 V 1 Vout Voltage reference output -- user trim 1.193 -- 1.197 V 1 Vstep Voltage reference trim step -- 0.5 -- mV 1 Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) -- -- 80 mV 1 Ac Aging coefficient -- -- 400 uV/yr -- Ibg Bandgap only current -- -- 80 A 1 V 1, 2 VLOAD Load regulation * current = 1.0 mA Tstup Buffer startup time Tchop_osc_st Internal bandgap start-up delay with chop oscillator enabled up Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) -- 200 -- -- -- 100 s -- -- 35 ms -- -- 2 -- mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 38. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 50 C Notes Table 39. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. Max. Unit 1.173 1.225 V Notes 3.6 Timers See General switching specifications. 3.7 Communication interfaces Kinetis K26 Sub-Family, Rev. 4, 04/2017 55 NXP Semiconductors Peripheral operating requirements and behaviors 3.7.1 USB Voltage Regulator Electrical Specifications Table 40. USB VREG electrical specifications Symbol VREG_IN0 Description Min. Typ.1 Max. Unit Notes Regulator selectable input supply voltages 2.7 -- 5.5 V 2 Quiescent current -- Run mode, load current equal zero, input supply (VREG_IN*) > 3.6 V -- VREG_IN1 IDDon VREG_IN0 A -- VREG_IN1 -- 157 -- 157 IDDstby VREG_IN0 Quiescent current -- Standby mode, load current equal zero 2 -- 2 -- -- 680 -- -- 920 -- -- -- A VREG_IN1 IDDoff VREG_IN0 Quiescent current -- Shutdown mode * VREG_IN*= 5.0 V and temperature=25 C VREG_IN1 nA ILOADrun Maximum load current -- Run mode -- -- 150 mA ILOADstby Maximum load current -- Standby mode -- -- 1 mA 300 -- -- mV 3 3.3 3.6 V 2.1 2.8 3.6 V 1.76 2.2 8.16 F 1 -- 100 m VDROPOUT Regulator drop-out voltage -- Run mode at maximum load current with inrush current limit disabled VREG_OUT Regulator programmable output target voltage -- Selected input supply > programmed output target voltage + VDROPOUT 3 4 * Run mode * Standby mode COUT External output capacitor ESR External output capacitor equivalent series resistance ILIM Short circuit current -- 350 -- mA 5 IINRUSH Inrush current limit 40 -- 100 mA 6, 7, 8, 9, 10 1. Typical values assume the selected input supply is 5.0 V, Temp = 25 C unless otherwise stated. 2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V. 3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on USB operation and device power dissipation limits. 4. The target voltage for the regulator is programmable, accounting for the range of the max and min values 5. Current limit disabled. 6. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator. 7. Limited Characterization 8. IINRUSH with VREGINx=4.0 V to 5.5 V 9. The minimum value of IINRUSH is stated for operation when only one of VREG_IN0 / VREG_IN1 is powered, or when VREG_IN0 and VREG_IN1 both have the same voltage level. When VREG_IN0 and VREG_IN1 are operated at 56 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors different voltage levels with the selected VREG_IN lower than the non-selected VREG_IN, the minumum value of IINRUSH may decrease to a lower value. 10. Total current load on startup should be less than IINRUSH min over full input voltage range of the regulator. 3.7.2 USB Full Speed Transceiver and High Speed PHY specifications This section describes the USB0 port Full Speed/Low Speed transceiver and USB1 port USB-PHY High Speed Phy parameters. The high speed phy is capable of full and low speed signalling as well. The USB0 (FS/LS Transceiver) and USB1 ((USB HS/FS/LS) meet the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the amendments below. * USB ENGINEERING CHANGE NOTICE * Title: 5V Short Circuit Withstand Requirement Change * Applies to: Universal Serial Bus Specification, Revision 2.0 * Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000 * USB ENGINEERING CHANGE NOTICE * Title: Pull-up/Pull-down resistors * Applies to: Universal Serial Bus Specification, Revision 2.0 * USB ENGINEERING CHANGE NOTICE * Title: Suspend Current Limit Changes * Applies to: Universal Serial Bus Specification, Revision 2.0 * On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification * Revision 2.0 version 1.1a July 27, 2012 * Battery Charging Specification (available from USB-IF) * Revision 1.2 (including errata and ECNs through March 15, 2012), March 15, 2012 USB1_VBUS pin is a detector function which is 5v tolerant and complies with the above specifications without needing any external voltage division components. Kinetis K26 Sub-Family, Rev. 4, 04/2017 57 NXP Semiconductors Peripheral operating requirements and behaviors 3.7.3 USB DCD electrical specifications Table 41. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC, VDM_SRC USB_DP and USB_DM source voltages (up to 250 A) 0.5 -- 0.7 V Threshold voltage for logic high 0.8 -- 2.0 V VLGC IDP_SRC USB_DP source current 7 10 13 A IDM_SINK, IDP_SINK USB_DM and USB_DP sink currents 50 100 150 A RDM_DWN D- pulldown resistance for data pin contact detect 14.25 -- 24.8 k VDAT_REF Data detect voltage 0.25 0.33 0.4 V 3.7.4 CAN switching specifications See General switching specifications. 3.7.5 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 42. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation -- 30 MHz 2 x tBUS -- ns Notes DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 2 -- ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 2 -- ns 2 DS5 DSPI_SCK to DSPI_SOUT valid -- 15.0 ns DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 15.8 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 58 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK (CPOL=0) DS4 DS8 DS7 DSPI_SIN DS1 DS2 First data DSPI_SOUT Data Last data DS5 First data DS6 Data Last data Figure 24. DSPI classic SPI timing -- master mode Table 43. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid DS12 DSPI_SCK to DSPI_SOUT invalid DS13 DSPI_SIN to DSPI_SCK input setup DS14 DSPI_SCK to DSPI_SIN input hold DS15 DS16 15 1 MHz 4 x tBUS -- ns (tSCK/2) - 2 (tSCK/2) + 2 ns -- 23.0 ns 0 -- ns 2.7 -- ns 7.0 -- ns DSPI_SS active to DSPI_SOUT driven -- 13 ns DSPI_SS inactive to DSPI_SOUT not driven -- 13 ns 1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60MHz, SPI clock should not be greater than 10MHz. Kinetis K26 Sub-Family, Rev. 4, 04/2017 59 NXP Semiconductors Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 25. DSPI classic SPI timing -- slave mode 3.7.6 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 44. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit Notes 1.71 3.6 V 1 -- 15 MHz 4 x tBUS -- ns DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) - 4 -- ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) - 4 -- ns 3 DS5 DSPI_SCK to DSPI_SOUT valid -- 15 ns DS6 DSPI_SCK to DSPI_SOUT invalid 1.0 -- ns DS7 DSPI_SIN to DSPI_SCK input setup 15.8 -- ns DS8 DSPI_SCK to DSPI_SIN input hold 0 -- ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. 60 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS4 DS8 DS7 (CPOL=0) DS1 DS2 DSPI_SCK DSPI_SIN Data First data DSPI_SOUT Last data DS5 DS6 First data Data Last data Figure 26. DSPI classic SPI timing -- master mode Table 45. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V -- 7.5 MHz 8 x tBUS -- ns (tSCK/2) - 4 (tSCK/2) + 4 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid -- 23.1 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 -- ns DS13 DSPI_SIN to DSPI_SCK input setup 2.6 -- ns DS14 DSPI_SCK to DSPI_SIN input hold 7.0 -- ns DS15 DSPI_SS active to DSPI_SOUT driven -- 13.0 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven -- 13.0 ns DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Data Last data DS14 First data Data Last data Figure 27. DSPI classic SPI timing -- slave mode Kinetis K26 Sub-Family, Rev. 4, 04/2017 61 NXP Semiconductors Peripheral operating requirements and behaviors 3.7.7 Inter-Integrated Circuit Interface (I2C) timing Table 46. I 2C timing Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit SCL Clock Frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.25 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Data hold time for I2C bus devices tHD; DAT 01 3.452 03 0.91 s tSU; DAT 2504 -- 1002, 5 Data set-up time Rise time of SDA and SCL signals tr Fall time of SDA and SCL signals tf -- 1000 -- ns 6 300 ns 5 20 +0.1Cb -- 300 20 +0.1Cb 300 ns Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Input signal Slew = 10 ns and Output Load = 50 pF 4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; 2 DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released. 6. Cb = total capacitance of the one bus line in pF. Table 47. I 2C 1 Mbps timing Characteristic Symbol Minimum Maximum Unit MHz SCL Clock Frequency fSCL 0 11 Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 0.26 -- s LOW period of the SCL clock tLOW 0.5 -- s HIGH period of the SCL clock tHIGH 0.26 -- s Set-up time for a repeated START condition tSU; STA 0.26 -- s Data hold time for I2C bus devices tHD; DAT 0 -- s Data set-up time tSU; DAT 50 -- ns Rise time of SDA and SCL signals tr 20 +0.1Cb, 2 120 ns Table continues on the next page... 62 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors Table 47. I 2C 1 Mbps timing (continued) Characteristic Symbol Minimum 2 Maximum Unit 120 ns Fall time of SDA and SCL signals tf 20 +0.1Cb Set-up time for STOP condition tSU; STO 0.26 -- s Bus free time between STOP and START condition tBUF 0.5 -- s Pulse width of spikes that must be suppressed by the input filter tSP 0 50 ns 1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across the full voltage range. 2. Cb = total capacitance of the one bus line in pF. SDA tf tSU; DAT tr tLOW tf tHD; STA tr tSP tBUF SCL S HD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 28. Timing definition for devices on the I2C bus 3.7.8 UART switching specifications See General switching specifications. 3.7.9 Low Power UART switching specifications See General switching specifications. 3.7.10 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 48. SDHC full voltage range switching specifications Num Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 63 NXP Semiconductors Peripheral operating requirements and behaviors Table 48. SDHC full voltage range switching specifications (continued) Num Symbol Description Min. Max. Unit Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz fOD Clock frequency (identification mode) 0 400 kHz SD2 tWL Clock low time 7 -- ns SD3 tWH Clock high time 7 -- ns SD4 tTLH Clock rise time -- 3 ns SD5 tTHL Clock fall time -- 3 ns SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 8.6 8.3 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 -- ns SD8 tIH SDHC input hold time 0 -- ns Table 49. SDHC limited voltage range switching specifications Num Symbol Description Min. Max. Unit Operating voltage 2.7 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz fOD Clock frequency (identification mode) 0 400 kHz tWL Clock low time 7 -- ns SD3 tWH Clock high time 7 -- ns SD4 tTLH Clock rise time -- 3 ns SD5 tTHL Clock fall time -- 3 ns SD2 SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 7.6 8.3 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 -- ns SD8 tIH SDHC input hold time 0 -- ns 64 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 29. SDHC timing 3.7.11 I2S switching specifications This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync (I2S_FS) shown in the figures below. Table 50. I2S master mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_BCLK cycle time S4 I2S_BCLK pulse width high/low S5 80 -- ns 45% 55% BCLK period I2S_BCLK to I2S_FS output valid -- 15 ns S6 I2S_BCLK to I2S_FS output invalid 0 -- ns S7 I2S_BCLK to I2S_TXD valid -- 15 ns S8 I2S_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 15 -- ns S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 -- ns Kinetis K26 Sub-Family, Rev. 4, 04/2017 65 NXP Semiconductors Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_BCLK (output) S4 S4 S6 S5 I2S_FS (output) S10 S9 I2S_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 30. I2S timing -- master mode Table 51. I2S slave mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_BCLK cycle time (input) 80 -- ns S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 4.5 -- ns S14 I2S_FS input hold after I2S_BCLK 2 -- ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid -- 20 ns S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_BCLK 4.5 -- ns S18 I2S_RXD hold after I2S_BCLK 2 -- ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear 66 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors S11 S12 I2S_BCLK (input) S12 S15 S16 I2S_FS (output) S13 I2S_FS (input) S14 S15 S19 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 31. I2S timing -- slave modes 3.7.11.1 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 52. I2S/SAI master mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 15 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns Kinetis K26 Sub-Family, Rev. 4, 04/2017 67 NXP Semiconductors Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 32. I2S/SAI timing -- master modes Table 53. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 4.5 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 23.1 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns -- 25 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear 68 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 33. I2S/SAI timing -- slave modes 3.7.11.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 54. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 45 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns Kinetis K26 Sub-Family, Rev. 4, 04/2017 69 NXP Semiconductors Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 34. I2S/SAI timing -- master modes Table 55. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 5 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 56.5 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 30 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 5 -- ns -- 72 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear 70 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Dimensions S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 35. I2S/SAI timing -- slave modes 3.8 Human-machine interfaces (HMI) 3.8.1 TSI electrical specifications Table 56. TSI electrical specifications Symbol Description Min. Typ. Max. Unit TSI_RUNF Fixed power consumption in run mode -- 100 -- A TSI_RUNV Variable power consumption in run mode (depends on oscillator's current selection) 1.0 -- 128 A TSI_EN Power consumption in enable mode -- 100 -- A TSI_DIS Power consumption in disable mode -- 1.2 -- A TSI_TEN TSI analog enable time -- 66 -- s TSI_CREF TSI reference capacitor -- 1.0 -- pF TSI_DVOLT Voltage variation of VP & VM around nominal values 0.19 -- 1.03 V 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. Kinetis K26 Sub-Family, Rev. 4, 04/2017 71 NXP Semiconductors Pinout To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 144-pin MAPBGA 98ASA00222D 169-pin MAPBGA 98ASA00628D 169-pin WLCSP 98ASA00640D 5 Pinout 5.1 MK26 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The pin functions SDRAM_D12, SDRAM_D13, SDRAM_D14, and SDRAM_D15 don't exist on 144 LQFP and 144 MAPBGA packages. 169 CSP 169 144 144 BGA LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 C11 A1 1 D3 PTE0 ADC1_ SE4a ADC1_ SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 TRACE_ CLKOUT A13 B1 2 D2 PTE1/ LLWU_P0 ADC1_ SE5a ADC1_ SE5a PTE1/ LLWU_P0 B12 -- -- -- PTE2/ LLWU_P1 ADC1_ SE6a ADC1_ SE6a B13 -- -- -- PTE3 ADC1_ SE7a -- C1 3 D1 PTE2/ LLWU_P1 -- D1 4 E4 F9 G5 5 -- C3 C12 D11 ALT6 ALT7 I2C1_SDA RTC_ CLKOUT SPI1_ SOUT UART1_RX SDHC0_D0 TRACE_D3 I2C1_SCL SPI1_SIN PTE2/ LLWU_P1 SPI1_SCK UART1_ CTS_b SDHC0_ DCLK TRACE_D2 ADC1_ SE7a PTE3 SPI1_SIN UART1_ RTS_b SDHC0_ CMD TRACE_D1 ADC1_ SE6a ADC1_ SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_ CTS_b SDHC0_ DCLK TRACE_D2 PTE3 ADC1_ SE7a ADC1_ SE7a PTE3 SPI1_SIN UART1_ RTS_b SDHC0_ CMD TRACE_D1 E5 VDD VDD VDD 6 H3 VSS VSS VSS E1 7 E3 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 TRACE_D0 D2 8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 72 NXP Semiconductors EZPORT SPI1_ SOUT SPI1_ SOUT FTM3_CH0 Kinetis K26 Sub-Family, Rev. 4, 04/2017 Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 C13 E2 9 E1 PTE6/ DISABLED LLWU_P16 PTE6/ SPI1_PCS3 UART3_ LLWU_P16 CTS_b I2S0_MCLK FTM3_CH1 USB0_ SOF_OUT E10 E3 10 F4 PTE7 DISABLED PTE7 I2S0_RXD0 FTM3_CH2 D12 E4 11 F3 PTE8 DISABLED PTE8 D13 F3 12 F2 F10 F4 13 E11 G4 E12 UART3_ RTS_b I2S0_RXD1 I2S0_RX_ FS LPUART0_ FTM3_CH3 TX PTE9/ DISABLED LLWU_P17 PTE9/ I2S0_TXD1 LLWU_P17 I2S0_RX_ BCLK LPUART0_ FTM3_CH4 RX F1 PTE10/ DISABLED LLWU_P18 PTE10/ I2C3_SDA LLWU_P18 I2S0_TXD0 LPUART0_ FTM3_CH5 USB1_ID CTS_b 14 G4 PTE11 DISABLED PTE11 I2S0_TX_ FS LPUART0_ FTM3_CH6 RTS_b H4 15 G3 PTE12 DISABLED PTE12 I2S0_TX_ BCLK FTM3_CH7 E13 G6 16 E6 VDD VDD VDD G8 G8 17 F7 VSS VSS VSS G9 H3 -- -- PTE16 ADC0_ SE4a ADC0_ SE4a PTE16 F11 F5 -- -- PTE17/ ADC0_ LLWU_P19 SE5a ADC0_ SE5a PTE17/ SPI0_SCK LLWU_P19 UART2_RX FTM_ CLKIN1 G10 F6 -- -- PTE18/ ADC0_ LLWU_P20 SE6a ADC0_ SE6a PTE18/ SPI0_ LLWU_P20 SOUT UART2_ CTS_b I2C0_SDA F12 F7 -- -- PTE19 ADC0_ SE7a ADC0_ SE7a PTE19 UART2_ RTS_b I2C0_SCL F13 G3 18 F6 VSS VSS VSS G13 G1 19 H1 USB0_DP USB0_DP USB0_DP H13 F1 20 H2 USB0_DM USB0_DM USB0_DM G11 G2 21 G1 VREG_ OUT VREG_ OUT VREG_ OUT G12 F2 22 G2 VREG_IN0 VREG_IN0 VREG_IN0 H12 H2 23 J2 VREG_IN1 DISABLED VREG_IN1 J12 K1 24 K2 USB1_VSS DISABLED USB1_VSS J13 J1 25 J1 USB1_DP DISABLED USB1_DP K13 H1 26 K1 USB1_DM DISABLED USB1_DM K12 J2 27 L1 USB1_ VBUS DISABLED USB1_ VBUS J11 L1 -- -- ADC1_DP1 ADC1_DP1 ADC1_DP1 K11 M1 -- -- ADC1_DM1 ADC1_DM1 ADC1_DM1 L13 M2 -- -- ADC0_DP0/ ADC0_DP0/ ADC0_DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 M13 L2 28 L2 ADC0_ ADC0_ ADC0_ DM0/ DM0/ DM0/ ADC1_DM3 ADC1_DM3 ADC1_DM3 L12 N1 29 M1 ADC1_DP0/ ADC1_DP0/ ADC1_DP0/ ADC0_DP3 ADC0_DP3 ADC0_DP3 Kinetis K26 Sub-Family, Rev. 4, 04/2017 I2C3_SCL SPI0_PCS0 UART2_TX FTM_ CLKIN0 SPI0_SIN FTM0_ FLT3 TPM_ CLKIN0 LPTMR0_ ALT3 TPM_ CLKIN1 EZPORT CMP3_OUT 73 NXP Semiconductors Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name Default ALT0 M12 N2 30 M2 ADC1_ ADC1_ ADC1_ DM0/ DM0/ DM0/ ADC0_DM3 ADC0_DM3 ADC0_DM3 L11 J3 31 H5 VDDA VDDA VDDA M11 K3 32 G5 VREFH VREFH VREFH N12 K4 33 G6 VREFL VREFL VREFL N13 J4 34 H6 VSSA VSSA VSSA H11 M3 35 K3 ADC1_ SE16/ CMP2_IN2/ ADC0_ SE22 ADC1_ SE16/ CMP2_IN2/ ADC0_ SE22 ADC1_ SE16/ CMP2_IN2/ ADC0_ SE22 K10 L3 36 J3 ADC0_ SE16/ CMP1_IN2/ ADC0_ SE21 ADC0_ SE16/ CMP1_IN2/ ADC0_ SE21 ADC0_ SE16/ CMP1_IN2/ ADC0_ SE21 L10 N3 37 M3 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 M10 M4 38 L3 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 N11 N4 39 L4 DAC1_ OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_ SE23 DAC1_ OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_ SE23 DAC1_ OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_ SE23 J10 M5 -- L5 RTC_ WAKEUP_ B RTC_ WAKEUP_ B RTC_ WAKEUP_ B H10 L4 -- -- NC NC NC H9 L5 -- -- NC NC NC J9 K5 -- -- NC NC NC N10 L6 -- -- NC NC NC K9 K6 -- -- NC NC NC M9 N5 40 M7 XTAL32 XTAL32 XTAL32 N9 N6 41 M6 EXTAL32 EXTAL32 EXTAL32 L9 M6 42 L6 VBAT VBAT VBAT H8 J6 -- -- NC NC NC J8 J5 -- -- NC NC NC 74 NXP Semiconductors ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EZPORT Kinetis K26 Sub-Family, Rev. 4, 04/2017 Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name Default ALT2 ALT3 K8 G7 43 -- VDD VDD VDD H7 N7 44 -- VSS VSS VSS N8 L7 45 M4 PTE24 ADC0_ SE17 ADC0_ SE17 PTE24 CAN1_TX UART4_TX I2C0_SCL EWM_ OUT_b M8 K7 46 K5 PTE25/ ADC0_ LLWU_P21 SE18 ADC0_ SE18 PTE25/ CAN1_RX LLWU_P21 UART4_RX I2C0_SDA EWM_IN L8 K8 47 K4 PTE26/ DISABLED CLKOUT32 K PTE26/ CLKOUT32 K UART4_ CTS_b J7 L8 48 J4 PTE27 DISABLED PTE27 UART4_ RTS_b K7 M7 49 H4 PTE28 DISABLED PTE28 N7 N8 50 J5 PTA0 JTAG_ TSI0_CH1 TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_ CTS_b/ UART0_ COL_b FTM0_CH5 LPUART0_ CTS_b JTAG_ TCLK/ SWD_CLK EZP_CLK M7 N9 51 J6 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 I2C3_SDA LPUART0_ RX JTAG_TDI EZP_DI L7 M9 52 K6 PTA2 JTAG_ TDO/ TRACE_ SWO/ EZP_DO TSI0_CH3 PTA2 UART0_TX FTM0_CH7 I2C3_SCL LPUART0_ TX JTAG_ TDO/ TRACE_ SWO EZP_DO J6 M8 53 K7 PTA3 JTAG_ TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_ RTS_b LPUART0_ RTS_b JTAG_ TMS/ SWD_DIO K6 L9 54 L7 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 N6 N10 55 M8 PTA5 DISABLED M6 H5 56 E7 VDD VDD VDD H6 H8 57 G7 VSS VSS VSS N5 M10 58 J7 PTA6 DISABLED L6 L10 59 J8 PTA7 ADC0_ SE10 M5 K9 60 K8 PTA8 ADC0_ SE11 J5 K10 61 L8 PTA9 DISABLED K5 N11 62 M9 PTA10/ DISABLED LLWU_P22 Kinetis K26 Sub-Family, Rev. 4, 04/2017 ALT0 ALT1 PTA5 FTM0_CH0 ALT4 ALT5 ALT6 RTC_ CLKOUT FTM0_CH1 USB0_ CLKIN ALT7 EZPORT USB0_ CLKIN NMI_b FTM0_CH2 CMP2_OUT I2S0_TX_ BCLK JTAG_ TRST_b PTA6 FTM0_CH3 CLKOUT TRACE_ CLKOUT ADC0_ SE10 PTA7 FTM0_CH4 TRACE_D3 ADC0_ SE11 PTA8 FTM1_CH0 FTM1_QD_ TRACE_D2 PHA/ TPM1_CH0 PTA9 FTM1_CH1 FTM1_QD_ TRACE_D1 PHB/ TPM1_CH1 PTA10/ LLWU_P22 FTM2_CH0 FTM2_QD_ TRACE_D0 PHA/ TPM2_CH0 EZP_CS_b 75 NXP Semiconductors Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name ALT5 ALT6 N4 M11 63 L9 PTA11/ DISABLED LLWU_P23 FTM2_CH1 I2C2_SDA FTM2_QD_ PHB/ TPM2_CH1 M4 L12 64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2C2_SCL I2S0_TXD0 FTM1_QD_ PHA/ TPM1_CH0 L5 L11 65 J9 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 I2C2_SDA I2S0_TX_ FS FTM1_QD_ PHB/ TPM1_CH1 N3 K13 66 L10 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2C2_SCL I2S0_RX_ BCLK I2S0_TXD1 L4 K12 67 L11 PTA15 CMP3_IN1 CMP3_IN1 PTA15 SPI0_SCK UART0_RX I2S0_RXD0 K4 J13 68 K10 PTA16 CMP3_IN2 CMP3_IN2 PTA16 SPI0_ SOUT UART0_ CTS_b/ UART0_ COL_b I2S0_RX_ FS L3 J12 69 K11 PTA17 ADC1_ SE17 ADC1_ SE17 PTA17 SPI0_SIN UART0_ RTS_b I2S0_MCLK M3 N12 70 E8 VDD VDD VDD M2 M12 71 G8 VSS VSS VSS N1 N13 72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_ FLT2 FTM_ CLKIN0 N2 M13 73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_ FLT0 FTM_ CLKIN1 M1 L13 74 L12 RESET_b RESET_b RESET_b K3 K11 75 K12 PTA24 CMP3_IN4 CMP3_IN4 PTA24 FB_A15/ SDRAM_ D15 FB_A29 J4 J11 76 J12 PTA25 CMP3_IN5 CMP3_IN5 PTA25 FB_A14/ SDRAM_ D14 FB_A28 J3 J10 77 J11 PTA26 DISABLED PTA26 FB_A13/ SDRAM_ D13 FB_A27 L2 H13 78 J10 PTA27 DISABLED PTA27 FB_A12/ SDRAM_ D12 FB_A26 L1 H12 79 H12 PTA28 DISABLED PTA28 FB_A25 K2 H11 80 H11 PTA29 DISABLED PTA29 FB_A24 K1 H10 -- -- PTA30 DISABLED PTA30 CAN0_TX FB_A11/ SDRAM_ D11 H5 J9 -- -- PTA31 DISABLED PTA31 CAN0_RX FB_A10/ SDRAM_ D10 76 NXP Semiconductors Default ALT0 ALT1 ALT2 PTA11/ LLWU_P23 ALT3 ALT4 ALT7 EZPORT I2S0_RXD1 TPM_ CLKIN0 LPTMR0_ ALT1 TPM_ CLKIN1 Kinetis K26 Sub-Family, Rev. 4, 04/2017 Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name H4 G13 81 H10 PTB0/ LLWU_P5 J2 G12 82 H9 ALT2 ALT3 ADC0_SE8/ ADC0_SE8/ PTB0/ ADC1_SE8/ ADC1_SE8/ LLWU_P5 TSI0_CH0 TSI0_CH0 I2C0_SCL FTM1_CH0 SDRAM_ CAS_b FTM1_QD_ PHA/ TPM1_CH0 ADC0_SE9/ ADC0_SE9/ PTB1 ADC1_SE9/ ADC1_SE9/ TSI0_CH6 TSI0_CH6 I2C0_SDA FTM1_CH1 SDRAM_ RAS_b FTM1_QD_ PHB/ TPM1_CH1 J1 G11 83 G12 PTB2 ADC0_ SE12/ TSI0_CH7 ADC0_ SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_ RTS_b SDRAM_ WE FTM0_ FLT3 H3 G10 84 G11 PTB3 ADC0_ SE13/ TSI0_CH8 ADC0_ SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_ CTS_b/ UART0_ COL_b SDRAM_ CS0_b FTM0_ FLT0 G7 -- -- -- VSS VSS VSS G6 -- -- -- VDD VDD VDD H2 H9 85 G10 PTB4 ADC1_ SE10 ADC1_ SE10 PTB4 SDRAM_ CS1_b FTM1_ FLT0 H1 F13 86 G9 PTB5 ADC1_ SE11 ADC1_ SE11 PTB5 G5 F12 87 F12 PTB6 ADC1_ SE12 ADC1_ SE12 PTB6 FB_AD23/ SDRAM_ D23 G4 F11 88 F11 PTB7 ADC1_ SE13 ADC1_ SE13 PTB7 FB_AD22/ SDRAM_ D22 G3 F10 89 F10 PTB8 DISABLED PTB8 UART3_ RTS_b FB_AD21/ SDRAM_ D21 G2 F9 90 F9 PTB9 DISABLED PTB9 SPI1_PCS1 UART3_ CTS_b FB_AD20/ SDRAM_ D20 G1 G9 91 E12 PTB10 ADC1_ SE14 ADC1_ SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19/ SDRAM_ D19 FTM0_ FLT1 F5 E13 92 E11 PTB11 ADC1_ SE15 ADC1_ SE15 PTB11 SPI1_SCK UART3_TX FB_AD18/ SDRAM_ D18 FTM0_ FLT2 F4 E12 -- -- PTB12 DISABLED PTB12 UART3_ RTS_b FTM1_CH0 FTM0_CH4 FB_A9/ FTM1_QD_ SDRAM_D9 PHA/ TPM1_CH0 F3 E11 -- -- PTB13 DISABLED PTB13 UART3_ CTS_b FTM1_CH1 FTM0_CH5 FB_A8/ FTM1_QD_ SDRAM_D8 PHB/ TPM1_CH1 F2 E10 -- -- PTB14 DISABLED PTB14 CAN1_TX FB_A7/ SDRAM_D7 F1 E9 -- -- PTB15 DISABLED PTB15 CAN1_RX FB_A6/ SDRAM_D6 -- -- 93 H7 VSS VSS PTB1 Default Kinetis K26 Sub-Family, Rev. 4, 04/2017 ALT0 ALT1 ALT4 ALT5 ALT6 ALT7 EZPORT FTM2_ FLT0 VSS 77 NXP Semiconductors Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name Default ALT0 -- -- 94 F5 VDD VDD VDD E1 F8 95 E10 PTB16 TSI0_CH9 TSI0_CH9 E2 D13 96 E9 PTB17 E3 D12 97 E4 D11 E5 ALT1 ALT3 ALT4 ALT5 ALT6 ALT7 SPI1_ SOUT UART0_RX FTM_ CLKIN0 FB_AD17/ SDRAM_ D17 EWM_IN TPM_ CLKIN0 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FTM_ CLKIN1 FB_AD16/ SDRAM_ D16 EWM_ OUT_b TPM_ CLKIN1 D12 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_ BCLK FB_AD15/ SDRAM_ A23 FTM2_QD_ PHA/ TPM2_CH0 98 D11 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_ FS FB_OE_b FTM2_QD_ PHB/ TPM2_CH1 D10 99 D10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31/ SDRAM_ D31 CMP0_OUT D1 D9 100 D9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30/ SDRAM_ D30 CMP1_OUT D2 C13 101 C12 PTB22 DISABLED PTB22 SPI2_ SOUT FB_AD29/ SDRAM_ D29 CMP2_OUT D3 C12 102 C11 PTB23 DISABLED PTB23 SPI2_SIN FB_AD28/ SDRAM_ D28 CMP3_OUT C1 B13 103 B12 PTC0 ADC0_ ADC0_ PTC0 SE14/ SE14/ TSI0_CH13 TSI0_CH13 SPI0_PCS4 PDB0_ EXTRG USB0_ SOF_OUT FB_AD14/ SDRAM_ A22 I2S0_TXD1 C2 B12 104 B11 PTC1/ LLWU_P6 ADC0_ ADC0_ PTC1/ SE15/ SE15/ LLWU_P6 TSI0_CH14 TSI0_CH14 SPI0_PCS3 UART1_ RTS_b FTM0_CH0 FB_AD13/ SDRAM_ A21 I2S0_TXD0 D4 A13 105 A12 PTC2 ADC0_ SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_ PTC2 SE4b/ CMP1_IN0/ TSI0_CH15 SPI0_PCS2 UART1_ CTS_b FTM0_CH1 FB_AD12/ SDRAM_ A20 I2S0_TX_ FS B1 A12 106 A11 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ BCLK F6 C11 107 H8 VSS VSS VSS E6 H6 108 -- VDD VDD VDD A1 B11 109 A9 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11/ SDRAM_ A19 CMP1_OUT B2 A11 110 D8 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK C3 A10 111 C8 PTC6/ CMP0_IN0 LLWU_P10 78 NXP Semiconductors CMP0_IN0 PTB16 ALT2 PTC6/ SPI0_ LLWU_P10 SOUT SPI0_PCS5 LPTMR0_ ALT2 I2S0_RXD0 FB_AD10/ SDRAM_ A18 CMP0_OUT FTM0_CH2 PDB0_ EXTRG I2S0_RX_ BCLK I2S0_MCLK FB_AD9/ SDRAM_ A17 EZPORT Kinetis K26 Sub-Family, Rev. 4, 04/2017 Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name Default ALT0 D5 B10 112 B8 C4 C10 113 A2 C9 B3 PTC7 CMP0_IN1 CMP0_IN1 PTC7 A8 PTC8 ADC1_ SE4b/ CMP0_IN2 ADC1_ SE4b/ CMP0_IN2 PTC8 FTM3_CH4 I2S0_MCLK FB_AD7/ SDRAM_ A15 114 D7 PTC9 ADC1_ SE5b/ CMP0_IN3 ADC1_ SE5b/ CMP0_IN3 PTC9 FTM3_CH5 I2S0_RX_ BCLK FB_AD6/ SDRAM_ A14 A8 115 C7 PTC10 ADC1_ SE6b ADC1_ SE6b PTC10 FTM3_CH6 I2S0_RX_ FS FB_AD5/ SDRAM_ A13 D6 A9 116 B7 PTC11/ ADC1_ LLWU_P11 SE7b ADC1_ SE7b PTC11/ I2C1_SDA LLWU_P11 FTM3_CH7 I2S0_RXD1 FB_RW_b C5 B9 117 A7 PTC12 DISABLED PTC12 UART4_ RTS_b FTM_ CLKIN0 FB_AD27/ SDRAM_ D27 A3 B8 118 D6 PTC13 DISABLED PTC13 UART4_ CTS_b FTM_ CLKIN1 FB_AD26/ SDRAM_ D26 B4 C8 119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25/ SDRAM_ D25 A4 D8 120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24/ SDRAM_ D24 F7 -- 121 -- VSS VSS VSS E7 -- 122 -- VDD VDD VDD A5 E8 123 A6 PTC16 DISABLED PTC16 CAN1_RX UART3_RX FB_CS5_b/ FB_TSIZ1/ FB_BE23_ 16_BLS15_ 8_b/ SDRAM_ DQM2 B5 E7 124 D5 PTC17 DISABLED PTC17 CAN1_TX UART3_TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_ 24_BLS7_ 0_b/ SDRAM_ DQM3 C6 D7 125 C5 PTC18 DISABLED PTC18 UART3_ RTS_b FB_TBST_ b/ FB_CS2_b/ FB_BE15_ 8_BLS23_ 16_b/ SDRAM_ DQM1 Kinetis K26 Sub-Family, Rev. 4, 04/2017 ALT1 ALT2 SPI0_SIN I2C1_SCL ALT3 ALT4 USB0_ SOF_OUT I2S0_RX_ FS ALT5 ALT6 ALT7 EZPORT FB_AD8/ SDRAM_ A16 FTM2_ FLT0 FTM3_ FLT0 TPM_ CLKIN0 TPM_ CLKIN1 79 NXP Semiconductors Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name B6 C7 126 B5 PTC19 DISABLED PTC19 UART3_ CTS_b FB_CS3_b/ FB_TA_b FB_BE7_0_ BLS31_24_ b/ SDRAM_ DQM0 A6 B7 -- -- PTC24 DISABLED PTC24 LPUART0_ TX FB_A5/ SDRAM_D5 D7 A7 -- -- PTC25 DISABLED PTC25 LPUART0_ RX FB_A4/ SDRAM_D4 E8 E6 -- -- PTC26 DISABLED PTC26 LPUART0_ CTS_b FB_A3/ SDRAM_D3 A7 D6 -- -- PTC27 DISABLED PTC27 LPUART0_ RTS_b FB_A2/ SDRAM_D2 B7 C6 -- -- PTC28 DISABLED PTC28 I2C3_SDA FB_A1/ SDRAM_D1 C7 B6 -- -- PTC29 DISABLED PTC29 I2C3_SCL FB_A0/ SDRAM_D0 D8 A6 127 A5 PTD0/ DISABLED LLWU_P12 A8 A5 128 D4 PTD1 B8 A4 129 C4 PTD2/ DISABLED LLWU_P13 PTD2/ SPI0_ LLWU_P13 SOUT UART2_RX FTM3_CH2 FB_AD4/ SDRAM_ A12 I2C0_SCL C8 B4 130 B4 PTD3 PTD3 UART2_TX FTM3_CH3 FB_AD3/ SDRAM_ A11 I2C0_SDA F8 B5 131 A4 PTD4/ DISABLED LLWU_P14 A9 C4 132 A3 PTD5 ADC0_ SE6b B9 C5 133 A2 PTD6/ ADC0_ LLWU_P15 SE7b -- J8 134 M10 VSS VSS VSS E9 H7 135 F8 VDD VDD VDD A10 E5 136 A1 PTD7 DISABLED C9 D5 137 C9 PTD8/ DISABLED LLWU_P24 PTD8/ I2C0_SCL LLWU_P24 LPUART0_ FB_A16 RX B10 D4 138 B9 PTD9 DISABLED PTD9 LPUART0_ FB_A17 TX A11 D3 139 B3 PTD10 DISABLED PTD10 80 NXP Semiconductors Default ADC0_ SE5b ALT0 ADC0_ SE5b DISABLED ALT1 ALT2 ALT3 ALT4 ALT5 PTD0/ SPI0_PCS0 UART2_ LLWU_P12 RTS_b FTM3_CH0 FB_ALE/ FB_CS1_b/ FB_TS_b PTD1 FTM3_CH1 FB_CS0_b SPI0_SCK SPI0_SIN UART2_ CTS_b ALT6 PTD4/ SPI0_PCS1 UART0_ LLWU_P14 RTS_b FTM0_CH4 FB_AD2/ SDRAM_ A10 ADC0_ SE6b PTD5 FTM0_CH5 FB_AD1/ EWM_ SDRAM_A9 OUT_b ADC0_ SE7b PTD6/ SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 LLWU_P15 FTM0_ FLT0 SPI1_ SOUT PTD7 FTM0_ FLT1 SPI1_SIN SPI0_PCS2 UART0_ CTS_b/ UART0_ COL_b CMT_IRO I2C0_SDA UART0_TX FTM0_CH7 SDRAM_ CKE EWM_IN ALT7 EZPORT SPI1_PCS0 SPI1_SCK LPUART0_ FB_A18 RTS_b Kinetis K26 Sub-Family, Rev. 4, 04/2017 Pinout 169 CSP 169 144 144 BGA LQFP BGA Pin Name Default ALT0 ALT1 ALT2 D9 C2 140 B2 PTD11/ DISABLED LLWU_P25 PTD11/ SPI2_PCS0 LLWU_P25 C10 B2 141 B1 PTD12 DISABLED PTD12 SPI2_SCK A12 B3 142 C3 PTD13 DISABLED PTD13 ALT3 ALT4 SDHC0_ CLKIN FTM3_ FLT0 ALT5 ALT6 ALT7 EZPORT LPUART0_ FB_A19 CTS_b SDHC0_D4 FB_A20 SPI2_ SOUT SDHC0_D5 FB_A21 B11 A2 143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 D10 A3 144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 -- K2 -- -- NC NC NC -- J7 -- M5 NC NC NC -- -- -- A10 NC NC NC -- -- -- B10 NC NC NC -- -- -- C10 NC NC NC 5.2 Recommended connection for unused analog and digital pins Table 57 shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application Table 57. Recommended connection for unused analog interfaces Pin Type K26 Short recommendation Detailed recommendation Analog/non GPIO ADCx/CMPx Float Analog input - Float Analog/non GPIO VREF_OUT Float Analog output - Float Analog/non GPIO DAC0_OUT, DAC1_OUT Float Analog output - Float Analog/non GPIO RTC_WAKEUP_B Float Analog output - Float Analog/non GPIO XTAL32 Float Analog output - Float Analog/non GPIO EXTAL32 Float Analog input - Float GPIO/Analog PTA18/EXTAL0 Float Analog input - Float GPIO/Analog PTA19/XTAL0 Float Analog output - Float GPIO/Analog PTx/ADCx Float Float (default is analog input) GPIO/Analog PTx/CMPx Float Float (default is analog input) GPIO/Analog PTx/TSIOx Float Float (default is analog input) GPIO/Digital PTA0/JTAG_TCLK Float Float (default is JTAG with pulldown) GPIO/Digital PTA1/JTAG_TDI Float Float (default is JTAG with pullup) GPIO/Digital PTA2/JTAG_TDO Float Float (default is JTAG with pullup) Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 81 NXP Semiconductors Pinout Table 57. Recommended connection for unused analog interfaces (continued) Pin Type K26 Short recommendation Detailed recommendation GPIO/Digital PTA3/JTAG_TMS Float Float (default is JTAG with pullup) GPIO/Digital PTA4/NMI_b 10k pullup or disable and float Pull high or disable in PCR & FOPT and float GPIO/Digital PTx Float Float (default is disabled) USB USB0_DP Float Float USB USB0_DM Float Float USB VREG_OUT Tie to input and ground through 10k Tie to input and ground through 10k USB VREG_IN0 Tie to output and ground through 10k Tie to output and ground through 10k USB VREG_IN1 Tie to output and ground through 10k Tie to output and ground through 10k USB USB1_VSS Always connect to VSS Always connect to VSS USB USB1_DP Float Float USB USB1_DM Float Float USB USB1_VBUS Float Float VBAT VBAT Float Float VDDA VDDA Always connect to VDD potential Always connect to VDD potential VREFH VREFH Always connect to VDD potential Always connect to VDD potential VREFL VREFL Always connect to VSS potential Always connect to VSS potential VSSA VSSA Always connect to VSS potential Always connect to VSS potential 5.3 MK26 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. 82 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 111 110 109 PTC13 PTC8 PTC14 118 112 PTC15 119 PTC9 VSS 120 113 VDD 121 PTC10 PTC16 122 115 PTC17 123 114 PTC18 124 PTC12 PTC19 125 PTC11/LLWU_P11 PTD0/LLWU_P12 126 116 PTD1 127 117 PTD2/LLWU_P13 VSS 134 128 VDD 135 PTD3 PTD7 136 129 PTD8/LLWU_P24 137 PTD4/LLWU_P14 PTD9 138 131 PTD10 139 130 PTD11/LLWU_P25 140 PTD6/LLWU_P15 PTD12 141 PTD5 PTD13 142 132 PTD14 143 133 PTD15 144 Pinout PTE0 1 108 VDD PTE1/LLWU_P0 2 107 VSS PTE2/LLWU_P1 3 106 PTC3/LLWU_P7 PTE3 4 105 PTC2 VDD 5 104 PTC1/LLWU_P6 VSS 6 103 PTC0 PTE4/LLWU_P2 7 102 PTB23 PTE5 8 101 PTB22 PTE6/LLWU_P16 9 100 PTB21 PTB20 PTE7 10 99 PTE8 11 98 PTB19 PTE9/LLWU_P17 12 97 PTB18 PTE10/LLWU_P18 13 96 PTB17 PTE11 14 95 PTB16 PTE12 15 94 VDD VDD 16 93 VSS VSS 17 92 PTB11 VSS 18 91 PTB10 USB0_DP 19 90 PTB9 USB0_DM 20 89 PTB8 VREG_OUT 21 88 PTB7 VREG_IN0 22 87 PTB6 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD VSS PTA6 PTA7 PTA8 PTA9 PTA10/LLWU_P22 PTA11/LLWU_P23 PTA12 PTA13/LLWU_P4 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 PTA19 55 RESET_b 73 PTA5 74 36 54 35 PTA4/LLWU_P3 ADC1_SE16/CMP2_IN2/ADC0_SE22 ADC0_SE16/CMP1_IN2/ADC0_SE21 53 PTA24 PTA3 75 52 34 PTA2 PTA25 VSSA 51 PTA26 76 50 77 33 PTA1 32 VREFL PTA0 VREFH 49 PTA27 PTE28 78 48 31 PTE27 PTA28 VDDA 47 79 PTE26/CLKOUT32K 30 46 PTA29 ADC1_DM0/ADC0_DM3 PTE25/LLWU_P21 80 45 29 PTE24 PTB0/LLWU_P5 ADC1_DP0/ADC0_DP3 44 81 VSS 28 43 PTB1 ADC0_DM0/ADC1_DM3 VDD 82 42 27 VBAT PTB2 USB1_VBUS 41 83 EXTAL32 26 40 PTB3 USB1_DM XTAL32 84 39 25 DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23 PTB4 USB1_DP 38 PTB5 85 37 86 24 DAC0_OUT/CMP1_IN3/ADC0_SE23 23 VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 VREG_IN1 USB1_VSS Figure 36. MK26 144 LQFP Pinout Diagram Kinetis K26 Sub-Family, Rev. 4, 04/2017 83 NXP Semiconductors Pinout 1 2 3 4 5 6 7 8 9 10 11 12 A PTD7 PTD6/ LLWU_P15 PTD5 PTD4/ LLWU_P14 PTD0/ LLWU_P12 PTC16 PTC12 PTC8 PTC4/ LLWU_P8 NC PTC3/ LLWU_P7 PTC2 A B PTD12 PTD11/ LLWU_P25 PTD10 PTD3 PTC19 PTC15 PTC7 PTD9 NC PTC1/ LLWU_P6 PTC0 B C PTD15 PTD14 PTD13 PTD2/ LLWU_P13 PTC18 PTC14 PTC10 PTC6/ LLWU_P10 PTD8/ LLWU_P24 NC PTB23 PTB22 C D PTE2/ LLWU_P1 PTE1/ LLWU_P0 PTE0 PTD1 PTC17 PTC13 PTC9 PTC5/ LLWU_P9 PTB21 PTB20 PTB19 PTB18 D E PTE6/ LLWU_P16 PTE5 PTE4/ LLWU_P2 PTE3 VDD VDD VDD VDD PTB17 PTB16 PTB11 PTB10 E F PTE10/ LLWU_P18 PTE9/ LLWU_P17 PTE8 PTE7 VDD VSS VSS VDD PTB9 PTB8 PTB7 PTB6 F G VREG_OUT VREG_IN0 PTE12 PTE11 VREFH VREFL VSS VSS PTB5 PTB4 PTB3 PTB2 G H USB0_DP USB0_DM VSS PTE28 VDDA VSSA VSS VSS PTB1 PTB0/ LLWU_P5 PTA29 PTA28 H J USB1_DP VREG_IN1 PTE27 PTA0 PTA1 PTA6 PTA7 PTA13/ LLWU_P4 PTA27 PTA26 PTA25 J K USB1_DM USB1_VSS CMP2_IN2/ ADC0_SE22 CLKOUT32K PTE25/ LLWU_P21 PTA2 PTA3 PTA8 PTA12 PTA16 PTA17 PTA24 K ADC0_DM0/ L USB1_VBUS ADC1_DM3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 RTC_ WAKEUP_B VBAT PTA4/ LLWU_P3 PTA9 PTA11/ LLWU_P23 PTA14 PTA15 RESET_b L VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 PTE24 NC EXTAL32 XTAL32 PTA5 PTA10/ LLWU_P22 VSS PTA19 PTA18 M 3 4 5 6 7 8 9 10 11 12 PTC11/ LLWU_P11 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC1_SE16/ ADC1_DP0/ M ADC0_DP3 1 ADC1_DM0/ ADC0_DM3 2 PTE26/ Figure 37. MK26 144 BGA Pinout Diagram 84 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Pinout 1 2 3 4 5 6 7 8 A PTE0 PTD14 PTD15 PTD2/ LLWU_P13 PTD1 PTD0/ LLWU_P12 PTC25 PTC10 B PTE1/ LLWU_P0 PTD12 PTD13 PTD3 PTD4/ LLWU_P14 PTC29 PTC24 PTC13 PTC12 PTC7 C PTE2/ PTD11/ LLWU_P1 LLWU_P25 VSS PTD5 PTD6/ LLWU_P15 PTC28 PTC19 PTC14 PTC9 PTD10 PTD9 PTD8/ LLWU_P24 PTC27 PTC18 PTC15 PTE7 PTE8 PTD7 PTC26 PTC17 D PTE3 PTE5 9 10 11 12 13 PTC3/ LLWU_P7 PTC2 A PTC4/ LLWU_P8 PTC1/ LLWU_P6 PTC0 B PTC8 VSS PTB23 PTB22 C PTB21 PTB20 PTB19 PTB18 PTB17 D PTC16 PTB15 PTB14 PTB13 PTB12 PTB11 E PTE19 PTB16 PTB9 PTB8 PTB7 PTB6 PTB5 F PTC11/ PTC6/ PTC5/ LLWU_P11 LLWU_P10 LLWU_P9 E PTE4/ PTE6/ LLWU_P2 LLWU_P16 F USB0_DM VREG_IN0 G USB0_DP VREG_OUT VSS PTE11 VDD VDD VDD VSS PTB10 PTB3 PTB2 PTB1 PTB0/ LLWU_P5 G H USB1_DM VREG_IN1 PTE16 PTE12 VDD VDD VDD VSS PTB4 PTA30 PTA29 PTA28 PTA27 H J USB1_DP USB1_VBUS VDDA VSSA NC NC NC VSS PTA31 PTA26 PTA25 PTA17 PTA16 J VREFH VREFL NC NC PTA8 PTA9 PTA24 PTA15 PTA14 K NC NC NC PTE24 PTE27 PTA4/ LLWU_P3 PTA7 PTA13/ LLWU_P4 PTA12 RESET_b L ADC0_DP0/ ADC1_SE16/ DAC0_OUT/ RTC_ CMP2_IN2/ CMP1_IN3/ ADC1_DP3 ADC0_SE22 ADC0_SE23 WAKEUP_B VBAT PTE28 PTA3 PTA2 PTA6 PTA11/ LLWU_P23 VSS PTA19 M VREF_OUT/ DAC1_OUT/ CMP1_IN5/ CMP0_IN4/ CMP0_IN5/ CMP2_IN3/ ADC1_SE18 ADC1_SE23 XTAL32 EXTAL32 VSS PTA0 PTA1 PTA5 PTA10/ LLWU_P22 VDD PTA18 N 5 6 7 8 9 10 11 12 13 NC PTE9/ PTE10/ PTE17/ PTE18/ LLWU_P17 LLWU_P18 LLWU_P19 LLWU_P20 K USB1_VSS L ADC1_DP1 ADC0_DM0/ CMP1_IN2/ M ADC1_DM1 N ADC1_DP0/ ADC1_DM0/ ADC0_DP3 ADC0_DM3 PTE25/ PTE26/ LLWU_P21 CLKOUT32K ADC0_SE16/ ADC1_DM3 ADC0_SE21 1 2 3 4 Figure 38. MK26 169 BGA Pinout Diagram Kinetis K26 Sub-Family, Rev. 4, 04/2017 85 NXP Semiconductors Ordering parts 1 2 3 4 5 6 7 8 9 10 11 12 13 A PTC4/ LLWU_P8 PTC9 PTC13 PTC15 PTC16 PTC24 PTC27 PTD1 PTD5 PTD7 PTD10 PTD13 PTE1/ LLWU_P0 A B PTC3/ LLWU_P7 PTC5/ LLWU_P9 PTC10 PTC14 PTC17 PTC19 PTC28 PTD9 PTD14 PTE2/ LLWU_P1 PTE3 B C PTC0 PTC8 PTC12 PTC18 PTC29 PTD8/ LLWU_P24 PTD12 PTE0 PTE4/ PTE6/ LLWU_P2 LLWU_P16 D PTB21 PTB22 PTB23 PTC2 PTC7 PTC11/ LLWU_P11 PTC25 PTD0/ PTD11/ LLWU_P12 LLWU_P25 PTD15 PTE5 PTE8 PTE9/ LLWU_P17 D E PTB16 PTB17 PTB18 PTB19 PTB20 VDD VDD PTC26 VDD PTE7 PTE11 PTE12 VDD E F PTB15 PTB14 PTB13 PTB12 PTB11 VSS VSS PTD4/ LLWU_P14 VDD PTE19 VSS F G PTB10 PTB9 PTB8 PTB7 PTB6 VDD VSS VSS PTE16 H PTB5 PTB4 PTB3 PTB0/ LLWU_P5 PTA31 VSS VSS NC NC J PTB2 PTB1 PTA26 PTA25 PTA9 PTA3 PTE27 NC NC K PTA30 PTA29 PTA24 PTA16 PTA10/ LLWU_P22 PTA4/ LLWU_P3 PTE28 VDD NC L PTA28 PTA27 PTA17 PTA15 PTA13/ LLWU_P4 PTA7 PTA2 PTE26/ CLKOUT32K VBAT M RESET_b VSS VDD PTA12 PTA8 VDD PTA1 PTE25/ LLWU_P21 XTAL32 N PTA18 PTA19 PTA14 PTA11/ LLWU_P23 PTA6 PTA5 PTA0 PTE24 EXTAL32 NC DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 VREFL VSSA 1 2 3 4 5 6 7 8 9 10 11 12 13 PTC1/ PTC6 LLWU_P6 /LLWU_P10 PTD2/ PTD6/ LLWU_P13 LLWU_P15 PTD3 PTE10/ PTE17/ LLWU_P18 LLWU_P19 PTE18/ VREG_OUT VREG_IN0 USB0_DP LLWU_P20 NC ADC1_SE16/ CMP2_IN2/ VREG_IN1 USB0_DM ADC0_SE22 RTC_ ADC1_DP1 USB1_VSS USB1_DP WAKEUP_B C G H J ADC0_SE16/ CMP1_IN2/ ADC1_DM1 USB1_VBUS USB1_DM ADC0_SE21 K VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 L VDDA DAC0_OUT/ CMP1_IN3/ ADC0_SE23 VREFH ADC1_DP0/ ADC0_DP0/ ADC0_DP3 ADC1_DP3 ADC1_DM0/ ADC0_DM0/ ADC0_DM3 ADC1_DM3 M N Figure 39. MK26 169 CSP Pinout Diagram 6 Ordering parts 86 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Part identification 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: MK26 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status * M = Fully qualified, general market flow * P = Prequalification K## Kinetis family * K26 A Key attribute * D = Cortex-M4 w/ DSP * F = Cortex-M4 w/ DSP and FPU M Flash memory type * N = Program flash only * X = Program flash and FlexMemory FFF Program flash memory size * * * * * * * 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB 2M0 = 2 MB Table continues on the next page... Kinetis K26 Sub-Family, Rev. 4, 04/2017 87 NXP Semiconductors Terminology and guidelines Field Description Values R Silicon revision * Z = Initial * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 * C = -40 to 85 PP Package identifier * * * * * * * * * * FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (12 mm x 12 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) * * * * * * * 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz 16 = 168 MHz 18 = 180 MHz N Packaging type * R = Tape and reel * (Blank) = Trays 7.4 Example This is an example part number: MK26FN2M0CAC18R 8 Terminology and guidelines 8.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. Table continues on the next page... 88 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Terminology and guidelines Term Definition NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. 8.2 Examples EX AM PL E Operating rating: EX AM PL E Operating requirement: EX AM PL E Operating behavior that includes a typical value: 8.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Kinetis K26 Sub-Family, Rev. 4, 04/2017 89 NXP Semiconductors Revision History Symbol Description Value Unit TA Ambient temperature 25 C VDD Supply voltage 3.3 V 8.4 Relationship between ratings and operating requirements O a gr tin ra pe g tin ( ) in. (m nt me n.) mi t era Op ing e uir req g tin era Op t en em uir req ax (m .) rat pe g tin ra ing ax (m .) O Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) dli n Ha ng ra g tin x.) ) in. (m li nd Ha ma g( tin a r ng Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 8.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9 Revision History The following table provides a revision history for this document. 90 NXP Semiconductors Kinetis K26 Sub-Family, Rev. 4, 04/2017 Revision History Table 58. Revision History Rev. No. Date Substantial Changes 0 02/2015 1 04/2015 * Editorial change * Updated OTG/EH and BC rev. 1.2 specification references in USB Full Speed Transceiver and High Speed PHY specifications section * Updated USBDCD electrical specifications table * Updated the typical values and maximum values of specs in Power consumption operating behaviors table * Removed PSTOP2 current from Power consumption operating behaviors table * Updated the values of DS5 and DS7 in Master mode DSPI timing (full voltage range) table * Updated the footnote and description of VDIO, VAIO and ID in Voltage and current operating ratings table * Updated the values and description of specs in Voltage and current operating requirements table * Updated the leakage current specs in Voltage and current operating behaviors table * Added Notes column in Thermal operating requirements * Updated the values of 48 MHz IRC in Low power mode peripheral adders table 2 05/2015 * Added new footnotes for IINRUSH in USB VREG electrical specifications table to better document operation. * Added a footnote to the figures, "SDRAM write timing diagram" and "SDRAM read timing diagram," for 144-pin packages, in the section "SDRAM controller specifications." * Added a note to the section "Pinouts" for pin functions not available in 144-pin packages. 3 01/2016 * * * * * * 4 03/2017 * Removed the verbiage of "except RTC_WAKEUP pins" from the description for RPU and RPD in Voltage and current operating behaviors table * Updated the unit of ADC conversion rate from "Kbps" to "kS/s" in 16-bit ADC operating conditions table * Updated I2C switching specifications section * Updated the minimum and maximum value of Voltage reference output with factory trim in VREF full-range operating requirements table in Voltage reference electrical specifications section Initial Release Updated the symbol in footnote of Thermal operating spec Updated description of PLL operating current in MCG specification table. Added the USB FS and USB HS logo in front matter Updated IRC48M specifications Updated Terminology and guidelines section Updated the maximum values of IDD_LLS2 and IDD_LLS3 in Power consumption operating behaviors table Kinetis K26 Sub-Family, Rev. 4, 04/2017 91 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM powered logo, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. The USB-IF Logo is a registered trademark of USB Implementers Forum, Inc. All rights reserved. (c) 2013-2017 NXP B.V. Document Number K26P169M180SF5 Revision 4, 04/2017