CY7C1020D
512K (32K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05463 Rev. *G Revised April 7, 2011
Features
■Pin- and function-compatible with CY7C1020B
■High speed
—t
AA = 10 ns
■Low active power
—I
CC = 80 mA @ 10ns
■Low complementary metal oxide semiconductor (CMOS)
standby power
—I
SB2 = 3 mA
■2.0 V data retention
■Automatic power-down when deselected
■CMOS for optimum speed/power
■Independent control of upper and lower bits
■Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin thin small outline package (TSOP) II packages
Functional Description [1]
The CY7C1020D is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.The input and output pins
(IO0 through IO15) are placed in a high-impedance state when:
■Deselected (CE HIGH)
■Outputs are disabled (OE HIGH)
■BHE and BLE are disabled (BHE, BLE HIGH)
■When the write operation is active (CE LOW, and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A14). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A14).
Reading from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
32K x 16
RAM Array IO
0
–IO
7
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
IO
8
–IO
15
CE
WE
BLE
BHE
A
8
Logic Block Diagram
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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Document #: 38-05463 Rev. *G Page 2 of 15
Contents
Pin Configurations ............................................................3
Selection Guide ................................................................ 3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics..................................................4
Capacitance ....................................................................... 5
Thermal Resistance...........................................................5
AC Test Loads and Waveforms........................................5
Switching Characteristics................................................. 6
Data Retention Waveform ................................................7
Switching Waveforms ...................................................... 7
Truth Table ........................................................................9
Ordering Information...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
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Document #: 38-05463 Rev. *G Page 3 of 15
Pin Configurations[2]
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
NC
A
3
A
2
A
1
A
0
A
14
A
4
A
8
A
9
A
10
A
11
A
12
A
13
NC NC
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
Top View
SOJ/TSOP II
Selection Guide
–10 (Industrial) Unit
Maximum access time 10 ns
Maximum operating current 80 mA
Maximum CMOS standby current 3 mA
Note
2. NC pins are not connected on the die.
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CY7C1020D
Document #: 38-05463 Rev. *G Page 4 of 15
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ........................................... –55 C to +125 C
Supply voltage on VCC to Relative GND [3] ..–0.5 V to +6.0 V
DC voltage applied to outputs
in High Z State [3] ................................. –0.5 V to VCC + 0.5 V
DC input voltage [3].............................. –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage............................................>2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ...................................................... >200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40 °C to +85 °C 5 V 0.5 V 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
–10 (Industrial)
Unit
Min Max
VOH Output HIGH voltage IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage IOL = 8.0 mA – 0.4 V
VIH Input HIGH voltage – 2.2 VCC + 0.5V V
VIL Input LOW voltage [3] ––0.50.8V
IIX Input load current GND < VI < VCC –1 +1 A
IOZ Output leakage current GND < VI < VCC, output disabled –1 +1 A
ICC VCC operating supply current VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz – 80 mA
83 MHz – 72 mA
66 MHz – 58 mA
40 MHz – 37 mA
ISB1 Automatic CE power-down
current—TTL inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fmax
–10mA
ISB2 Automatic CE Power-Down
current—CMOS inputs
Max VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
–3mA
Note
3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
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Document #: 38-05463 Rev. *G Page 5 of 15
Capacitance [4]
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 5.0 V 8 pF
COUT Output capacitance 8 pF
Thermal Resistance [4]
Parameter Description Test Conditions SOJ TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52 53.91 C/W
JC Thermal resistance
(junction to case)
36.75 21.24 C/W
AC Test Loads and Waveforms [5]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: 3 ns Fall Time: 3 ns
30 pF*
OUTPUT
Z = 50
50
1.5V
(b)
(a)
5V
OUTPUT
5 pF
(c)
R1 480
R2
255
High-Z characteristics:
INCLUDING
JIG AND
SCOPE
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
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Document #: 38-05463 Rev. *G Page 6 of 15
Switching Characteristics (Over the Operating Range) [6]
Parameter Description –10 (Industrial) Unit
Min Max
Read Cycle
tpower [7] VCC(typical) to the first access 100 s
tRC Read cycle time 10 ns
tAA Address to data valid 10 ns
tOHA Data hold from address change 3 ns
tACE CE LOW to data valid 10 ns
tDOE OE LOW to data valid 5ns
tLZOE OE LOW to Low Z [9] 0ns
tHZOE OE HIGH to High Z [8, 9] 5ns
tLZCE CE LOW to Low Z [9] 3ns
tHZCE CE HIGH to High Z [8, 9] 5ns
tPU [10] CE LOW to power-up 0 ns
tPD [10] CE HIGH to power-down 10 ns
tDBE Byte enable to data valid 5 ns
tLZBE Byte enable to Low Z 0 ns
tHZBE Byte disable to High Z 5ns
Write Cycle [11, 12]
tWC Write cycle time 10 ns
tSCE CE LOW to write end 7 ns
tAW Address set-up to write end 7 ns
tHA Address hold from write end 0 ns
tSA Address set-up to write start 0 ns
tPWE WE pulse width 7 ns
tSD Data set-up to write end 6 ns
tHD Data hold from write end 0 ns
tLZWE WE HIGH to Low Z [9] 3ns
tHZWE WE LOW to High Z [8, 9] 5ns
tBW Byte enable to end of write 7 ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 5. Transition is measured when the
outputs enter a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write and
the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Max Unit
VDR VCC for data retention 2.0 V
ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
3mA
tCDR [13] Chip deselect to data retention time 0ns
tR [14] Operation recovery time tRC ns
Data Retention Waveform
Switching Waveforms
Figure 1. Read Cycle No.1 (Address Transition Controlled) [15, 16]
Figure 2. Read Cycle No.2 (OE Controlled) [16, 17]
4.5V4.5V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
ICC
HIGH
IMPEDANCE
ISB
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
BHE,BLE
CURRENT
Notes
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
15. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
16. WE is HIGH for read cycle.
17. Address valid prior to or coincident with CE transition LOW.
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Document #: 38-05463 Rev. *G Page 8 of 15
Figure 3. Write Cycle No. 1 (CE Controlled) [18, 19]
Figure 4. Write Cycle No. 2 (BLE or BHE Controlled) [18, 19]
Switching Waveforms(continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA IO
ADDRESS
CE
WE
BHE,BLE
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA IO
ADDRESS
BHE,BLE
WE
CE
Notes
18. Data IO is high impedance if OE or BHE and/or BLE= VIH.
19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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Document #: 38-05463 Rev. *G Page 9 of 15
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [20, 21]
Truth Table
CE OE WE BLE BHE IO0–IO7IO8–IO15 Mode Power
H X X X X High Z High Z Power-down Standby (ISB)
L L H L L Data out Data out Read – All bits Active (ICC)
L H Data out High Z Read – Lower bits only Active (ICC)
H L High Z Data out Read – Upper bits only Active (ICC)
L X L L L Data in Data in Write – All bits Active (ICC)
L H Data in High Z Write – Lower bits only Active (ICC)
H L High Z Data in Write – Upper bits only Active (ICC)
L H H X X High Z High Z Selected, outputs disabled Active (ICC)
L X X H H High Z High Z selected, outputs disabled Active (ICC)
Notes
20. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms(continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
DATA IO
ADDRESS
CE
WE
BHE,BLE
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Document #: 38-05463 Rev. *G Page 10 of 15
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
10 CY7C1020D-10VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1020D-10ZSXI 51-85087 44-pin TSOP Type II (Pb-free)
Ordering Code Definitions
Please contact your local Cypress sales representative for availability of these parts.
Temperature Range:
I = Industrial
Package Type: XXX = VX or ZSX
VX = 44-pin Molded SOJ (Pb-free)
ZSX = 44-pin TSOP Type II (Pb-free)
Speed: 10 ns
D = C9, 90 nm Technology
0 = Data width × 16-bits
02 = 512-Kbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 - 10 XXX702 ID0
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Acronyms
Document Conventions
Units of Measure
Acronym Description
BGA
ball grid array
CMOS complementary metal oxide semiconductor
FBGA very fine ball gird array
I/O input/output
TSOP thin small outline package
SRAM static random access memory
TTL Transistor transistor logic
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliampere
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
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Document #: 38-05463 Rev. *G Page 14 of 15
Document History Page
Document Title: CY7C1020D, 512K (32K x 16) Static RAM
Document #: 38-05463
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Data sheet for C9 IPP
*A 233695 See ECN RKF 1) DC parameters modified as per EROS (Spec # 01-0216)
2) Pb-free Offering in the ‘Ordering Information’
*B 263769 See ECN RKF 1) Corrected pin #18 on SOJ/TSOPII Pinout (Page #1) from A15 to A4
2) Changed IO1 - IO16 to IO0 - IO15 on the Pin-out diagram
3) Added Tpower Spec in Switching Characteristics Table
4) Added Data Retention Characteristics Table and Waveforms
5) Shaded ‘Ordering Information’
*C 307594 See ECN RKF Reduced Speed bins to –10, –12 and –15 ns
*D 560995 See ECN VKN Converted from Preliminary to Final
Removed Commercial Operating range
Removed 12 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3
*E 802877 See ECN VKN Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for
83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
*F 3109992 12/14/2010 AJU Added Ordering Code Definitions.
Updated Package Diagrams.
*G 3219056 04/07/2011 PRAS Added TOC
Added Acronyms and Units of Measure table.
Updated Datasheet as per template.
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Document #: 38-05463 Rev. *G Revised April 7, 2011 Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1020D
© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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