W78E516B 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The W78E516B is an 8-bit microcontroller which has an in-system programmable FLASH-ROM for firmware updating. The instruction set of the W78E516B is fully compatible with the standard 8052. The W78E516B contains a 64K bytes of main FLASH-ROM and a 4K bytes of auxiliary FLASH-ROM which allows the contents of the 64KB main FLASH-ROM to be updated by the loader program located at the 4KB auxiliary FLASH-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the FLASH-ROM inside the W78E516B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E516B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES * Fully static design 8-bit CMOS microcontroller up to 40 MHz. * 64K bytes of in-system programmable FLASH-ROM for Application Program (APROM). * 4K bytes of auxiliary FLASH-ROM for Loader Program (LDROM). * 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable) * 64K bytes program memory address space and 64K bytes data memory address space. * Four 8-bit bi-directional ports. * One 4-bit multipurpose programmable port. * Three 16-bit timer/counters * One full duplex serial port * Six-sources, two-level interrupt capability * Built-in power management * Code protection * Packaged in - DIP 40: W78E516B-24/40 - PLCC 44: W78E516BP-24/40 -1 - Publication Release Date: February 2000 Revision A3 W78E516B PIN CONFIGURATIONS 40-pin DIP (W78E516B) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS VDD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-pin PLCC (W78E516BP) T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 P1.5 P1.6 P1.7 RST RXD, P3.0 P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 T 2 , P 1 . 0 A D 0 , P P 4 V 0 . D . 2 D 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 10 36 35 11 34 12 13 33 32 14 15 31 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X V P P P P T S 4 2 2 2 A S . . . . L 0 0 1 2 1 , , , A A A 8 9 1 0 -2 - P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 W78E516B PIN DESCRIPTION SYMBOL TYPE DESCRIPTIONS EA I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high. PSEN O H PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. RST I L RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS I GROUND: ground potential. VDD I POWER SUPPLY: Supply voltage for operation. P0.0-P0.7 I/O D PORT 0: Function is the same as that of standard 8052. P1.0-P1.7 I/O H PORT 1: Function is the same as that of standard 8052. P2.0-P2.7 I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. P3.0-P3.7 I/O H PORT 3: Function is the same as that of the standard 8052. P4.0-P4.3 I/O H PORT 4: A bi-directional I/O. See details below. * Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, Example: P4 REG 0D8H MOV P4, #0AH MOV A, P4 SETB P4.0 ; Set bit P4.0 CLR P4.1 ; Clear bit P4.1 ; Output data "A" through P4.0-P4.3. ; Read P4 status to Accumulator. -3 - Publication Release Date: February 2000 Revision A3 W78E516B BLOCK DIAGRAM P1.0 Port 1 Port 1 Latch P1.7 ACC B P0.0 Port 0 Interrupt T1 Latch T2 P0.7 Timer 2 Timer 0 Port 0 DPTR Stack Pointer PSW ALU Temp Reg. Timer 1 PC Incrementor UART Addr. Reg. P3.0 Port 3 Port 3 Instruction Decoder & Sequencer Latch P3.7 SFR RAM Address 64KB 64KB FLASH MTP-ROM ROM 512 bytes RAM & SFR 4KB 4KB MTP-ROM FLASH ROM Port 2 Latch Bus & Clock Controller P4.0 P4.3 Port 4 P2.0 Port 2 P2.7 Port 4 Latch Oscillator XTAL1 XTAL2 Reset Block ALE PSEN RST Power control VCC Vss FUNCTIONAL DESCRIPTION The W78E516B architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three timer/counters, a serial port and an internal 74373 latch and 74244 buffer which can be switched to port2. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. RAM The internal data RAM in the W78E516B is 512 bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways. * RAM 0H-127H can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank. * RAM 128H-255H can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank. -4 - W78E516B * AUX-RAM 0H-255H is addressed indirectly as the same way to access external data memory with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than 255H will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD . Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. Clock The W78E516B is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E516B relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78E516B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts. Power Management Idle Mode Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered. Reduce EMI Emission -5 - Publication Release Date: February 2000 Revision A3 W78E516B The W78E516B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E516B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. W78E516B Special Function Registers (SFRs) and Reset Values F8 F0 FF +B 00000000 CHPENR 00000000 F7 E8 EF E0 +ACC 00000000 E7 D8 +P4 xxxx1111 DF D0 +PSW 00000000 D7 C8 +T2CON 00000000 C0 XICON 00000000 B8 +IP 00000000 B0 +P3 00000000 B7 A8 +IE 00000000 AF A0 +P2 11111111 A7 98 +SCON 00000000 90 +P1 11111111 88 +TCON 00000000 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 SFRAL 00000000 SFRAH 00000000 SBUF xxxxxxxx CF SFRFD 00000000 SFRCN 00000000 C7 CHPCON 0xx00000 BF 9F 97 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 -6 - TH1 00000000 8F W78E516B 80 +P0 11111111 SP 00000111 DPL 00000000 DPH 00000000 PCON 00110000 87 Notes: 1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers. Port 4 (D8H) BIT NAME FUNCTION 7 - Reserve 6 - Reserve 5 - Reserve 4 - Reserve 3 P43 Port 4 Data bit which outputs to pin P4.3. 2 P42 Port 4 Data bit. which outputs to pin P4.2. 1 P41 Port 4 Data bit. which outputs to pin P4.1. 0 P40 Port 4 Data bit which outputs to pin P4.0. In-System Programming (ISP) Mode The W78E516B equips one 64K byte of main FLASH-ROM bank for application program (called APROM) and one 4K byte of auxiliary FLASH-ROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78E516B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute. The W78E516B achieves all n i -system programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the device will clear the program counter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a software reset for switching back to APROM while the content of APROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The software reset serves as a external reset. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis. -7 - Publication Release Date: February 2000 Revision A3 W78E516B SFRAH, SFRAL: The objective address of on-chip FLASH-ROM in the in-system programming mode. SFRFAH contains the high-order byte of address, SFRFAL contains the low-order byte of address. SFRFD: The programming data for on-chip FLASH-ROM in programming mode. SFRCN: The control byte of on-chip FLASH-ROM programming mode. SFRCN (C7) BIT NAME 7 - 6 WFWIN FUNCTION Reserve. On-chip FLASH-ROM bank select for in-system programming. = 0: 64K bytes FLASH-ROM bank is selected as destination for reprogramming. = 1: 4K bytes FLASH-ROM bank is selected as destination for re-programming. 5 OEN FLASH-ROM output enable. 4 CEN FLASH-ROM chip enable. 3, 2, 1, 0 CTRL[3:0] The flash control signals WFWIN CTRL<3:0> OEN CEN SFRAH, SFRAL SFRFD Erase 64KB APROM MODE 0 0010 1 0 X X Program 64KB APROM 0 0001 1 0 Address in Data in Read 64KB APROM 0 0000 0 0 Address in Data out Erase 4KB LDROM 1 0010 1 0 X X Program 4KB LDROM 1 0001 1 0 Address in Data in Read 4KB LDROM 1 0000 0 0 Address in Data out In-System Programming Control Register (CHPCON) CHPCON (BFH) BIT 7 6 5 4 NAME FUNCTION SWRESET When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will (F04KMODE) enforce microcontroller reset to initial condition just like power on reset. This action will re-boot the microcontroller and start to normal operation. To read this bit in logic-1 can determine that the F04KBOOT mode is running. - Reserve. - Reserve. ENAUXRAM 1: Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM -8 - W78E516B 3 0 Must set to 0. 2 0 Must set to 0. 1 FBOOTSL The Program Location Select. 0: The Loader Program locates at the 64 KB APROM. 4KB LDROM is destination for re-programming. 1: The Loader Program locates at the 4 KB memory bank. 64KB APROM is destination for re-programming. -9 - Publication Release Date: February 2000 Revision A3 W78E516B CHPCON (BFH), continued BIT 0 NAME FUNCTION FPROGEN FLASH-ROM Programming Enable. = 1: enable. The microcontroller enter the in-system programming mode after entering the idle mode and wake-up from interrupt. During in-system programming mode, the operation of erase, program and read are achieve when device enters idle mode. = 0: disable. The on-chip flash memory is read-only. In-system programmability is disabled. F04KBOOT Mode (Boot From LDROM) By default, the W78E516B boots from APROM program after a power on reset. On some occasions, user can force the W78E516B to boot from the LDROM program via following settings. The possible situation that you need to enter F04KBOOT mode when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this F04KBOOT mode to force the W78E516B jumps to LDROM and executes in-system programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the APROM program fails to execute the normal application program. User can press both two buttons at the same time and then turn on the power of the personal computer to force the W78E516B to enter the F04KBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or F04KBOOT mode. F04KBOOT MODE P4.3 X L P2.7 L X P2.6 L X MODE FO4KBOOT FO4KBOOT The Reset Timing For Entering F04KBOOT Mode P2.7 Hi-Z P2.6 Hi-Z RST 30 mS 10 mS - 10 - W78E516B The Algorithm of In-System Programming Part 1:64KB APROM START procedure of entering In-System Programming Mode Enter In-System Programming Mode ? (conditions depend on user's application) No Yes Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Execute the normal application program Setting Timer (about 1.5 us) and enable timer interrupt END Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode) CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program. Go - 11 - Publication Release Date: February 2000 Revision A3 W78E516B Part 2: 4KB LDROM Go Procedure of Updating the 64KB APROM Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM Yes Yes Is F04KBOOT Mode? (CHPCON.7=1) End of Programming ? No No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) Yes Is currently in the F04KBOOT Mode ? No Get the parameters of new code Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) Setting erase operation mode: MOV SFRCN,#22H (Erase 64KB APROM) Start Timer and enter IDLE Mode. (Erasing...) (Address and data bytes) through I/O ports, UART or other interfaces. Software reset CPU and re-boot from the 64KB APROM. MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#83H Setting control registers for programming: Hardware Reset to re-boot from new 64 KB APROM. (S/W reset is invalid in F04KBOOT Mode) MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H End of erase operation. CPU will be wakened by Timer interrupt. END Executing new code from address 00H in the 64KB APROM. PGM - 12 - W78E516B SECURITY During the on-chip FLASH-ROM programming mode, the FLASH-ROM can be programmed and verified repeatedly. Until the code inside the FLASH-ROM is confirmed OK, the code can be protected. The protection of FLASH-ROM and those operations on it are described below. The W78E516B has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in programming mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The contents of the Company ID and Device ID registers have been set in factory. The Security Register is located at the 0FFFFH of the LDROM space. D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 1 0 1 0 0 1 1 0 0 0 1 0 0000h Company ID (#DAH) 4KB ROM 4KB FLASH MTP ROM Device ID (#62H) Program Memory LDROM 0FFFh B7 Reserved B2 B1 B0 Security Bits 64KB ROM 64KB FLASH MTP ROM B0: Lock bit, logic 0: active B1: MOVC inhibit, logic 0: the MOVC instruction in external memory cannot access the code in internal memory. logic 1: no restriction. B2: Encryption logic 0: the encryption logic enable logic 1: the encryption logic disable B07: Osillator Control logic 0: 1/2 gain logic 1: Full gain Default 1 for all security bits. Reserved bits must be kept in logic 1. Program Memory APROM Reserved Reserved Security Register FFFFh Special Setting Registers Lock bit This bit is used to protect the customer's program code in the W78E516B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the FLASH ROM data and Special Setting Registers can not be accessed again. MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will - 13 - Publication Release Date: February 2000 Revision A3 W78E516B reset this bit. - 14 - W78E516B Oscillator Control W78E516B/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT VDD-VSS -0.3 +6.0 V Input Voltage VIN VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 C Storage Temperature TST -55 +150 C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. D.C. ELECTRICAL CHARACTERISTICS (V DD-V SS = 5V 10%, TA = 25C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER SYM. SPECIFICATION TEST CONDITIONS MIN. MAX. UNIT Operating Voltage VDD 4.5 5.5 V Operating Current IDD - 20 mA RST = 1, P0 = VDD No load VDD = 5.5V Idle Current IIDLE - 6 mA Idle mode VDD = 5.5V Power Down Current IPWDN - 50 A Power-down mode VDD = 5.5V Input Current IIN1 -50 +10 A P1, P2, P3, P4 Input Current VIN = 0V or VDD IIN2 -10 +300 A RST Input Leakage Current ILK -10 +10 A VDD = 5.5V 0V< VIN < VDD ITL [*4] -500 - A P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA VDD = 5.5V 0< VIN