NAND Flash Memory

MT29F64G08CBAA[A/B], MT29F128G08C[E/F]AAA, MT29F128G08CFAAB,

MT29F256G08C[J/K/M]AAA, MT29F256G08CJAAB, MT29F512G08CUAAA,

MT29F64G08CBCAB, MT29F128G08CECAB, MT29F256G08C[K/M]CAB,

Features

• Open NAND Flash Interface (ONFI) 2.2-compliant1

• Multiple-level cell (MLC) technology

• Organization

512Gb: 32,786 blocks

• Synchronous I/O performance

– Up to synchronous timing mode 52

– Clock rate: 10ns (DDR)

– Read/write throughput per pin: 200 MT/s

• Asynchronous I/O performance

– Up to asynchronous timing mode 5

– Up to asynchronous timing mode 5

– Read/write throughput per pin: 50 MT/s

– VCCQ: 1.7–1.95V, 2.7–3.6V

• Command set: ONFI NAND Flash Protocol

• Advanced Command Set

– Program cache

– Read cache sequential

– Read cache random

– One-time programmable (OTP) mode

– Multi-plane commands

– Multi-LUN operations

– Read unique ID

• Operation status byte provides software method for

– Operation completion

– Pass/fail condition

– Write-protect status

• Data strobe (DQS) signals provide a hardware meth-

od for synchronizing data DQ in the synchronous

interface

• Copyback operations supported within the plane

from which data is read

– Industrial (IT): –40ºC to +85ºC

• Package

– 52-pad LGA

– 48-pin TSOP

– 100-ball BGA

Notes: 1. The ONFI 2.2 specification is available at

www.onfi.org.

2. BGA devices up to Synchronous timing

mode 5. TSOP devices up to Synchronous

timing mode 4.

Part Numbering Information

Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by

using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,

visit www.micron.com/products. Contact the factory for devices not found.

Figure 1: Part Numbering

Note: 1. Pb-free package.

General Description ......................................................................................................................................... 9

Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9

Signal Assignments ......................................................................................................................................... 11

Package Dimensions ....................................................................................................................................... 15

Architecture ................................................................................................................................................... 20

PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 95

List of Tables

Table 1: Asynchronous and Synchronous Signal Definitions .............................................................................. 9

Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 27

Table 3: Asynchronous Interface Mode Selection ............................................................................................ 28

Table 4: Synchronous Interface Mode Selection .............................................................................................. 38

Table 5: Command Set .................................................................................................................................. 50

List of Figures

Figure 1: Part Numbering ................................................................................................................................ 2

Figure 2: 48-Pin TSOP Type 1 (Top View) ........................................................................................................ 11

Figure 3: 52-Pad LGA (Top View) .................................................................................................................... 12

Figure 4: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 13

Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................. 15

Figure 60: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation .................................................................... 98

Figure 112: COPYBACK (1 of 3) ..................................................................................................................... 158

General Description

mains the same from one density to another, enabling future upgrades to higher densi-

ties with no board redesign.

Asynchronous and Synchronous Signal Descriptions

Table 1: Asynchronous and Synchronous Signal Definitions

Signal1

WE# CLK Input Write enable and clock: WE# transfers commands, addresses, and seri-

WP# WP# Input Write protect: Enables or disables array PROGRAM and ERASE opera-

R/B# R/B# Output Ready/busy: An open-drain, active-low output that requires an exter-

Architecture

and cache registers act as a single register. During cache operations, the data and cache

registers operate independently to increase data throughput.

Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active.

2. Some devices do not include the synchronous interface.

Device and Array Organization

DQ[7:0] DQ[7:0]

N/A DQS

WP# WP#

LUN 1

Target 1

Figure 12: Device Organization for Two-Die Package (TSOP)

LUN 1

Target 1

LUN 1

Target 2

Note: 1. LGA devices do not support the synchronous interface.

Asynchronous Data Output

Data can be output from a die (LUN) if it is in a READY state. Data output is supported

following a READ operation from the NAND Flash array. Data is output from the cache

register of the selected die (LUN) to DQ[7:0] on the falling edge of RE# when CE# is

LOW, ALE is LOW, CLE is LOW, and WE# is HIGH.

If the host controller is using a tRC of 30ns or greater, the host can latch the data on the

The combination of Rp and capacitive loading of the R/B# circuit determines the rise

2. tRise dependent on external capacitance and resistive loading and output transistor im-

3. tRise primarily dependent on external pull-up resistor and external capacitive loading.

4. tFall = 10ns at 3.3V

5. See TC values in Figure 29 (page 37) for approximate Rp value and TC.

Figure 26: tFall and tRise (VCCQ = 1.7-1.95V)

2. tRise is primarily dependent on external pull-up resistor and external capacitive loading.

3. tFall ≈ 7ns at 1.8V.

4. See TC values in Figure 29 (page 37) for TC and approximate Rp value.

Rp (Ω)

I (mA)

Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V)

Bus Operation – Synchronous Interface

The NAND Flash command protocol for both the asynchronous and synchronous inter-

When the synchronous interface is activated on a target (see Activating Interfaces), the

comes W/R#. CLK provides a clock reference to the NAND Flash device.

The direction of DQS and DQ[7:0] is controlled by the W/R# signal. When the W/R# sig-

nal is latched HIGH, the controller is driving the DQ bus and DQS. When the W/R# is

latched LOW, the NAND Flash is driving the DQ bus and DQS.

Table 4: Synchronous Interface Mode Selection

Notes: 1. CLK can be stopped when the target is disabled, even when R/B# is LOW.

2. WP# should be biased to CMOS LOW or HIGH for standby.

3. Commands and addresses are latched on the rising edge of CLK.

register.

5. During data output from the NAND Flash device, DQS is an output generated from CLK

Before enabling a target, CLK must be running and ALE and CLE must be LOW. When

CE# is driven LOW, all of the signals for the selected target are enabled. The target is not

enabled until tCS completes; the target's bus is then idle.

Prior to disabling a target, the target's bus must be idle. A target is disabled when CE# is

driven HIGH, even when it is busy. All of the target's signals are disabled except CE#,

WP#, and R/B#. After the target is disabled, CLK can be stopped.

A target enters low-power standby when it is disabled and is not busy. If the target is

busy when it is disabled, the target enters standby after all of the die (LUNs) complete

their operations.

Synchronous Bus Idle/Driving

mode, the only valid bus modes supported are: bus driving, command, address, and

DDR data input.

The bus is driving when W/R# transitions LOW and is latched by CLK. During the bus

driving mode, all signals are enabled; DQS is LOW and DQ[7:0] is driven LOW or HIGH,

but no valid data is output. Following the bus driving mode, the only valid bus modes

supported are bus idle and DDR data output.

Note: 1. Only the selected die (LUN) drives DQS and DQ[7:0]. During an interleaved die (multi-

LUN) operation, the host must use the READ STATUS ENHANCED (78h) to prevent data

output contention.

Synchronous Commands

A command is written from DQ[7:0] to the command register on the rising edge of CLK

when CE# is LOW, ALE is LOW, CLE is HIGH, and W/R# is HIGH.

After a command is latched—and prior to issuing the next command, address, or

data I/O—the bus must go to bus idle mode on the next rising edge of CLK, except

Activating Interfaces

Each target's interface is independent of other targets, so the host is responsible for

changing the interface for each target.

synchronize the interfaces.

Activating the Asynchronous Interface

To activate the asynchronous NAND interface, once the synchronous interface is active,

the following steps are repeated for each target:

1. The host pulls CE# HIGH, disables its input to CLK, and enables its asynchronous

interface.

2. The host pulls CE# LOW and issues the RESET (FFh) command, using an asyn-

chronous command cycle.

3. R/B# goes LOW for tRST.

4. After tITC, and during tRST, the device enters the asynchronous NAND interface.

Activating the Synchronous Interface

To activate the synchronous NAND Flash interface, the following steps are repeated for

each target:

1. Issue the SET FEATURES (EFh) command.

2. Write address 01h, which selects the timing mode.

3. Write P1 with 1Xh, where "X" is the timing mode used in the synchronous inter-

face (see Configuration Operations).

4. Write P2–P4 as 00h-00h-00h.

5. R/B# goes LOW for tITC. The host should pull CE# HIGH. During tITC, the host

should not issue any type of command, including status commands, to the NAND

CE# may

Note: 1. TM = Timing mode.