BLF8G10LS-300PJ - NXP Semiconductors

1. Product profile

1.1 General description

300 W LDMOS power transistor for base station applications at frequencies from

700 MHz to 1000 MHz.

[1] Test signal: 3GPP test model 1; 1 to 64 DPCH; PAR = 7.2 dB at 0.01 % probability on CCDF per carrier;

carrier spacing 5 MHz.

1.2 Features and benefits

Excellent ruggedness

High efficiency

Low thermal resistance providing excellent thermal stability

Lower output capacitance for improved performance in Doherty applications

Designed for low memory effects providing excellent pre-distortability

Internally matched for ease of use

Integrated ESD protection

Compliant to Restriction of Hazardous Substances (RoHS) Directive 2002/95/EC

1.3 Applications

RF power amplifier for multi standards and multi carrier applications in the 700 MHz to

1000 MHz frequency range

BLF8G10LS-300P

Power LDMOS transistor

Rev. 3 — 1 September 2015 Product data sheet

Table 1. Typical performance

Ty pical RF performance at Tcase = 25



C in a common source class-AB production test circuit.

Test signal f VDS PL(AV) GpDACPR

(MHz) (V) (W) (dB) (%) (dBc)

2-carrier W-CDMA 758 to 803 28 65 20.5 32 35 [1]

Product data sheet Rev. 3 — 1 September 2015 2 of 13

BLF8G10LS-300P

Power LDMOS transistor

2. Pinning information

[1] Connected to flange.

3. Ordering information

4. Limiting values

[1] Continuous use at maximum temperature will affect the reliability, for details refer to the on-line MTF

calculator

5. Thermal characteristics

Table 2. Pinning

Pin Description Simplified outline Graphic symbol

1drain1

2drain2

3gate1

4gate2

5source [1]

sym117

Table 3. Ordering information

Type number Package

Name Description Version

BLF8G10LS-300P - earless flanged balanced ceramic package; 4 leads SOT539B

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage - 65 V

VGS gate-source voltage 0.5 +13 V

Tstg storage temperature 65 +150 C

Tjjunction temperature [1] - 225 C

Table 5. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-case) thermal resistance from junction to case Tcase =80C; PL= 65 W 0.29 K/W

Product data sheet Rev. 3 — 1 September 2015 3 of 13

BLF8G10LS-300P

Power LDMOS transistor

6. Characteristics

7. Test information

7.1 Ruggedness in class-AB operation

The BLF8G10LS-300P is capable of withstanding a load mismatch corresponding to

VSWR = 10 : 1 through all phases under the following conditions: VDS =28V;

IDq = 2000 mA; PL= 65 W (2-carrier W-CDMA); f = 758 MHz.

Table 6. DC characteristics

Tj = 25



C; values per section unless otherwise specifie d.

Symbol Parameter Conditions Min Typ Max Unit

V(BR)DSS drain-source breakdown

voltage

VGS =0V; I

D=2.2mA 65 - - V

VGS(th) gate-source threshold voltage VDS =20 V; I

D= 220 mA 1.5 1.9 2.3 V

VGSq gate-source quiescent voltage VDS =28 V;

ID= 1000 mA

-2.0-V

IDSS drain leakage current VGS =0V; V

DS =28V - - 2.4 A

IDSX drain cut-off current VGS =V

GS(th) + 3.75 V;

VDS =20V

-38.1-A

IGSS gate leakage current VGS =11V; V

DS = 0 V - - 240 nA

gfs forward transconductance VDS =20V; I

D=11A - 15.0 - S

RDS(on) drain-source on-state

resistance

VGS =V

GS(th) + 3.75 V;

ID=7.7A

-0.086-

Table 7. RF characteristics

Test signal: 2-carrier W-CDMA; PAR = 7.2 dB at 0.01 % probability on CCDF; 3GPP test model 1;

1 to 64 DPCH; f1= 760.5 MHz; f2= 765.5 MHz; f 3= 795.5 MHz; f4= 800.5 MHz; RF performance at

VDS = 28 V; IDq = 2000 mA; Tcase =25



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Gppower gain PL(AV) = 65 W 19.5 20.5 - dB

RLin input return loss PL(AV) = 65 W - 12 8dB

Ddrain efficiency PL(AV) = 65 W 28 32 - %

ACPR adjacent channel power ratio PL(AV) = 65 W - 35 32 dBc

Product data sheet Rev. 3 — 1 September 2015 4 of 13

BLF8G10LS-300P

Power LDMOS transistor

7.2 Impedance information

[1] ZS and ZL defined in Figure 1.

Table 8. Typical impedance

Measured load-pull data per section; IDq = 1000 mA; VDS = 28 V

f ZS[1] ZL[1] PL(3dB)

(MHz) () ()(W)

720 2.3  j2.8 1.6  j2.7 204.4

746 2.5  j3.2 1.7 j2.6 220.0

757 2.3  j3.6 1.6  j2.5 225.2

769 2.6  j3.6 1.7  j2.4 227.9

791 2.6  j3.9 1.5  j2.8 214.8

805 2.6  j3.9 1.8  j2.3 207.2

820 2.7  j4.2 1.6  j2.1 228.5

869 2.8  j4.1 1.2  j2.1 217.2

881 2.9  j4.4 1.2  j2.1 219.9

894 3.3  j4.7 1.1  j2.1 215.4

925 3.6  j5.2 1.2  j2.1 223.5

942 4.1 j 5.7 1.1  j2.2 220.5

960 4.7  j5.9 1.1  j2.2 218.8

Fig 1. Definition of transistor impedance

001aaf059

drain

gate

Product data sheet Rev. 3 — 1 September 2015 5 of 13

BLF8G10LS-300P

Power LDMOS transistor

7.3 Test circuit

7.4 Graphical data

Following are typical RF measurements of the BLF8G10LS-300P in its class-AB test

circuit.

Printed-Circuit Board (PCB): Rogers RO4350; r = 3.66 F/m; thickness = 0.76 mm;

thickness copper plating = 35 m

See Table 9 for list of components.

Fig 2. Component layout

Table 9. List of components

See Figure 2 for component layout.

Component Description Value Remarks

C1, C2 multilayer ceramic chip capacitor 82 pF ATC 800B

C3, C6, C9 multilayer ceramic chip capacitor 10 F, 50 V Murata

C4, C5, C8 multilayer ceramic chip capacitor 82 pF ATC 100B

C7 electrolytic capacitor 470 F, 63 V

R1 chip resistor 4.7 SMD 1206

aaa-010381

60 mm

70 mm 70 mm

C1 C2

Product data sheet Rev. 3 — 1 September 2015 6 of 13

BLF8G10LS-300P

Power LDMOS transistor

7.4.1 CW pulsed

VDS = 28 V; IDq = 2000 mA; tp= 100 s: = 10 %.

(1) f = 758 MHz

(2) f = 780.5 MHz

(3) f = 803 MHz

VDS = 28 V; IDq = 2000 mA; tp= 100 s: = 10 %.

(1) f = 758 MHz

(2) f = 780.5 MHz

(3) f = 803 MHz

Fig 3. Power gain as a function of output power;

typical values

Fig 4. Drain efficiency as a function of output power;

typical values

VDS = 28 V; IDq = 2000 mA; tp= 100 s: = 10 %.

(1) f = 758 MHz

(2) f = 780.5 MHz

(3) f = 803 MHz

Fig 5. Input return loss as a function of output power; typical values

aaa-010348

0 50 100 150 200 250 300 350 400

PL (W)

(dB)(dB)(dB)

(3)(3)(3)

(2)(2)(2)

(1)(1)(1)

aaa-010349

0 50 100 150 200 250 300 350 400

PL (W)

ηD

(%)(%)(%)

(3)(3)(3)

(2)(2)(2)

(1)(1)(1)

aaa-010350

0 50 100 150 200 250 300 350 400

-26

-22

-18

-14

-10

PL (W)

RLinin

RLin

(dB)(dB)(dB)

(1)(1)(1)

(2)

(2)(2)

(3)

(3)(3)

Product data sheet Rev. 3 — 1 September 2015 7 of 13

BLF8G10LS-300P

Power LDMOS transistor

7.4.2 1-Carrier W-CDMA

VDS = 28 V; IDq = 2000 mA.

(1) f = 758 MHz

(2) f = 803 MHz

VDS = 28 V; IDq = 2000 mA.

(1) f = 758 MHz

(2) f = 803 MHz

Fig 6. Power gain as a function of output power;

typical values

Fig 7. Drain efficiency as a function of output power;

typical values

VDS = 28 V; IDq = 2000 mA.

(1) f = 758 MHz

(2) f = 803 MHz

Fig 8. Adjacent channel power ratio (5 MHz) as a function of output power; typical values

aaa-010351

0 20 40 60 80 100 120 140 160

PL (W)

(dB)(dB)(dB)

(1)(1)(1)

(2)(2)(2)

aaa-010352

0 20 40 60 80 100 120 140 160

PL (W)

ηD

(%)(%)(%)

(1)(1)(1)

(2)(2)(2)

aaa-010353

0 20 40 60 80 100 120 140 160

-50

-45

-40

-35

-30

-25

-20

PL (W)

ACPR

ACPR5M5M

ACPR5M

(dBc)(dBc)(dBc)

(1)(1)(1)

(2)(2)(2)

Product data sheet Rev. 3 — 1 September 2015 8 of 13

BLF8G10LS-300P

Power LDMOS transistor

7.4.3 2-Carrier W-CDMA

VDS = 28 V; IDq = 2000 mA.

(1) f = 758 MHz

(2) f = 803 MHz

VDS = 28 V; IDq = 2000 mA.

(1) f = 758 MHz

(2) f = 803 MHz

Fig 9. Power gain as a function of output power;

typical values

Fig 10. Drain efficiency as a function of output power;

typical values

VDS = 28 V; IDq = 2000 mA.

(1) f = 758 MHz

(2) f = 803 MHz

Fig 11. Adjacent channel power ratio (5 MHz) as a function of output power; typical values

aaa-010354

0 20 40 60 80 100 120 140 160

PL (W)

(dB)(dB)(dB)

(1)(1)(1)

(2)(2)(2)

aaa-010355

0 20 40 60 80 100 120 140 160

PL (W)

ηD

(%)(%)(%)

(1)(1)(1)

(2)(2)(2)

aaa-010356

0 20 40 60 80 100 120 140 160

-50

-45

-40

-35

-30

-25

-20

PL (W)

ACPR

ACPR5M5M

ACPR5M

(dBc)(dBc)(dBc)

(1)(1)(1)

(2)(2)(2)

Product data sheet Rev. 3 — 1 September 2015 9 of 13

BLF8G10LS-300P

Power LDMOS transistor

8. Package outline

Fig 12. Package outline SOT539B

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT539B

sot539b_po

12-05-02

13-05-24

Unit(1)

max

nom

min

4.7

4.2

11.81

11.56

31.55

30.94

31.52

30.96

9.5

9.3

9.53

9.27

1.75

1.50

17.12

16.10

3.48

2.97

10.29

10.03

0.25

Dimensions

Earless flanged balanced ceramic package; 4 leads SOT539B

0.18

0.10

1EE

13.72

FHH

25.53

25.27

2.26

2.01

32.39

32.13

U2w2

0.25

inches

max

nom

min

0.185

0.165

0.465

0.455

1.242

1.218

1.241

1.219

0.374

0.366

0.375

0.365

0.069

0.059

0.674

0.634

0.137

0.117

0.405

0.395

0.01

0.007

0.004

0.54

1.005

0.995

0.089

0.079

1.275

1.265

0.01

0 5 10 mm

scale

Dw2

1 2

3 4

Note

1. millimeter dimensions are derived from the original inch dimensions.

Product data sheet Rev. 3 — 1 September 2015 10 of 13

BLF8G10LS-300P

Power LDMOS transistor

9. Handling information

10. Abbreviations

11. Revision history

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

Table 10. Abbreviations

Acronym Description

3GPP 3rd Generation Partnership Project

CCDF Complementary Cumulative Distribution Function

CW Continuous Wave

DPCH Dedicated Physical CHannel

ESD ElectroStatic Discharge

LDMOS Laterally Diffused Metal-Oxide Semiconductor

MTF Median Time to Failure

PAR Peak-to-Average Ratio

SMD Surface Mounted Device

VSWR Voltage Standing-Wave Ratio

W-CDMA Wideband Code Division Multiple Access

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

BLF8G10LS-300P#3 20150901 Product data sheet - BLF8G10LS-300P v.2

Modifications: •The format of this document has been redesigned to comply with the new identity

guidelines of Ampleon.

•Legal texts have been adapted to the new company name where appropriate.

BLF8G10LS-300P v.2 20131217 Product data sheet - BLF8G10LS-300P v.1

BLF8G10LS-300P v.1 20131118 Objective data sheet - -

Product data sheet Rev. 3 — 1 September 2015 11 of 13

BLF8G10LS-300P

Power LDMOS transistor

12. Legal information

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[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.ampleon.com.

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Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Ampleon does not give any representations or

warranties as to the accuracy or completeness of information included herein

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Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

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case of any inconsistency or conflict with the short data sheet, the full data

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Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

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subject to the general terms and conditions of commercial sale, as published

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Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 3 — 1 September 2015 12 of 13

BLF8G10LS-300P

Power LDMOS transistor

Non-automotive qualified products — Unless this data sheet expressly

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13. Contact information

For more information, please visit:

http://www.ampleon.com

For sales office addresses, please visit:

http://www.ampleon.com/sales

BLF8G10LS-300P

Power LDMOS transistor

For more information, please visit: http://www.ampleon.com

For sales office addresses, please visit: http://www.ampleon.com/sales

Date of release: 1 September 2015

Document identifier: BLF8G10LS-300P#3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

14. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . 2

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 3

7.1 Ruggedness in class-AB operation . . . . . . . . . 3

7.2 Impedance information . . . . . . . . . . . . . . . . . . . 4

7.3 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.4 Graphical data . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.4.1 CW pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.4.2 1-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 7

7.4.3 2-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 8

8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

9 Handling information. . . . . . . . . . . . . . . . . . . . 10

10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10

11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11

12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11

12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13 Contact information. . . . . . . . . . . . . . . . . . . . . 12

14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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