512K x 24 Static RAM
CY7C1012AV33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05254 Rev. *D Revised November 12, 2002
Features
• High speed
—tAA = 8, 10, 12 ns
• Low active power
—1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic pow er -do wn wh en dese lec ted
• TTL-compatible inputs and outputs
• Easy memory expans ion with CE0, CE1 and CE2
features
Functional Description
The CY7C1012A V33 is a high-performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is
separa tel y control led by th e indi vidua l chi p sel ect s (CE 0, CE1,
CE2). CE0 controls the data on the I/O0–I/O7, while CE1
controls the data on I/O8–I/O15, and CE2 controls the data on
the data pins I/O16–I/O23. This device has an automatic
power-down feature that significantly reduces power
co nsumption when desel ected.
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the a ddre ss pi ns (A0–A18). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output en able (OE) remains L OW . Unde r these co nditions, the
conten ts of th e memory location sp ecified o n the addre ss pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7 C1012A V 33 is availabl e in a standa rd 1 19 -ball BGA.
Selection Guide
–8–10 –12 Unit
Maxi mu m A cc es s Ti me 8 10 12 ns
Maximum Operat ing Curre nt Comme rci al 300 275 260 mA
Industrial 300 275 260
Maximum CMOS Standby Current Commercial/Industrial 50 50 50 mA
Functional Block Diagram
15
16
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
512K x 24
ARRAY
A0
A12
A14
A13
A
A
A17
A18
A10
A11
4096 x 4096
I/O0–I/O7
OE
I/O8–I/O15
CE0, CE1, CE 2
WE
A9
I/O16–I/O23
CONTROL LOGIC
CY7C1012AV33
Document #: 38-05254 Rev. *D Page 2 of 9
Pin Configurations
119 BGA
Top View
1234567
ANCAAAAANC
BNC A A CE0 AANC
CI/O12 NC CE1 NC CE2 NC I/O0
DI/O13 VDD VSS VSS VSS VDD I/O1
EI/O14 VSS VDD VSS VDD VSS I/O2
FI/O15 VDD VSS VSS VSS VDD I/O3
GI/O16 VSS VDD VSS VDD VSS I/O4
HI/O17 VDD VSS VSS VSS VDD I/O5
JNC VSS VDD VSS VDD VSS DNU
KI/O18 VDD VSS VSS VSS VDD I/O6
LI/O19 VSS VDD VSS VDD VSS I/O7
MI/O20 VDD VSS VSS VSS VDD I/O8
NI/O21 VSS VDD VSS VDD VSS I/O9
PI/O22 VDD VSS VSS VSS VDD I/O10
RI/O23 ANCNCNCAI/O
11
TNC A A WE AANC
UNC A A OE AANC
CY7C1012AV33
Document #: 38-05254 Rev. *D Page 3 of 9
Maximum Ratings
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] ....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C3.3V ± 0.3V
Industrial –40°C to +85°C
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions[2] –8–10 –12 UnitMin. Max. Min. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC
+ 0.3 2.0 VCC
+ 0.3 2.0 VCC
+ 0.3 V
VIL[1] Input LOW Voltage –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1+1–1+1–1+1µA
IOZ Output Leakage Cu rrent GND < VOUT < VCC, Output Disabled –1+1–1+1–1+1µA
ICC VCC Operating
Supply Current VCC = Max.,
f = fMAX = 1/tRC Commercial 300 275 260 mA
Industrial 300 275 260 mA
ISB1 Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
100 100 100 mA
ISB2 Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3 V,
or VIN < 0.3V, f = 0
Commercial
/Industrial 50 50 50 mA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
COUT I/O Capacitance 10 pF
Notes:
1. VIL (min.) = –2.0V for p ulse dura tions of less than 20 ns.
2. CE refers to a combination of CE0, CE1, and CE2. CE is active LOW when all three of these signals are active LOW at the same time.
3. Tested initially and after any design or process changes that may affect these parameters.
CY7C1012AV33
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AC Test Loads and Waveforms[4]
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
R1 317 Ω
R2
351Ω
Rise time > 1 V/ns Fall time:
> 1 V/ns
(c)
OUTPUT 50Ω
Z0= 50Ω
VTH = 1.5V
30 pF*
* Capacitive Load consists of all compo-
nents of the test environment.
AC Switching Characteristics Over the Operating Range [5]
Parameter Description
–8–10 –12
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
tpower[6] VCC(typical) to the first access 1 1 1 ms
tRC Read Cycle Time 8 10 12 ns
tAA Address to Data Valid 8 10 12 ns
tOHA Data Hold from Address Change 3 3 3 ns
tACE CE1, CE2, and CE3 LOW to Data Valid 8 10 12 ns
tDOE OE LOW to Data Valid 5 5 6 ns
tLZOE OE LOW to Low-Z[7] 111 ns
tHZOE OE HIGH to High-Z[7] 556ns
tLZCE CE1, CE2, and CE3 LOW to Low-Z[7] 333 ns
tHZCE CE1, CE2, or CE3 HIGH to High-Z[7] 556ns
tPU CE1, CE2, and CE3 LOW to Power-up[8] 000 ns
tPD CE1, CE2, or CE3 HIGH to Power-down[8] 81012ns
tDBE Byte Enable to Data Valid 5 5 6 ns
tLZBE Byte Enable to Low-Z[7] 111 ns
tHZBE Byte Disable to High-Z[7] 556ns
Write Cycle[9, 10]
tWC Write Cycle Time 8 10 12 ns
tSCE CE1, CE2, and CE3 LOW to Write End 6 7 8 ns
Notes:
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching
the minimum operating VDD , normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V , and outpu t loadin g of the spec ified
IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless s peci fie d ot her wis e.
6. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation
is started.
7. tHZOE, tHZCE, tHZWE, t HZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC T est Loads. Transition is measured
±200 mV from steady-state voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal write time of the memory is defined by the overlap of CE1, CE2, and CE3 LOW and WE LOW. The chip enables must be active and WE must
be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to
the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1012AV33
Document #: 38-05254 Rev. *D Page 5 of 9
tAW Address Set-up to Write End 6 7 8 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-up to Write Start 0 0 0 ns
tPWE WE Pulse Width 678 ns
tSD Data Set-up to Write End 5 5.5 6 ns
tHD Data Hold from Write End 0 0 0 ns
tLZWE WE HIGH to Low-Z[7] 333 ns
tHZWE WE LOW to High-Z[7] 556ns
tBW Byte Enable to End of Write 6 7 8 ns
AC Switching Characteristics Over the Operating Range (continued)[5]
Parameter Description
–8–10 –12
UnitMin. Max. Min. Max. Min. Max.
Switching Waveforms
Read Cycle No. 1[11, 12]
Read Cycle No. 2 (OE Controlled)[2, 12, 13]
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE t ransiti on LOW.
PREVIOUS DATA VALID DATA VALI D
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VA LID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDAN C E
tHZOE tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
CY7C1012AV33
Document #: 38-05254 Rev. *D Page 6 of 9
Write Cycle No. 1 (CE Controlled)[2, 14, 15]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
Write Cycle No. 3 (WE Controlled, OE LOW)[2, 15 ]
Notes:
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simult aneously wi th WE goin g HIGH, the o utput remains i n a hig h-imped ance st ate.
16. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 16
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 16
CY7C1012AV33
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Truth Table
CE0CE1CE2OE WE I/O0–I/O23 Mode Power
H H H X X High-Z Power-down Standby (ISB)
L H H L H I/O0–I/O7 Data Out Read Active (ICC)
H L H L H I/O8–I/O15 Data Out Read Active (ICC)
H H L L H I/O16–I/O23 Data Out Read Active (ICC)
L L L L H Full Da ta Out Read Active (ICC)
L H H X L I/O0–I/O7 Data In Write Active (ICC)
H L H X L I/O8–I/O15 Data In Write Active (ICC)
H H L X L I/O16–I/O23 Data In Write Active (ICC)
L L L X L Full Data In Write Active (ICC)
L L L H H High-Z Sele ct ed, Ou tputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
8 CY7C1012AV33-8BGC BG119 14 × 22 mm 119-ball BGA Commercial
CY7C1012AV33-8BGI Industrial
10 CY7C1012AV33-10BGC Commercial
CY7C1012AV33-10BGI Industrial
12 CY7C1012AV33-12BGC Commercial
CY7C1012AV33-12BGI Industrial
CY7C1012AV33
Document #: 38-05254 Rev. *D Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
All product and company names mentioned in this document may be the trademarks of their respective holders.
51-85115-*B
119-ball PBGA (14 x 22 x 2.4 mm) BG119
CY7C1012AV33
Document #: 38-05254 Rev. *D Page 9 of 9
Document History Page
Document Title: CY7C1012AV33 512K x 24 Static RAM
Document Number: 38-05254
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 113711 03/11/02 NSL New Data Sheet
*A 117057 07/31/02 DFP Removed 15-ns bin.
*B 117988 09/03/02 DFP Added 8-ns bin.
*C 118992 09/19/02 DFP Change Cin - input capacitance -from 6 pF to 8 pF.
Change Cout -output capacitance from 8 pF to 10 pF.
*D 120382 11/15/02 DFP Final data sheet. Added note 4 to “AC Test Loads and Waveforms.”
