IRLR024Z
IRLU024Z
HEXFET® Power MOSFET
VDSS = 55V
RDS(on) = 58mΩ
ID = 16A
06/21/04
www.irf.com 1
AUTOMOTIVE MOSFET
PD - 95825A
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating tempera-
ture, fast switching speed and improved repetitive avalanche
rating . These features combine to make this design an extremely
efficient and reliable device for use in Automotive applications and
a wide variety of other applications.
S
D
G
Description
Features
nLogic Level
nAdvanced Process Technology
nUltra Low On-Resistance
n175°C Operating Temperature
nFast Switching
nRepetitive Avalanche Allowed up to Tjmax
D-Pak
IRLR024Z I-Pak
IRLU024Z
HEXFET® is a registered trademark of International Rectifier.
Absolute Maximum Ratings
Parameter Units
I
D
@ T
C
= 25°C Contin uous Drain Current, VGS @ 10V (Silicon Limited)
I
D
@ T
C
= 100°C Contin uous Drain Current, VGS @ 10V A
I
DM
Pu ls ed D rain C ur rent
c
P
D
@T
C
= 25°C Power Dissipation W
Li ne ar D erating Factor W/°C
V
GS
Gate- to- S our c e Voltage V
EAS (Thermally limited) Si ngle Pulse Av alanc he E n er g y
d
mJ
EAS (Tested ) Single Pulse Avalanche Energy Tested Value
h
IAR Avalanche Current
c
A
EAR Repeti ti ve Avalanche Ener gy
g
mJ
T
J
Ope r ating J unc t ion and
T
STG
Storage Tem perature Range °C
Soldering Temperature, for 10 seconds
Therm al Resi stance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 4.28
RθJA Junction- to-Am bient ( PC B mo unt)
i
––– 40 °C/W
RθJA Junction-to-Ambient ––– 110
Max.
16
11
64
-5 5 t o + 17 5
300 ( 1.6m m f r o m ca se )
35
0.23
± 16
25
25
See Fig.12a, 12b, 15, 16
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S
D
G
S
D
G
Electrical Characteristics @ T
J
= 25 ° C (u n l es s o t h e rw i s e sp ec i f i ed)
Parameter Min. Typ. Max. Units
V
(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V
∆
V
(BR)DSS
/
∆
T
J Bre akdow n V oltage Tem p. C o ef fi c ient ––– 0.0 53 ––– V/ °C
––– 46 58
R
DS(on) Static Drain- to- Source On-Resistance ––– ––– 80
m
Ω
––– ––– 100
V
GS(th) Gate Threshold Voltage 1.0 ––– 3.0 V
gfs Forward Transconductance 7.4 ––– ––– S
I
DSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
I
GSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leakage ––– ––– -200
Q
gT otal Gate Char ge ––– 6 .6 9.9
Q
gs Gate-to-Source Charge ––– 1.6 ––– nC
Q
gd Gate-to-Drain ("Miller") Charge ––– 3.9 –––
t
d(on) Turn-On Delay Time ––– 8. 2 – ––
t
rRise Time ––– 43 –––
t
d(off) Turn-Of f D e lay Time – –– 1 9 ––– n s
t
fFall Time ––– 16 –––
L
DInternal Drain Inductance ––– 4 .5 ––– Bet ween lead,
nH 6m m ( 0.25in.)
L
SInternal Source Inductance ––– 7.5 ––– from package
and center of die contact
C
iss Input Capacitance ––– 380 –––
C
oss Output Capacitance ––– 62 –––
C
rss Re verse Tr a nsfer Capacitanc e ––– 39 ––– pF
C
oss Output Capacitance ––– 180 –––
C
oss Output Capacitance ––– 50 –––
C
oss
eff.
Effective Output Capacitance ––– 81 –––
S o u r ce -D ra i n Ra tings an d Ch ar ac t e ri s tics
Parameter Min. Typ. Max. Units
ISCont i n uous S o ur ce Cur rent ––– ––– 16
(B ody Diode) A
ISM Pulsed Source Current ––– ––– 64
(B ody Diode)
c
VSD Di ode Forwar d Voltage ––– ––– 1. 3 V
trr Rever s e Rec ov ery Time ––– 16 24 n s
Qrr Re verse Rec over y Charge ––– 1 1 17 nC
ton For ward Turn-On Tim e I n tri n si c t urn -on tim e is neg li gi bl e (tu rn-o n is dom inated by LS +LD)
VGS = 5.0V, ID = 5.0A
e
VGS = 4.5V, ID = 3.0A
e
VGS = 0V, VDS = 1.0V, ƒ = 1.0MH
z
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
VDS = 25V , I D = 9.6A
ID = 5.0A
VDS = 44V
VGS = 16V
VGS = -16V
VGS = 5.0V
e
VDD = 28V
ID = 5.0A
RG = 28 Ω
TJ = 25°C, IS = 9.6A, VGS = 0V
e
TJ = 25°C, IF = 9.6A, VDD = 28V
di/dt = 1 00A/µ s
e
Conditions
VGS = 0V, ID = 250µA
R ef e r enc e t o 25°C , I D = 1mA
VGS = 10V, ID = 9 .6A
e
VDS = VGS, I D = 250µA
VDS = 55V , V GS = 0V
VDS = 55V , V GS = 0V, TJ = 125°C
MO SFET symbol
showing the
integral revers e
p-n junction diode.
Conditions
VGS = 5.0V
e
VGS = 0V
VDS = 25V
ƒ = 1.0MH z
VGS = 0V, VDS = 0V to 44V
f
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
vs. Drain Current
0.1 110
VDS, Dr ain-t o-Sour ce Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
3.0V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
0.1 110
VDS, Dr ain-t o-Sour ce Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
≤60µs PULSE WIDTH
Tj = 25°C
3.0V
0246810 12
VGS, Gate-t o-Sour ce Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 10V
≤60µs PU LSE WID TH
0 2 4 6 8 10 12 14 16
ID,Drai n-to- Source Current (A)
0
5
10
15
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 8.0V
300 µs PULSE WIDTH
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drai n-to-Source Voltage (V)
10
100
1000
10000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VSD, Source-to- Drai n Voltage (V )
1
10
100
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100 1000
VDS, Dr ain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
01234567
QG Total Gate Char ge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VGS, Gate-to-Source Voltage (V)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 5.0A
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature Fig 10. Normalized On-Resistance
vs. Temperature
25 50 75 100 125 150 175
TC , C ase Temperature (°C)
0
2
4
6
8
10
12
14
16
ID, Drain Current (A)
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , R ectangu lar Pulse Du ra tion ( sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( TH E R MAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
2.354 0.000354
1.926 0.001779
τJ
τJ
τ1
τ1τ2
τ2
R1
R1R2
R2
τ
τ
C
Ci= i/Ri
Ci= τi/Ri
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperat ure (° C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 5.0A
VGS = 5.0V
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Q
G
Q
GS
Q
GD
V
G
Charge
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
1K
VC
C
DUT
0
L
25 50 75 100 125 150 175
Start ing TJ , Juncti on Temperature (°C)
0
20
40
60
80
100
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 1.2A
1.8A
BOTTOM9.6A
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
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Fig 15. Typical Avalanche Current vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV· Zth]
EAS (AR) = PD (ave)·tav
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
Avalanche Current (A)
0.05
Dut y Cycle = Si ngle Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperatur e (°C)
0
5
10
15
20
25
30
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 9.6A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.03 5)
0.64 (.02 5)
0.25 (.010) M A M B
4.57 (.180)
2.28 (.090)
2X 1.14 (.045)
0.76 (.030)
1.52 (.060)
1.15 (.045)
1
.02 (.040)
1
.64 (.025)
5.46 (.215)
5.21 (.205) 1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086) 1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020)
MIN.
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENT S
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
10.42 (.410)
9.40 ( .370)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y1 4.5M, 1982
.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
INTERNATIONAL
LOGO
RECTIFIER
3412
IRFR120
916A
LOT CODE
AS S E MB LY
EXAMPLE: WIT H ASS EMBLY
THIS IS AN IRFR120
YEAR 9 = 1999
DATE CODE
LINE A
WE EK 16
IN THE ASSEMBLY LINE "A"
ASSEMBLED ON WW 16, 1999
LOT COD E 1234
PART NUMBER
Note: "P" in assembly line
position indic ates "Lead-Free"
OR
P916A
IRFR120
LOT CODE
AS S E MB LY
INTERNATIONAL
RECTIFIER
LOGO 12
PART N UMBER
WEEK 16
A = AS SEMBLY S IT E CODE
DATE CODE
YEAR 9 = 1999
34 P = DE S IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
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IRLR/U024Z
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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
- A -
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
2.28 (.090)
1.14 (.045)
0.76 (.030)
5.46 ( .215)
5.21 ( .205) 1.27 (.050)
0.88 (.035)
2.38 ( .094)
2.19 ( .086)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018) L EAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SO URCE
4 - DRAIN
NOTES:
1 DIMENSIONING & TOLERANCING P ER ANSI Y1 4.5M, 1982
.
2 CO NTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
9.65 ( .380)
8.89 ( .350)
2X
3X
2
.28 (.090)
1
.91 (.075)
1.52 (.060)
1.15 (.045)
4
1 2 3
6.45 (.245)
5.68 (.224)
0.58 (.023)
0.46 (.018)
I-Pak (TO-251AA) Part Marking Information
AS S E MBL Y
EXAMPLE: WITH ASSE MBLY
THIS IS AN IRFU120
YEAR 9 = 199
9
DATE CODE
LINE A
WEEK 19
IN THE ASSEMBLY LINE "A"
ASSEMBLED ON WW 19, 1999
LOT CODE 5678
PART NUMBER
56
IRFU120
INTERNATIONAL
LOGO
RECTIFIER
LOT CODE
919A
78
Note: "P" in assembly line
pos ition indicates "L ead-Free"
OR
56 78
AS S EMB LY
LOT CODE
RECTIFIER
LOGO
INTERNATIONAL IRFU120
PART NUMBER
WEEK 19
DA TE C ODE
YEAR 9 = 1999
A = AS SEMB LY S IT E CODE
P = DE S IGNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/04
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.54mH
RG = 25Ω, IAS = 9.6A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to
80% VDSS .
Notes:
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994.
Rθ
is measured at T
J of approximately 90°C.
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRE CTION
16.3 ( .641
)
15.7 ( .619
)
TRR TRL
N
OTES :
1
. CONTROLLING DIMENSION : MILLIMETE R.
2
. ALL D IMENS IONS ARE SHOWN IN MILL IMET E R S ( IN C H ES ) .
3
. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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