AX6108 Dot Matrix Liquid Crystal Graphic
Display Column Driver
Description
AX6108 is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores
the display data transferred from a 8-bit micro controller in the internal display RAM and generates dot
matrix liquid crystal driving signals.
Each bit data of display RAM corresponds to the on/off state of a dot of a liquid crystal display to
provide more flexible than character display.
As it is internally equipped with 64 output drivers for display, it is available for liquid crystal graphic
display with many dots.
The AX6108, which is produced in the CMOS process, can complete portable battery drive equipment
in combination with a CMOS microcontroller, utilizing the liquid crystal display's low power
dissipation.
Moreover it can facilitate dot matrix liquid crystal graphic display system configuration in combination
with the row (common) driver AX6107
Features
¡´ Dot matrix liquid crystal graphic display column driver incorporating display RAM
¡´ RAM data direct display by internal display RAM
¡´ RAM bit data 1:On
¡´ RAM bit data 1:Off
¡´ Internal display RAM address counter preset, increment
¡´ Display RAM capacity : 512 bytes (4096 bits)
¡´ 8-bit parallel interface
¡´ Internal liquid crystal display driver circuit : 64
¡´ Display duty cycle : Drives liquid crystal panels with 1/32 - 1/64 duty cycle multiplexing
¡´ Wide range of instruction function : Display Data Read/Write, Display On/Off, Set Address, Set
Display Start Line, Read Status
¡´ Lower power dissipation : during display 2 mW max
¡´ Power supply : Vcc: 5V¡Ó10%
¡´ Liquid crystal display driving voltage : 8V to 17.0V
¡´ CMOS process
¡´ 100-pin flat plastic package (FP-100)
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Absolute Maximum Ratings
¢J-55 to + 125TstgStorage temperature ¢J-20 to + 75ToprOperating temperature
2, 5V-0.3 to Vcc + 0.3VT2Terminla voltage (2)
4VVEE - 0.3 to Vcc + 0.3VT1Terminal voltage (1)
3VVcc -19.0 to Vcc + 0.3VEE1
VEE2
2V-0.3 to +7.0Vcc
Supply voltage
NoteUnitValueSymbolItem
Notes : 1. LSls may be destroyed if they are used beyond the absolute maximum ratings.
In ordinary operation, it is desirable to use them within the recommended
operation conditions.
Using them beyond these conditons may cause malfunction and poor reliability.
2. All voltage values are referenced to GND = 0V.
3. Apply the same supply voltage to VEE1 and VEE2.
4. Applies to V1L, V2L, V3L, V4L, V1R, V2R, V3R, and V4R.
Maintain
Vcc¡ÙV1L=V1R¡ÙV3L¡Ù=V3R¡ÙV4L=V4R¡ÙV2L=V2R¡ÙVEE
5. Applies to M, FRM, CL, RST, ADC, £p1, £p2, CS1, CS2, CS3, E, R/W, D/i,
and DB0 - DB7.
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Pin Arrangement
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Y42
Y41
Y40
Y39
Y38
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
50494847
4645
44
43
42
31 32 33 34 35 36 4140
39
38
37
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51 Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
11
10
9
8
7
6
5
4
3
2
1
ADC
M
Vcc
V4R
V3R
V2R
V1R
VEE2
Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
FRM
E
£p
1
£p
2
CL
D/I
R/W
RST
CS1
CS2
CS3
NC
NC
NC
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
GND
V4L
V3L
V2L
V1L
V1
EE
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Electrical Characterisstics
(GND = 0 V, Vcc = 4.5 to 5.5V, Vcc - VEE = 8 to 17.0 V, Ta = -20 to +75¢J)
7During access
access cycle =
1MHz
£gA500----ICC (2)
7During display£gA100----ICC (1)Dissipation current
8Vcc - VEE= 15V
¡ÓILOAD = 0.1 mA
k£[7.5----RON
Driver on resistance
6Vin= VEE - Vcc£gA2---2ILSL
Liquid crystal supply leakage
current
5Vin= GND - Vcc£gA5---5ITSL
Three-state (off) input current
4Vin= GND - Vcc£gA1---1IIL
Input leakage current
3IOL= -1.6mAV0.4----VOL
Output low voltage
3IOH= -205£gAV----2.4VOH
Output high voltage
2V0.8--0VILT
1V0.3xVcc--0VILC
Input low voltage
2VVcc--2VIHT
1VVcc--0.7xVccVIHC
Input high voltage
NoteTest ConditionUnitMaxTypMinSymbolItem
Limit
Notes : 1. Applies to M, FRM, CL, RST, £p1 and £p2.
2. Applies to CS1, CS2, CS3, E, R/W, D/I, and DB0 - DB7.
3. Applies to DB0 - DB7.
4. Applies to terminals except for DB0 - DB7.
5. Applies to DB0 - DB7 at high impedance.
6. Applies to V1L - V4L and V1R - V4R.
7. Specified when liquid crystal display is in 1/64 duty cycle mode.
Operation frequency fCLK = 250 kHz (£p1 and £p2 frequency)
Frame frequency fM = 70 Hz (FRM frequency)
Specified in the state of
Output terminal : not loaded
Input level : VIH = Vcc (V)
VIL = GND (V)
Measured at Vcc terminal
8. Resistance between terminal Y and terminal V (one of V1L, V1R, V2L, V2R, V3L, V3R,
V4L and V4R) when load current flows through one of the treminals Y1 to Y64. This value
is specified under the following condition :
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Vcc - VEE = 15.5V
V1L = V1R, V3L = V3R = Vcc - 2/7 (Vcc - VEE)
V2L = V2R, V4L = V4R = Vcc + 2/8 (Vcc - VEE)
The following is a description of the range of power supply voltage for liquid crystal display drive.
Apply positive voltage to V1L = V1R and V3L = V3R and negative voltage to V2L = V2R and V4L
= V4R within the ¡µV range. This range allows stable impedance on driver output (RON). Notice
that ¡µV depends on power supply voltage Vcc - VEE.
Correlation between Driver Correlation between Power
Output Waveform and Power Supply Voltage Vcc - VEE and ¡µV
Supply Voltages for Liquid
Crystal Display Drive
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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RON
Terminal Y
(Y1 - Y64)
V1L, V1R
V3L, V3R
V4L, V4R
V2L, V2R
¡´
¡´
¡´
¡µ
V
¡µ
V
Vcc
V1 (V1L =V1R)
V3 (V3L = V3R)
V4 (V4L = V4R)
V2 (V2L = V2R)
VEE
Range of Power Supply
Voltage for Liquid Crystal
Display Drive
817.0
5.0
3
¡µ
V(V)
Vcc - VEE (V)
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Terminal Configuration
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Input Terminal
¡´ ¡´
¡´
¡´
Vcc
PMOS
NMOS
Applicable terminals :
M, FRM, CL, RST,
£p
1,
£p
2, CS1,
CS2, CS3, E, R/W, D/I, ADC
Input/Output Terminal
¡´ ¡´
¡´
¡´
Vcc
PMOS
NMOS
¡´¡´
¡´
¡´
Vcc
PMOS
NMOS
Enable
Data
(Output circuit)
(three state)
Applicable terminals : DB0 - DB7
(Input circuit)
¡´
¡´
Output Terminal
PMOS
PMOS
NMOS
NMOS
V1L, V1R
V3L, V3R
V4L, V4R
V2L, V2R
Vcc
Vcc
VEE
VEE
Applicable Terminals :
Y1 - Y64
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Interface AC Characteristics
MPU Interface
(GND = 0 V, Vcc = 4.5 to 5.5 V, Ta = -20 to +75¢J
2ns----20tDHR
Data hold time (Read)
1ns----10tDHW
Data hold time (Write)
2, 3ns320----tDDR
Data delay time
1ns----200tDSW
Data setup time
1, 2ns----10tAH
Address hold time
1, 2ns----140tAS
Address setup time
1, 2ns25----tfE fall time
1, 2ns25----trE rise time
1, 2ns----450PWEL
E low level width
1, 2ns----450PWEH
E high level width
1, 2ns----1,000tCYC
E cycle time
NoteUnitMaxTypMinSymbolItem
Notes : 1.
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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2.0V
0.8V PWEL
2.0V
0.8V t
t
AS
AS
PWEL
cyc
t
tf
tAH
tr
2.0V
0.8V
2.0V
0.8V
t t
tAH
DSW DHW
E
R/W
CS1 - CS3
D/I
DB0 - DB7
Figure 1 CPU Write Timing
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Notes : 2.
3. DB0 - DB7 : load circuit
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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PWEL
2.0V
0.8V t
t
AS
AS
PWEH
cyc
t
tf
tAH
tr
2.0V
0.8V
2.4V
0.4V
t
t
tAH
DDR
DHR
E
R/W
CS1 - CS3
D/I
DB0 - DB7
Figure 2 CPU Read Timing
¡´
D1
CR
RL
D2
D3
D4
Test
point
RL = 2.4k
£[
R = 11k
£[
C = 130pF (including jig capacitance)
Diodes D1 - D4 are all 1S2074 H
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Clock Timing
(GND = 0 V, Vcc = 4.5 to 5.5 V, Ta = -20 to + 75¢J)
Fig. 3ns150----tf£p1 - £p2 fall time
Fig. 3ns150----tr£p1 - £p2 rise time
Fig. 3ns----625tD21
£p2 - £p1 phase
difference
Fig. 3ns----625tD12
£p1 - £p2 phase
difference
Fig. 3ns----1,875tWH£p2
£p2 high level width
Fig. 3ns----1,875tWH£p1
£p1 high level width
Fig. 3ns----625tWL£p2
£p2 low level width
Fig. 3ns----625tWL£p1
£p1 low level width
Fig. 3ns20--2.5tCYC
£p1, £p2 cycle time
Test ConditionUnitMaxTypMinSymbolItem Limit
Figure 3 External Clock Waveform
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tcyc
tWH
£p
1
tf tr
0.7 Vcc
0.3 Vcc
tWL
£p
1tD12 tD21
0.7 Vcc
0.3 Vcc
tf ttr tcyc
t
WL
£p
2
WH
£p
2
£p
1
£p
2
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Display Control Timing
(GND = 0V, Vcc = 4.5 to 5.5 V, Ta = -20 to +75¢J)
Fig. 4 £gs----35tWHCL
CL high level width
Fig. 4 £gs----35tWLCL
CL low level width
Fig. 4 £gs2---2tDM
M delay time
Fig. 4 £gs2---2tDFRM
FRM delay time
Test ConditionUnitMaxTypMinSymbolItem
Limit
Figure 4 Display Control Signal Waveform
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0.7Vcc
0.3Vcc
0.7Vcc
0.3Vcc
t
t
t
t
t
0.7Vcc
0.3Vcc
CL
FRM
M
WLCL
DFRM
WHCL
DFRM
DM
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Block Diagram
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V1L
V2L
V3L
V4L
Y1
Y2
Y3
Y62
Y63
Y64
V1R
V2R
V3R
V4R
Liquid crystal display
driver circuit
1
2
3
62
63
64
64 64
1
2
3
Display date latch
62
63
64
¡´
XY address counter
Display data RAM
4096 bit
Instruction
register
Z address counter
Display start
line register
Display
on/off
Input
register Output
register Busy
flag
I/O buffer
Interface control
CS1, CS2, CS3
9
9
6
6
6
M
ADC
Vcc
GND
V
VEE1
EE2
¡´
RST
£p
1
£p
2
R/W
D/I
E
DB0 - DB7
3
88
8
CL
FRM
¡´
¡´
¡´¡´
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Terminal Functions
Data/instruction.
D/I = High : Indicates that the data of DB0 to DB7 is
display data.
D/I = Low : Indicates that the data of DB0 to DB7 is
display control data.
MPUI1D/I
Read/write.
R/W = High : Data appears at DB0 to DB7 and can be
read by the CPU.
When E = high, CS1, CS2 = low and CS3
= high.
R/W = Low : DB0 to db7 can accept at fall of E when
CS1, CS2 = low and CS3 = high.
MPUI1R/W
Enable.
At write (R/W = Low) : Data of DB0 to DB7 is latched at the
fall of E.
At read (R/W = High) : Data appears at DB0 to DB7 while E
is at high level.
MPUI1E
Chip selection.
Data can be input or output when the terminals are in the
following conditions :
Terminal Name CS1 CS2 CS3
Condition L L H
MPUI3
CS1
CS2
CS3
Power supply for liquid crystal display drive.
Apply the voltage specified depending on liquid crystals within
the limit of VEE through Vcc.
V1L (V1R), V2L (V2R) : Selection level
V3L (V3R), V4L (V4R) : Non-selection level
Power supplies connected with V1L and V1R (V2L & V2R,
V3L & V3R, V4L & V4R) should have the same voltages.
Power
supply8
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
Power supply for liquid crystal display drive circuit.
Recommended power supply voltage is Vcc - Vee = 8 to 17.0
V. Connect the same power supply to VEE1 and VEE2. VEE1 and
VEE2 are not connected each other in the LSI.
Power
supply
2VEE1
VEE2
Power supply for internal logic.
Recommended voltage is :
GND = 0 V
Vcc = 5 V ¡Ó 10%
Power
supply2
Vcc
GND
Functions
Connected to
I/ONumber of
Terminals
Terminal
Name
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Unused terminals. Don't connect any lines to these terminals.Open3NC
The following registers can be initialized by setting the RST
signal to low level.
1. On/off register 0 set (display off)
2. Display start line register line 0 set (displays from line 0)
After releasing reset, this condition can be changed only by
instruction.
CPU or
external CR
I1RST
Liquid crystal display column (segmnet) drive output.
These pins outputs light on level when 1 is in the display RAM,
and light off level when 0 is it.
Relation among output level, M, and display data (D) is as
follows:
M
D
Output
level
10
1 0 10
V1 V3 V2 V4
Liquid
crystal
display
O64Y1 - Y64
2-phase clock signal for internal operation.
The £p 1 and £p2 clocks are used to preform operations (I/O
of display data and execution of instructions) other than display.
AX6107I2£p1, £p2
Synchronous signal to latch display data. The rising CL signal
increments the disiplay output address counter and latches the
display data.
AX6107I1CL
Display synchronous signal (frame signal).
Presets the 6-bit display line counter and synchronizes the
common signal with the frame timing when the FRM signal
becomes high.
AX6107I1FRM
Switch signal to convert liquid crystal drive wavefojrm into AC.AX6107I1M
Data bus, three-state I/O common terminal.MPUI/O8DB1 - DB7
Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC = High : Y1 : $0, Y64 : $63
ADC = Low : Y64 : $0, Y1 : $63
Vcc/GNDI1ADC
FunctionsConnected
to
I/ONumber of
Terminals
Terminal
Name
Note : 1 corresponds to high level in positive logic.
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AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Function of Each Block
Interface Control
1. I/O buffer
Data is transferred through 8 data bus lines (DB0 - DB7) .
DB7 : MSB (Most significant bit)
DB0 : LSB (lleast significant bit)
Data can neither be input nor output unless CS1 to CS3 are in the active mode. Therefore, when CS1
to CS3 are not in active mode it is useless to switch the signals of input terminals except RST and
ADC: that is namely, the internal state is maintained and no instruction excutes. Besides, pay attention
to RST and ADC which operate irrespectively of CS1 to CS3.
2. Register
Both input register and output register are provided to interface to an MPU whose speed is different
from that of internal operation. The selection of these registers depend on the combination of R/W and
D/I signals (table 1).
a. Input register
The input register is used to store data temporarily before writing it into display data RAM.
The data from MPU is written into the input register, then into display data RAM automatically by
internal operation. When CS1 to CS3 are in the active mode and D/I and R/W select the input register
as shown in table 1, data is latched at the fall of the E signal.
b. Output register
The output register is used to store data temporarily that is read from display data RAM. To read out
the data from output register, CS1 to CS3 should be in the active mode and both D/I and R/W should
be 1. With the read display data instruction, data stored in the output register is output while E is high
level. Then, at the fall of E, the display data at the indicated address is latched into the output register
and the address is increased by 1.
The contents in the output register are rewritten by the read display data instructiion. but ree held by
address set instruction, etc.
Therefore, the data of the specified address cannot be output with the read display data instruction
right after the address is set, but can be output at the second read of data. That is to say, one dummy
read is necessary. Figure 5 shows the CPU read timing.
_________________________________________________________________________________
Table 1 Register Selection
Instruction00
Busy check. Read of status data.10
Writes data into input register as internal operation (input register ¡÷ display data RAM)01
Reads data out of output register as internal operation (display data RAM ¡÷ output register)11
OperationR/WD/I
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AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Figure 5 CPU Read Timing
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D/I
R/W
E
N + 2
N + 1N
Data at address N Data at address N + 1
Data read
address
N + 1
Busy
check
Read
data at
address
N
Busy
check
Read
data
(dummy)
Busy
check
Write
address
N
Busy
check
Address
Output
register
DB0 - DB7
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Busy Flay
Busy flag = 1 indicates that AX6108 is operating and no instructions except status read instruction can
be accepted. The value of the busy flag is read out on DB7 by the status read instruction. Make sure
that the busy flag is reset (0) before issuing insstructions.
Figure 6 Busy Flag
Display On/Off Flip/Flop
The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In
on state, the display data corresponding to that in RAM is output to the segments. On the other hand,
the display data at all segments. On the other hand, thedisplay data at all segments disappear in off
state independent of the data in RAM. It is controlled by display on/off instruction. RST signal = 0 sets
the segments in off state. The status of the flip/flop is output to DB5 by status read instruction. Display
on/off instruction does not influence data in RAM. To control display data latch by this flip/flop, CL
signal (display synchronous signal) should be input correctly.
Display Start Line Register
The display start line register specifies the line in RAM which corresponds to the top line of LCD
panel, when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the
screen.
6-bit display start line information is written into this register by the display start line set instruction.
When high level of the FRM signal starts the display, the information in this register is transferred to
the Z address counter, which controls the display address, presetting the Z address counter.
X, Y Adddress Counter
A 9-bit counter which designates addresses of the internal display data RAM. X address counter
(upper 3 bits) and Y address counter (lower 6 bits) should be set to each address by the respective
instructions.
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E
Busy
flag T Busy 1/fCLK
CLK
CLK
¡Ø
T Busy
¡Ø
3/f
fis
£p
1,
£p
2 frequency
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1. X address counter
Ordinary register with no count functions. An address is set by instruction.
2. Y address counter
An address is set by instruction and is increased by 1 automatically by R/W operations of display data
The Y address counter loops the values of 0 to 63 to count.
Display Data RAM
Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off
(data = 0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and
segment pins can be reversed by ADC signal.
As the ADC signal controls the Y address counter, reversing of the signal during the operation causes
malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to
connnect ADC pin to Vcc or GND when using.
Figure 7 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1
and ADC = 0 (display start line = 0, 1/64 duty cycle).
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AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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COM1 (AX61203 X1)
COM2 (AX61203 X2)
COM3 (AX61203 X3)
COM4 (AX61203 X4)
COM5 (AX61203 X5)
COM6 (AX61203 X6)
COM7 (AX61203 X7)
COM8 (AX61203 X8)
COM9 (AX61203 X9)
COM62 (AX61203 X62)
COM63 (AX61203 X63)
COM64 (AX61203 X64)
LCD
display pattern
0
1
1
1
1
1
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Y1 Y2 Y3 Y4 Y5
Y
62 Y
63 Y64
1
012 3 4 5 61 62 63 RAM Y Address
DB0(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7(MSB)
¡´
¡´
¡´
¡´
¡´
¡´
¡´
¡´
Line 0
Line 1
Line 2
X = 0
Display
RAM data
X = 1
X = 7
Line 62
Line 63
ADC = 1 (Connected to Vcc)
AX61202 Pin Name
------------------------------------------------------------------------------------------------------------------------
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
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COM1 (AX61203 X1)
COM2 (AX61203 X2)
COM3 (AX61203 X3)
COM4 (AX61203 X4)
COM5 (AX61203 X5)
COM6 (AX61203 X6)
COM7 (AX61203 X7)
COM8 (AX61203 X8)
COM9 (AX61203 X9)
COM62 (AX61203 X62)
COM63 (AX61203 X63)
COM64 (AX61203 X64)
LCD
display pattern
0
1
1
1
1
1
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Y1Y2
Y3
62
63
1
012 3 4 5 61 62 63 RAM Y Address
DB0(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7(MSB)
¡´
¡´
¡´
¡´
¡´
¡´
¡´
¡´
Line 0
Line 1
Line 2
X = 0
Display
RAM data
X = 1
X = 7
Line 62
Line 63
ADC = 0 (Connected to GND)
Y
64
YYY
61 Y
59 AX61202 Pin Name
Z Address Counter
The Z address counter generates addresses for outputting the display data synchronized with the
common signal. This counter consists of 6 bits and counts up at the fall of the CL signal. At the high
level of FRM, the contents of the display start line register is preset at the Z counter.
Display Data Latch
The display data latch stores the display data temporarily that is output from display data RAM to the
liquid crystal driving circuit. Data is latched at the rise of the CL signal. The display on/off instruction
controls the data in this latch and does not influence data in display data RAM.
Liquid Crystal Display Driver Circuit
The combination of latched display data and M signal causes one of the 4 liquid crystal driver levels,
V1, V2, V3 and V4 to be output.
Reset
The system can be initialized by setting RST terminal at low level when turning power on.
1. Display off
2. Set display start line register line 0.
While RST is low level, no instruction except status read can be accepted. Therefore, execute other
instructions after making sure that DB4 = 0 (clear RESET) and DB7 = 0 (Ready) by status read
instruction. The conditions of power supply at initial power up are shown in table 1.
Do not fail to set the system again becaise RESET during operation may destroy the data in
all the registers except on/off register and in RAM.
------------------------------------------------------------------------------------------------------------------------
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
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Table 1 Power Supply Initial Conditions
Item Symbol Min Typ Max Unit
Reset time
Rise time
tRST
tr
1.0
200
£g
s
ns
4.5V
ttr
RST
0.7Vcc
0.3Vcc
RST
Display Control Instructions
Outline
Table 2 shows the instructions. Read/write (R/W) signal, data/instruction (D/I) signal, and data bus
signals (DB0 to DB7) are also called instructions because the internal operation depends on the signals
from the MPU.
These explanations are detailed in the following pages. Generally, there are following three kinds of
instructions :
1. Instruction to set addresses in the internal RAM.
2. Instruction to transfer data from/to the internal RAM.
3. Other instructions.
In general use, the second type of instruction is used most frequently. Since Y address of the internal
RAM is increased by 1 automatically after writing (reading) data, the program can be shortened.
During the execution of an instruction, the system cannot accept instructions other than status read
instruction. Send instructions from MPU after making sure that the busy flag is 0, which is proof that
an instruction is not being excuted.
------------------------------------------------------------------------------------------------------------------------
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
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Table 2 Instructions
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Page22
Code
Instructions
Display on/off
Display start line
Set page (X address)
Set address
Status read
Write display data
Read display data
R/W
0
0
0
0
1
0
1
D/I
0
0
0
0
1
1
0
DB7
0
1
1
0
Busy
Write data
Read data
DB6
0
1
0
1
0
DB5
1
Display start line (0 - 63)
1
Y address (0 - 63)
ON/
OFF
DB4
1
1
Reset
DB3
1
1
0
DB2
1
Page (0 - 7)
0
DB1
1
0
DB0
1/0
0
Functions
Controls display on/off. RAM data and
inte
rnal status are not affected. 1: on, 0:off.
Specifies the RAM line displayed at the top
of the screen.
Sets the page (X address) of RAM at the
page (X address) register.
Sets the Y address in the Y address counter.
Reads the status.
RESET 1 : Reset
0 : Normal
ON/OFF 1 : Display off
0 : Display on
Busy 1 : Internal operation
0 : Ready
Writes data DB0 (LSB)
to DB7 (MSB) on the
data bus into display
RAM.
Has access to the
address of the display
RAM specified in
advance. After the
access, Y address is
is increased by 1.
Reads data DB0 (LSB)
to DB7 (MSB) from the
display RAM to the data
bus.
Note : 1. Busy time varies with the frequency (f ) of £p1, and £p2.
(1/f ¡Ø T ¡Ø 3/f ) CLK
CLK BUSY CLK
!" #
$%&"'()#
*+,'()"&'+-'-)#
./
************************************************************************************************************************
0(%&.1/2/3
************************************************************************************************************************
4-+
************************************************************************************************************************
0(%&.1/2/3
************************************************************************************************************************
4-)
0" #0
45&&67
8" #88
345
************************************************************************************************************************
0(%&.1/2/3
************************************************************************************************************************
4-9
Status Read
Busy : When Busy is 1, the LSI is executing internal operations. No instructions are accepted
while Busy is 1, so you should make sure that Busy is 0 before writing the next
instruction.
ON/OFF : Shows the liquid crystal display conditions: on condition or off condition.
When ON/OFF is 1, the display is in off condition.
When ON/OFF is 0, the display is in on condition.
RESET : RESET = 1 shows that the system is being initialized. In this condition, no instructions
except status read can be accepted.
RESET = 0 shows that initializing has finished and the system is in the usual operation
condition.
Write Display Data
Writes 8-bit data DDDDDDDD (binary) into the display data RAM. Then Y address is increased by 1
automatically.
Read Display Data
Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased
by 1 automatically.
One dummy read is necessary right after the address setting. For details, refer to the explanation of
output register in "FUNCTION OF EACH BLOCK".
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00 0 111
R/W D/I DB7 DB0
Code
high-order bit low-order bit
1AAA
0
R/W D/I DB7 DB0
Code
high-order bit low-order bit
1D D DD D DDD
0
R/W D/I DB7 DB0
Code
high-order bit low-order bit
1D D DD D DDD
0
R/W D/I DB7 DB0
Code
high-order bit low-order bit
1D D DD D DDD
------------------------------------------------------------------------------------------------------------------------
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
Use of AX6108
Interface with AX6103 (1/64 duty cycle)
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¡´
Vcc
V1L, V1R
V6L, V6R
V5L, V5R
V2L, V2R
V
GND
EE
X1
X64
Vcc
V1
V6
V5
V2
VEE
¡´
¡´
¡´
¡´
¡´
¡´
¡´
Vcc
Vcc
V1
V2
V3
V4
VEE
Rf Cf
RCR C
COM1
COM64
LCD Panel
64x64 dots
SEG1
SEG64
Open
Open
SHL
DS1
DS2
TH
CL1
FS
M/S
FCS
STB
DL
DR
M
CL2
FRM
£p1
£p2
Y1 Y64
M
CL
FRM
£p1
£p2
Vcc
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
VEE1, EE2
V
GND
AX61202
CS1
CS2
CS3
R/W
D/I
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CPU
-
-
+
+
-
+
-
+
¡´ ¡´
¡´
¡´
¡´
¡´
¡´
¡´ ¡´
¡´
¡´
¡´
¡´
¡´
¡´
Contrast
R3 V1
R3 V6
R3 V3
R3 V4
R1
R1
R2
R1
R1
R3 V5
R3 V2
VEE
-10V
R3 = 15
£[
ADC
RST
Vcc
External CR
Power supply circuit
~
AX61203
+5V (Vcc)
--------------------------------------------------------------------
----------------------------------------------------
AX6102 Dot Matrix Liquid Crystal Graphic Display Column Driver
--------------------------------------------------------------------
----------------------------------------------------
Figure 10 LCD Driver Timing Chart (1/64 duty cycle)
Page28
!"
#$ %!
~~
Y1
Y64
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
Interface with CPU
1. Example of connection with HD6800
Figure 11 Example of Connection with HD6800 Series
In this decoder, addresses of AX6108 in the address area of HD6800 are :
Read/write of the display data $FFFF
write of display insstruction $FFFF
Read out of status $FFFF
Therefore, you can control AX6108 by reading/writing the data at these addresses.
------------------------------------------------------------------------------------------------------------------------
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
¸àµØ¹q¤lªÑ¥÷¦³--¤½¥q
ASLIC MICROELECTRONICS CORP. Page29
Decoder
A15
A1
VMA
A0
R/W
£p2
D0
D7
RES
~
~
HD6800
CS1
CS2
CS3
D/I
R/W
E
DB0
DB7
RST
~
Vcc
¡´
¡´
Vcc
Decoder
A15
A1
VMA
A0
R/W
£p2
D0
D7
RES
~
~
HD6800
CS1
CS2
CS3
D/I
R/W
E
DB0
DB7
RST
~
Vcc
¡´
¡´
Vcc
AX6108
------------------------------------------------------------------------------------------------------------------------
2. Example of connection with HD6801
¡´ Set HD6801 to mode 5. P10 to P14 are used as the output port and P30 to P37 as the data bus.
¡´ 74LS154 4-to-16 decoder generates chip select signal to make specified AX6108 active after
decoding 4 bits of P10 to P13.
¡´ Therefore, after enabling the operation by P10 to P13 and specifying D/I signal by P14, read/write
from/to the external memory area ($0100 to $01FE) to control AX6108. In this case, IOS signal is
output from SC1 and R/W signal from SC2.
¡´ For details of HD6800 and HD6801, refer to their manuals.
------------------------------------------------------------------------------------------------------------------------
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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HD6801
CS1
CS2
CS3
D/I
R/W
E
DB0
DB7
AX6108
Vcc
No.1
74LS154
A
B
C
D
Y0
Y1
G1 G2
Y15
P10
P11
P12
P13
(IOS)(SC1)
(R/W)(SC2)
P14
E
P30
P31
P37
(Date bus) DB1
------------------------------------------------------------------------------------------------------------------------
Example of Application
Note : In this example, two AX6107s output the equivalent waveforms. So, stand-alone operation is
possible. In this case, connect COM1 and COM65 to X1, COM2 and COM66 to X2, ..., and
COM64 and COM128 to X64. However, for the large screen display, it is better to drive in 2
rows as in this example to guarantee display qualitty.
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AX6108
No. 9
Y1 Y64
~AX6108
No. 10
Y1 Y64
~AX6108
No. 16
Y1 Y32
~
Y1 Y64
AX6108
No. 1
Y1 Y64
AX6108
No. 2
Y1 Y64
AX6108
No. 8
~~ ~
COM1
COM2
COM3
COM64 LCD Panel
128 x 480 dots
COM65
COM66
COM67
COM128
AX6107
(Slave) AX6107
(Master)
X1
X2
X3
X1
X2
X3
X64
X64
~~
¡½
