LPC2388FBD144,551 - NXP Semiconductors

1. General description

The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with

real-time emulation that combines the microcontroller with 512 kB of embe dded

high-speed flash memory. A 128-bit wide memory interface and a unique accelerator

architecture enable 32-bit code execution at the maximum clock rate. For critical

performance in interrupt ser vice routines and DSP algorithms, this increases pe rformance

up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit

Thumb mode reduces code by more than 30 % with minimal performance penalty.

The LPC2388 is ideal for mu lti-purpos e serial communication applications. It incorp orates

a 10/100 Ethernet Media Access Controller (MAC), USB device/host/OTG with 4 kB of

endpoint RAM, fo ur UAR Ts, two CAN channels, an SPI inter face, two Synchronous Seria l

Ports (SSP), three I2C interfaces, an I2S interface, and an External Memory Controller

(EMC). This blend of serial communications interfaces combined with an on-chip 4 MHz

internal oscillator, SRAM of 64 kB, 16 kB SRAM for Etherne t, 16 kB SRAM for USB and

general purpose use, together with 2 kB battery powered SRAM make this device very

well suited for communication gateways and protocol converters. Various 32-bit timers, an

improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up to 104 fast GPIO

lines with up to 50 edge and up to four level sensitive external interrupt pi ns make these

microcontrollers particularly suitable for industrial control and medical systems.

2. Features

ARM7TDMI-S processor, running at up to 72 MHz.

Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programmin g (I AP) capabilities. Flash program memory is on the ARM

local bus for high performance CPU access.

64 kB of SRAM on the ARM local bus for high performance CPU access.

16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

16 kB SRAM for general purpose DMA use also accessible by the USB.

Dual Advanced High-performance Bus (AHB) system that provides for simultaneous

Ethernet DMA, USB DMA, and program execution from on-chip flash with no

contention between those functions. A bus bridge allows the Ethernet DMA to access

the other AHB subsy ste m .

EMC provides support for static devices such as flash and SRAM as well as off-chip

memory mapped peripherals.

Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

LPC2388

Single-chip 16-bit/32-bit microcontroller; 512 kB flash with

ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit

ADC/DAC

Rev. 00.01 — 23 October 2007 Preliminary data sheet

Preliminary data sheet Rev. 00.01 — 23 October 2007 2 of 57

NXP Semiconductors LPC2388

Fast communication chip

General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial

interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port,

as well as for memory-to-memory transfers.

Serial Interfaces:

Ethernet MAC with associated DMA controller. These functions reside on an

independent AHB bus.

USB 2.0 device/host/O T G with on-ch ip PHY an d associated DMA cont ro ller.

Four UARTs with fractiona l bau d rate ge ner ation, o ne with modem control I/O, one

with IrDA support, all with FIFO.

CAN controller with two channels.

SPI controller.

Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing it s interrupt an d pins. These can be used with the GPDMA

controller.

Three I2C-bus interfaces (one with open-drain and two with standard port pins).

I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

Other periph er als :

SD/MMC memory card interface.

104 General purpose I/O pins with configurable pull-up/d own resistors.

10-bit ADC with input multiplexing among 8 pins.

10-bit DAC.

Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

One PWM/timer block with support for three-phase motor control. The PWM has

two external count inputs.

Real-Time Clock (RTC) with separate power pin, clock source can be the RTC

oscillator or the APB clock.

2 kB SRAM powered from the R TC p ower pin, allowin g dat a to be store d when the

rest of the chip is powered off.

WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

Standard ARM test/debug interface for compatibility with existing tools.

Emulation trace module supports real-time trace.

Single 3.3 V power supply (3.0 V to 3.6 V).

Three reduced power modes: idle, sleep, and power-down.

Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0

and PORT2 can be used as edge sensitive interrupt sources.

Processor wake-up from Power-down mode via any interru pt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt).

Two independent power domains allow fine tuning of power consumption based on

needed features.

Each peripheral ha s its own clock divider for further power saving.

Brownout detect with separate thresholds for interrupt and forced reset.

On-chip power-on reset.

On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.

Preliminary data sheet Rev. 00.01 — 23 October 2007 3 of 57

NXP Semiconductors LPC2388

Fast communication chip

4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

the system clock. When used as the CPU clock, does not allow CAN and USB to run.

On-chip PLL allows CPU operation up to the maximum CPU rate without the need for

a high frequency crystal. May be run from the main oscillator, the internal RC oscillator ,

or the RTC oscillator.

Boundary scan for simplified board testing.

Versatile pin function selections allow more possibilities for using on-chip peripheral

functions.

3. Applications

Industrial control

Medical systems

Protocol converter

Communications

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC2388FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1

Table 2. Ordering options

Type number Flash

(kB) SRAM (kB) External bus Ether

net USB

device

host

OTG+

4 kB

FIFO

CAN channels

SD/

MMC GP

DMA

ADC channels

DAC channels

Temp

range

Local bus

Ethernet buffer

GP/USB

RTC

Total

LPC2388FBD144 512 64 16 16 298 MiniBus: 8 data, 16

address, and 2 chip

select lines

RMII yes 2 yes yes 8 1 −40 °C to

+85 °C

Preliminary data sheet Rev. 00.01 — 23 October 2007 4 of 57

NXP Semiconductors LPC2388

Fast communication chip

5. Block diagram

Fig 1. LPC2388 block diagram

PWM1

ARM7TDMI-S

PLL

EINT3 to EINT0

FLASH

P3, P4

P0, P1, P2,

LEGACY GPI/O

56 PINS TOTAL

P0, P1

SCK, SCK0

MOSI, MOSI0

SSEL, SSEL0

SCK1

MOSI1

MIS01

SSEL1

SCL0, SCL1, SCL2

I2SRX_CLK

I2STX_CLK

I2SRX_WS

I2STX_WS

8 × AD0

RTCX1

RTCX2

MCICLK, MCIPWR

RXD0, RXD2, RXD3

TXD1

RXD1

RD1, RD2

TD1, TD2

CAN1, CAN2

USB port 1

XTAL1

TCK TDO

EXTIN0

XTAL2

RESET

TRST

TDITMS

HIGH-SPEED

GPI/O

104 PINS

TOTAL

LPC2388

USB port 2

64 kB

SRAM

512 kB

FLASH

INTERNAL

CONTROLLERS

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

trace signals

AHB

BRIDGE

AHB

BRIDGE

ETHERNET

MAC WITH

DMA

16 kB

SRAM

MASTER

PORT

AHB TO

AHB BRIDGE

SLAVE

PORT

system

clock

SYSTEM

FUNCTIONS

INTERNAL RC

OSCILLATOR

VDDA

VDD(3V3)

VREF

VSSA, VSS

VECTORED

INTERRUPT

CONTROLLER

16 kB

SRAM

USB WITH

4 kB RAM

AND DMA

GP DMA

CONTROLLER

I2S INTERFACE

SPI, SSP0 INTERFACE

I2SRX_SDA

I2STX_SDA

MISO, MISO0

SSP1 INTERFACE

SD/MMC CARD

INTERFACE MCICMD,

MCIDAT[3:0]

TXD0, TXD2, TXD3

UART0, UART2, UART3

UART1 DTR1, RTS1

DSR1, CTS1, DCD1,

RI1

I2C0, I2C1, I2C2 SDA0, SDA1, SDA2

EXTERNAL INTERRUPTS

CAPTURE/COMPARE

TIMER0/TIMER1/

TIMER2/TIMER3

A/D CONVERTER

D/A CONVERTER

2 kB BATTERY RAM

RTC

OSCILLATOR

REAL-

TIME

CLOCK

WATCHDOG TIMER

SYSTEM CONTROL

2 × CAP0/CAP1/

CAP2/CAP3

4 × MAT2,

2 × MAT0/MAT1/

MAT3

6 × PWM1

2 × PCAP1

AOUT

VBAT

AHB TO

APB BRIDGE

SRAM

RMII(8)

VBUS

002aad332

P0, P2

power domain 2

AHB2 AHB1

power domain 2

VDD(DCDC)(3V3)

A[15:0]

D[7:0]

EXTERNAL

MEMORY

CONTROLLER OE, CS0, CS1,

BLS0

Preliminary data sheet Rev. 00.01 — 23 October 2007 5 of 57

NXP Semiconductors LPC2388

Fast communication chip

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. LPC2388 pinn ing

LPC2388FBD144

108

144

109

002aad333

Table 3. Pin description

Symbol Pin Type Description

P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 0 pins depends upon the pin function selected via the Pin Connect

block.

P0[0]/RD1/TXD/

SDA1 66[1] I/O P0[0] — General purpose digital input/output pin.

IRD1 — CAN1 receiver input.

OTXD3 — Transmitter output for UART3.

I/O SDA1 — I2C1 data input/output (this is not an open-drain pin).

P0[1]/TD1/RXD3/

SCL1 67[1] I/O P0[1] — General purpose digital input/output pin.

OTD1 — CAN1 transmitter output.

IRXD3 — Receiver input for UART3.

I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin).

P0[2]/TXD0 141[1] I/O P0[2] — Gen eral purpose digital input/output pin.

OTXD0 — Transmitter output for UART0.

P0[3]/RXD0 142[1] I/O P0[3] — Gen eral purpose digital input/output pin.

IRXD0 — Receiver input for UART0.

P0[4]/

I2SRX_CLK/

RD2/CAP2[0]

116[1] I/O P0[4] — General purpose digital input/output pin.

I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.

Corresponds to the signal SCK in the I2S-bus specification.

IRD2 — CAN2 receiver input.

ICAP2[0] — Capture input for T imer 2, channel 0.

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  6 of 57
NXP Semiconductors LPC2388
Fast communication chip
P0[5]/ 
I2SRX_WS/ 
TD2/CAP2[1]
115[1] I/O P0[5] — General purpose digital input/output pin.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the 
slave. Corresponds to the signal WS in the I2S-bus specification.
OTD2 — CAN2 transmitter output.
ICAP2[1] — Capture input for T imer 2, channel 1.
P0[6]/ 
I2SRX_SDA/ 
SSEL1/MAT2[0]
113[1] I/O P0[6] — General purpose digital input/output pin.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the 
receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O SSEL1 — Slave Select for SSP1.
OMAT2[0] — Match output for Timer 2, channel 0.
P0[7]/ 
I2STX_CLK/ 
SCK1/MAT2[1]
112[1] I/O P0[7] — General purpose digital input/output pin.
I/O I2STX_CLK — T ransmit Clock. It is driven by the master and received by the slave. 
Corresponds to the signal SCK in the I2S-bus specification.
I/O SCK1 — Serial Clock for SSP1.
OMAT2[1] — Match output for Timer 2, channel 1.
P0[8]/ 
I2STX_WS/ 
MISO1/MAT2[2]
111[1] I/O P0[8] — General purpose digital input/outp ut pin.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the 
slave. Corresponds to the signal WS in the I2S-bus specification.
I/O MISO1 — Master In Slave Out for SSP1.
OMAT2[2] — Match output for Timer 2, channel 2.
P0[9]/ 
I2STX_SDA/ 
MOSI1/MAT2[3]
109[1] I/O P0[9] — General purpose digital input/output pin.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the 
receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O MOSI1 — Master Out Slave In for SSP1.
OMAT2[3] — Match output for Timer 2, channel 3.
P0[10]/TXD2/ 
SDA2/MAT3 [0] 69[1] I/O P0[10] — General purpose digital input/output pin.
OTXD2 — Transmitter output for UART2.
I/O SDA2 — I2C2 data input/output (this is not an open-drain pin).
OMAT3[0] — Match output for Timer 3, channel 0.
P0[11]/RXD2/ 
SCL2/MAT3[1] 70[1] I/O P0[11] — General purpose digital input/output pin.
IRXD2 — Receiver input for UART2.
I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin).
OMAT3[1] — Match output for Timer 3, channel 1.
P0[12]/MISO1/ 
AD0[6] 29[2] I/O P0[12] — General purpose digital input/output pin.
I/O MISO1 — Master In Slave Out for SSP1.
IAD0[6] — A/D converter 0, input 6.
P0[13]/ 
USB_UP_LED2/ 
MOSI1/AD0[7]
32[2] I/O P0[13] — General purpose digital input/output pin.
OUSB_UP_LED2 — USB port 2 Good Link LED indicator. It is LOW when device is 
configured (non-control endpoints enabled). It is HIGH when the device is not 
configured or during global suspend.
I/O MOSI1 — Master Out Slave In for SSP1.
IAD0[7] — A/D converter 0, input 7.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  7 of 57
NXP Semiconductors LPC2388
Fast communication chip
P0[14]/ 
USB_HSTEN2/ 
USB_CONNECT2/
SSEL1
48[1] I/O P0[14] — General purpose digital input/output pin.
OUSB_HSTEN2 — Host Enabled status for USB port 2.
OUSB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an 
external 1.5 kΩ resistor under software control. Used with the SoftConnect USB 
feature.
I/O SSEL1 — Slave Select for SSP1.
P0[15]/TXD1/ 
SCK0/SCK 89[1] I/O P0[15] — General purpose digital input/output pin.
OTXD1 — Transmitter output for UART1.
I/O SCK0 — Serial clock for SSP0.
I/O SCK — Serial clock for SPI.
P0[16]/RXD1/ 
SSEL0/SSEL 90[1] I/O P0 [16] — General purpose digital input/output pin.
IRXD1 — Receiver input for UART1.
I/O SSEL0 — Slave Select for SSP0.
I/O SSEL — Slave Select for SPI.
P0[17]/CTS1/ 
MISO0/MISO 87[1] I/O P0[17] — General purpose digital input/output pin.
ICTS1 — Clear to Send input for UART1.
I/O MISO0 — Master In Slave Out for SSP0.
I/O MISO — Master In Slave Out for SPI.
P0[18]/DCD1/ 
MOSI0/MOSI 86[1] I/O P0[18] — General purpose digital input/output pin.
IDCD1 — Data Carrier Detect input for UART1.
I/O MOSI0 — Master Out Slave In for SSP0.
I/O MOSI — Master Out Slave In for SPI.
P0[19]/DSR1/ 
MCICLK/SDA1 85[1] I/O P0[19] — General purpose digital input/output pin.
IDSR1 — Data Set Ready input for UART1.
OMCICLK — Clock output line for SD/MMC inte rface.
I/O SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0[20]/DTR1/ 
MCICMD/SCL1 83[1] I/O P0[20] — General purpose digital input/output pin.
ODTR1 — Data Terminal Ready output for UART1.
IMCICMD — Command line for SD/MMC interface.
I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin).
P0[21]/RI1/ 
MCIPWR/RD1 82[1] I/O P0[21] — General purpose digital input/output pin.
IRI1 — Ring Indicator input fo r UART1.
OMCIPWR — Power Supply Enable for external SD/MMC power supply.
IRD1 — CAN1 receiver input.
P0[22]/RTS1/ 
MCIDAT0/TD1 80[1] I/O P0[22] — General purpose digital input/output pin.
ORTS1 — Request to Send output for UART1.
OMCIDAT0 — Data line for SD/MMC inte rface.
OTD1 — CAN1 transmitter output.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  8 of 57
NXP Semiconductors LPC2388
Fast communication chip
P0[23]/AD0[0]/ 
I2SRX_CLK/ 
CAP3[0]
13[2] I/O P0[23] — General purpose digital input/output pin.
IAD0[0] — A/D converter 0, input 0.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. 
Corresponds to the signal SCK in the I2S-bus specification.
ICAP3[0] — Capture input for T imer 3, channel 0.
P0[24]/AD0[1]/ 
I2SRX_WS/ 
CAP3[1]
11[3] I/O P0[24] — General purpose digital input/output pin.
IAD0[1] — A/D converter 0, input 1.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the 
slave. Corresponds to the signal WS in the I2S-bus specification.
ICAP3[1] — Capture input for T imer 3, channel 1.
P0[25]/AD0[2]/ 
I2SRX_SDA/ 
TXD3
10[2] I/O P0[25] — General purpose digital input/output pin.
IAD0[2] — A/D converter 0, input 2.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the 
receiver. Corresponds to the signal SD in the I2S-bus specification.
OTXD3 — Transmitter output for UART3.
P0[26]/AD0[3]/ 
AOUT/RXD3 8[2] I/O P0[26] — General purpose digital input/output pin.
IAD0[3] — ]A/D converter 0, inpu t 3.
OAOUT — D/A converter output.
IRXD3 — Receiver input for UART3.
P0[27]/SDA0 35[4] I/O P0[27] — General purpose digital input/output pin.
I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance).
P0[28]/SCL0 34[4] I/O P0[28] — General purpose digital input/output pin.
I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
P0[29]/USB_D+1 42[5] I/O P0[29] — General purpose digital input/output pin.
I/O USB_D+1 — USB port 1 bidirectional D+ line.
P0[30]/USB_D−143[5] I/O P0[30] — General purpose digital input/output pin.
I/O USB_D−1 — USB port 1 bidirectional D− line.
P0[31]/USB_D+2 36[5] I/O P0[31] — General purpose digital input/output pin.
I/O USB_D+2 — USB port 2 bidirectional D+ line.
P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The 
operation of port 1 pins depends upon the pin function selected via the Pin Connect 
block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.
P1[0]/ 
ENET_TXD0 136[1] I/O P1[0] — General purpose digital input/output pin.
OENET_TXD0 — Ethernet tr an smi t da ta 0.
P1[1]/ 
ENET_TXD1 135[1] I/O P1[1] — General purpose digital input/output pin.
OENET_TXD1 — Ethernet tr an smi t da ta 1.
P1[4]/ 
ENET_TX_EN 133[1] I/O P1[4] — General purpose digital input/output pin.
OENET_TX_EN — Ethernet transmit data enable.
P1[8]/ 
ENET_CRS 132[1] I/O P1[8] — General purpose digital input/output pin.
IENET_CRS — Ethernet carrier sense.
P1[9]/ 
ENET_RXD0 131[1] I/O P1[9] — General purpose digital input/output pin.
IENET_RXD0 — Ethernet receive data.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  9 of 57
NXP Semiconductors LPC2388
Fast communication chip
P1[10]/ 
ENET_RXD1 129[1] I/O P1[10] — General purpose digital input/output pin.
IENET_RXD1 — Ethernet receive data.
P1[14]/ 
ENET_RX_ER 128[1] I/O P1[14] — General purpose digital input/output pin.
IENET_RX_ER — Ethernet receive error.
P1[15]/ 
ENET_REF_CLK 126[1] I/O P1[15] — General purpose digital input/output pin.
IENET_REF_CLK/ENET_RX_CLK — Ethernet receiver clock.
P1[16]/ 
ENET_MDC 125[1] I/O P1[16] — General purpose digital input/output pin.
OENET_MDC — Ethernet MIIM clock.
P1[17]/ 
ENET_MDIO 123[1] I/O P1[17] — General purpose digital input/output pin.
I/O ENET_MDIO — Ethernet MI data input and output.
P1[18]/ 
USB_UP_LED1/ 
PWM1[1]/ 
CAP1[0]
46[1] I/O P1[18] — General purpose digital input/output pin.
OUSB_UP_LED1 — USB port 1 Good Link LED indicator. It is LOW when device is 
configured (non-control endpoints enabled). It is HIGH when the device is not 
configured or during global suspend.
OPWM1[1] — Pulse Width Modulator 1, channel 1 outpu t.
ICAP1[0] — Capture input for T imer 1, channel 0.
P1[19]/ 
USB_TX_E1/ 
USB_PPWR1/ 
CAP1[1]
47[1] I/O P1[19] — General purpose digital input/output pin.
OUSB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver).
OUSB_PPWR1 — Port Power enable signal for USB port 1.
ICAP1[1] — Capture input for T imer 1, channel 1.
P1[20]/ 
USB_TX_DP1/ 
PWM1[2]/SCK0
49[1] I/O P1[20] — General purpose digital input/output pin.
OUSB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).
OPWM1[2] — Pulse Width Modulator 1, channel 2 outpu t.
I/O SCK0 — Serial clock for SSP0.
P1[21]/ 
USB_TX_DM1/ 
PWM1[3]/SSEL0
50[1] I/O P1[21] — General purpose digital input/output pin.
OUSB_TX_DM1 — D− transmit data for USB port 1 (OTG transceiver).
OPWM1[3] — Pulse Width Modulator 1, channel 3 outpu t.
I/O SSEL0 — Slave Select for SSP0.
P1[22]/ 
USB_RCV1/ 
USB_PWRD1/ 
MAT1[0]
51[1] I/O P1[22] — General purpose digital input/output pin.
IUSB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).
IUSB_PWRD1 — Power Status for USB port 1 (host power switch).
OMAT1[0] — Match output for Timer 1, channel 0.
P1[23]/ 
USB_RX_DP1/ 
PWM1[4]/MISO0
53[1] I/O P1[23] — General purpose digital input/output pin.
IUSB_RX_DP1 — D+ receive dat a fo r USB port 1 (OTG transceiver).
OPWM1[4] — Pulse Width Modulator 1, channel 4 outpu t.
I/O MISO0 — Master In Slave Out for SSP0.
P1[24]/ 
USB_RX_DM1/ 
PWM1[5]/MOSI0
54[1] I/O P1[24] — General purpose digital input/output pin.
IUSB_RX_DM1 — D− receive data for USB port 1 (OTG transceiver).
OPWM1[5] — Pulse Width Modulator 1, channel 5 outpu t.
I/O MOSI0 — Master Out Slave in for SSP0.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  10 of 57
NXP Semiconductors LPC2388
Fast communication chip
P1[25]/ 
USB_LS1/ 
USB_HSTEN1/ 
MAT1[1]
56[1] I/O P1[25] — General purpose digital input/output pin.
OUSB_LS1 — Low-speed status for USB port 1 (OTG transceiver).
OUSB_HSTEN1 — Host Enabled status for USB port 1.
OMAT1[1] — Match output for Timer 1, channel 1.
P1[26]/ 
USB_SSPND1/ 
PWM1[6]/ 
CAP0[0]
57[1] I/O P1[26] — General purpose digital input/output pin.
OUSB_SSPND1 — USB port 1 bus suspend status (OTG transceiver).
OPWM1[6] — Pulse Width Modulator 1, channel 6 outpu t.
ICAP0[0] — Capture input for T imer 0, channel 0.
P1[27]/ 
USB_INT1/ 
USB_OVRCR1/ 
CAP0[1]
61[1] I/O P1[27] — General purpose digital input/output pin.
IUSB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver).
IUSB_OVRCR1 — USB port 1 Over-Current status.
ICAP0[1] — Capture input for T imer 0, channel 1.
P1[28]/ 
USB_SCL1/ 
PCAP1[0]/ 
MAT0[0]
63[1] I/O P1[28] — General purpose digital input/output pin.
I/O USB_SCL1 — USB port 1 I2C-bus serial clock (OTG transceiver).
IPCAP1[0] — Capture input for PWM1, chan nel 0.
OMAT0[0] — Match output for Timer 0, channel 0.
P1[29]/ 
USB_SDA1/ 
PCAP1[1]/ 
MAT0[1]
64[1] I/O P1[29] — General purpose digital input/output pin.
I/O USB_SDA1 — USB port 1 I2C-bus serial data (OTG transceiver).
IPCAP1[1] — Capture input for PWM1, chan nel 1.
OMAT0[1] — Match output for Timer 0, channel 0.
P1[30]/ 
USB_PWRD2/ 
VBUS/AD0[4]
30[2] I/O P1[30] — General purpose digital input/output pin.
IUSB_PWRD2 — Power Status for USB port 2.
IVBUS — Monitors the presence of USB bus power .
Note: This signal must be HIGH for USB reset to occur.
IAD0[4] — A/D converter 0, input 4.
P1[31]/ 
USB_OVRCR2/ 
SCK1/AD0[5]
28[2] I/O P1[31] — General purpose digital input/output pin.
IUSB_OVRCR2 — Over-Current status for USB port 2.
I/O SCK1 — Serial Clock for SSP1.
IAD0[5] — A/D converter 0, input 5.
P2[0] to P2[31] I/O Port 2: Port 2 is a 32 bit I/O port with individual direction controls for each bit. Th e 
operation of port 2 pins depends upon the pin function selected via the Pin Connect 
block. Pins 14 through 31 of this port are not available.
P2[0]/PWM1[1]/ 
TXD1/ 
TRACECLK
107[1] I/O P2[0] — General purpose digital input/output pin.
OPWM1[1] — Pulse Width Modulator 1, channel 1 outpu t.
OTXD1 — Transmitter output for UART1.
OTRACECLK — Trace Clock.
P2[1]/PWM1[2]/ 
RXD1/ 
PIPESTAT0
106[1] I/O P2[1] — General purpose digital input/output pin.
OPWM1[2] — Pulse Width Modulator 1, channel 2 outpu t.
IRXD1 — Receiver input for UART1.
OPIPESTAT0 — Pipelin e Status, bit 0.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  11 of 57
NXP Semiconductors LPC2388
Fast communication chip
P2[2]/PWM1[3]/ 
CTS1/ 
PIPESTAT1
105[1] I/O P2[2] — General purpose digital input/output pin.
OPWM1[3] — Pulse Width Modulator 1, channel 3 outpu t.
ICTS1 — Clear to Send input for UART1.
OPIPESTAT1 — Pipelin e Status, bit 1.
P2[3]/PWM1[4]/ 
DCD1/ 
PIPESTAT2
100[1] I/O P2[3] — General purpose digital input/output pin.
OPWM1[4] — Pulse Width Modulator 1, channel 4 outpu t.
IDCD1 — Data Carrier Detect input for UART1.
OPIPESTAT2 — Pipelin e Status, bit 2.
P2[4]/PWM1[5]/ 
DSR1/ 
TRACESYNC
99[1] I/O P2[4] — General purpose digital input/output pin.
OPWM1[5] — Pulse Width Modulator 1, channel 5 outpu t.
IDSR1 — Data Set Ready input for UART1.
OTRACESYNC — Trace Synchronization.
P2[5]/PWM1[6]/ 
DTR1/ 
TRACEPKT0
97[1] I/O P2[5] — General purpose digital input/output pin.
OPWM1[6] — Pulse Width Modulator 1, channel 6 outpu t.
ODTR1 — Data Terminal Ready output for UART1.
OTRACEPKT0 — Trace Packet, bit 0.
P2[6]/PCAP1[0]/ 
RI1/ 
TRACEPKT1
96[1] I/O P2[6] — General purpose digital input/output pin.
IPCAP1[0] — Capture input for PWM1, chan nel 0.
IRI1 — Ring Indicator input fo r UART1.
OTRACEPKT1 — Trace Packet, bit 1.
P2[7]/RD2/ 
RTS1/ 
TRACEPKT2
95[1] I/O P2[7] — General purpose digital input/output pin.
IRD2 — CAN2 receiver input.
ORTS1 — Request to Send output for UART1.
OTRACEPKT2 — Trace Packet, bit 2.
P2[8]/TD2/ 
TXD2/ 
TRACEPKT3
93[1] I/O P2[8] — General purpose digital input/output pin.
OTD2 — CAN2 transmitter output.
OTXD2 — Transmitter output for UART2.
OTRACEPKT3 — Trace Packet, bit 3.
P2[9]/ 
USB_CONNECT1/ 
RXD2/ 
EXTIN0
92[1] I/O P2[9] — General purpose digital input/output pin.
OUSB_CONNECT1 — USB port 1 Soft Connect control. Signal used to switch an 
external 1.5 kΩ resistor under the software control. Used with the SoftConnect USB 
feature.
IRXD2 — Receiver input for UART2.
IEXTIN0 — External Trigger Input.
P2[10]/EINT0 76[6] I/O P2[10] — General purpose digital input/output pin.
Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to take over 
control of the part after a reset.
IEINT0 — External interru pt 0 input.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  12 of 57
NXP Semiconductors LPC2388
Fast communication chip
P2[11]/EINT1/ 
MCIDAT1/ 
I2STX_CLK
75[6] I/O P2[11] — General purpose digital input/output pin.
IEINT1 — External interru pt 1 input.
OMCIDAT1 — Data line for SD/MMC inte rface.
I/O I2STX_CLK — T ransmit Clock. It is driven by the master and received by the slave. 
Corresponds to the signal SCK in the I2S-bus specification.
P2[12]/EINT2/ 
MCIDAT2/ 
I2STX_WS
73[6] I/O P2[12] — General purpose digital input/output pin.
IEINT2 — External interru pt 2 input.
OMCIDAT2 — Data line for SD/MMC inte rface.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the 
slave. Corresponds to the signal WS in the I2S-bus specification.
P2[13]/EINT3/ 
MCIDAT3/ 
I2STX_SDA
71[6] I/O P2[13] — General purpose digital input/output pin.
IEINT3 — External interru pt 3 input.
OMCIDAT3 — Data line for SD/MMC inte rface.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the 
receiver. Corresponds to the signal SD in the I2S-bus specification.
P3[0] to P3[31] I/O Port 3: Port 3 is a 32 bit I/O port with individual direction controls for each bit. The 
operation of port 3 pins depends upon the pin function selected via the Pin Connect 
block. Pins 8 through 22, and 27 through 31 of this port are not available.
P3[0]/D0 137[1] I/O P3[0] — Gen eral purpose digital input/output pin.
I/O D0 — External memory data line 0.
P3[1]/D1 140[1] I/O P3[1] — Gen eral purpose digital input/output pin.
I/O D1 — External memory data line 1.
P3[2]/D2 144[1] I/O P3[2] — Gen eral purpose digital input/output pin.
I/O D2 — External memory data line 2.
P3[3]/D3 2[1] I/O P3[3] — General purpose digital input/output pin.
I/O D3 — External memory data line 3.
P3[4]/D4 9[1] I/O P3[4] — General purpose digital input/output pin.
I/O D4 — External memory data line 4.
P3[5]/D5 12[1] I/O P3[5] — General purpose digital input/output pin.
I/O D5 — External memory data line 5.
P3[6]/D6 16[1] I/O P3[6] — General purpose digital input/output pin.
I/O D6 — External memory data line 6.
P3[7]/D7 19[1] I/O P3[7] — General purpose digital input/output pin.
I/O D7 — External memory data line 7.
P3[23]/CAP0[0]/ 
PCAP1[0] 45[1] I/O P3[23] — General purpose digital input/output pin.
ICAP0[0] — Capture input for T imer 0, channel 0.
IPCAP1[0] — Capture input for PWM1, chan nel 0.
P3[24]/CAP0[1]/ 
PWM1[1] 40[1] I/O P3[24] — General purpose digital input/output pin.
ICAP0[1] — Capture input for T imer 0, channel 1.
OPWM1[1] — Pulse Width Modulator 1, output 1.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  13 of 57
NXP Semiconductors LPC2388
Fast communication chip
P3[25]/MAT0[0]/ 
PWM1[2] 39[1] I/O P3[25] — General purpose digital input/output pin.
OMAT0[0] — Match output for Timer 0, channel 0.
OPWM1[2] — Pulse Width Modulator 1, output 2.
P3[26]/MAT0[1]/ 
PWM1[3] 38[1] I/O P3[26] — General purpose digital input/output pin.
OMAT0[1] — Match output for Timer 0, channel 1.
OPWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31] I/O Port 4: Port 4 is a 32 bit I/O port with individual direction controls for each bit. The 
operation of port 4 pins depends upon the pin function selected via the Pin Connect 
block. Pins 16 through 23, 26, and 27 of this port are not available.
P4[0]/A0 52[1] I/O P4[0] — ]General purpose digital input/output pin.
I/O A0 — External memory address line 0.
P4[1]/A1 55[1] I/O P4[1] — General purpose digital input/output pin.
I/O A1 — External memory address line 1.
P4[2]/A2 58[1] I/O P4[2] — General purpose digital input/output pin.
I/O A2 — External memory address line 2.
P4[3]/A3 68[1] I/O P4[3] — General purpose digital input/output pin.
I/O A3 — External memory address line 3.
P4[4]/A4 72[1] I/O P4[4] — General purpose digital input/output pin.
I/O A4 — External memory address line 4.
P4[5]/A5 74[1] I/O P4[5] — General purpose digital input/output pin.
I/O A5 — External memory address line 5.
P4[6]/A6 78[1] I/O P4[6] — General purpose digital input/output pin.
I/O A6 — External memory address line 6.
P4[7]/A7 84[1] I/O P4[7] — General purpose digital input/output pin.
I/O A7 — External memory address line 7.
P4[8]/A8 88[1] I/O P4[8] — General purpose digital input/output pin.
I/O A8 — External memory address line 8.
P4[9]/A9 91[1] I/O P4[9] — General purpose digital input/output pin.
I/O A9 — External memory address line 9.
P4[10]/A10 94[1] I/O P4[10] — General purpose digital input/output pin.
I/O A10 — External memory address line 10.
P4[11]/A11 101[1] I/O P4[11] — General purpose digital input/outp ut pin.
I/O A11 — External memory address line 11.
P4[12]/A12 104[1] I/O P4[12] — General purpose digital input/output pin.
I/O A12 — External memory address line 12.
P4[13]/A13 108[1] I/O P4[13] — General purpose digital input/output pin.
I/O A13 — External memory address line 13.
P4[14]/A14 110[1] I/O P4[14] — General purpose digital input/output pin.
I/O A14 — External memory address line 14.
P4[15]/A15 120[1] I/O P4[15] — General purpose digital input/output pin.
I/O A15 — External memory address line 15.
Table 3. Pin description …continued
Symbol Pin Type Description

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  14 of 57
NXP Semiconductors LPC2388
Fast communication chip
P4[24]/OE 127[1] I/O P4[24] — General purpose digital input/output pin.
OOE — LOW active Output Enable signal.
P4[25]/BLS0 124[1] I/O P4[25] — General purpose digital input/output pin.
OBLS0 — LOW active Byte Lane select signal 0.
P4[28]/MAT2[0]/ 
TXD3 118[1] I/O P4 [28] — General purpose digital input/output pin.
OMAT2[0] — Match output for Timer 2, channel 0.
OTXD3 — Transmitter output for UART3.
P4[29]/MAT2[1]/ 
RXD3 122[1] I/O P4[29] — General purpose digital input/output pin.
OMAT2[1] — Match output for Timer 2, channel 1.
IRXD3 — Receiver input for UART3.
P4[30]/CS0 130[1] I/O P4[30] — General purpose digital input/output pin.
OCS0 — LOW active Chip Select 0 signal.
P4[31]/CS1 134[1] I/O P4[31] — General purpose digital input/output pin.
OCS1 — LOW active Chip Select 1 signal.
ALARM 26[8] OALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC 
alarm is generated.
USB_D−237 I/O USB_D−2 — USB port 2 bidirectional D− line.
DBGEN 6[1] IDBGEN — JTAG interface control signal. Also used for boundary scanning.
TDO 1[1] OTDO — Test Data out for JTAG interface.
TDI 3[1] ITDI — Test Data in for JTAG interface.
TMS 4[1] ITMS — Test Mode Select for JTAG interface.
TRST 5[1] ITRST — Test Reset for JTAG interface.
TCK 7[1] ITCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU 
clock (CCLK) for the JTAG interface to operate.
RTCK 143[1] I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate 
as Trace port after reset.
RSTOUT 20 ORSTOUT — This is a 1.8 V pin. LOW on this pin indicates LPC2388 being in Reset 
state.
RESET 24[7] Iexternal reset input: A LOW on this pin resets the device, causing I/O ports and 
peripherals to take on their default states, and processor execution to begin at 
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 31[8] IInput to the oscillator circuit and internal clock generator circuits.
XTAL2 33[8] OOutput from the oscillator amplifier .
RTCX1 23[8] IInput to the RTC oscillator circuit.
RTCX2 25[8] OOutput from the RTC oscillator circuit.
VSS 22, 44, 
59, 65, 
79, 103, 
117,119, 
139[9]
Iground: 0 V reference.
VSSA 15[10] Ianalog ground: 0 V reference. This should  nominally be the same voltage as VSS, 
but should be isolated to minimize noise and error.
Table 3. Pin description …continued
Symbol Pin Type Description

Preliminary data sheet Rev. 00.01 — 23 October 2007 15 of 57

NXP Semiconductors LPC2388

Fast communication chip

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,

digital section of the pad is disabled.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires an external pull-up to provide output

functionality. When pow er is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[6] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[8] Pad provides special analog functionality.

[9] Pad provides special analog functionality.

[10] Pad provides special analog functionality.

[11] Pad provides special analog functionality.

[12] Pad provides special analog functionality.

[13] Pad provides special analog functionality.

[14] Pad provides special analog functionality.

7. Functional description

7.1 Architectural overview

The LPC2388 microcontroller consists of an ARM7TDMI-S CPU with emulation support,

the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip

memory, the AMBA AHB interfacing to high-speed on-chip periphe rals and external

memory, and the AMBA APB for connection to other on-chip peripheral functions. The

microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte

order.

The LPC2388 implements two AHB buses in order to allow the Ethernet block to operate

without interference caused by other system activity. The primary AHB, referred to as

AHB1, includes the VIC, GPDMA controller, and EMC.

VDD(3V3) 41, 62,

77, 102,

114,

138[11]

I3.3 V supply voltage: This is the power supply voltage for the I/O ports.

n.c. 21, 81,

98[12] ILeave these pins unconnected.

VDD(DCDC)(3V3) 18, 60,

121[13] I3.3 V DC-to-DC converter supply voltage: This is the power supply for the on-chip

DC-to-DC converter only.

VDDA 14[14] Ianalog 3.3 V pad supply voltage: This should be nomi nally the same voltage as

VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to

power the ADC and DAC.

VREF 17[14] IADC reference: This should be nominally the same voltage as VDD(3V3) but should

be isolated to minimize noise and error. The level on this pin is used as a reference

for ADC and DAC.

VBAT 27[14] IRTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.

Table 3. Pin description …continued

Symbol Pin Type Description

Preliminary data sheet Rev. 00.01 — 23 October 2007 16 of 57

NXP Semiconductors LPC2388

Fast communication chip

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,

and the Ethernet b lock (via the bus bridge fr om AHB2). Bus masters with access to AHB2

are the ARM7 and the Ethernet block.

AHB peripherals are al located a 2 MB range of addresses at the very top of the 4 GB

ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the

AHB address space. Lower speed peripheral functions are connected to the APB bus.

The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also

allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB

peripheral is allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers

high performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed complex

instruction set computers. This simplicity results in a high instruction th ro ug h pu t an d

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are em ployed so that all p arts of the processing and memory system s

can operate continuously. Typically, while one instructio n is being e xecuted, its successor

is being decoded, and a thir d instruction is being fetched from memory.

The ARM7TDMI-S processor also empl oys a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instru ction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

•the standard 32-bit ARM set

•a 16-bit Thum b set

The Thumb set’ s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memor y syst em .

7.2 On-chip flash programming memory

The LPC2388 incorporates a 5 12 kB flash memory system. This memory may be used for

both code and data storage. Programming of the flash memory may be accomplished in

several ways. It may be programmed In System via the serial port (UART0). The

application program may also erase and/or program the flash while the application is

running, allowing a great degree of flexibility for data storage field and firmware upgrades.

Preliminary data sheet Rev. 00.01 — 23 October 2007 17 of 57

NXP Semiconductors LPC2388

Fast communication chip

The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to

allow it to operate at SRAM speeds of 72 MHz.

The LPC2388 provides a minimum of 100 000 write/erase cycles and 20 years of data

retention.

7.3 On-chip SRAM

The LPC2388 includes a SRAM memory of 64 kB reserved for the ARM processor

exclusive use. This RAM may be used for code and/or dat a storage and ma y be accessed

as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM

associated with the USB device can be used both for data and code storage, too. The

2 kB RTC can be used for data storage only. The RTC SRAM is battery powered and

retains the content in the absence of the main power supply.

7.4 Memory map

The LPC2388 memory map incorporates several distinct regions as shown in Figure 3.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either

flash memory (default), boot ROM, or SRAM (see Section 7.26.6).

Preliminary data sheet Rev. 00.01 — 23 October 2007 18 of 57

NXP Semiconductors LPC2388

Fast communication chip

7.5 Interrupt controller

The ARM processor cor e has two interrupt input s called Inte rrupt Request (IRQ) an d Fast

Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be

programmed as FIQ or vectored IRQ types. The programmable assignment scheme

means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

Fig 3. LPC2388 memory map

0.0 GB

1.0 GB

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

0x0000 0000

0x0007 FFFF

0x0008 0000

RESERVED FOR ON-CHIP MEMORY

64 kB LOCAL ON-CHIP STATIC RAM

RESERVED ADDRESS SPACE

0x4000 0000

0x4001 0000

0x7FD0 0000

0x7FE0 0000

0x7FD0 3FFF

0x7FE0 3FFF

0x4000 FFFF

2.0 GB 0x8000 0000

BOOT ROM AND BOOT FLASH

(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)

3.0 GB 0xC000 0000

RESERVED ADDRESS SPACE

3.75 GB

4.0 GB

3.5 GB

AHB PERIPHERALS

APB PERIPHERALS

0xE000 0000

0xF000 0000

0xFFFF FFFF

USB RAM (16 KB)

ETHERNET RAM (16 kB)

002aad331

0x8000 0000

0x8000 FFFF

0x8100 FFFF

0x8100 0000

EXTERNAL MEMORY BANK 0 (64 kB)

EXTERNAL MEMORY BANK 1 (64 kB)

Preliminary data sheet Rev. 00.01 — 23 October 2007 19 of 57

NXP Semiconductors LPC2388

Fast communication chip

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs

the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ

latency is achieved when only one request is classified as FIQ, because then the FIQ

service routine can simply start dealing with that device. But if more than one request is

assigned to the FIQ class, the FIQ service routine can read a word from the VIC that

identifies which FIQ source(s) is (are) requestin g an inte rr up t.

Vectored IRQs, which include all interrupt requests that are not cla ssified as FIQs, have a

programmable interrupt priority. When more than one interrupt is assigned the same

priority and occu r simultaneously, the one connected to the lowest numbered VIC chan nel

will be serviced first.

The VIC ORs the reques ts from all of the ve ctored IRQs to produce the IRQ signal to the

ARM processor. The IRQ service routine can start by reading a register from the VIC and

jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several

interrupt flags. Individual interrup t flags may also represent more than one interrupt

source.

Any pin on PORT0 and PORT2 (total of 46 pins) regardless of the selected function, can

be programmed to gener ate an interrupt on a rising edge, a falling edge, or both. Such

interrupt request coming from PORT0 and/or PORT2 will be combined with the EINT3

interrupt requests.

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on chip peripherals.

Peripherals should be conn ected to th e appro priate pins prior to being activated and prior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 External memory controller

The LPC2388 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering

support for asynchronous static memory devices such as RAM, ROM, and flash. In

addition, it can be used as an interface with off-chip memory-mapped devices and

peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant

peripheral.

7.7.1 Features

•Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode

•Low transaction latency

•Read and write buffers to reduce latency and to improve performance

•8 data and 16 addr ess lines wide static memory support

•Tw o chip selects for static memory devices

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•Static memory features include :

–Asynchronous page mode read

–Programmable Wait Stat es (WST)

–Bus turnaround delay

–Output enable and write enable delays

–Extended wait

7.8 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2388

peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral- to -p e riphe ra l, an d m em o ry- to -m e mo ry tran sa ct ion s. Eac h DM A stre am

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receive. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the AHB master.

7.8.1 Features

•Two DMA channels. Each channel can support a unidirectional transfer.

•The GPDMA can transfer data between the 16 kB SRAM and peripherals such as the

SD/MMC, two SSP, and I2S interfaces.

•Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the GPDMA.

•Memory-to-memory, memory-to-peripheral, peripheral-to- memory, and

peripheral-to-peripheral transfers.

•Scatter or gather DMA is supported through the use of linked lists . This means that

the source and destination areas do not have to occupy contiguous areas of memory.

•Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest prior ity. If

requests from two channels become active at the same time, the channel with the

highest priority is serviced first.

•AHB slave DMA programming interface. The GPDMA is programmed by writing to th e

DMA control register s ove r the AHB slav e int er fa ce.

•One AHB bus master for transferring dat a. This interface transfers data when a DMA

request goes active.

•32-bit AHB master bus width.

•Incrementing or non-incrementing addressing for source and destination.

•Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the

peripheral.

•Internal four-word FIFO per channel.

•Supports 8-bit, 16-bit, and 32-bit wide transactions.

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•An interrupt to the pr ocessor ca n be gene rated o n a DMA comp letion or when a DMA

error has occurred.

•Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

•Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

LPC2388 use accelerated GPIO functions:

•GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved .

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All GPIO registers are byte and half-word addressable.

•Entire port value can be written in one instruction.

Additionally, any pin on PORT0 and PORT2 (total of 46 pins) providing a digital function

can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The

edge detection is asynchronous, so it may operate when clocks are not present such as

during Power-down mode. Each enabled interrupt can be used to wake up the chip from

Power-down mode.

7.9.1 Features

•Bit level set and clear registers allow a single instr uction to set or clear any nu mber of

bits in one port.

•Direction control of individual bits.

•All I/O default to inputs after reset.

•Backward compatibility with other earlier devices is maintained with legacy PORT0

and POR T1 registers appearing a t the original addresses on the APB bus.

7.10 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, flow control, control frames, hardware acceleration for transmit retry, receive

packet filtering an d wa ke-u p o n LAN activity. Automatic frame transmission and reception

with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access

the Ethernet SRAM for Ethernet da ta, contr ol, and st atus information. All other AHB traffic

in the LPC2388 t akes pla ce on a dif ferent AHB subsystem, ef fectively separ ating Ethernet

activity from the rest of the system. The Ethernet DMA can also access off-chip memory

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via the EMC, as well as the SRAM located on another AHB, if it is not being used by the

USB block. However, using memory other than the Ethernet SRAM, especially off-chip

memory, will slow Ethernet access to memory and increase the loading of its AHB.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII

(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial

bus.

7.10.1 Features

•Ethernet st andards support:

–Support s 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

–Fully compliant with IEEE standard 802.3.

–Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back

pressure.

–Flexible transmit and receive frame options.

–Vir tual Local Area Network (VLAN) frame suppor t.

•Memory management:

–Independent transmit and receive buffers memory mapped to shared SRAM.

–DMA managers with scatter/gather DMA and arrays of frame descriptors.

–Memory traffic optimized by buffering and pre-fetching.

•Enhanced Ethernet features:

–Receive filtering.

–Multicast and broadcast frame support for both transmit and receive.

–Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

–Selectable automatic transmit frame padding.

–Over-length frame suppor t for both transmit and receive allows any length frames.

–Promiscuous receive mode.

–Automatic collision back-off and frame retransmission.

–Includes power management by clock switching.

–Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

•Physical interface:

–Attachment of external PHY chip through standard RMII interface.

–PHY register access is available via the MIIM interface.

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7.11 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The Host Controller allocates the USB

bandwidth to attached devices th rough a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

Host Controller.

The LPC2388 USB interface includes a device, Host, and OTG Controller. Details on

typical USB interfacing solutions can be found in Section 11.1.

7.11.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host Controller. It

consists of a register interface, serial interface engine, endpoint buffer memory, and a

DMA controller. The serial interface e ngine dec odes the USB data stream a nd writes dat a

to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled. When

enabled, the DMA controller transfer s data between the endpoint buffer and the USB

RAM.

7.11.1.1 Features

•Fully compliant with USB 2.0 specification (full speed).

•Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

•Supports Control, Bulk, Interrupt and Isochronous endpoints.

•Scalable realization of endpoi nts at run time.

•Endpoint Maximum pa cket size selection (up to USB maximum specification) by

software at run time.

•Supports SoftConnect and GoodLink features.

•While the USB is in the Suspend mode, the LPC2388 can enter one of the reduced

power modes and wake up on USB activity.

•Supports DMA transfers with th e DM A RAM of 16 kB on all non-control endpoints.

•Allows dynamic switching between CPU-controlled and DMA modes.

•Double buffer implementation for Bulk and Isochronous endpoints.

7.11.2 USB Host Controller

The Host Controller enables full- and low-speed data exchange with USB devices

attach ed to the bus. It consists of register inte rface, serial interface engine and DMA

controller. The register interface complies with the OHCI specification.

7.11.2.1 Features

•OHCI compliant.

•Tw o do wn str e am por ts.

•Supports per-port power switching.

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7.11.3 USB OTG Controller

USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that au gments the

capability of existing mobile devices and USB peripherals by adding host functionality for

connection to USB peripherals.

The OTG Controller integrates the Host Controller, device controller, and a master-only

I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface

controls an external OTG transceiver.

7.11.3.1 Features

•Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

1.0a.

•Hardware support for Host Negotiation Protocol (HNP).

•Includes a programmable timer required for HNP and Session Request Protocol

(SRP).

•Supports any OTG transceiver compliant with the OTG Transceiver Specification

(CEA-2011), Rev. 1.0.

7.12 CAN controller and acceptance filters

The Controller Area Network (C AN) is a serial communications protocol which efficiently

supports distributed real-time control with a very high level of security. Its dom ain of

application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a gateway, switch, or router among a number of CAN buses in

industrial or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN

Library block, but the 8-bit registers of those devices have been combined in 32-bit words

to allow simult aneous access in the ARM environment. Th e main operationa l dif ference is

that the recognition of received Identifiers, known in CAN terminology as Acceptance

Filtering, has been removed from the CAN controllers and centralized in a global

Acceptance Filter.

7.12.1 Features

•Two CAN controllers and buses.

•Data rates to 1 Mbit/s on each bus.

•32-bit register and RAM access.

•Compatible with CAN specification 2.0B, ISO 11898-1.

•Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN

buses.

•Acceptance Filter can provide FullC AN-style automatic reception for selected

Standard Identifiers.

•Full CAN messages can generate interrupts.

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7.13 10-bit ADC

The LPC2388 contains one ADC. It is a single 10-bit successive approximation ADC with

eight channels.

7.13.1 Features

•10-bit successive approximation ADC

•Input multiplexing among 8 pins

•Power-down mode

•Measurement range 0 V to Vi(VREF)

•10-bit conver sio n time ≥ 2.44 μs

•Burst conversion mode for single or multiple inputs

•Optional conversion on transition of input pin or Timer Match signal

•Individual result registers for each ADC channel to reduce interrupt overhead

7.14 10-bit DAC

The DAC allows the LPC2388 to generate a vari able analog ou tput. The maximum outp ut

value of the DAC is Vi(VREF).

7.14.1 Features

•10-bit DAC

•Resistor string architecture

•Buffered output

•Power-down mode

•Selectable output drive

7.15 UARTs

The LPC2388 contains four UARTs. In addition to standard transmit and receive data

lines, UART1 also provides a full modem control handshake interface.

The UARTs inclu de a fractional baud r ate generator. S t andard baud rates such as 115 200

can be achieved with an y crystal frequency above 2 MHz.

7.15.1 Features

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud ra te generator covering wide range of baud rates without a

need for external crystals of particular values.

•Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

•UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

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•UART3 includes an IrDA mode to support infrared communication.

7.16 SPI serial I/O controller

The LPC2388 cont ains on e SPI controller. SPI is a full duplex serial interface designed to

handle multiple maste rs and slaves co nnected to a given bus. Only a single ma ster and a

single slave can communicate on the inte rface during a given data transfer. During a data

transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave

always sends 8 bits to 16 bits of data to the master.

7.16.1 Features

•Compliant with SPI specification

•Synchronous, Serial, Full Duplex Communication

•Combined SPI master and slave

•Maximum data bit rate of one eighth of the input clock rate

•8 bits to 16 bits per transfer

7.17 SSP serial I/O controller

The LPC2388 cont ains two SSP controllers. The SSP controller is cap able of operation on

a SPI, 4-wire SSI, or Microwire bus. It can intera ct with multiple masters and slaves on the

bus. Only a single maste r and a sin gle slav e can communicate on the bus during a given

data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of

data flowing from the master to the slave and from the slave to the master. In practice,

ofte n only one of these data flo ws carries meaningful data.

7.17.1 Features

•Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire

buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

•DMA transfers supp orte d by GPDMA

7.18 SD/MMC card interface

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD

memory cards. The SD card interface conforms to the SD Multimedia Card Specification

Version 2.11.

7.18.1 Features

•The MCI provides all functions specific to the SD/MMC memory card. These include

the clock generation unit, power management control, and command and dat a

transfer.

•Conforms to Multimedia Card Specification v2.11.

•Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

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•Can be used as a multimedia card bus or a secure d igit al memo ry card bus ho st. The

SD/MMC can be connected to several multimedia cards or a single secure digital

memory card.

•DMA supported through the GPDMA controller.

7.19 I2C-bus serial I/O controllers

The LPC2388 contains three I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Eac h device is recognized by a unique address and

can operate as either a r eceiver-only de vice ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on whe ther th e chip ha s

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus and can

be controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2388 supports bit rates up to 400 kbit/s (Fast I2C-bus).

7.19.1 Features

•I2C0 is a standard I2C compliant bus interface with open-drain pins.

•I2C1 and I2C2 use standard I/O pins and do no t support powering off of individual

devices connected to the same bus lines.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with diff erent bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer.

•The I2C-bus can be used for test an d diagnostic purposes.

7.20 I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio applications.

The I2S-bus specificatio n defines a 3-wire serial bus using one da ta line, one clock line,

and one word select signal. The basic I2S-bus connection has one master, which is

always the master, and one slave. The I2S interface on the LPC238 8 pro vides a separate

transmit and re ce ive chann el, each of whic h ca n op er at e as either a master or a slav e.

7.20.1 Features

•The interface has sep arate input/output channels each of which can o perate in master

or slave mode.

•Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

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•Mono and stereo au dio data supported.

•The sampling frequency can range from 16 kHz to 48 kHz ((16, 22.05, 32, 44.1,

48) kHz).

•Configurable word select period in master mode (separately for I2S input and output).

•Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

•Generates interrupt requests when buffer levels cross a pr ogrammable boundary.

•Two DMA requests, controlled by programmable buf fer levels. These are connected

to the GPDMA block.

•Controls include reset, stop and mute optio ns separately for I2S input and I2S output.

7.21 General purpose 32-bit timers/external event counters

The LPC2388 includes four 32-bit Timer/Counters. The Timer/Counter is designed to

count cycles of the system derived clock or an externally-supplied clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. The Timer/Counter also includes four capture inputs to trap the timer

value when an input signal transitions, optionally generating an interrupt.

7.21.1 Features

•A 32-bit Timer/Counter with a programmable 32-bit prescaler.

•Counter or Timer operation.

•Up to four 32-bit capture channels per timer, that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match.

–St op timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.22 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2388. The Timer is designed to count

cycles of the system derived clock and optionally switch pins, generate interrupts or

perform other actions when spe cified timer values occur , based on seven match registers.

The PWM function is in addition to these features, and is based on match register events.

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The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

controlled PWM ou tp u ts require on ly on e m atc h register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM output s will all have a

rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edge s co ntr o lled .

Again, the PWMMR0 match register controls the PWM cycle rate. The other match

registers control the two PWM edge positions. Additional double edge controlled PWM

outputs require only two match registers each, since the repetition rate is the same for all

PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

7.22.1 Features

•LPC2388 has one PWM block with Counter or Timer operation (may use the

peripheral clock or one of the capture inputs as the clock source).

•Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

–Continuous operation with optional interrupt generation on match.

–St op timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the

output is a constant low. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

•Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

•Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

•Match register updates are synchronized with pulse outputs to preven t ge ne ra tio n of

erroneous pulses. Sof tware must ‘release’ new ma tch values before they can b ecome

effective.

•May be used as a standard timer if the PWM mode is not enabled.

•A 32-bit Timer/Counter with a programmable 32-bit Prescale r.

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7.23 Watchdog timer

The purpose of the watchdog is to rese t the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.23.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 32-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in

multiples of Tcy(WDCLK) × 4.

•The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the

Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of

potential timing choices of Watchdog operation under d ifferent power reduction

conditions. It also provides the ability to run the WDT from an entirely internal source

that is not dependent on an external crystal and it s associated components a nd

wiring, for increased reliability.

7.24 RTC and battery RAM

The R TC is a set of counte rs for measur ing time when system power is on, and optiona lly

when it is of f. It uses little power in Power-down mode. On the LPC2388, the RTC can be

clocked by a sep arate 32.768 kHz oscillator or by a programmable prescale divider based

on the APB clock. Also, the R TC is powered by its own power supply pin, VBAT, which can

be connected to a battery or to the same 3.3 V supply used by the rest of the device.

The VBAT pin supplies power only to the RTC and the Battery RAM. Th ese two fu nctions

require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC

can supply an alarm output that can be used by external hardware to restore chip power

and resume operation.

7.24.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra low power design to support battery powered systems.

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

•Dedicated 32 kHz oscillator or programmable prescaler from APB clock.

•Dedicated power supply pin can be connected to a batte ry or to the main 3.3 V.

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•An alarm output pin is included to assist in waking up from Power-down mode, or

when the chip has had po wer removed to all functions except the RTC and Battery

RAM.

•Periodic interru pts can be generated fr om increments o f any field of the time registers,

and selected fractional second values.

•2 kB data SRAM powered by VBAT.

•RTC and Battery RAM power supply is isolated from the rest of the chip.

7.25 Clocking and power control

7.25.1 Crystal oscillators

The LPC2388 includes three independent oscillators. These are the Main Oscillator, the

Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than

one purpose as r eq uired in a particular applicatio n. Any of th e three clock sour ce s can be

chosen by software to drive the PLL and ultimately the CPU.

Following reset, the LPC2388 will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

7.25.1.1 Internal RC oscillator

The IRC may be used as th e clock source for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is

trimmed to 1 % accuracy.

Upon power-up or any chip reset, the LPC2388 uses the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.25.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or withou t using the

PLL. The main oscillator operates at frequencies of 1 MHz to 24 MHz. This frequency can

be boosted to a higher frequency, up to the maximum CPU operatin g frequency, by the

PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock

frequency is referred to as CCLK elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The

clock frequency for each peripheral can be selected individually and is referred to as

PCLK. Refer to Section 7.25.2 for additional information.

7.25.1.3 RTC oscillator

The RTC oscillator can be used as the clock source for the R TC and/or the WDT. Also, the

RTC oscillator can be used to drive the PLL and the CPU.

7.25.2 PLL

The PLL accepts an input clock frequency in the range of 32 kHz to 50 MHz. The input

frequency is multiplied up to a high frequency, then divided down to provide the actual

clock used by the CPU and the USB block.

The PLL input, in the range of 32 kH z to 50 MHz, may initially be divided down by a value

‘N’, which may be in the range of 1 to 256. This input division provides a wide range of

output frequencies from the same input frequency.

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Following the PLL input divider is the PLL multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the

range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to

550 MHz. The multiplier works by dividing the CCO outp ut by the value of M, then using a

phase-frequency detector to compare the divided CCO output to the multiplier input. The

error value is used to adjust the CCO frequency.

The PLL is turned off and bypassed following a chip Reset and by entering Power-down

mode. PLL is enabled by sof tware only. The program must configure an d activate the PLL,

wait for the PLL to lock, then connect to the PLL as a clock source.

7.25.3 Wake-up timer

The LPC2388 begins opera tion at power-up and when awakened from Power-down mode

by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to

resume quickly. If the main oscillator or the PLL is needed by the application, software will

need to enable these features and wait for them to stabilize before they are used as a

clock source.

When the main oscillator is initially activated, the wake-up timer allows sof twa re to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on , all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the wake-up Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some event caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufficie nt amplitude to drive the clock logic. The amount of time depe nds on many factors,

including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its

electrical characte ristics (if a q uartz cr yst al is used) , as well as any other external circ uitry

(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.25.4 Power control

The LPC2388 su pports a var iety of power control features. There are three special modes

of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU

clock rate may also be controlled as needed by changing clock sources, reconfiguring

PLL values, and/ or alte ring th e CPU cl oc k divi der value. This allows a trade-off of power

versus processing speed based on ap plication requirements. In addition, Peripheral

Power Control allows shutting down the clocks to individual on-chip peripherals, allowing

fine tuning of power consum ption by eliminat ing all dynamic power use in an y peripher als

that are not required for the application. Each of the peripherals has its own clock divider

which provides even better power control.

The LPC2388 also implements a separate power domain in order to allow turning off

power to the bulk of the device while maint aining opera tion of the RTC and a small SRAM,

referred to as the Battery RAM.

Preliminary data sheet Rev. 00.01 — 23 October 2007 33 of 57

NXP Semiconductors LPC2388

Fast communication chip

7.25.4.1 Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mod e and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.25.4.2 Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The

processo r state and re gis t e rs, per iph e ra l registers, and internal SRAM values are

preserved throughout Sleep mode and the logic levels of chip pins remain static. The

output of the IRC is disabled but the IRC is not powered down fo r a fast wake-up later . The

32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnecte d. The CCLK and

USB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset or

certain specific interrupts that are able to function without clocks. Since all dynamic

operation of the chip is suspended, Sleep mode reduces chip power consumption to a

very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.

On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the

code execution and peripherals activities will resume after 4 cycles expire. If the main

external oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconfigur e the PLL and clock dividers accordingly.

7.25.4.3 Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRC

oscillator and the flash memory. This saves more power, but requires waiting for

resumption of flash operation before execution of code or dat a access in the flash memory

can be accomplished.

On the wake-up of power-down mode, if the IRC was used before entering power- down

mode, it will take IRC 60 μs to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. In the meantime, the

flash wake-up timer then coun ts 4 MHz IRC clock cycles to make the 100 μs flash start-up

time. When it times out, access to the flash will be allowed. The customers need to

reconfigure the PLL and clock dividers accordingly.

7.25.4.4 Power domains

The LPC2388 provides two independent power domains that allow the bulk of the device

to have power removed while maintaining operation of the RTC and the Battery RAM.

On the LPC2388, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the

VDD(DCDC)(3V3) pin powers the on-chip DC-to-DC converte r which in turn provides power to

the CPU and most of the peripherals.

Depending on the LPC2388 application, a design can use two power options to manage

power consum p tion .

Preliminary data sheet Rev. 00.01 — 23 October 2007 34 of 57

NXP Semiconductors LPC2388

Fast communication chip

The first option assumes that power consumption is not a concern and the de sign ties the

VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and

a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-to-DC

converter powered independently from the I/O pad ring enables shutting down of the I/O

pad power supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC and the Battery RAM. Th ese two fu nctions

require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC

can supply an alarm output that may be used by external hardware to restore chip power

and resume operation.

7.26 System control

7.26.1 Reset

Reset has four sources on the LPC2388: the RESET pin, the Watchdog reset, power-on

reset, and the BrownOut Detection (BOD) cir cuit. The RESET pin is a Schmitt trigger input

pin. Assertion of chip Reset by any source, once the oper ating voltage attains a usable

level, st arts the Wake-up timer (see description in Section 7.25.3 “Wake-up timer”),

causing reset to remain asserted until the external Reset is de-asserted, the oscillator is

running, a fixed number of clocks have p assed , and th e fla sh control ler ha s comp leted it s

initialization.

When the internal Reset is removed, th e processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At th at point , all of the pr ocessor

and peripheral registers have been initialized to predetermined values.

7.26.2 Brownout detection

The LPC2388 includes 2-stage monitori ng of the voltage on the VDD(3V3) pins. If this

voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt

Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the

VIC in order to cause a CPU interrupt; if no t, so ftware can mo nitor the sig nal by rea ding a

dedicated status register.

The second stage of low-vo ltage detection assert s Reset to inactivate the LPC2388 when

the voltage on the VDD(3V3) pins falls below 2.65 V. This Reset prevents alteration of the

flash as operation of the various elements of the chip would otherwise become unreliable

due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point

the power-on res et circu itry maintains the overall Reset .

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regu larly executed event

loop to sense the condition.

Preliminary data sheet Rev. 00.01 — 23 October 2007 35 of 57

NXP Semiconductors LPC2388

Fast communication chip

7.26.3 Code security (Code Read Protection - CRP)

This feature of the LPC2388 allows user to enabl e differ ent levels of security in the system

so that access to the on-chip flash and use of the JTAG and ISP can be restrict ed . When

needed, CRP is invoked by pr ogramming a specific p attern into a dedicated flash location.

IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables ac cess to ch ip via th e JTAG and only allows full flash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

7.26.4 AHB bus

The LPC2388 implements two AHB buses in order to allow the Ethernet block to operate

without interference caused by other system activity. The primary AHB, referred to as

AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and

8 kB SRAM primarily intended for use by the USB.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the

GPDMA function, and the Etherne t block (via the bus bridge from AHB2). Bus m ast er s

with access to AHB2 are the ARM7 and the Ethernet block.

7.26.5 External interrupt inputs

The LPC2388 includes up to 50 edge sensitive interrupt inputs combined with up to four

level sensitive external interrupt inputs as selectable pin functions. The external interrupt

inputs can optionally be used to wake up the processor from Power-down mode.

7.26.6 Memory mapping control

The memory mapping control alter s the mapping of the interrupt vectors that appear at the

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot

ROM, the SRAM, or external memory. This allows code running in different memory

spaces to have control of the interrupts.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Preliminary data sheet Rev. 00.01 — 23 October 2007 36 of 57

NXP Semiconductors LPC2388

Fast communication chip

7.27 Emulation and debugging

The LPC2388 support emulation and debugging via a JTAG serial port. A trace port allows

tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface

peripherals residing on other pins are available during the development and debugging

phase as they are when the application is run in the embedded system itself.

7.27.1 EmbeddedICE

The EmbeddedICE logic provides on-chip de bug support. The debugging of the target

system requires a host computer running the debugger software and an EmbeddedICE

protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug

Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present

on the tar get system.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC

allows a program runn ing on the target to communica te with the host debugger or another

separate host without stopping the program flow or even entering the debug state. The

DCC is accessed as a coprocessor 14 by t he program running on the ARM7TDMI-S core.

The DCC allows the JTAG port to be used for sending and receiving dat a without af fecting

the normal progr am flow. The DCC dat a and contro l registers ar e mapped in to addresses

in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG

interface to operate.

7.27.2 Embedded trace

Since the LPC2388 have significant amounts of on-chip memories, it is not possible to

determine how the processor core is operating simply by observing the external pins. The

ETM provides real-time trace capability for deeply embedded processor cores. It outputs

information about processor execution to a trace port. A software debugger allows

configuration of the ETM using a JTAG interface and displays the trace information that

has been captured.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

Trace Port Analyzer captures the trace information under software debugger control. The

trace port can broadcast the Instruction trace information. Instruction trace (or PC trace)

shows the flow of execution of the processor and pro vides a list of all the instructio ns that

were executed. Instruction trace is significantly compressed by only broadcasting branch

addresses as well as a set of status signals that indicate the pipeline st atus on a cycle by

cycle basis. Trace information generation can be controlled by selecting the trigger

resource. Trigger resources include address comparators, counters and sequencers.

Since trace information is compressed the software debugger requires a static image of

the code being executed. Self-modifying code can not be traced because of this

restriction.

Preliminary data sheet Rev. 00.01 — 23 October 2007 37 of 57

NXP Semiconductors LPC2388

Fast communication chip

7.27.3 RealMonitor

RealMonitor is a configurab le software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while user s

debug their fo reground application. It co mmunicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2388 contain a specific configuration of

RealMonitor software programmed into the on-chip ROM memory.

Preliminary data sheet Rev. 00.01 — 23 October 2007 38 of 57

NXP Semiconductors LPC2388

Fast communication chip

8. Limiting values

[1] The following applies to the Limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] Dependent on package type.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(3V3) supply voltage (3.3 V) core and external

rail 3.0 3.6 V

VDD(DCDC)(3V3) DC-to-DC converter supply voltage

(3.3 V) 3.0 3.6 V

VDDA analog 3.3 V pad supply voltage −0.5 +4.6 V

Vi(VBAT) input voltage on pin VBAT for the RTC −0.5 +4.6 V

Vi(VREF) input voltage on pin VREF −0.5 +4.6 V

VIA analog input voltage on ADC related

pins −0.5 +5.1 V

VIinput voltage 5 V tolerant I/O

pins; only valid

when the VDD(3V3)

supply voltage is

present

[2] −0.5 +6.0 V

other I/O pins [2][3] −0.5 VDD(3V3) +

0.5 V

IDD supply current per supply pin [4] -100 mA

ISS ground current per ground pin [4] -100 mA

Tstg storage temperature [5] −65 +150 °C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device pow e r

consumption

-1.5 W

Vesd electrostatic discharge voltage human body

model; all pins [6] −2 000 +2 000 V

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  39 of 57
NXP Semiconductors LPC2388
Fast communication chip
9. Static characteristics
 
Table 5. Static characteristics 
Tamb = 
−
40 
°
C to +85 
°
C for commercial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V
VDD(DCDC)(3V3) DC-to-DC converter 
supply voltage (3.3 V) 3.0 3.3 3.6 V
VDDA analog 3.3 V pad 
supply voltage 3.0 3.3 3.6 V
Vi(VBAT) input voltage on pin 
VBAT [2] 2.0 3.3 3.6 V
Vi(VREF) input voltage on pin 
VREF 2.5 3.3 VDDA V
Standard port pins, RESET, RT CK
IIL LOW-level input 
current VI = 0 V; no pull-up --3μA
IIH HIGH-level input 
current VI = VDD(3V3); no pull-down --3μA
IOZ OFF-state output 
current VO = 0 V; VO = VDD(3V3); 
no pull-up/down --3μA
Ilatch I/O latch-up current −(0.5VDD(3V3)) < VI < 
(1.5VDD(3V3));
Tj < 125 °C
--100 mA
VIinput voltage pin configured to provide a 
digital function [3][4][5] 0 - 5.5 V
VOoutput voltage  output active 0 - VDD(3V3) V
VIH HIGH-level input 
voltage 2.0 - - V
VIL LOW-level input 
voltage --0.8 V
Vhys hysteresis voltage -0.4 - V
VOH HIGH-level output 
voltage IOH = −4 mA [6] VDD(3V3) − 
0.4 - - V
VOL LOW-level output 
voltage IOL = −4 mA [6] --0.4 V
IOH HIGH-level output 
current VOH = VDD(3V3) − 0.4 V [6] −4 - - mA
IOL LOW-level output 
current VOL = 0.4 V [6] 4 - - mA
IOHS HIGH-level 
short-circuit output 
current
VOH = 0 V [7] --−45 mA
IOLS LOW-level short-circuit 
output current VOL = VDDA [7] --50 mA
Ipd pull-down current VI = 5 V [8] 10 50 150 μA
Ipu pull-up current VI = 0 V −15 −50 −85 μA
VDD(3V3) < VI < 5 V [8] 000μA

Preliminary data sheet Rev. 00.01 — 23 October 2007 40 of 57

NXP Semiconductors LPC2388

Fast communication chip

IDD(DCDC)act(3V3) active mode DC-to-DC

converter supply

current (3.3 V)

VDD(DCDC)(3V3) = 3.3 V;

Tamb = 25 °C; code

while(1){}

executed from flash; no

peripherals enabled;

PCLK = CCLK

CCLK = 10 MHz -15 -mA

CCLK = 72 MHz -63 -mA

all peripherals enabled;

PCLK = CCLK / 8

CCLK = 10 MHz -21 -mA

CCLK = 72 MHz -92 -mA

all peripherals enabled;

PCLK = CCLK

CCLK = 10 MHz -27 -mA

CCLK = 72 MHz -125 -mA

IDD(DCDC)pd(3V3) power-down mode

DC-to-DC con v e rter

supply current (3.3 V)

VDD(DCDC)(3V3) = 3.3 V;

Tamb = 25 °C-150

μA

IBATact active mode battery

supply current [9] -20 -μA

I2C-bus pins (P0[27] and P0[28])

VIH HIGH-level input

voltage 0.7VDD(3V3) - - V

VIL LOW-level input

voltage --0.3VDD(3V3) V

Vhys hysteresis voltage -0.5VDD(3V3) - V

VOL LOW-level output

voltage IOLS = 3 mA [6] --0.4 V

ILI input leakage curren t VI = VDD(3V3) [10] - 2 4 μA

VI = 5 V - 10 22 μA

Oscillator pins

Vi(XTAL1) i nput voltage on pin

XTAL1 0 - 1.8 V

Vo(XTAL2) o utput voltage on pin

XTAL2 0 - 1.8 V

Vi(RTCX1) input voltage on pin

RTCX1 0 - 1.8 V

Vo(RTCX2) output voltage on pin

RTCX2 0 - 1.8 V

USB pins

IOZ OFF-state output

current 0 V < VI < 3.3 V - - ±10 μA

VBUS bus suppl y voltage --5.25 V

Table 5. Static characteristics …continued

Tamb =

−

C to +85

C for commercial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  41 of 57
NXP Semiconductors LPC2388
Fast communication chip
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages 
[2] The RTC typically fails when Vi(VBAT) drops below 1.6 V.
[3] Including voltage on outputs in 3-state mode.
[4] VDD(3V3) supply voltages must be present.
[5] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[6] Accounts for 100 mV voltage drop in all supply lines.
[7] Only allowed for a short time period.
[8] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[9] On pin VBAT.
[10] To VSS.
[11] Includes external resistors of 18 Ω ± 1 % on D+ and D−.
 
VDI differential input 
sensitivity |(D+) − (D−)|0.2 - - V
VCM differential common 
mode voltage range includes VDI range 0.8 -2.5 V
Vth(rs)se single-ended receiver 
switching threshold 
voltage
0.8 -2.0 V
VOL LOW-level output 
voltage for 
low-/full-speed
RL of 1.5 kΩ to 3.6 V - - 0.18 V
VOH HIGH-level output 
voltage (driven) for 
low-/full-speed
RL of 15 kΩ to GND 2.8 -3.5 V
Ctrans transceiver 
capacitance pin to GND --20 pF
ZDRV driver output 
impedance for driver 
which is not 
high-speed capable 
with 33 Ω series resistor; 
steady state drive [11] 36 -44.1 Ω
Rpu pull-up resistance SoftConnect = ON 1.1 -1.9 kΩ
Table 5. Static characteristics …continued
Tamb = 
−
40 
°
C to +85 
°
C for commercial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 6. ADC static characteristics 
VDDA = 2.5 V to 3.6 V; Tamb = 
−
40 
°
C to +85 
°
C unless otherwise specified; ADC frequency 4.5 MHz.
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input voltage 0 - VDDA V
Cia analog input capacitance --1pF
EDdifferential linearity error [1][2][3] --±1LSB
EL(adj) integral non-linearity [1][4] --±2LSB
EOoffset error [1][5] --±3LSB
EGgain error [1][6] --±0.5 %
ETabsolute er ror [1][7] --±4LSB
Rvsi voltage source interface 
resistance [8] --40 kΩ

Preliminary data sheet Rev. 00.01 — 23 October 2007 42 of 57

NXP Semiconductors LPC2388

Fast communication chip

[1] Conditions: VSSA = 0 V, VDDA = 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.

[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 4.

[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 4.

[7] The absolute error (ET) is the maximum difference between the center of the steps of the actu al transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 4.

[8] See Figure 5.

Preliminary data sheet Rev. 00.01 — 23 October 2007 43 of 57

NXP Semiconductors LPC2388

Fast communication chip

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 4. ADC characteristics

002aab136

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDDA − VSSA

1024

offset

error

gain

error

offset error

Via (LSBideal)

1 LSB =

Preliminary data sheet Rev. 00.01 — 23 October 2007 44 of 57

NXP Semiconductors LPC2388

Fast communication chip

Fig 5. Suggested ADC interface - LPC2388 AD0[y] pin

LPC2378

AD0[y]

SAMPLE

AD0[y]

20 kΩ

3 pF 5 pF

Rvsi

VEXT

002aac610

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007  45 of 57
NXP Semiconductors LPC2388
Fast communication chip
10. Dynamic characteristics
 
[1] Characterized but not implemented as production test. Guaranteed by design.
 
[1] Parameters are valid over operating temperature range unless otherwise specified. 
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.
Table 7. Dynamic characteristics of USB pins (full-speed) 
CL = 50 pF; Rpu = 1.5 k
Ω
 on D+ to VDD(3V3),unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
trrise time 10 % to 90 % 8.5 -13.8 ns
tffall time 10 % to 90 % 7.7 -13.7 ns
tFRFM differential rise and fall time 
matching  tr / tf- - 109 %
VCRS output signal crossover voltage 1.3 -2.0 V
tFEOPT source SE0 interval of EOP see Figure 7 160 -175 ns
tFDEOP source jitter for differential transition 
to SE0 transition see Figure 7 −2 - +5 ns
tJR1 receiver jitter to next transition −18.5 -+18.5 ns
tJR2 receiver jitter for paired transitions 10 % to 90 % −9 - +9 ns
tEOPR1 EOP width at receiver must reject as 
EOP; see 
Figure 7
[1] 40 - - ns
tEOPR2 EOP width at receiver must accept as 
EOP; see 
Figure 7
[1] 82 - - ns
Table 8. Dynamic characteristics 
Tamb = 
−
40 
°
C to +85 
°
C for commercial applications; VDD(3V3) over specified ranges.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
External clock
fosc oscillator frequency 1 - 24 MHz
Tcy(clk) clock cycle time 42 -1000 ns
tCHCX clock HIGH time Tcy(clk) × 0.4 - - ns
tCLCX clock LOW time Tcy(clk) × 0.4 - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns
I2C-bus pins (P0[27] and P0[28])
tf(o) output fall time  VIH to VIL 20 + 0.1 × Cb[3] - - ns
SSP interface
tsu(SPI_MISO) SPI_MISO set-up time Tamb = 25 °C; 
measured in 
SPI Master 
mode; see 
Figure 8
-11 -ns

Preliminary data sheet Rev. 00.01 — 23 October 2007 46 of 57

NXP Semiconductors LPC2388

Fast communication chip

10.1 Timing

VDD = 1.8 V.

Fig 6. Externa l cl oc k timing

CHCL

CLCX

CHCX

cy(clk)

CLCH

002aaa907

0.2V

+ 0.9 V

0.2V

− 0.1 V

− 0.5 V

0.45 V

Fig 7. Differential data-to-EOP transition skew and EOP width

002aab561

tPERIOD

differential

data lines

crossover point

source EOP width: tFEOPT

receiver EOP width: tEOPR1, tEOPR2

crossover point

extended

differential data to

SE0/EOP skew

n × tPERIOD + tFDEOP

Fig 8. MISO line set-up time in SSP Master mode

su(SPI_MISO)

SCK

shifting edges

MOSI

MISO

002aad326

sampling edges

Preliminary data sheet Rev. 00.01 — 23 October 2007 47 of 57

NXP Semiconductors LPC2388

Fast communication chip

11. Application information

11.1 Suggested USB interface solutions

Fig 9. LPC2388 USB interface on a self-powered device

LPC23XX

USB-B

connector

USB_D+

USB_CONNECT

soft-connect switch

USB_D−

VBUS

VSS

VDD(3V3)

1.5 kΩ

RS = 33 Ω

002aac578

RS = 33 Ω

USB_UP_LED

Fig 10. LPC2388 USB interface on a bus-powered device

LPC23XX

VDD(3V3)

1.5 kΩ

USB_UP_LED

002aac579

USB-B

connector

USB_D+

USB_D−

VBUS

VSS

RS = 33 Ω

Preliminary data sheet Rev. 00.01 — 23 October 2007 48 of 57

NXP Semiconductors LPC2388

Fast communication chip

Fig 11. LPC2388 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host

USB_UP_LED1

USB_D+1

USB_D−1

USB_PWRD2

USB_SDA1

USB_SCL1

RSTOUT

15 kΩ15 kΩ

LPC2388

USB-A

connector

Mini-AB

connector

33 Ω

VDD

USB_UP_LED2

VDD

USB_OVRCR2

LM3526-L

ENA

5 V

OUTA

FLAGA

VDD

D+

D−

VBUS

USB_PPWR2

USB_D+2

USB_D−2

002aad336

R4 R5 R6

R1 R2 R3 R4

USB_INT1

RESET_N

ADR/PSW

SPEED

SUSPEND

OE_N/INT_N

SCL

SDA

INT_N

VBUS

ISP1301

VSS

Preliminary data sheet Rev. 00.01 — 23 October 2007 49 of 57

NXP Semiconductors LPC2388

Fast communication chip

Fig 12. LPC2388 USB OTG port configuration: VP_VM mode

USB_TX_DP1

USB_TX_DM1

USB_RCV1

USB_RX_DP1

USB_RX_DM1

USB_SCL1

USB_SDA1

SPEED

ADR/PSW

SDA

SCL

RESET_N

INT_N

SUSPEND

OE_N/INT_N

SE0_VM

DAT_VP

RCV

VBUS

LPC2388

ISP1301

USB MINI-AB

connector

33 Ω

002aad337

USB_TX_E1

RSTOUT

VDD

USB_INT1

USB_UP_LED1

VDD

VSS

Preliminary data sheet Rev. 00.01 — 23 October 2007 50 of 57

NXP Semiconductors LPC2388

Fast communication chip

Fig 13. LPC2388 USB OTG port configuration: USB port 2 device, USB po rt 1 host

USB_UP_LED1

USB_D+1

USB_D−1

USB_PWRD1

15 kΩ15 kΩ

LPC2388

USB-A

connector

USB-B

connector

33 Ω

002aad335

VDD

USB_UP_LED2

USB_CONNECT2

VDD

USB_OVRCR1

USB_PPWR1

LM3526-L

ENA

5 V

FLAGA

OUTA

VDD

D+

D−

D+

D−

VBUS

USB_D+2

USB_D−2

VBUS VBUS

VSS

Preliminary data sheet Rev. 00.01 — 23 October 2007 51 of 57

NXP Semiconductors LPC2388

Fast communication chip

Fig 14. LPC2388 USB OTG port configuration: USB port 1 host, USB port 2 host

USB_UP_LED1

USB_D+1

USB_D−1

USB_PWRD1

USB_PWRD2

15 kΩ

15 kΩ15 kΩ

15 kΩ

LPC2388

USB-A

connector

USB-A

connector

33 Ω

002aad338

VDD

USB_UP_LED2

VDD

USB_OVRCR1

USB_OVRCR2

USB_PPWR1

LM3526-L

ENA

ENB

5 V

FLAGA

OUTA

OUTB

FLAGB

VDD

D+

D−

D+

D−

VBUS

USB_PPWR2

USB_D+2

USB_D−2

VSS

Preliminary data sheet Rev. 00.01 — 23 October 2007 52 of 57

NXP Semiconductors LPC2388

Fast communication chip

12. Package outline

Fig 15. P ackage outline SOT486 -1 (LQFP144)

UNIT A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

1.45

1.35 0.25 0.27

0.17

0.20

0.09

20.1

19.9 0.5 22.15

21.85

1.4

1.1

0.080.2 0.081

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT486-1 136E23 MS-026 00-03-14

03-02-20

D(1) (1)(1)

20.1

19.9

22.15

21.85

1.4

1.1

0 5 10 mm

scale

detail X

(A )

HA2

HvMB

vMA

max.

1.6

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1

108

109

pin 1 index

144

Preliminary data sheet Rev. 00.01 — 23 October 2007 53 of 57

NXP Semiconductors LPC2388

Fast communication chip

13. Abbreviations

Table 9. Acronym list

Acronym Description

ADC Analog-to-Digital Converter

AHB Advanced High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

BLS Byte Lane Select

BOD BrownOut Detection

CAN Controller Area Network

CTS Clear To Send

DAC Digital-to-Analog Converter

DCC Debug Communication Channel

DMA Direct Memory Access

DSP Digital Signal Processing

EOP End Of Packet

ETM Embedded Trace Macrocell

GPIO General Purpose Input/Output

IrDA Infrared Data Association

JTAG Joint Test Action Group

MII Media Independent Interface

PHY Physical Layer

PLL Phase-Locked Loop

PWM Pulse Width Modulator

RMII Reduced Media Independent Interface

RTS Request To Send

SE0 Single Ended Zero

SPI Serial Peripheral Interface

SSI Synchronous Serial Interface

SSP Synchronous Serial Port

TTL Transistor-T ransistor Logic

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Bus

Preliminary data sheet Rev. 00.01 — 23 October 2007 54 of 57

NXP Semiconductors LPC2388

Fast communication chip

14. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2388_0.01 <tbd>

Preliminary data sheet Rev. 00.01 — 23 October 2007 55 of 57

NXP Semiconductors LPC2388

Fast communication chip

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

15.3 Disclaimers

General — In formation in this document is beli eved to be accurate and

reliable. However, NXP Semiconductors does not give any repr esenta tions or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconducto rs product can reasonably b e expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause pe rmanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

SoftConnect — is a trademark of NXP B.V.

GoodLink — is a trademark of NXP B.V.

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales office addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specif ication.

Product [short] dat a sheet Production This document contains the product specification.

Preliminary data sheet Rev. 00.01 — 23 October 2007 56 of 57

continued >>

NXP Semiconductors LPC2388

Fast communication chip

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . 15

7.1 Architectural overview . . . . . . . . . . . . . . . . . . 15

7.2 On-chip flash programming memory . . . . . . . 16

7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 17

7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 18

7.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19

7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 19

7.7 External memory controller. . . . . . . . . . . . . . . 19

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.8 General purpose DMA controller . . . . . . . . . . 20

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.9 Fast general purpose parallel I/O . . . . . . . . . . 21

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.10 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.11 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.11.1 USB device controller. . . . . . . . . . . . . . . . . . . 23

7.11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.11.2 USB Host Controller. . . . . . . . . . . . . . . . . . . . 23

7.11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.11.3 USB OTG Controller. . . . . . . . . . . . . . . . . . . . 24

7.11.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.12 CAN controller and acceptance filters . . . . . . 24

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.14 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.15 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.16 SPI serial I/O controller . . . . . . . . . . . . . . . . . . 26

7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.17 SSP serial I/O controller. . . . . . . . . . . . . . . . . 26

7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.18 SD/MMC card interface . . . . . . . . . . . . . . . . . 26

7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.19 I2C-bus serial I/O controllers . . . . . . . . . . . . . . 27

7.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 27

7.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.21 General purpose 32-bit timers/e xternal event

counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 28

7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.23 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 30

7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.24 RTC and battery RAM . . . . . . . . . . . . . . . . . . 30

7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.25 Clocking and power control . . . . . . . . . . . . . . 31

7.25.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 31

7.25.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 31

7.25.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 31

7.25.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 31

7.25.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.25.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 32

7.25.4 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 32

7.25.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.25.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.25.4.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 33

7.25.4.4 Power domains . . . . . . . . . . . . . . . . . . . . . . . 33

7.26 System control. . . . . . . . . . . . . . . . . . . . . . . . 34

7.26.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.26.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 34

7.26.3 Code security (Code Read Protecti on - CRP) 35

7.26.4 AHB bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.26.5 External interrup t inputs. . . . . . . . . . . . . . . . . 35

7.26.6 Memory mapping control . . . . . . . . . . . . . . . . 35

7.27 Emulation and debugging . . . . . . . . . . . . . . . 36

7.27.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 36

7.27.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 36

7.27.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Static characteristics . . . . . . . . . . . . . . . . . . . 39

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 45

10.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11 Application information . . . . . . . . . . . . . . . . . 47

11.1 Suggested USB interface solutions . . . . . . . . 47

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 52

13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 54

15 Legal information . . . . . . . . . . . . . . . . . . . . . . 55

15.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 55

NXP Semiconductors LPC2388

Fast communication chip

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 23 October 2007

Document identifier: LPC2388_0

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 55

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 55

16 Contact information. . . . . . . . . . . . . . . . . . . . . 55

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56