MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CSD120
FLAT-BASE TYPE
INSULATED PACKAGE
Sep. 2001
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CSD120
FLAT-BASE TYPE
INSULATED PACKAGE
PM50CSD120 FEATURE
a) Adopting new 4th generation planar IGBT chip, which per-
formance is improved by 1µm fine rule process.
b) Using new Diode which is designed to get soft reverse
recovery characteristics.
c) Keeping the package compatibility.
The layout/position of both terminal pin and mounting hole
is same as S-series 3rd generation IPM.
•3φ 50A, 1200V Current-sense IGBT for 15kHz switching
• Monolithic gate drive & protection logic
• Detection, protection & status indication circuits for over-
current, short-circuit, over-temperature & under-voltage
(P-Fo available from upper leg devices)
• Acoustic noise-less 5.5/7.5kW class inverter application
APPLICATION
General purpose inverter, servo drives and other motor controls
PACKAGE OUTLINES Dimensions in mm
PBT
19
18
17
16
15
14
13
12
11
9
10
78654321
BPN
WVU
A
MOUNTING HOLES
10
12
19- 0.5
31.6
2-φ2.54
32.6
110
±1
95
±0.5
24.5
17.5
0.5
±0.3
3.22
2
±0.5
17
74
±0.5
89
±1
4
19.4
66.44
22
4.5
2626
2020
17.02 10
10
3-2
4-R6
6-M5NUTS
4-φ5.5
6-2
3-23-2
10
LABEL
10.6
11.61.6
3.22 3-2
φ2.54
22
21.2
–0.5
+1.0
1. VUPC
2. UFO
3. UP
4. VUP1
5. VVPC
6. VFO
7. VP
8. VVP1
9. VWPC
10. WFO
11. WP
12. VWP1
13. VNC
14. VN1
15. NC
16. UN
17. VN
18. WN
19. Fo
Screwing depth
Min9.0
Terminal code
A : DETAIL
0.5
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CSD120
FLAT-BASE TYPE
INSULATED PACKAGE
Sep. 2001
INTERNAL FUNCTIONS BLOCK DIAGRAM
Rfo=1.5kΩ
W
P
V
WP1
V
WPC
U
N
NC Fo
NC N W V PU
V
P
V
VP1
V
VPC
U
P
V
UP1
V
UPC
W
N
V
N1
V
NC
V
N
U
FO
W
FO
V
FO
RfoRfo Rfo
Rfo
Th
Gnd In Fo Vcc
Gnd Si Out
Gnd In Fo
TEMP
Vcc
Gnd Si Out
Gnd In Fo Vcc
Gnd Si Out
Gnd In Fo Vcc
Gnd Si Out
Gnd In Fo Vcc
Gnd Si Out
Gnd In Fo Vcc
Gnd Si Out
VCES
±IC
±ICP
PC
Tj
Collector-Emitter Voltage
Collector Current
Collector Current (Peak)
Collector Dissipation
Junction Temperature
VD = 15V, VCIN = 15V
TC = 25°C
TC = 25°C
TC = 25°C
V
A
A
W
°C
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol Parameter Condition Ratings Unit
1200
50
100
328
–20 ~ +150
VFO
IFO
CONTROL PART
V
mA
20
20
Supply Voltage
Input Voltage
Fault Output Supply Voltage
Fault Output Current
Symbol Parameter Condition Ratings Unit
Applied between : VUP1-VUPC
VVP1-VVPC, VWP1-VWPC, VN1-VNC
Applied between : UP-VUPC, VP-VVPC
WP-VWPC, UN • VN • WN-VNC
Applied between : UFO-VUPC, VFO-VVPC, WFO-VWPC
FO-VNC
Sink current at UFO, VFO, WFO, FO terminals
20
20
VD
VCIN
V
V
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CSD120
FLAT-BASE TYPE
INSULATED PACKAGE
Sep. 2001
ParameterSymbol
Supply Voltage Protected by
OC & SC
Supply Voltage (Surge)
Module Case Operating
Temperature
Storage Temperature
Isolation Voltage
Condition
VCC(surge)
TC
Tstg
Viso
Ratings
VCC(PROT) 800
1000
–20 ~ +100
–40 ~ +125
2500
Unit
V
°C
°C
Vrms
V
VD = 13.5 ~ 16.5V, Inverter Part,
Tj = 125°C Start
Applied between : P-N, Surge value or without switching
(Note-1)
60Hz, Sinusoidal, Charged part to Base, AC 1 min.
(Note-1) TC measurement point is as shown below. (Base plate depth 3mm)
TOTAL SYSTEM
PBT
BPN
WVU
Tc65mm
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
3.2
2.8
3.5
2.5
0.3
1.0
3.5
1.2
1
10
Min. Typ. Max.
Collector-Emitter
Saturation Voltage
Collector-Emitter
Cutoff Current
–IC = 50A, VD = 15V, VCIN = 15V (Fig. 2)
Tj = 25°C
Tj = 125°C
ParameterSymbol Test Condition
VCE(sat)
ICES
VEC
ton
trr
tc(on)
toff
tc(off)
Limits
—
—
—
0.5
—
—
—
—
—
—
2.4
2.1
2.5
1.0
0.15
0.4
2.5
0.7
—
—
Tj = 25°C
Tj = 125°C
FWDi Forward Voltage
Switching Time
VD = 15V, VCIN = 15V↔0V
VCC = 600V, IC = 50A
Tj = 125°C
Inductive Load (upper and lower arm) (Fig. 3)
V
CE
= V
CES
, V
CIN
= 15V
(Fig. 4)
VD = 15V, IC = 50A
VCIN = 0V, Pulsed (Fig. 1) V
mA
V
µs
Unit
0.38
0.70
0.23
0.36
0.027
°C/W
Rth(j-c)Q
Rth(j-c)F
Rth(j-c’)Q
Rth(j-c’)F
Rth(c-f)
Inverter IGBT part (per 1 element), (Note-1)
Inverter FWDi part (per 1 element), (Note-1)
Inverter IGBT part (per 1 element), (Note-2)
Inverter FWDi part (per 1 element), (Note-2)
Case to fin, Thermal grease applied (per 1 module)
Symbol Parameter Test Condition Unit
Limits
Min. Typ. Max.
—
—
—
—
—
—
—
—
—
—
Junction to case Thermal
Resistances
THERMAL RESISTANCES
Contact Thermal Resistance
(Note-2) TC measurement point is just under the chips.
If you use this value, Rth(f-a) should be measured just under the chips.
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CSD120
FLAT-BASE TYPE
INSULATED PACKAGE
Sep. 2001
3.5
3.5
—
—
—
—
Main terminal screw : M5
Mounting part screw : M5
—
Symbol Parameter
Mounting torque
Mounting torque
Weight
Test Condition Unit
N • m
N • m
g
Limits
Min. Typ. Max.
2.5
2.5
—
3.0
3.0
560
MECHANICAL RATINGS AND CHARACTERISTICS
VD = 15V, VCIN = 15V
Applied between : UP-VUPC, VP-VVPC, WP-VWPC
UN • VN • WN-VNC
ID
°C
V
mA
ms
55
18
1.8
2.3
—
—
—
—
125
—
12.5
—
0.01
15
—
mA
Circuit Current
Input ON Threshold Voltage
Input OFF Threshold Voltage
Over Current Trip Level
Short Circuit Trip Level
Over Current Delay Time
Over Temperature Protection
Supply Circuit Under-Voltage
Protection
Fault Output Current
Minimum Fault Output Pulse
Width
Vth(on)
Vth(off)
OC
SC
toff(OC)
OT
OTr
UV
UVr
IFO(H)
IFO(L)
tFO
CONTROL PART
—
—
1.2
1.7
93
59
—
—
111
—
11.5
—
—
—
1.0
Parameter
Symbol Test Condition Max.
Min. Typ. Unit
Limits
40
13
1.5
2.0
157
—
183
10
118
100
12.0
12.5
—
10
1.8
(Note-3) Fault output is given only when the internal OC, SC, OT & UV protection.
Fault output of OC, SC and UV protection operate by upper and lower arms.
Fault output of OT protection operate by lower arm.
Fault output of OC, SC protection given pulse.
Fault output of OT, UV protection given pulse while over level.
Base-plate
Temperature detection, VD = 15V
–20 ≤ Tj ≤ 125°C
VD = 15V, VFO = 15V (Note-3)
VD = 15V (Note-3)
V
µs
VD = 15V (Fig. 5,6)
–20≤ Tj ≤ 125°C, VD = 15V (Fig. 5,6)
VD = 15V (Fig. 5,6)
VN1-VNC
VXP1-VXPC
Tj = 25°C
Tj = 125°CA
A
Trip level
Reset level
Trip level
Reset level
RECOMMENDED CONDITIONS FOR USE
Recommended value Unit
Test Condition
Symbol Parameter
V
Applied across P-N terminals
Applied between : VUP1-VUPC, VVP1-VVPC
VWP1-VWPC, VN1-VNC (Note-4)
Applied between : UP-VUPC, VP-VVPC, WP-VWPC
UN • VN • WN-VNC
Using Application Circuit input signal of IPM, 3φ
sinusoidal PWM VVVF inverter (Fig. 8)
For IPM’s each input signals (Fig. 7)
Supply Voltage
Control Supply Voltage
Input ON Voltage
Input OFF Voltage
PWM Input Frequency
Arm Shoot-through
Blocking Time
≤ 800
15 ±1.5
≤ 0.8
≥ 4.0
≤ 20
≥ 3.0
VCC
VCIN(on)
VCIN(off)
fPWM
tdead
VDV
kHz
µs
V
(Note-4) Allowable Ripple rating of Control Voltage : dv/dt ≤ ±5V/µs, 2Vp-p
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CSD120
FLAT-BASE TYPE
INSULATED PACKAGE
Sep. 2001
PRECAUTIONS FOR TESTING
1. Before appling any control supply voltage (VD), the input terminals should be pulled up by resistores, etc. to their corre-
sponding supply voltage and each input signal should be kept off state.
After this, the specified ON and OFF level setting for each input signal should be done.
2. When performing “OC” and “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not
be allowed to rise above VCES rating of the device.
(These test should not be done by using a curve tracer or its equivalent.)
U,V,W
N
V
CINN
V
CINP
V
D
V
D
P
Ic
Vcc
V
CINN
0V
0V
V
CINP
t
t
t
dead
t
dead
t
dead
P, (U,V,W)
U,V,W, (N) U,V,W, (N)
VD (all)
IN
Fo
IN
Fo
VD (all)
V
CIN
(0V)
Ic
V V
P, (U,V,W)
V
CIN
(15V)
–Ic
V
D
(all)
U,V,W, (N)
P, (U,V,W) A
Pulse
V
CE
V
CIN
(15V)
V
D
(all)
U,V,W, (N)
P, (U,V,W)
V
CIN
V
CC
I
C
I
C
I
C
OC
SC
V
CIN
t
off (OC)
IN
Fo
Fo
IN
10%
90%
trr
Irr
trtd (on)
tc (on) tc (off)
td (off)
V
CIN
Ic
V
CE
10%
10% 10%
90%
tf
(ton= td (on) + tr) (toff= td (off) + tf)
Fo
P
N
N
C
S
C
S
U,V,W
Vcc
Vcc
Ic
Ic
V
D
(all)
V
D
(all)
P
U,V,W
V
CIN
V
CIN
V
CIN
(15V)
V
CIN
(15V)
Fo
Fo
Fo
Short Circuit Current
Over Current
Constant Current
Constant Current
Fig. 5 OC and SC Test Fig. 6 OC and SC Test waveform
Fig. 7 Dead time measurement point example
Fig. 3 Switching time Test circuit and waveform
Fig. 1 V
CE(sat)
Test Fig. 2 V
EC
Test
a) Lower Arm Switching
Signal input
(Upper Arm)
Signal input
(Lower Arm)
Signal input
(Upper Arm)
Signal input
(Lower Arm)
b) Upper Arm Switching
Fig. 4 I
CES
Test
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CSD120
FLAT-BASE TYPE
INSULATED PACKAGE
Sep. 2001
NOTES FOR STABLE AND SAFE OPERATION ;
•Design the PCB pattern to minimize wiring length between opto-coupler and IPM’s input terminal, and also to minimize the
stray capacity between the input and output wirings of opto-coupler.
•Quick opto-couplers: TPLH, TPLH ≤ 0.8µs. Use High CMR type. The line between opto-coupler and intelligent module
should be shortened as much as possible to minimize the floating capacitance.
•Slow switching opto-coupler: recommend to use at CTR = 100 ~ 200%, Input current = 8 ~ 10mA, to work in active.
•Use 4 isolated control power supplies (VD). Also, care should be taken to minimize the instantaneous voltage charge of the
power supply.
•Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N
terminal.
•Use line noise filter capacitor (ex. 4.7nF) between each input AC line and ground to reject common-mode noise from AC line
and improve noise immunity of the system.
OUT
Si
GNDGND
In
Vcc
U
V
W
NC
N
P
M
→
I
F
+
–
OUT
Si
GNDGND
In
Vcc
OUT
Si
GNDGND
In
Vcc
OUT
Si
GNDGND
In
Fo
Fo
Fo
Fo
Vcc
OUT
Si
GNDGND
In
Fo
TEMP
Vcc
OUT
Si
GND
GND
In
Fo
Vcc
V
WP1
W
P
V
WPC
Th
U
N
V
N
V
N1
W
N
V
NC
Rfo
Rfo
Rfo
Rfo
Fo
V
VP1
V
P
V
VPC
≥0.1µ
1k
≥0.1µ
≥0.1µ
20k
20k
20k
≥10µ
≥10µ
≥10µ
20k ≥10µ
≥0.1µ
V
FO
W
FO
U
FO
V
UP1
U
P
V
UPC
NC
→
→
I
F
I
F
I
F
5V
→
V
D
V
D
V
D
V
D
: Interface which is the same as the U-phase
Fig. 8 Application Example Circuit
