5962-9201001MXC - Cypress Semiconductor

VMEbus Interface Controlle r

VIC068A

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-09004 Rev. ** Revised July 23, 1997

Features

• Complete VMEbus interface controller and arbiter

—58 internal registers provide configuration control

and status of VMEbus and local operations

—Drives arbitration, interrupt, address modifier utility,

strobe, address lines A07 through A01 and data lines

D07 through D00 directly, and provides signals for

control logic to drive remaining address and data

lines

—Direct connection to 68xxx family and mappable to

non-68xxx processors

•Complete master/slave capability

—Supports re ad, write, write posting , and block trans-

fers

—Accommodates VMEbus timing requirements with

internal digital delay line (1⁄2-clock granularity)

—Programmable metastability delay

—Programmable data acquisition delays

—Provides timeout timers for local bus and VMEbus

transactions

•Interleaved block transfers over VMEbus

—Acts as DMA master on local bus

—Programmable burst count, transfer length, and in-

terleav ed period inter val

— Supports local module-based DMA

•Arbitration support

—Supports singl e-level, priority and roun d robin arbi-

tration

—Supports fair request option as requester

•Interrupt support

—Complete support for the VMEbus interrupts: inter-

rupter and interrupt handler

—Seven local interrupt lines

—8-level interrupt priority encode

—Total of 29 interrupts mapped through the VIC068A

•Miscellaneous features

—Refresh option for local DRAM

—Four broadcast location monitors

—Four module-specific location monitors

—Eight interprocessor communications registers

—PGA or QFP packages

—Compatible with IEEE Specification 1014, Rev. C

—Supports RMC operations

•See the VM Ebus Interfac e Handbook for more informa-

tion

Functional Description

The VMEbus interface controller (VIC068A) is a single chip

designed to minimize the cost and board area requirements

and to maximize performance of the VMEbus interface of a

VMEbus master/slave module. This can be implemented on

VIC068A ei ther an 8-bit, 16-bit, or 32-b it VMEbus system. The

VIC068A performs all VMEbus system controller functions

plus many others, which simplify the development of

VIC068Aa VMEbus interface. The VIC068A utilizes patented

on-chip output buffers. These CMOS high-drive buffers pro-

vide direct connection to the address and data lines. In addi-

tion to these signals, the VIC068A connects directly to the ar-

bitration, interrupt, address modifier, utility and strobe lines.

Signals are provided which control data direction and latch

functions needed for a 32-bit implementation.

The VIC068A was developed through the efforts of a consor-

tium of board vendors, under the auspices of the VMEbus In-

ternational Trade Association (VITA). The VIC068A thus in-

sures compatibility between boards designed by different

manufacturers.

VIC068A

Document #: 38-09004 Rev. ** Page 2 of 15

Pin Configurations

AB CDE FG HJ KL MN P R

GND

LD6

LD2

LA7

LA3

LA2

LA1

CS*

PAS*

DSACK0*

HALT*

FC2

SIZ1

BLT*

LD5

LD3

LD0

LA5

LA4

LA0

DSACK1*

LBERR*

R/W*

IPL2*

RMC*

SIZ0

IRESET*

ABEN*

LIACKO*

IPL1*

DEDLK*

LD7

LD4

LA6

GND

VCC

DS*

RESET*

FC1

LBR*

SCON*

LADO

VCC

LIRQ2*

VCC

IPL0*

LOCATOR

CLK64M

LEDI

LEDO

LIRQ5*

LIRQ1*

LAEN

ASIZ1

LIRQ4*

LIRQ3*

LADI

DDIR

UWDENIN*

GND

LWDENIN*

SWDEN*

ASIZ0

LIRQ6*

LIRQ7*

VCC

DENO*

ISOBE*

SLSEL1*

ICFSEL*

GND

D06

D07

WORD*

MWB*

SLSEL0*

VCC

D03

D05

FIACK*

A01

GND

D00

D01

D04

A02

A03

A06

BGOUT1*

GND

D02

A04

A05

IRQ1*

BGIN2*

BGOUT0*

BGOUT3*

VCC

A07

IRQ2*

IRQ5*

SYSFAIL*

IACKIN*

GND

VCC

BERR*

BR2*

BBSY*

BGIN0*

BGIN3*

BGOUT2*

GND

IRQ3*

IRQ6*

VCC

SYSRESET*

IACK*

AS*

AM2

LWORD*

WRITE*

DS1*

BR1*

BR3*

BGIN1*

SYSCLK

IRQ4*

IRQ7*

ACFAIL*

IACKOUT*

DTACK*

AM0

AM1

AM3

AM4

AM5

DS0*

BR0*

GND

BCLR*

GND

Pin Grid Array (PGA)

Bottom View

LBG*

LD1

VIC068A–1

VIC068A

Document #: 38-09004 Rev. ** Page 3 of 15

Pin Configurations (continued)

VIC068A–2

1GND 120 GND

2GND 119 GND

3IPL0* 118 LBG*

4IPL1* 117 IRESET*

5IPL2* 116 SCON*

6VCC 115 CLK64M

7LAEN 114 ABEN*

8LIAKO* 113 LADO

9LIRQ1* 112 LADI

10LIRQ2* 111 LEDI

11LIRQ3* 110 VCC

12LIRQ4* 109 LEDO

13LIRQ5* 108 DDIR

14LIRQ6* 107 UWDENIN*

15LIRQ7* 106 GND

16ASIZ1* 105 LWDENIN*

17ASIZ0* 104 DENO*

18ICFSEL* 103 SWDEN*

19SLSEL1* 102 ISOBE*

20GND 101 VCC

21SLSEL0* 100 GND

22WORD* 99 D07

23FCIACK* 98 D06

24MWB* 97 D05

25A1 96 D04

26GND 95 VCC

27A2 94 D03

28A3 93 D02

29A4 92 D01

30VCC 91 D00

31A5 90 BGOUT3*

32A6 89 GND

33A7 88 BGOUT2*

34VSS 87 BGOUT1*

35IRQ1* 86 BGOUT0*

36IRQ2* 85 SYSCLK

37IRQ3* 84 BGIN3*

38IRQ4* 83 BGIN2*

39GND 82 GND

40GND 81 GND

VCC 160 VCC

VCC 159 VCC

IRQ5* 158 GND

IRQ6* 157 BLT*

IRQ7* 156 DEDLK*

VCC 155 LD7

SYSFAIL* 154 LD6

ACFAIL* 153 LD5

SYSRESET* 152 LD4

IACKOUT* 151 LD3

IACKIN* 150 LD2

IACK* 149 LD1

DTACK* 148 LD0

AS* 147 LA7

GND 146 LA6

AM0 145 LA5

AM1 144 LA4

AM2 143 LA3

AM3 142 LA2

GND 141 GND

VCC 140 VCC

AM4 139 LA1

AM5 138 LA0

LWORD* 137 CS*

WRITE* 136 PAS*

BERR* 135 DS*

DS0* 134 DSACK1*

DS1* 133 DSACK0*

BR0* 132 LBERR*

GND 131 RESET*

BR1* 130 HALT*

BR2* 129 R/W*

BR3* 128 FC2

BCLR* 127 FC1

BBSY* 126 RMC*

BGIN0* 125 SIZ1

BGIN1* 124 SIZ0

GND 123 LBR*

VCC 122 VCC

VCC 121 VCC

160-Pin Quad Flatpack (QFP)

Top View

VIC068A

Document #: 38-09004 Rev. ** Page 4 of 15

Pin Configurations (continued)

144-Pin ThinQuad Flatpack (TQFP)

TopView

VIC068A–3

GND

LBG*

IRQ5*

IPL0* 2

IPL1* IRESET*

IPL2* SCON*

VCC CLK64M

LAEN ABEN*

LIAKO* LADO

LIRQ1* LADI

LIRQ2* LEDI

LIRQ3* VCC

LIRQ4* LEDO

LIRQ5*

108

DDIR

LIRQ6*

107

UWDENIN*

LIRQ7*

106

GND

ASIZ1*

105

LWDENIN*

ASIZ0*

104

DENO*

ICFSEL*

103

SWDEN*

SLSEL1*

102

ISOBE*

GND

101

VCC

SLSEL0*

100

GND

WORD*

D07

FCIACK*

D06

MWB*

D05

D04

GND

VCC

D03

D02

D01

VCC

D00

BGOUT3*

GND

BGOUT2*

GND

BGOUT1*

IRQ1*

BGOUT0*

IRQ2*

SYSCLK

IRQ3*

BGIN3*

IRQ4*

BGIN2*

IRQ6* BLT*

IRQ7* DEDLK*

VC C LD7

SYSFAIL* LD6

ACFAIL* LD5

SYSRESET* LD4

IACKOUT* LD3

IACKIN* LD2

IACK* LD1

DTACK* LD0

AS* LA7

GND LA6

AM0 LA5

AM1 LA4

AM2

143

LA3

AM3

142

LA2

GND

141

GND

VCC

140

VCC

AM4

139

LA1

AM5

138

LA0

LWORD*

137

CS*

WRITE*

136

PAS*

BERR*

135

DS*

DS0*

134

DSACK1*

DS1*

133

DSACK0*

BR0*

132

LBERR*

VSS

131

RESET*

BR1*

130

HALT*

BR2*

129

R/W*

123

BR3*

128

FC2

122

BCLR*

127

FC1

121

BBSY*

126

RMC*

120

BGIN0*

125

SIZ1

119

BGIN1*

124

SIZ0

118

GND LBR*

117

116

115

114

113

112

111

110

109

144

VIC068A

Document #: 38-09004 Rev. ** Page 5 of 15

VIC068A on 68030 Board

512/256K X 36 DRAM 512/256K X 36 DRAM

Address

Mux

Latching Transceivers Latching Transceivers

68030

32 32

Parity Check

Logic

4 JEDEC EPROMs

LA0 –LA31

D24–D31

D16–D23

FCT

543

A1 –A7

SYSCLK

D00 –D07

AM0 – AM5

AS*, DS0*, DS1*, DTACK*,

WRITE*, LWORD*, BERR*

BGiIN*, BGiOUT*, BRi*, BBSY*

IACK*, IACKIN*, IACKOUT*

IRQ1*, IRQ7*, ACFAIL*,

SYSFAIL*

STSRESET*

DDIR

VIC068A

FCT

543

FCT

245

FCT

245

FCT

245

FCT

245

FCT

543 FCT

543

FCT

543

Slave

Select

Decode

LIRQ1* - LIRQ7*LIACKO*

SLSEL0*

SLSEL1*

ICFSEL

A31–A24 A23–16 A15–A08

DRAM I/O

EPROM

VMEbus

SWDEN*

D08–D16

ISOBE*

LD0 –LD7

LA0 –LA7

SCON*

MWB*

WORD*

ASIZ1

ASIZ0

LD0 –LD31

Map Decoder

VIC068A–4

VIC068A

Document #: 38-09004 Rev. ** Page 6 of 15

Theory of Operation

The VIC 068A is an in terface between a local CPU bus and the

VMEbus. The local bus interface of the VIC068A emulates Mo-

torola’s family of 32-bit CISC processor interfaces. Other pro-

cessors can easily be adapted to interface to the VIC068A

using the appropriate logic.

Resetting the VIC068A

The V IC 0 68A ca n be r es et by a ny o f t h ree di sti nc t re se t c on-

ditions:

Inte rnal Re set. This reset is the most common means of re-

setting the VIC068A. It resets select register values and all

logic within the device.

System Reset. This reset pro vides a me ans of r esetting the

VIC068A through the VMEbus backplane. The VIC068A may

also signal a SYSRESET* by writing a configuration register.

Global Reset. This provides a complete reset of the VIC068A.

This reset resets all of the VIC068A’s configuration registers.

This reset should be used with caution since SYSCLK is not

driven while a global reset is in progress.

All three reset options are implemented in a different manner

and ha ve d if fere nt ef fec ts o n the VIC068 A con figurat ion re gis-

ters.

VIC068A VMEbus System Controller

The VIC068A is capable of operating as the VMEbus system

controll er. It provides VMEbus arb itra tion functions , inc lu din g:

•Priority, round-robin, and single-level arbitration schemes

•Driving IACK* Daisy-Chain

•Driving BGiOUT* Daisy-Chain (All four levels)

•Driving SYSCLK output

•VMEbus arbitration timeout timer

The System controller functions are enabled by the SCON* pin

of the VIC 06 8A. Wh en stra pped LOW, the VIC068A function s

as th e VMEbus sy stem cont roller.

VIC068A VMEbus Master Cycles

The VIC068A is capable of becoming the VMEbus master in

response to a request from local resources. In this situation,

the local resource req uests that a VMEbu s transfer is des ired.

The VIC068A makes a request for the VMEbus. When the

VMEbus is gran ted to the VIC068A, it the n performs the tran s-

fer and a cknowledg es the local res ource and the cycle is com-

plete. T he VIC068 A is capabl e of all four VMEbus request lev-

els. The following release modes are supported:

•Release on request (ROR)

•Release when done (RWD)

•Release o n clear (ROC)

•Release under RMC* control

•Bus capture and hold (BCAP)

The VIC068A supports A32, A24, and A16, as well as user-de-

fined address spaces.

Master Write-Posting

The VIC068A is capable of performing master write-posting

(bus decoupling). In this situation, the VIC068A acknowledges

the local resource immediately after the request to the

VIC068A is made, thus freeing the local bus. The VIC068A

latches the local data to be written and performs the VMEbus

transfer without the local resource having to wait for VMEbus

arbitration.

Indivisible Cycles

Read-modify-write cycles and indivisible multiple-address cy-

cles (EMACS) are easily performed using the VIC068A. Sig-

nificant control is allowed to:

•Requesting the VMEbus on the assertion of RMC* indepen-

dent of MWB* (this prevents any slave access from inter-

rupting local indivisible cycles)

•Stretching the VMEbus AS*

•Making the above behaviors dependent on the local SIZi signals

Deadlock Condition

If a master operation is attempted when a slave operation to

the same modul e is in pro gre ss , a de adlock condition ha s oc -

curred. The VIC068A will signal a deadlock condition by as-

sert ing the DEDLK * signal . This should be us ed by th e local

resource requesting the VMEbus to try the transfer after the

slave acc es s has com ple ted.

Self-Access Condition

If the VIC068A, while it is VMEbus master, has a slave select

signal ed, a sel f access i s said to have occ urred. The VIC068A

will issue a BERR*, which in turn will cause a LBERR* to be

asserted.

VIC068A VMEbus Slave Cycles

The VIC0 68A is capable of operat ing as a VMEbus slave co n-

troller. The VIC068A contains a high ly programmable env iron-

ment to allow for a wide variety of slave configurations. The

VIC068A allow s for:

•D32, D16, or D8 configuration

•A32, A24, A16, or user-defined address spaces

•Programmable block transfer support including:

—DMA-type block transfer (P AS* and DSACKi* held

asserted)

—non-DMA-type block transfer (toggle P AS* and DSACKi*)

—No support for block transfer

•Programmable data acquisition delays

•Programmable PAS* and DS* timing

•Restricted slave accesses (supervisory accesses only)

When a s lave access is required, th e VIC068A will req uest the

local bus. When local bus mastership is obtained, the VIC068A

will read or write the d ata to/from the local resou rce and asse rt

the DTACK* signal to complete the transfer.

Slave Wr ite -Posti ng

The VIC068A is capable of performing a slave write-post op-

eratio n (bus decoupli ng). When enab led, the VIC068A l atches

the data to be written and acknowledge the VMEbus (asserts

DTACK*) immediately thereafter. This prevents the VMEbus

from having to wait for local bus access.

Address Modifie r (AM) Codes

The VIC068A encodes and decodes the VMEbus address

modif ier co des. For V MEbus m aster ac cesses, the VIC0 68A

encodes the appropriate AM codes through the VIC068A FCi

and ASIZi signals, as well as the block transfer status. For

VIC068A

Document #: 38-09004 Rev. ** Page 7 of 15

slave accesses, the VIC068A decodes the AM codes and

checks the slave select control registers to see if the slave

request i s to be su pp orted w ith re gar d to ad dre ss space s, s u-

pervisory accesses, and block transfers. The VIC068A also

supports us er-d efi ned AM c ode s; t hat i s, th e VIC0 68A c an be

made to assert and respond to user-defined AM codes.

VIC068A VMEbus Block Transfers

The VIC 068A is c apable o f both ma ster and slave block tran s-

fers. The master VIC068A performs a block transfer in one of

two modes:

•MOVEM-type Block Transfer

•Master Bloc k Transfer with Local DMA

In addition to these VMEbus block transfers, the VIC068A is

also capable of performing block transfers from one local re-

source to another i n a D MA-l ike fa shion. This is referred to as

a Module-based DMA transfer.

The VMEbu s specifica tion restricts bl ock transfers from cross-

ing 256-byte boundaries without toggling the address strobe,

in additi on to res tric t in g the ma xim um le ngth of th e tran sfe r to

256 bytes. The VIC068A allows for easy implementation of

block tran sf ers that exc ee d the 25 6-by te res tric ti on by relea s-

ing the VMEbus at the appropriate time and rearbitrating for

the bus at a programmed time later (this in-between time is

referred to as the interleave period), while at the same time

holding both the local and VMEbus addresses with internal

latches . All of this is perfo rme d without proc esso r/softwar e in-

tervention until the transfer is complete.

The VIC06 8A contai ns tw o se par ate ad dres s c oun ters for the

VMEbus and the local address buses. In addition, a separate

address is counter-provided for slave block transfers. The

VIC068A address counters are 8-bit up-counters that provide

for transfers up to 256 bytes. For transfers that exceed the

256-byte limit, the Cypress CY7C964 or external counters and

latches are required.

The VIC06 8A allo ws slav e acce sses to oc cur duri ng the int er-

leave period. Master accesses are also allowed during inter-

leave with pro gram m ing and ex terna l log ic. This is referre d to

as the “dual path” option.

MOVEM Master Block Transfer

This mode of block transfer provides the simplest implementa-

tion of VMEbus block transfers. For this mode, the local re-

source simply configures the VIC068A for a MOVEM block

transfer and proceeds with the consecutive-address cycles

(such as a 680X0 MOVEM instruction). The local resource

continues as th e local bus master in this mode.

Master Block Transfers with Local DMA

In this mode, the VIC068A becomes the local bus master and

reads or writes the local data in a DMA-like fashion. This pro-

vides a much faste r interfac e than th e MOVEM blo ck tran sfer,

but with less control and fault tolerance.

VIC068A Slave Block Transfer

The process of receiving a block transfer is referred to as a

slave block transfer. The VIC068A is capable of decoding the

address modifier codes to determine that a slave block transfer

is desired. In this mode, the VIC068A captures the VMEbus

address, and latches them into internal counters. For subse-

quent cycles, the VIC068A simply increments this counter for

each transfer. The local protocol for slave block transfers can

be config ured in a f ull handsh ake mode by toggling both PAS*

and DS* and ex pecti ng DSACKi * to toggle, or in an acce lerat-

ed mode in which only DS* toggles and PAS* is asserted

throughout the cycle.

Module-Based DMA Transfers

The VIC068A is capable of acting as a DMA controller be-

tween two local resources. This mode is similar to that of mas-

ter block transfers with local DMA, with the exception that the

VMEbus is not the second source or destin ation.

VIC068A Interrupt Generation and Handling Facilities

The VIC068A is capable of generating and handling a sev-

en-level prioritized interrupt scheme similar to that used by the

Motorola CISC processors. These interrupts include the seven

VMEbus interrupts, seven local interrupts, five VIC068A er-

ror/status interrupts, and eight interprocessor communication

interrupts.

The VIC068A can be configured to act as handler for any of

the seven VMEbus interrupts. The VIC068A can generate the

seven VMEbus interrupts as well as supplying a user-defined

status/ID vector . The local priority level (IPL) fo r VMEbus inter-

rupts is programmable. When configured as the system con-

troller, the VIC068 will drive the IACK daisy-chain.

The local interrupts can be configured with the following:

•User-defined local interrupt priority level (IPL)

•Option for VIC068A to provide the status/ID vector

•Edge or level sensitivity

•Polarity (rising/falling edge, active HIGH/LOW)

The VIC 068A is a lso capabl e of gene rating loc al interrupts on

certain error or status conditions. These include:

•ACFAIL* asser ted

•SYSFAIL* asserted

•Failed master write-post (BERR* asserted)

•Local DMA completion for block transfers

•Arbitration timeout

•VMEbus interrupter interrupt

The VIC0 68A c an al so inte rrup t on the settin g of a m odu le or

global sw it ch in the inte rpro ce ss or com mu nic at ion facil iti es .

Interprocessor Communication Facilities

The VIC068A includes interprocessor registers and switches

that can be written and read through VMEbus accesses.

These are the only such registers that are directly accessible

from the VM Ebu s. Inc lud ed in the interproc es so r co mm un ic a-

tion facili tie s are:

•Four general purpose 8-bit registers

•Four module switches

•Four global switches

•VIC068A ver sio n/re vi si on regi ste r (read-o nly)

•VIC068A Rese t/H al t cond iti on (read -on ly)

•VIC068A interprocessor communication register sema-

phores

When set through a VMEbus access, these switches can in-

terrupt a local resource. The VIC068A includes module switch-

es that are intended for a single module, and global switches

which are intended to be used as a broadcast.

VIC068A

Document #: 38-09004 Rev. ** Page 8 of 15