D a t a S he et , V 1 . 1 , F e b r u a r y 2 00 8 TLE8104E S m a r t Q ua d C h a n ne l P ow er t r a i n S w i t c h coreFLEX A u to m o t i v e P o w e r TLE8104E Smart Quad Channel Powertrain Switch Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 4.1 4.2 Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.4.1 5.3.4.2 5.3.5 5.4 5.5 5.5.1 5.5.2 5.6 Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: Diagnosis Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: Read Back Input and 1-bit Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: Echo Function of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: OR Operation and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: AND Operation and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: All Other Command Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Sheet 2 18 19 19 19 19 20 20 21 V1.1, 2008-03-03 Smart Quad Channel Powertrain Switch coreFLEX 1 TLE8104E Overview Features * * * * * * * * * * * Overload Protection DMOS Overtemperature protection Overvoltage protection Open load detection Low quiescent current mode Electrostatic discharge (ESD) protection IC Overtemperature warning 8-Bit SPI (for diagnosis and control) Short to GND detection Green Product (RoHS compliant) AEC Qualified PG-DSO-20-30 Description Quad Low-Side Switch in Smart Power Technology (SPT) with four open drain DMOS output stages. The TLE8104E is protected by embedded protection functions and designed for automotive applications. The output stages can be controlled directly by parallel inputs for PWM applications (e.g. gasoline port injection) or by SPI. The parallel inputs can be programmed to be active high or active low. Diagnosis can be read from an 8-bit SPI or by the external fault pin. Type Package Marking TLE8104E PG-DSO-20-30 TLE8104E Data Sheet 3 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Overview Table 1 Product Summary VS VDS(AZ) RDS(ON) 4.5 ... 5.5 V Maximum On-state resistance CH 1 - 4 at Tj = 150C RDS(ON) 650 m Nominal load current CH 1 - 4 ID ID (lim) 1A Operating voltage Drain source voltage Typical On-state resistance CH 1 - 4 at Tj = 25C Minimum current limitation CH 1 - 4 45 ... 60 V 320 m 3A VS IN1 IN2 IN3 OUT1 OUT2 OUT3 input control OUT4 IN4 PRG RESET CS SCLK SI SO temperature sensor reset / stand-by SPI hardware configuration control, diagnostic and protective functions short circuit detection gate control output monitor FAULT open load detection diagnosis register GND Figure 1 Data Sheet O Block Diagram 4 i f V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Terms 2 Terms Figure 2 shows all terms used in this Data Sheet. I VS IRESET V DD I FAULT VRESET IPRG VFAULT I IN1 V PRG IIN2 V IN1 IIN3 VIN2 IIN4 VIN3 ICS V IN4 V CS I SCLK VSCLK I SI VSI ISO V SO Vbat VS RESET FAULT PRG IN1 OUT1 IN2 OUT2 IN3 OUT3 IN4 OUT4 I D1 I D2 I D3 I D4 VDS1 V DS2 VDS3 VDS4 CS SCLK SI SO GND I GND Figure 2 Terms The following is valid for all electrical characteristics cables: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS1, VDS2, VDS3 and VDS4). Data Sheet 5 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Pin Configuration 3 Pin Configuration 3.1 Pin Assignment (top view) Figure 3 GND IN2 1 20 2 19 OUT1 VS 3 18 4 17 RESET CS 5 16 6 15 PRG OUT2 7 14 8 13 IN1 GND 9 12 10 11 GND IN3 OUT4 SI SCLK SO FAULT OUT3 IN4 GND Pin Configuration (top view) All GND pins and the heat sink must be connected to GND externally. 3.2 Pin Definitions and Functions Pin Symbol Function 1 GND Ground 2 IN2 Input Channel 2 3 OUT1 Power Output Channel 1 4 VS Supply Voltage 5 RESET Reset Input 6 CS SPI Chip Select 7 PRG Program Input 8 OUT2 Power Output Channel 1 9 IN1 Input Channel 1 10 GND Ground 11 GND Ground 12 IN4 Input Channel 4 13 OUT3 Power Output Channel 3 14 FAULT Fault Output 15 SO SPI Signal Out 16 SCLK SPI Clock 17 SI SPI Signal In 18 OUT4 Power Output Channel 4 19 IN3 Input Channel 3 20 GND Ground Data Sheet 6 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Maximum Ratings and Operating Conditions 4 Maximum Ratings and Operating Conditions 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. 4.1.1 Supply Voltage -0.3 4.1.2 Continuous Drain Source Voltage (OUT1 to OUT4) VS VDS 7 V - -0.3 45 V - 4.1.3 Input Voltage, All Inputs and Data outputs, Sense Lines VIN -0.3 7 V - 4.1.4 Output Current per Channel2) 4.1.5 Maximum Voltage for short circuit Protection (single event)3) ID VSC, single 0 3 A Output ON - 30 V 4.1.6 Electrostatic Discharge Voltage (human body model) according to EIA/JESD22-A114-E VESD -2000 2000 V 1) Not subject to production test, specified by design. 2) Output current rating as long as maximum junction temperature is not exceeded. The maximum output current in the application has to be calculated using RthJA depending on mounting conditions. 3) Device mounted on PCB (100 mm x 100 mm x 1.5 mm epoxy, FR4); PCB in test chamber without blown air. All channels have identical loads. Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 7 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Maximum Ratings and Operating Conditions 4.2 Pos. 4.2.1 Operating Conditions Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. - - 50 mJ ID(0) = 1 A, TJ(0) = 150 C RthJSP RthJA - 2.1 3 K/W PV = 3W - 26.2 - K/W PV = 3W Tj Tstg -40 - 150 C - -55 - 150 C - Output Clamping Energy (single EAS event), linearly decreasing current1) Thermal Resistance 4.2.2 Junction to case 4.2.3 Junction to ambient, all channels active2) Temperature Range 4.2.4 Operating Temperature Range 4.2.5 Storage Temperature Range 1) Pulse shape represents inductive switch off: ID(t) = ID(0) x (1 - t / tpulse); 0 < t < tpulse 2) PCB set-up according Figure 4 PCB Dimensions: 76.2 x 114.3 x 1.5 mm, FR4 Thermal Vias: diameter = 0.3 mm; plating 25 m; 24 pcs. Metallisation according JEDEC 2s2p (JESD 51-7) + (JESD 51-5) 70m modeled (traces) 1,5 mm 35m, 90% metalization 35m, 90% metalization 70m, 5% metalization Thermal_Setup.vsd Figure 4 Thermal Simulation - PCB setup Note: Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given by the related electrical characteristics table. Data Sheet 8 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks 5 Electrical and Functional Description of Blocks 5.1 Power Supply The TLE8104E is supplied by power supply line VS, used for the digital as well as the analog functions of the device including the gate control of the power stages. A capacitor between pins VS to GND is recommended. A RESET pin is available. When a low level is applied to this pin, the device enters sleep mode. In this case, all registers are set to their default values and the quiescent supply current is minimized. After start-up of the power supply, the RESET pin should be kept low until the Reset Duration Time has expired, reseting all SPI registers to their default values. Electrical Characteristics: Power Supply VS = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol 5.1.1 Supply Voltage 5.1.2 Supply Current 5.1.3 Supply Current in Sleep Mode VS IS(ON) IS(sleep) 5.1.4 Input Low Voltage of pin RESET 5.1.5 Input High Voltage of pin RESET Limit Values Unit Conditions Min. Typ. Max. 4.5 - 5.5 V - - 1 2 mA all channels ON - - 100 A VRESET = 0 V VINn = 0 V VSCLK = 0 V VSI = 0 V VCS = VS VPRG = VS VFAULT = VS - 1.0 V - - VS V - A VRESET = 0 V, VRESET(L) -0.3 VRESET(H) 2.0 +0.3 5.1.6 Low Input Pull-up Current through pin RESET IRESET(L) 20 50 100 5.1.7 Reset duration time1) tRESET(L) 10 - - s - 1) For proper startup, after the supply VS has reached its final voltage, the RESET pin should be held low until the reset duration time has expired. 5.2 Parallel Inputs Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1, IN2 controls OUT2, etc. Please refer to Figure 4 for details. The PRG pin selects if the input pins are active high or active low and activates either a pull-down or pull-up current source. If PRG is high, the input pins are active high and the pull-down current source is active. If PRG is low, the input pins are active low and the pull-up current source is active. The respective current sources at the input pin ensure that the channels switch off in case of an unconnected pin. The zener diode protects the input circuit against ESD pulses. The BOL bit can be set via SPI. This bit determines if a Boolean OR or AND operation is performed on the INn signals and their corresponding data bits CHnIN . The default setting of the BOL bit programs the device to perform an OR operation. Data Sheet 9 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks PRG channel 4 channel 3 channel 2 channel 1 I IN1(L) Closed if PRG = 0 OR IN1 I IN1(H) Closed if PRG = 1 PRG = 1: Active High PRG = 0: Active Low CH1IN Figure 4 gate control & BOL Input Control and Boolean Operator Electrical Characteristics: Parallel Inputs VS = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter 5.2.1 Input Low Voltage of pin INn 5.2.2 Input High Voltage of pin INn Symbol VINL VINH Limit Values Unit Conditions Min. Typ. Max. -0.3 - 1.0 V - 2.0 - VS V - +0.3 5.2.3 Input Voltage Hysteresis1) 5.2.4 Low Input Pull-up Current through pin INn VINHys IIN(L) 100 200 mV - 20 50 100 A VIN = 0 V, PRG = 0 High Input Pull-down Current through pin INn IIN(L) 5.2.6 Input Low Voltage of pin PRG 5.2.7 Input High Voltage of pin PRG VPRG(L) VPRG(H) 5.2.5 50 20 50 100 A VIN = VS, PRG = 1 -0.3 - 1.0 V - 2.0 - VS V - A VPRG = 0 V, +0.3 5.2.8 Low Input Pull-up Current through pin PRG IPRG(L) 20 50 100 1) Not subject to production test, specified by design. Data Sheet 10 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks 5.3 Power Outputs 5.3.1 Electrical Characteristics Electrical Characteristics: Power Outputs VS = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. 5.3.1 Parameter Symbol RDS(ON) ON Resistance 5.3.2 Output Clamping Voltage 5.3.3 Over load current limitation 5.3.4 Output Leakage Current VDS(AZ) ID(lim) ID(lkg) Limit Values Unit Conditions TJ = 25 C, VS = 5 V, ID = 1A TJ = 150 C, VS = 5 V, ID = 1A Min. Typ. Max. - 0.32 - - 0.52 0.65 45 53 60 V output OFF 3 4.5 6 A - - 10 A VDS = 12 V TJ = 150 C, VDS = 35 V, VS = 5 V, RESET = 0 5.3.5 5.3.6 tON Turn-On Time tOFF Turn-Off Time - - 5 - - 5 10 s ID = 1 A, resistive load 10 s ID = 1 A, resistive load 5.3.7 Over temperature shutdown threshold1) Tj(OT) 170 - 200 C - 5.3.8 Over temperature restart hysteresis1) Tj(OT) - 10 - - 1) Not subject to production test, specified by design. 5.3.2 Timing Diagrams The power transistors are switched on and off with a dedicated slope either via the parallel inputs or by the CHnIN bits of the serial peripheral interface SPI. The switching times tON and tOFF are designed equally. See Figure 5 for details CS VDS SPI: ON SPI: OFF tON tOFF t 80% 20% Figure 5 Data Sheet Switching a Resistive Load 11 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks 5.3.3 Inductive Output Clamp When switching off inductive loads, the potential at pin OUT rises to VDS(CL), as the inductance continues to drive current. The inductive output clamp is necessary to prevent destruction of the device. See Figure 6 for details. The maximum allowed load inductance and current, however, are limited. V bat OUT ID L, RL VDS VDS(CL) GND Figure 6 Inductive Output Clamp Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the TLE8104E. This energy can be calculated with following equation: V bat - V DS(CL) R L ID L - ln 1 - -----------------------------------E = V DS(CL) ------------------------------------ + I D -----R RL V - V L bat DS(CL) The equation simplifies under the assumption of RL = 0: V bat 2 1 E = --- LI D 1 - ------------------------------------ 2 V - V bat DS(CL) The energy, which is converted into heat, is limited by the thermal design of the component. 5.3.4 Protection Functions The TLE8104E provides embedded protective functions. Integrated protection functions are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered "outside" the normal operating range. Protection functions are not designed for continuous repetitive operation. Over load and over temperature protections are implemented in the TLE8104E. Figure 7 gives an overview of the protective functions. INn OUTn Tn Input Control temperature monitor T gate control CS SCLK SI current limitation SPI SO CLn GND Figure 7 Data Sheet Protection Functions 12 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks 5.3.4.1 Over Load Protection The TLE8104E is protected in case of over load or short circuit of the load. The current is limited to IDS(lim). After time td(fault), the corresponding over load flag CLn is set. The channel may shut down due to over temperature. The over load flag (CLn) of the affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission. For timing information, please refer to Figure 8 for details. IN t FAULT t CS t ID I D(lim) t d(fault) t d(fault) t CL = 1b Figure 8 Over Load Behavior 5.3.4.2 Over Temperature Protection CL = 0b CL = 1b CL = 0b A dedicated temperature sensor for each channel detects if the temperature of its channel exceeds the over temperature shutdown threshold. If the channel temperature exceeds the over temperature shutdown threshold, the overheated channel is switched off immediately to prevent destruction. At the same time (no delay), the over temperature flag Tn is set. After cooling down, the channel is switched on again with thermal hysteresis Tj. The over temperature flag of the affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission. 5.3.5 Reverse Polarity Protection In the case of reverse polarity when outputs are turned off, the intrinsic body diode of the power transistor causes power dissipation. The reverse current through the intrinsic body diode has to be limited by the connected load. The VS supply pin must be protected against reverse polarity externally. Please note that neither the over load nor over temperature are functional in reverse current operation. Data Sheet 13 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks 5.4 Diagnostic Functions The TLE8104E provides diagnosis information about the device and about the load. The following diagnosis functions are implemented: * * * The protective functions (flags CLn and Tn) of channel n are registered in the diagnosis flag Pn. The open load diagnosis of channel n is registered in the diagnosis flag OLn. The short to ground monitor information of channel n is registered in the diagnosis flag SGn The diagnosis information of the TLE8104E can either be accessed by the SPI interface or FAULT pin. With the exception of over temperature, a fault is only recognized if it lasts longer than the fault delay time td(fault). When using the SPI interface and fault pin, diagnosis flags are latched in the diagnosis register of the SPI interface. In this case, diagnosis flags are cleared by the rising edge of the CS signal after a successful SPI transmission. Please see Figure 9 for details. VS VDS (S G) SPI CHn MUX 00 01 10 IDS (S G) SGn VDS (OL) IDS (P D) OLn FAULT OUTn OR gate control CLn Pn OR protective functions Tn GND Figure 9 Block Diagram of Diagnostic Functions Electrical Characteristics: Diagnostic Functions VS = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol Limit Values 5.4.1 Open Load Detection Voltage (Channel OFF) VDS(OL) VS - 2.5 VS - 2.0 VS - 1.3 V 5.4.2 Output Pull-down Current (Channel OFF) IPD(OL) 50 5.4.3 Short to Ground Detection Voltage VDS(SHG) 5.4.4 Output Pull-up Current (Channel OFF) IPU(SHG) -50 -100 -150 A VDS = 0 V 5.4.5 FAULT Filtering Time 50 110 200 s - 5.4.6 Low level output voltage of pin FAULT td(fault) VFAULT 0 - 0.4 V IFAULT = 1.6 mA Min. Data Sheet Typ. 90 Unit Max. 150 A VS - 3.3 VS - 2.9 VS - 2.5 V 14 Conditions - VDS = 32 V - V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks 5.5 SPI Interface The diagnosis and control interface is based on a serial peripheral interface (SPI). The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO MSB 6 5 4 3 2 1 SI MSB 6 5 4 3 2 1 LSB LSB CS SCLK time Figure 10 Serial Peripheral Interface The SPI protocol is described in Section 6. All registers are reset to default values after power-on reset or if the chip is programmed via SPI to enter sleep mode. 5.5.1 SPI Signal Description CS - Chip Select: The system micro controller selects the TLE8104E by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: * The diagnosis information is transferred into the shift register. CS Low to High transition: * * * Command decoding is only done after the falling edge of CS and a exact multiple (1, 2, 3, ...) of eight SCLK signals have been detected. Data from shift register is transferred into the input matrix register. The diagnosis flags are cleared. SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 6 for further information. SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 6 for further information. Data Sheet 15 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks 5.5.2 Daisy Chain Capability The SPI of TLE8104E is daisy chain capable. In this configuration several devices are activated by the same signal CS. The SI line of one device is connected with the SO line of another device (see Figure 11), which builds a chain. The ends of the chain are connected with the output and input of the master device, SO and SI respectively. The master device provides the master clock SCLK, which is connected to the SCLK line of each device in the chain. SO SPI SI SCLK SCLK SI SI device 3 SO SPI CS SO SPI CS SI CS SO device 2 SCLK device 1 CS SCLK Figure 11 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain configuration the data shifted out at device 1 has been shifted in to device 2. When using three TLE8104E devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the CS line must go high (see Figure 12). SI SO SO device 3 SO device 2 SO device 1 SI device 3 SI device 2 SI device 1 CS CLK time Figure 12 Data Transfer in Daisy Chain Configuration Electrical Characteristics: SPI Interface VS = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol Limit Values Min. Max. 20 50 A 20 50 A VS - 0.4 - - V - - 0.4 V VSI,SCLK = VS VCS = 0 V ISOH = 2 mA ISOL = 2.5 mA DC - 5 MHz - Input Pull-down Current (SI, SCLK) IIN(SI,SCLK) 10 5.5.2 Input Pull-up Current (CS) 5.5.3 SO High State Output Voltage 5.5.4 SO Low State Output Voltage 5.5.5 Serial Clock Frequency (depending on SO load) Data Sheet Conditions Typ. 5.5.1 IIN(CS) VSOH VSOL fSCK Unit 10 16 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Electrical and Functional Description of Blocks Electrical Characteristics: SPI Interface (cont'd) VS = 4.5 V to 5.5 V, Tj = -40 C to +150 C, (unless otherwise specified) all voltages with respect to ground, positive current flowing into pin Pos. Parameter Symbol Unit Conditions - ns - - - ns - 50 - - ns - 250 - - ns - 250 - - ns - 20 - - ns - 20 - - ns - - - 150 ns - 200 - - ns - - - 110 ns CL = 50 pF Typ. Max. tp(SCK) tSCKH tSCKL tlead 200 - 50 tlag 5.5.6 Serial Clock Period (1/fsclk) 5.5.7 Serial Clock High Time 5.5.8 Serial Clock Low Time 5.5.9 Enable Lead Time (falling edge of CS to rising edge of SCLK) 5.5.10 Enable Lag Time (falling edge of SCLK to rising edge of CS) 5.5.11 Data Setup Time (required time SI tSU to falling of SCLK) 5.5.12 Data Hold Time (falling edge of SCLK to SI) 5.5.13 Disable Time1) 5.5.14 Limit Values Min. tH tDIS Transfer Delay Time (CS high time tdt 2) between two accesses) 5.5.15 Data Valid Time3) tvalid 1) Not subject to production test, specified by design. 2) This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time td(fault)max = 200 s. 3) Not subject to production test, specified by design. 5.6 Timing Diagrams tCS(lead) tCS(lag) tCS(td) tSCLK(P) CS 0.7Vdd 0.2Vdd tSCLK(H) tSCLK(L) 0.7Vdd 0.2Vdd SCLK tSI(su) tSI(h) 0.7Vdd SI 0.2Vdd tSO(v) tSO(dis) 0.7Vdd SO Figure 13 Data Sheet 0.2Vdd Serial Interface Timing Diagram 17 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch SPI Control 6 SPI Control The SPI protocol of the TLE8104E provides two types of registers: control and diagnosis. After power-on reset, all register bits are set to default values. Serial Input Default Value: 00H 7 6 5 4 3 CMD w w w w w 2 1 0 DATA (CH4IN CH3IN CH2IN CH1IN) w w w Field Bits Type Description CMD 7:4 w Command 0000 Diagnosis only 1100 Read back input and 1-bit diagnosis 1010 Echo function of SPI 0011 BOL bit set for logic OR operation of INn and data bits. The default value for the BOL bit is logic OR. 1111 BOL bit set for logic AND operation of INn and data bits XXXX All other command words are accepted as an OR or AND command with valid data bits depending on the previously programmed Boolean operation. DATA 3:0 w Data If Command is 0000Data bits are ignored. If Command is 1100Data bits are ignored. If Command is 1010Data bits will appear as bits 3:0 at SO during the next CS period. If Command is 0011Each of the data bits is OR'ed with its corresponding input signal INn. If Command is 1111Each of the data bits is AND'ed with its corresponding input signal INn. All other CommandsEach of the data bits is OR'ed or AND'ed with its corresponding input signal INn, depending on the previously programmed Boolean operation. E Serial Output (Standard Diagnosis) Default Value: FFH 7 6 5 3 CH3 (CH31 CH30) CH4 (CH41 CH40) r 4 r r 2 CH2 (CH21 CH20) r r r Bits Type Description CHn 2n-2 :2n-1 r Standard Diagnosis for Channel n 00 Short circuit to ground 01 Open load 10 Over load / over temperature 11 Normal operation 18 0 CH1 (CH11 CH10) Field Data Sheet 1 r r V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch SPI Control 6.1 SPI Examples Below are examples of the different SPI command words and the resulting behavior of the output channels and Seiral Output pin. 6.1.1 Example: Diagnosis Only The contents of the diagnosis register will be returned during the next SPI access. This command is only active once unless the next control command is again "Diagnosis only" (see Figure 14). In the example shown in Figure 14, the standard diagnosis reports short circuit to ground for channel 1 (00), open load for channel 2 (01), over load / over temperature for channel 3 (10) and normal operation for channel 4 (11). CS t Diagnosis Only SI 0 0 0 0 X X X X X X SO X X X X X X X X 1 1 X X X X X X 0 0 t Standard Diagnosis 1 0 0 1 t Figure 14 Diagnosis Only 6.1.2 Example: Read Back Input and 1-bit Diagnosis The first four bits of SO during the next SPI access give the state of the parallel inputs, denoted by INn. The second four-bit word fed out at SO contains 1-bit diagnosis information of the output (1 = no fault, 0 = fault), denoted by Fn (see Figure 15). CS t Read Back Input and 1-bit Diagnosis SI 1 0 1 0 X X X X SO X X X X X X X X X X X X States of INn IN4 IN3 IN2 IN1 X X X X 1-bit Diagnosis F4 F3 F2 t F1 t Figure 15 Read Back Input and 1-bit Diagnosis 6.1.3 Example: Echo Function of SPI This function can be used to check the proper function of the serial interface. This command connects directly the SI to the SO during the next CS period. This internal connection is only active once unless the next control command is again "Echo function of SPI" (see Figure 16). Data Sheet 19 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch SPI Control CS t Echo Function of SPI SI 1 0 1 0 X X X X SO X X X X X X X X X X X SIX word X X X X IN2 SI IN1word F4 F3 F2 F1 t IN4 IN3 t Figure 16 Echo Function of SPI 6.1.4 Example: OR Operation and Diagnosis Sets the BOL bit to perform an OR operation on the INn signals and their corresponding data bits CHnIN . The contents of the diagnosis register will be returned during the next SPI access (see Figure 17). If the OR operation is programmed, it is latched until overwritten by an AND operation. This is the default operation after the device emerges from power-up or Reset mode. CS BOL set to OR t OR with INn signals SI 0 0 1 1 SO X X X X X CH4IN CH3 IN CH2IN CH1 IN X X X X X X X t Standard Diagnosis X X X X CH41 CH40 CH31 CH30 CH21 CH20 CH11 CH10 t Figure 17 OR Operation and Diagnosis 6.1.5 Example: AND Operation and Diagnosis Sets the BOL bit to perform an AND operation on the INn signals and their corresponding data bits CHnIN . The contents of the diagnosis register will be returned during the next SPI access (see Figure 18). If the AND operation is programmed, it is latched until overwritten by an OR operation, the device enters Reset mode or becomes shut down. CS BOL set to AND SI 11 11 11 11 SO X X X X t AND with INn signals CH4 CH4 CH3 CH3ININCH2 CH2 CH1 CH1ININ ININ ININ X X X X X X X X Standard Diagnosis X X X X t CH41 CH40 CH31 CH30 CH21 CH20 CH11 CH10 t Figure 18 Data Sheet AND Operation and Diagnosis 20 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch SPI Control 6.1.6 Example: All Other Command Words All other control words except for Diagnosis Only, Read Back Input and Echo Function will be accepted as an OR or an AND command with valid data bits, depending on the Boolean operation which was previously programmed (see Figure 19). CS BOL set to AND SI 11 11 11 11 SO X X X X AND with INn signals CH4 CH4ININCH3 CH3IN CH2 CH2ININCH1 CH1IN IN IN X X X X AND with INn signals CH4IN CH3IN CH2IN CH1IN Standard Diagnosis X X X X t t CH41 CH40 CH31 CH30 CH21 CH20 CH11 CH10 t Figure 19 Data Sheet All Other Command Words (with previously programmed AND command) 21 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Application Description 7 Application Description Vbat OUT1 IN1 IN2 IN3 LDO 5V VDD 10F RESET PRG I/O I/O PWM PWM FAULT CS C control, protection and diagnosis IN4 SCLK SPI OUT2 OUT3 OUT4 SI SO Figure 20 Data Sheet Application Circuit 22 V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Package Outlines 8 Package Outlines Figure 21 PG-DSO-20-30 (Plastic Dual Small Outline Package) Green Product Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 23 Dimensions in mm V1.1, 2008-03-03 TLE8104E Smart Quad Channel Powertrain Switch Revision History 9 Version Revision History Date Changes V1.0 -> V1.1: 2008-03-02 V1.1 2008-03-03 typo corrected page 3: from "Description / Quad Current Sense Low-Side Switch in Smart Power Technology (SPT) with four open drain DMOS output stages...." to "Description / Quad Low-Side Switch in Smart Power Technology (SPT) with four open drain DMOS output stages. ... V0.5 -> V1.0: 2007-06-11 Version Change to "Final" Data Sheet V1.0 2007-06-11 Information under Maximum Ratings about "DIN Humidity Category" and "IEC Climatic Category" according data sheet standards removed. V1.0 2007-07-10 Thermal Information Chapter 4.2 added V1.0 2007-07-26 Fig 21 updated Data Sheet 24 V1.1, 2008-03-03 Edition 2008-03-03 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. 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