TLE8104E
Smart Quad Channel Powertrain Switch
coreFLEX
Data Sheet, V1.1, February 2008
Automotive Power
Data Sheet 2 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3.2 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3.3 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3.4 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3.4.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.4.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.5 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 SPI Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1.1 Example: Diagnosis Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1.2 Example: Read Back Input and 1-bit Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1.3 Example: Echo Function of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1.4 Example: OR Operation and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.5 Example: AND Operation and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.6 Example: All Other Command Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table of Contents
PG-DSO-20-30
Type Package Marking
TLE8104E PG-DSO-20-30 TLE8104E
Data Sheet 3 V1.1, 2008-03-03
Smart Quad Channel Powertrain Switch
coreFLEX
TLE8104E
1 Overview
Features
• Overload Protection
• DMOS Overtemperature protection
• Overvoltage protection
• Open load detection
• Low quiescent current mode
•Electrostatic discharge (ESD) protection
• IC Overtemperature warning
• 8-Bit SPI (for diagnosis and control)
• Short to GND detection
• Green Product (RoHS compliant)
•AEC Qualified
Description
Quad Low-Side Switch in Smart Power Technology (SPT) with four open drain DMOS output stages. The
TLE8104E is protected by embedded protection functions and designed for automotive applications. The output
stages can be controlled directly by parallel inputs for PWM applications (e.g. gasoline port injection) or by SPI.
The parallel inputs can be programmed to be active high or active low. Diagnosis can be read from an 8-bit SPI
or by the external fault pin.
TLE8104E
Smart Quad Channel Powertrain Switch
Overview
Data Sheet 4 V1.1, 2008-03-03
Figure 1 Block Diagram
Table 1 Product Summary
Operating voltage VS4.5 … 5.5 V
Drain source voltage VDS(AZ) 45 … 60 V
Typical On-state resistance CH 1 - 4
at Tj = 25°C
RDS(ON) 320 mΩ
Maximum On-state resistance CH 1 - 4
at Tj = 150°C
RDS(ON) 650 mΩ
Nominal load current CH 1 - 4 ID1 A
Minimum current limitation CH 1 - 4 ID (lim) 3 A
Oi f
CS
SI
SCLK
SO
SPI
control,
diagnostic
and
protective
functions
open load
detection
temperature
sensor
gate
control
short circuit
detection
GND
IN1
RESET
VS
OUT4
OUT3
OUT2
OUT1
hardware
configuration
output monitor
input control
diagnosis register
reset / stand-by
IN2
IN3
IN4
PRG
FAULT
Data Sheet 5 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Terms
2Terms
Figure 2 shows all terms used in this Data Sheet.
Figure 2Terms
The following is valid for all electrical characteristics cables: Channel related symbols without channel number are
valid for each channel separately (e.g. VDS specification is valid for VDS1, VDS2, VDS3 and VDS4).
VCS
VSC L K
VIN 4
VSI ISO
SO
ISC L K
ISI
SCLK
SI
ICS
CS
VSO
GND
I GND
OUT1
VDS1
ID2
OUT2
OUT3
VDS3
VDS2
ID4
OUT4
VDS4
IIN 4
IN4
ID1
ID3
Vbat
VR ESET
IIN 2
VIN 3
IN3
IIN 1
VDD
IN2
IN1
PRG
FAULT
RESET
VS
IIN 3
IPR G
IFAU LT
IR ESET
IVS
VIN 2
VIN 1
VPR G
VFAU LT
TLE8104E
Smart Quad Channel Powertrain Switch
Pin Configuration
Data Sheet 6 V1.1, 2008-03-03
3 Pin Configuration
3.1 Pin Assignment
Figure 3 Pin Configuration (top view)
All GND pins and the heat sink must be connected to GND externally.
3.2 Pin Definitions and Functions
Pin Symbol Function
1GND Ground
2 IN2 Input Channel 2
3OUT1 Power Output Channel 1
4VS Supply Voltage
5RESET Reset Input
6CS SPI Chip Select
7PRG Program Input
8OUT2 Power Output Channel 1
9 IN1 Input Channel 1
10 GND Ground
11 GND Ground
12 IN4 Input Channel 4
13 OUT3 Power Output Channel 3
14 FAULT Fault Output
15 SO SPI Signal Out
16 SCLK SPI Clock
17 SI SPI Signal In
18 OUT4 Power Output Channel 4
19 IN3 Input Channel 3
20 GND Ground
(top view)
IN3
OUT4
SI
SCLK
GND
SO
20
19
18
17
16
15
IN2
OUT1
VS
RESET
GND
CS
1
2
3
4
5
6
PRG
7
8
9
10
14
13
12
11
OUT3
IN4
GND
FAULT
OUT2
IN1
GND
Data Sheet 7 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Maximum Ratings and Operating Conditions
4 Maximum Ratings and Operating Conditions
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
1) Not subject to production test, specified by design.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.1.1 Supply Voltage VS-0.3 7 V –
4.1.2 Continuous Drain Source Voltage
(OUT1 to OUT4)
VDS -0.3 45 V –
4.1.3 Input Voltage, All Inputs and Data
outputs, Sense Lines
VIN -0.3 7 V –
4.1.4 Output Current per Channel2)
2) Output current rating as long as maximum junction temperature is not exceeded. The maximum output current in the
application has to be calculated using RthJA depending on mounting conditions.
ID0 3 A Output ON
4.1.5 Maximum Voltage for short circuit
Protection (single event)3)
3) Device mounted on PCB (100 mm × 100 mm × 1.5 mm epoxy, FR4); PCB in test chamber without blown air. All channels
have identical loads.
VSC, single –30 V
4.1.6 Electrostatic Discharge Voltage
(human body model) according to
EIA/JESD22-A114-E
VESD -2000 2000 V
TLE8104E
Smart Quad Channel Powertrain Switch
Maximum Ratings and Operating Conditions
Data Sheet 8 V1.1, 2008-03-03
4.2 Operating Conditions
Note: Within the functional range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given by the related electrical characteristics table.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
4.2.1 Output Clamping Energy (single
event), linearly decreasing current1)
1) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse
EAS ––50 mJ ID(0) = 1 A,
TJ(0) = 150 °C
Thermal Resistance
4.2.2 Junction to case RthJSP –2.1 3K/W PV = 3W
4.2.3 Junction to ambient, all channels
active2)
2) PCB set-up according Figure 4
Figure 4 Thermal Simulation - PCB setup
RthJA –26.2 –K/W PV = 3W
Temperature Range
4.2.4 Operating Temperature Range Tj-40 –150 °C –
4.2.5 Storage Temperature Range Tstg -55 –150 °C –
70µm modeled (traces)
35µm, 90% metalization
35
µ
m
,
90
%
metalization
1
,5
mm
70
µ
m
,
5% metalization
Ther mal_Setup.vsd
PCB Dimensions: 76.2 x 114.3 x 1.5 mm³, FR4
Thermal Vias: diameter = 0.3 mm; plating 25 µm; 24 pcs.
Metallisation according JEDEC 2s2p (JESD 51-7) + (JESD 51-5)
Data Sheet 9 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
5 Electrical and Functional Description of Blocks
5.1 Power Supply
The TLE8104E is supplied by power supply line VS, used for the digital as well as the analog functions of the device
including the gate control of the power stages. A capacitor between pins VS to GND is recommended.
A RESET pin is available. When a low level is applied to this pin, the device enters sleep mode. In this case, all
registers are set to their default values and the quiescent supply current is minimized.
After start-up of the power supply, the RESET pin should be kept low until the Reset Duration Time has expired,
reseting all SPI registers to their default values.
5.2 Parallel Inputs
Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1, IN2 controls
OUT2, etc. Please refer to Figure 4 for details.
The PRG pin selects if the input pins are active high or active low and activates either a pull-down or pull-up current
source. If PRG is high, the input pins are active high and the pull-down current source is active. If PRG is low, the
input pins are active low and the pull-up current source is active. The respective current sources at the input pin
ensure that the channels switch off in case of an unconnected pin. The zener diode protects the input circuit
against ESD pulses.
The BOL bit can be set via SPI. This bit determines if a Boolean OR or AND operation is performed on the INn
signals and their corresponding data bits CHnIN . The default setting of the BOL bit programs the device to perform
an OR operation.
Electrical Characteristics: Power Supply
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.1.1 Supply Voltage VS4.5 –5.5 V –
5.1.2 Supply Current IS(ON) –12mA all channels ON
5.1.3 Supply Current in Sleep Mode IS(sleep) ––100 µAVRESET = 0 V
VINn = 0 V
VSCLK = 0 V
VSI = 0 V
VCS = VS
VPRG = VS
VFAULT = VS
5.1.4 Input Low Voltage of pin RESET VRESET(L) -0.3 –1.0 V –
5.1.5 Input High Voltage of pin RESET VRESET(H) 2.0 –VS
+0.3
V –
5.1.6 Low Input Pull-up Current
through pin RESET
IRESET(L) 20 50 100 µAVRESET = 0 V,
5.1.7 Reset duration time1)
1) For proper startup, after the supply VS has reached its final voltage, the RESET pin should be held low until
the reset duration time has expired.
tRESET(L) 10 ––µs –
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 10 V1.1, 2008-03-03
Figure 4 Input Control and Boolean Operator
Electrical Characteristics: Parallel Inputs
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.2.1 Input Low Voltage of pin INn VINL -0.3 –1.0 V –
5.2.2 Input High Voltage of pin INn VINH 2.0 –VS
+0.3
V –
5.2.3 Input Voltage Hysteresis1)
1) Not subject to production test, specified by design.
VINHys 50 100 200 mV –
5.2.4 Low Input Pull-up Current
through pin INn
IIN(L) 20 50 100 µAVIN = 0 V,
PRG = 0
5.2.5 High Input Pull-down Current
through pin INn
IIN(L) 20 50 100 µAVIN = VS,
PRG = 1
5.2.6 Input Low Voltage of pin PRG VPRG(L) -0.3 –1.0 V –
5.2.7 Input High Voltage of pin PRG VPRG(H) 2.0 –VS
+0.3
V –
5.2.8 Low Input Pull-up Current
through pin PRG
IPRG(L) 20 50 100 µAVPRG = 0 V,
channel 4
channel 3
channel 2
channel 1
&
OR
IN1
I
IN1(H)
CH1
IN
BOL
gate
control
PRG
Closed if
PRG = 1
PRG = 1: Active High
PRG = 0: Active Low
I
IN1(L)
Closed if
PRG = 0
Data Sheet 11 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.3 Power Outputs
5.3.1 Electrical Characteristics
5.3.2 Timing Diagrams
The power transistors are switched on and off with a dedicated slope either via the parallel inputs or by
the CHnIN bits of the serial peripheral interface SPI. The switching times tON and tOFF are designed equally. See
Figure 5 for details
Figure 5 Switching a Resistive Load
Electrical Characteristics: Power Outputs
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.3.1 ON Resistance RDS(ON) –0.32 –ΩTJ = 25 °C,
VS = 5 V,
ID = 1A
–0.52 0.65 ΩTJ = 150 °C,
VS = 5 V,
ID = 1A
5.3.2 Output Clamping Voltage VDS(AZ) 45 53 60 Voutput OFF
5.3.3 Over load current limitation ID(lim) 34.5 6 A VDS = 12 V
5.3.4 Output Leakage Current ID(lkg) ––10 µATJ = 150 °C,
VDS = 35 V,
VS = 5 V,
RESET = 0
5.3.5 Turn-On Time tON –
–
510 µsID = 1 A,
resistive load
5.3.6 Turn-Off Time tOFF –
–
510 µsID = 1 A,
resistive load
5.3.7 Over temperature shutdown
threshold1)
1) Not subject to production test, specified by design.
Tj(OT) 170 –200 °C –
5.3.8 Over temperature restart
hysteresis1)
∆Tj(OT) –10 –Κ–
CS
V
DS
t
t
ON
t
OFF
20%
80%
SPI: ON SPI: OFF
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 12 V1.1, 2008-03-03
5.3.3 Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL), as the inductance continues to drive
current. The inductive output clamp is necessary to prevent destruction of the device. See Figure 6 for details.
The maximum allowed load inductance and current, however, are limited.
Figure 6 Inductive Output Clamp
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE8104E. This energy can be
calculated with following equation:
The equation simplifies under the assumption of RL = 0:
The energy, which is converted into heat, is limited by the thermal design of the component.
5.3.4 Protection Functions
The TLE8104E provides embedded protective functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in this data sheet. Fault conditions are considered “outside” the
normal operating range. Protection functions are not designed for continuous repetitive operation.
Over load and over temperature protections are implemented in the TLE8104E. Figure 7 gives an overview of the
protective functions.
Figure 7 Protection Functions
V
bat
I
D
V
DS(CL)
OUT
V
DS
GND
L,
R
L
EV
DS(CL)
Vbat V–DS(CL)
RL
-------------------------------------ln⋅1RLID
⋅
Vbat V–DS(CL)
-------------------------------------–
ID
+L
RL
------
⋅⋅=
E1
2
---LID
21Vbat
Vbat V–DS(CL)
-------------------------------------–
⋅=
OUTn
SPI
INn
temper atur e
monitor
cur r ent
lim itation
gate contr ol
T
Tn
CLn
GND
CS
Input C ontr ol
SCLK
SI
SO
Data Sheet 13 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.3.4.1 Over Load Protection
The TLE8104E is protected in case of over load or short circuit of the load. The current is limited to IDS(lim). After
time td(fault), the corresponding over load flag CLn is set. The channel may shut down due to over temperature.
The over load flag (CLn) of the affected channel is cleared by the rising edge of the CS signal after a successful
SPI transmission. For timing information, please refer to Figure 8 for details.
Figure 8 Over Load Behavior
5.3.4.2 Over Temperature Protection
A dedicated temperature sensor for each channel detects if the temperature of its channel exceeds the over
temperature shutdown threshold. If the channel temperature exceeds the over temperature shutdown threshold,
the overheated channel is switched off immediately to prevent destruction. At the same time (no delay), the over
temperature flag Tn is set. After cooling down, the channel is switched on again with thermal hysteresis ∆Tj.
The over temperature flag of the affected channel is cleared by the rising edge of the CS signal after a successful
SPI transmission.
5.3.5 Reverse Polarity Protection
In the case of reverse polarity when outputs are turned off, the intrinsic body diode of the power transistor causes
power dissipation. The reverse current through the intrinsic body diode has to be limited by the connected load.
The VS supply pin must be protected against reverse polarity externally. Please note that neither the over load nor
over temperature are functional in reverse current operation.
IN
I
D
t
t
t
d(fault)
CL = 1
b
CL = 0
b
I
D( lim)
FAULT
t
CS
t
t
d(fault)
CL = 1
b
CL = 0
b
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 14 V1.1, 2008-03-03
5.4 Diagnostic Functions
The TLE8104E provides diagnosis information about the device and about the load. The following diagnosis
functions are implemented:
• The protective functions (flags CLn and Tn) of channel n are registered in the diagnosis flag Pn.
• The open load diagnosis of channel n is registered in the diagnosis flag OLn.
• The short to ground monitor information of channel n is registered in the diagnosis flag SGn
The diagnosis information of the TLE8104E can either be accessed by the SPI interface or FAULT pin. With the
exception of over temperature, a fault is only recognized if it lasts longer than the fault delay time td(fault). When
using the SPI interface and fault pin, diagnosis flags are latched in the diagnosis register of the SPI interface. In
this case, diagnosis flags are cleared by the rising edge of the CS signal after a successful SPI transmission.
Please see Figure 9 for details.
Figure 9 Block Diagram of Diagnostic Functions
Electrical Characteristics: Diagnostic Functions
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.4.1 Open Load Detection Voltage
(Channel OFF)
VDS(OL) VS - 2.5 VS - 2.0 VS - 1.3 V –
5.4.2 Output Pull-down Current
(Channel OFF)
IPD(OL) 50 90 150 µAVDS = 32 V
5.4.3 Short to Ground Detection Voltage VDS(SHG) VS - 3.3 VS - 2.9 VS - 2.5 V –
5.4.4 Output Pull-up Current
(Channel OFF)
IPU(SHG) -50 -100 -150 µAVDS = 0 V
5.4.5 FAULT Filtering Time td(fault)50 110 200 µs –
5.4.6 Low level output voltage of pin
FAULT
VFAULT 0–0.4 VIFAULT = 1.6 mA
OUTn
I
DS(PD)
SGn
VS
V
DS(SG)
I
DS(SG)
protective functions
CLn
Tn
OR
SPI MUX
00
01
10
OLn
V
DS(OL)
CHn
gate contr ol
Pn
GND
ORFAULT
Data Sheet 15 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.5 SPI Interface
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
Figure 10 Serial Peripheral Interface
The SPI protocol is described in Section 6. All registers are reset to default values after power-on reset or if the
chip is programmed via SPI to enter sleep mode.
5.5.1 SPI Signal Description
CS - Chip Select: The system micro controller selects the TLE8104E by means of the CS pin. Whenever the pin
is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are
ignored and SO is forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
CS Low to High transition:
• Command decoding is only done after the falling edge of CS and a exact multiple (1, 2, 3, …) of eight SCLK
signals have been detected.
• Data from shift register is transferred into the input matrix register.
• The diagnosis flags are cleared.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 6
for further information.
SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance
state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Section 6 for further information.
6 5
6 5MSB
MSB LSB2 1
2 1 LSB
4
4
3
3
SO
SI
CS
SCLK
time
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 16 V1.1, 2008-03-03
5.5.2 Daisy Chain Capability
The SPI of TLE8104E is daisy chain capable. In this configuration several devices are activated by the same signal
CS. The SI line of one device is connected with the SO line of another device (see Figure 11), which builds a
chain. The ends of the chain are connected with the output and input of the master device, SO and SI respectively.
The master device provides the master clock SCLK, which is connected to the SCLK line of each device in the
chain.
Figure 11 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain
configuration the data shifted out at device 1 has been shifted in to device 2. When using three TLE8104E devices
in daisy chain, three times 8 bits have to be shifted through the devices. After that, the CS line must go high (see
Figure 12).
Figure 12 Data Transfer in Daisy Chain Configuration
Electrical Characteristics: SPI Interface
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.5.1 Input Pull-down Current (SI, SCLK) IIN(SI,SCLK) 10 20 50 µAVSI,SCLK = VS
5.5.2 Input Pull-up Current (CS)IIN(CS)10 20 50 µAVCS = 0 V
5.5.3 SO High State Output Voltage VSOH VS - 0.4 ––VISOH = 2 mA
5.5.4 SO Low State Output Voltage VSOL ––0.4 VISOL = 2.5 mA
5.5.5 Serial Clock Frequency
(depending on SO load)
fSCK DC –5MHz –
SI
device 1
SPI
SCLK
SO
CS
SI
device 2
SPI
SCLK
SO
CS
SI
device 3
SPI
SCLK
SO
CS
SO
SI
CS
SCLK
SI
SO
CS
CLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
time
Data Sheet 17 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.6 Timing Diagrams
Figure 13 Serial Interface Timing Diagram
5.5.6 Serial Clock Period (1/fsclk)tp(SCK) 200 ––ns –
5.5.7 Serial Clock High Time tSCKH 50 ––ns –
5.5.8 Serial Clock Low Time tSCKL 50 ––ns –
5.5.9 Enable Lead Time (falling edge of
CS to rising edge of SCLK)
tlead 250 ––ns –
5.5.10 Enable Lag Time (falling edge of
SCLK to rising edge of CS)
tlag 250 ––ns –
5.5.11 Data Setup Time (required time SI
to falling of SCLK)
tSU 20 ––ns –
5.5.12 Data Hold Time (falling edge of
SCLK to SI)
tH20 ––ns –
5.5.13 Disable Time1) tDIS ––150 ns –
5.5.14 Transfer Delay Time2) (CS high time
between two accesses)
tdt 200 ––ns –
5.5.15 Data Valid Time3) tvalid ––110 ns CL = 50 pF
1) Not subject to production test, specified by design.
2) This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has
to be extended to the maximum fault delay time td(fault)max = 200 µs.
3) Not subject to production test, specified by design.
Electrical Characteristics: SPI Interface (cont’d)
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
CS
SCLK
SI
tCS(lead) tCS( td )
tCS( l a g )
tSCL K( H) tSCL K( L )
tSCL K( P)
tSI( su ) tSI( h )
SO
t
SO ( v) tSO ( d is)
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
TLE8104E
Smart Quad Channel Powertrain Switch
SPI Control
Data Sheet 18 V1.1, 2008-03-03
6 SPI Control
The SPI protocol of the TLE8104E provides two types of registers: control and diagnosis. After power-on reset, all
register bits are set to default values.
E
Serial Input
Default Value: 00H
76543210
CMD DATA
(CH4IN CH3IN CH2IN CH1IN)
wwwwwwww
Field Bits Type Description
CMD 7:4 wCommand
0000 Diagnosis only
1100 Read back input and 1-bit diagnosis
1010 Echo function of SPI
0011 BOL bit set for logic OR operation of INn and data bits.
The default value for the BOL bit is logic OR.
1111 BOL bit set for logic AND operation of INn and data bits
XXXX All other command words are accepted as an OR or AND
command with valid data bits depending on the previously
programmed Boolean operation.
DATA 3:0 wData
If Command is 0000Data bits are ignored.
If Command is 1100Data bits are ignored.
If Command is 1010Data bits will appear as bits 3:0 at SO during
the next CS period.
If Command is 0011Each of the data bits is OR’ed with its
corresponding input signal INn.
If Command is 1111Each of the data bits is AND’ed with its
corresponding input signal INn.
All other CommandsEach of the data bits is OR’ed or AND’ed
with its corresponding input signal INn,
depending on the previously programmed
Boolean operation.
Serial Output (Standard Diagnosis)
Default Value: FFH
76543210
CH4
(CH41 CH40)
CH3
(CH31 CH30)
CH2
(CH21 CH20)
CH1
(CH11 CH10)
rrrrrrrr
Field Bits Type Description
CHn 2n-2
:2n-1
rStandard Diagnosis for Channel n
00 Short circuit to ground
01 Open load
10 Over load / over temperature
11 Normal operation
Data Sheet 19 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
SPI Control
6.1 SPI Examples
Below are examples of the different SPI command words and the resulting behavior of the output channels and
Seiral Output pin.
6.1.1 Example: Diagnosis Only
The contents of the diagnosis register will be returned during the next SPI access. This command is only active
once unless the next control command is again “Diagnosis only” (see Figure 14).
In the example shown in Figure 14, the standard diagnosis reports short circuit to ground for channel 1 (00), open
load for channel 2 (01), over load / over temperature for channel 3 (10) and normal operation for channel 4 (11).
Figure 14 Diagnosis Only
6.1.2 Example: Read Back Input and 1-bit Diagnosis
The first four bits of SO during the next SPI access give the state of the parallel inputs, denoted by INn. The
second four-bit word fed out at SO contains 1-bit diagnosis information of the output (1 = no fault, 0 = fault),
denoted by Fn (see Figure 15).
Figure 15 Read Back Input and 1-bit Diagnosis
6.1.3 Example: Echo Function of SPI
This function can be used to check the proper function of the serial interface. This command connects directly the
SI to the SO during the next CS period. This internal connection is only active once unless the next control
command is again “Echo function of SPI” (see Figure 16).
Standard Diagnosis
Diagnosis Only
CS
t
t
t
00XXXX00
XXXXXXXX
XXXXXXXXSI
SO 10010011
1-bit DiagnosisStates of INn
Read Back Input and 1-bit Diagnosis
CS
IN2 IN1 F4 F3 F2 F1IN3IN4
t
t
t
10XXXX01
XXXXXXXX
XXXXXXXXSI
SO
TLE8104E
Smart Quad Channel Powertrain Switch
SPI Control
Data Sheet 20 V1.1, 2008-03-03
Figure 16 Echo Function of SPI
6.1.4 Example: OR Operation and Diagnosis
Sets the BOL bit to perform an OR operation on the INn signals and their corresponding data bits CHnIN . The
contents of the diagnosis register will be returned during the next SPI access (see Figure 17). If the OR operation
is programmed, it is latched until overwritten by an AND operation. This is the default operation after the device
emerges from power-up or Reset mode.
Figure 17 OR Operation and Diagnosis
6.1.5 Example: AND Operation and Diagnosis
Sets the BOL bit to perform an AND operation on the INn signals and their corresponding data bits CHnIN . The
contents of the diagnosis register will be returned during the next SPI access (see Figure 18). If the AND operation
is programmed, it is latched until overwritten by an OR operation, the device enters Reset mode or becomes shut
down.
Figure 18 AND Operation and Diagnosis
CS
IN2 IN1 F4 F3 F2 F1IN3IN4
t
t
t
10XXXX01
XXXXXXXX
XXXXXXXXSI
SO
SI word
SI word
Echo Function of SPI
BOL set to OR
Standard Diagnosis
CS
CH3
1
CH3
0
CH2
1
CH2
0
CH1
1
CH1
0
CH4
0
CH4
1
t
t
t
11
CH4
IN
CH3
IN
CH2
IN
CH1
IN
00
XXXXXXXX
XXXXXXXXSI
SO
OR with INn signals
Standard Diagnosis
CS
CH3
1
CH3
0
CH2
1
CH2
0
CH1
1
CH1
0
CH4
0
CH4
1
t
t
t
11
CH4
IN
CH3
IN
CH2
IN
CH1
IN
11
XXXXXXXX
XXXXXXXXSI
SO
BOL set to AND
11
CH4
IN
CH3
IN
CH2
IN
CH1
IN
11
AND with INn signals
Data Sheet 21 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
SPI Control
6.1.6 Example: All Other Command Words
All other control words except for Diagnosis Only, Read Back Input and Echo Function will be accepted as an OR
or an AND command with valid data bits, depending on the Boolean operation which was previously programmed
(see Figure 19).
Figure 19 All Other Command Words (with previously programmed AND command)
Standard Diagnosis
CS
CH3
1
CH3
0
CH2
1
CH2
0
CH1
1
CH1
0
CH4
0
CH4
1
t
t
t
11
CH4
IN
CH3
IN
CH2
IN
CH1
IN
11
XXXXXXXX
SI
SO
AND with INn signals
XX
CH4
IN
CH3
IN
CH2
IN
CH1
IN
XX
AND with INn signalsBOL set to AND
11
CH4
IN
CH3
IN
CH2
IN
CH1
IN
11
TLE8104E
Smart Quad Channel Powertrain Switch
Application Description
Data Sheet 22 V1.1, 2008-03-03
7 Application Description
Figure 20 Application Circuit
IN1
IN2
CS
SI
SCLK
SO
VDD
control, protection and diagnosis
Vbat
5V
SPI
LDO
PWM
I/O
IN3
IN4
FAULT
µC
I/O
PWM
PRG
RESET
OUT1
OUT2
OUT3
OUT4
10µF
Data Sheet 23 V1.1, 2008-03-03
TLE8104E
Smart Quad Channel Powertrain Switch
Package Outlines
8 Package Outlines
Figure 21 PG-DSO-20-30 (Plastic Dual Small Outline Package) Green Product
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
TLE8104E
Smart Quad Channel Powertrain Switch
Revision History
Data Sheet 24 V1.1, 2008-03-03
9 Revision History
Version Date Changes
V1.0 -> V1.1: 2008-03-02
V1.1 2008-03-03 typo corrected page 3: from “Description / Quad Current Sense Low-Side Switch
in Smart Power Technology (SPT) with four open drain DMOS output stages....”
to “Description / Quad Low-Side Switch in Smart Power Technology (SPT) with
four open drain DMOS output stages. ...
V0.5 -> V1.0: 2007-06-11 Version Change to “Final” Data Sheet
V1.0 2007-06-11 Information under Maximum Ratings about “DIN Humidity Category” and “IEC
Climatic Category” according data sheet standards removed.
V1.0 2007-07-10 Thermal Information Chapter 4.2 added
V1.0 2007-07-26 Fig 21 updated
Edition 2008-03-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
