USE ULTRA37000™ FOR
ALL NEW DESIGNS
UltraLogic™ 32-Macrocell Flash CPLD
CY7C371i
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-03032 Rev. *A Revised April 19, 2004
Features
•32 macrocells in two logic blocks
•32 I/O pins
•Five dedica te d inputs includ ing two clock pins
•In-System Reprogrammable (ISR™) Flash technology
—JTAG interface
•Bus Hold capabilities on all I/Os and dedi ca te d in put s
•No hidden delays
•High speed
—fMAX = 143 MHz
—tPD= 8.5 n3s
—tS = 5 ns
—tCO = 6 ns
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, and TQFP packages
• Pin-compatible with the CY7C372i
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C371i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enab led
using the programming voltage pin (ISREN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic desi gns while
simultaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the FLASH370i architecture are connected
with an extreme ly fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the FLASH370i family , the CY7C371i is rich
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7 C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
Selection Guide
7C371i-143 7C371i-110 7C371i-83 7C371iL-83 7C371i-66 7C371iL-66 Unit
Maximum Propagation Delay[1], tPD 8.5 10 12 12 15 15 ns
Minimum Set-up, tS5 6 8 8 10 10 ns
Maximum Clock to Output[1], tCO 6 6.5 8 8 10 10 ns
T ypical Supply Current, ICC Comm./Ind. 75 75 75 45 75 45 mA
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
PIM
3
INPUT
MACROCELLS
2
Clock
Inputs
Inputs
LOGIC
BLOCK
A
LOGIC
BLOCK
B
22
36
16 16
36
16 I/Os 16 I/Os
16 16
INPUT/CLOCK
MACROCELLS
I/O0–I/O15 I/O16–I/O31
Logic Block Diagram
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 2 of 12
Functional Description
Finally, the CY7C371i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C371i remain the same.
Logic Block
The number of logic blocks d istinguishes the membe rs of the
FLASH370i family. The CY7C371i includes two logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i logic block in cludes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C371i has a separate
associated I/O pin. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The macrocell also features a
separate feedback path to the PIM so that the register can be
buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
two logic blocks on the CY7C371i to the inputs and to each
other. All inpu ts (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Speci fication publishe d by the PCI Sp ecial
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
3.3V or 5.0V I/O Operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input bu ffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the ou tput requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
Pin Configurations
I/O27/SDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
I2
I/O23
I/O22
I/O21
I/O5/SCLK
I/O6
I/O7
I0
ISREN
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
GND
I/O20
I/O2
GND
VCCIO
VCCINT
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
6534 2
8
9
7
10
11
144
18
15
16
14
13
12
17 19 20 2221 23 24 2726 2825
31
30
29
32
33
34
39
37
38
36
35
43 42 4041
I/O2
GND
VCCIO
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O27/SDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
I2
I/O23
I/O22
I/O21
GND
I/O20
VCCINT
I/O18
I/O17
I/O16
I/O15
I/O14
I/O12
I/O5/SCLK
I/O6
I/O7
I0
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
8
9
7
10
11
3
4
2
5
6
1
18 19 20 222113 14 15 171612
31
30
29
32
33
26
25
24
27
28
23
44 43 42 4041 39 38 37 3536 34
PLCC
Top View
TQFP
TopView
/SMODE
/SDO
I/O13/SMODE
I/O19/SDO
ISREN
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 3 of 12
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The adde d flexibility of 3.3V I/O capability
is available in commercial and industri al temperature ranges.
Bus Hold Cap abilities on all I/Os and Dedicated Input s
In addition to ISR capability , a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor , is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the de vice without cutting
trace connections to VCC or GND.
Design Tools
Development software for the CY7C371i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 4 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential.................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z S tate.....................................................−0.5V to +7.0V
DC Input V oltage.................................................−0.5V to +7.0V
DC Program Voltage............... .............. ... .............. ... ....12.5V
Output Current into Outputs (LOW).............................16 mA
Static Discharge V o ltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCCVCCINT VCCIO
Commercial 0°C to +70°C5V ± 0.25V 5V ± 0.25V or
3.3V ± 0.3V
Industrial −40°C to +85°C5V ± 0.5V 5V ± 0.5V or
3.3V ± 0.3V
Electrical Characteristics Over the Operating Range[2,3]
Parameter Description Test Conditions Min. Typ. Max. Unit
VOH Output HIGH V oltage with
Output Enabled VCC = Min. IOH = −3.2 mA (Com’l/Ind)[4] 2.4 V
VOHZ Output HIGH V oltage with
Output Disabled[8] VCC = Max. IOH = 0 µA (Com’l/Ind)[4,5] 4.0 V
IOH = −50 µA (Com’l/Ind)[4,5] 3.6 V
VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)[4] 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all inputs[6] 2.0 7.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all inputs[6] −0.5 0.8 V
IIX Input Load Current VI = Internal GND, VI = VCC −10 +10 µA
IOZ Output Leakage Current VCC = Max., VO = GND or VO =VCC, Output Disabled −50 +50 µA
VCC = Max., VO = 3.3V, Output Disabled[5] 0 –70 –125 µA
IOS Output Short Circuit
Current[7,8] VCC = Max., VOUT = 0.5V −30 −160 mA
ICC Power Supply Current VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC[9] Com’l/Ind. 75 125 mA
Com’l “L” −66, −83 45 75 mA
IBHL Input Bus Hold LOW
Sustaining Current VCC = Min., VIL = 0.8V +75 µA
IBHH Input Bus Hold HIGH
Sustaining Current VCC = Min., VIH = 2.0V −75 µA
IBHLO Input Bus Hold LOW
Overdrive Current VCC = Max. +500 µA
IBHHO Input Bus Hold HIGH
Overdrive Current VCC = Max. −500 µA
Capacitance[8]
Parameter Description Test Conditions Min. Max. Unit
CI/O[10] Input Capacitance VIN = 5.0V at f=1 MHz 8 pF
CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz 5 12 pF
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. If VCCIO is not specifi ed, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.
4. IOH = −2 mA, IOL = 2 mA for SDO.
5. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This volt age is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
6. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
7. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
8. Tested initially and after any design or process changes that may affect these pa rameters.
9. Measured with 16-bit counter pr ogrammed into each logic block.
10.CI/O for ISREN is 15 pF Max.
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 5 of 12
Note:
11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Inductance[8]
Parameter Description Test Conditions 44-Lead TQFP 44-Lead PLCC Unit
L Maximum Pin Inductance VIN = 5.0V at f= 1 MHz 2 5 nH
Endurance Characteristics[8]
Parameter Description Test Conditions Max. Unit
N Maximum Reprogramming Cycles Normal Programming Conditions 100 Cycles
AC Test Loads and Waveforms
Parameter[11] Vx Output Waveform Measurement Level
tER(–) 1.5V
tER(+) 2.6V
tEA(+) 1.5V
tEA(–) Vthe
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2ns <2ns
OUTPUT
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
236Ω(MIL)
99Ω(COM'L)
136Ω(MIL)
Equivalent to: THÉ VENIN EQUIVALENT
2.08V(COM'L)
2.13V(MIL)
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
236Ω(MIL)
(c)
VOH
0.5V VX
VOL
0.5V VX
VOH
0.5V
VX
VX
0.5V VOL
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 6 of 12
Switching Characteristics Over the Operating Range [12]
Parameter Description 7C371i−143 7C371i−110 7C371i−83
7C371iL−83 7C371i−66
7C371iL−66 UnitMin. Max. Min. Max. Min. Max. Min. Max.
Combinatorial Mode Parameters
tPD Input to Combinato r ial Output[1] 8.5 10 12 15 ns
tPDL Input to Output Through Transp arent Input or
Output Latch[1] 11.5 13 18 22 ns
tPDLL Input to Output Through Transparent Input
and Output Latches[1] 13.5 15 20 24 ns
tEA Input to Output Enable[1] 13 14 19 24 ns
tER Input to Output Disable 13 14 19 24 ns
Input Registered/Latch ed Mode Parameters
tWL Clock or Latch Enable Input LOW Time[8] 2.5 3 4 5 ns
tWH Clock or Latch Enable Input HIGH Time[8] 2.5 3 4 5 ns
tIS Input Register or Latch Set-up Time 2 2 3 4 ns
tIH Input Register or Latch Hold Time 2 2 3 4 ns
tICO Input Regi st er C lo ck or Latch Enable to
Combinatorial Output[1] 12 14 19 24 ns
tICOL Input Register Clock or Latch Enable to Output
Through Transparent Output Latch[1] 14 16 21 26 ns
Output Registered/Latched Mod e Parameters
tCO Clock or Latch Enable to Output[1] 66.5810ns
tSSet-up Time from Input to Clock or Latch
Enable 56810ns
tHRegister or Latch Data Hold Time 0 0 0 0 ns
tCO2 Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1] 12 14 19 24 ns
tSCS Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array) 7 9 12 15 ns
tSL Set-up Time from Input Through T ransparent
Latch to Output Register Clock or Latch Enable 9101215ns
tHL Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable 0000ns
fMAX1 Maximum Frequency with Internal Feedback
(Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[8] 143 111 83.3 66.6 MHz
fMAX2 Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL
+t
WH), 1/(tS + tH), or 1/tCO)[8]
166.7 153.8 100 83.3 MHz
fMAX3 Maximum Frequency with external feedback
(Lesser of 1/(tCO + tS) and 1/(tWL + tWH))[8] 91 80 50 41.6 MHz
tOH-tIH
37x Output Data Stable from Output clock minus
Input Register Hold Time for 7C37x[8,13] 0000ns
Pipelined Mode Paramete rs
tICS Input Register Clock to Output Register Clock 7 9 12 15 ns
fMAX4 Maximum Frequency in Pipelined Mode
(Least of 1/(tCO + tIS), 1/tICS, 1/ (tWL + tWH),
1/(tIS + tIH), or 1/tSCS)
125 111 76.9 62.5 MHz
Notes:
12.All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
13.This specification is intended t o guaran tee interf ace comp ati bilit y of t he other me mbers o f the CY7 C370i fami ly with t he CY7C371 i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 7 of 12
Reset/Preset Parameters
tRW Asynchronous Reset Width[8] 8101520ns
tRR Asynchronous Reset Recovery Time[8] 10 12 17 22 ns
tRO Asynchronous Reset to Output[1] 14 16 21 26 ns
tPW Asynchronous Preset Width[8] 8101520ns
tPR Asynchronous Preset Recovery Time[8] 10 12 17 22 ns
tPO Asynchronous Preset to Output[1] 14 16 21 26 ns
Tap Controller Parameters
fTAP Tap Controller Frequency 500 500 500 500 kHz
3.3V I/O Mode Parameters
t3.3IO 3.3V I/O mode timing adder 1 1 1 1 ns
Switching Characteristics Over the Operating Range (continued)[12]
Parameter Description 7C371i−143 7C371i−110 7C371i−83
7C371iL−83 7C371i−66
7C371iL−66 UnitMin. Max. Min. Max. Min. Max. Min. Max.
Switching Waveforms
Combinatorial Output
tPD
INPUT
COMBINATORIAL
OUTPUT
Latched Output
tS
INPUT
LATCH ENABLE
tCO
LATCHED
OUTPUT
tH
tPDL
Registered Input
tIS
REGISTERED
INPUT
INPUT REGISTER
CLOCK tICO
COMBINATORIAL
OUTPUT
tIH
CLOCK
tWL
tWH
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 8 of 12
Switching Waveforms (continued)
Clock to Clock
REGISTERED
INPUT
INPUT REGISTER
CLOCK
tICS
OUTPUT
REGISTER CLOCK
tSCS
Latched Input
tIS
LATCHED INPUT
LATCH ENABLE
tICO
COMBINATORIAL
OUTPUT
tIH
tPDL
LATCH ENABLE
tWL
tWH
Latched Input and Output
tICS
LATCHED INPUT
OUTPUT LATCH
ENABLE
LATCHED
OUTPUT
tPDLL
LATCH ENABLE
tWL
tWH
tICOL
INPUT LATCH
ENABLE
tSL tHL
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 9 of 12
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
143 CY7C371i−143AC A44 44-Lead Thin Plastic Quad Flat Pack Commercial
CY7C371i−143JC J67 44-Lead Plastic Leaded Chip Carrier
110 CY7C371i−110AC A44 44-Lead Thin Plastic Quad Flat Pack Commercial
CY7C371i−110JC J67 44-Lead Plastic Leaded Chip Carrier
CY7C371i–110AI A44 44-Lead Thin Plastic Quad Flat Pack Industrial
CY7C371i–110JI J67 44-Lead Plastic Leaded Chip Carrier
Switching Waveforms (continued)
Asynchronous Rese t
INPUT
tRO
REGISTERED
OUTPUT
CLOCK
tRR
tRW
Asynchronous Prese t
INPUT
tPO
REGISTERED
OUTPUT
CLOCK
tPR
tPW
Output Enable/Disable
INPUT
tER
OUTPUTS
tEA
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 10 of 12
83 CY7C371i−83AC A44 44-Lead Thin Plastic Quad Flat Pack Commercial
CY7C371i−83JC J67 44-Lead Plastic Leaded Chip Carrier
CY7C371i−83AI A44 44-Lead Thin Plastic Quad Flat Pack Industrial
CY7C371i−83JI J67 44-Lead Plastic Leaded Chip Carrier
CY7C371iL−83AC A44 44-Lead Thin Plastic Quad Flat Pack Commercial
CY7C371iL−83JC J67 44-Lead Plastic Leaded Chip Carrier
CY7C371iL−83AI A44 44-Lead Thin Plastic Quad Flat Pack Industrial
CY7C371iL−83JI J67 44-Lead Plastic Leaded Chip Carrier
66 CY7C371i−66AC A44 44-Lead Thin Plastic Quad Flat Pack Commercial
CY7C371i−66JC J67 44-Lead Plastic Leaded Chip Carrier
CY7C371i−66AI A44 44-Lead Thin Plastic Quad Flat Pack Industrial
CY7C371i−66JI J67 44-Lead Plastic Leaded Chip Carrier
CY7C371iL−66AC A44 44-Lead Thin Plastic Quad Flat Pack Commercial
CY7C371iL−66JC J67 44-Lead Plastic Leaded Chip Carrier
CY7C371iL−66AI A44 44-Lead Thin Plastic Quad Flat Pack Industrial
CY7C371iL−66JI J67 44-Lead Plastic Leaded Chip Carrier
Ordering Information (continued)
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
Package Diagrams
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-B
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circ uitry other than cir cuitry embodied i n a Cypress Semi conductor product. Nor does it convey or imply any l icense under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor product s in life-support syste ms application implies th at th e manu fac turer assu mes all risk of such use and in doing so ind emnifie s Cypress Semicondu ctor ag ainst all charges.
FLASH370, FLASH370i, ISR, UltraLogic, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are trademarks of their respective hol ders.
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
USE ULTRA37000™ FOR
ALL NEW DESIGNS CY7C371i
Document #: 38-03032 Rev. *A Page 12 of 12
Document History Page
Document Title: CY7C371i UltraLogic™ 32-Macrocell Fla sh CPLD
Document Number: 38-03032
REV. ECN NO. Issue Date Orig. of
Change Description o f Change
** 106377 06/18/01 SZV Changed from Spec #: 38-00497 to 38-03032
*A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”
