DM74LS573WMX - Fairchild Semiconductor

October 1988

Revised March 2000

DM74LS573 Octal D-Type Latch with 3-STATE Outputs

DM74LS573

Octal D-Type Latch with 3-STATE Outputs

General Descript ion

The DM74LS573 is a high speed octal latch with buffered

common Latch Enable (LE) and buffered common Output

Enable (OE) inputs.

This device is functionally identical to the DM74LS373, but

has different pinouts.

Features

■Inputs and outputs on op posite sides of package allow-

ing easy interface with microprocessors

■Useful as input or output port for microprocessors

■Functionally identical to DM74LS373

■Input clamp diodes limit high speed termination effects

■Fully TTL and CMOS compatible

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the orderin g c ode.

Logic Symbol

VCC = Pin 20

GND = Pin 10

Connection Diagram

Pin Descriptions Function Tables

L = LOW State

H = HIGH State

X = Don't Care

Z = High Imp edance St at e

QO = Previou s C ondition of O

Order Number Package Number Package Description

DM74LS573WM M20B 20-Lead Small Outline Int egrated Circui t (SOIC), JE DEC MS-013, 0.300 Wide

DM74LS573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

D0–D7 Data Inputs

LE Latch Enable Input (Active HIGH)

OE 3-STATE Output Enable Input (Active LOW)

O0–O7 3-STATE Latch Outputs

Output Latch DOutput

Enable Enable O

LHHH

LHLL

LLXQ

HXXZ

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DM74LS573

Absolute Maximum Ratings(No te 1) Note 1: The “A bsolute Maxim um Ratin gs” are those valu es beyon d which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not gua rant eed at the absolute maximum ratin gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typic als are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Supply Voltage 7V

Input Voltag e 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Input Current −2.6 mA

IOL LOW Level Output Current 24 mA

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, I OH = Max, 2.7 3.4 V

Output Voltage VIL = Max

VOL LOW Level VCC = Min, IOL = Max, 0.35 0.5

Output Voltage VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 1 mA

IIH HIGH Level Input Curre nt VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOS Short Circuit VCC = Max −30 −130 mA

Output Current (Note 3)

ICC Supply Current VCC = Max 50 mA

IOZH 3-STATE Output VCC = VCCH 20 µA

OFF Current HIGH VOZH = 2.7V

IOZL 3-STATE Output VCC = VCCH −20 µA

OFF Current LOW VOZL = 0.4V

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DM74LS573

Switching Characteristics

at VCC = 5V and TA = 25°CRL = 2 kΩ,

Symbol Parameter CL = 50 pF Units

Min Max

tPLH Propagation Delay 27 ns

tPHL Data to Q 18

tPLH Propagation Delay 36 ns

tPHL LE to Q 25

tPZH 3-STATE Enable Time 20 ns

tPZL OE to Q 25

tPHZ 3-STATE Enable Time 20 ns

tPLZ OE to Q 25

tS(H) Setup Time (HIGH/LOW) 3 ns

tS(L) Data to LE 7

tH(H) Hold Time (HIGH/LOW) 10 ns

tH(L) Data to LE 10

tW(H) Pulse Width (HIGH) 15 ns

Data to LE

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DM74LS573

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

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DM74LS573 Octal D-Type Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Packag e Num be r N20A

Fairchild does not assume any responsibility for use of any circu itry descr ibed, no circu it patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.