General Description
The MAX9209/MAX9213 serialize 21 bits of LVTTL/
LVCMOS parallel input data to three LVDS outputs. A
parallel rate clock on a fourth LVDS output provides
timing for deserialization.
The MAX9209/MAX9213 feature programmable DC bal-
ance, which allows isolation between the serializer and
deserializer using AC-coupling. The DC balance circuits
on each channel code the data, limiting the imbalance
of transmitted ones and zeros to a defined range. The
companion MAX9210/MAX9214 deserializers decode
the data. When DC balance is not programmed, the
serializers are compatible with non-DC-balanced, 21-bit
serializers such as the DS90CR215 and DS90CR217.
Two frequency ranges and two DC-balance default
conditions are available for maximum replacement flexi-
bility and compatibility with existing non-DC-balanced
serializers.
The MAX9209/MAX9213 are available in TSSOP and
space-saving thin QFN packages.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Features
♦Programmable DC-Balanced or Non-DC-Balanced
Operation
♦DC Balance Allows AC-Coupling for Ground-Shift
Tolerance
♦As Low as 8MHz Operation
♦Pin Compatible with DS90CR215 and DS90CR217
in Non-DC-Balanced Mode
♦Integrated 110Ω(DC-Balanced) and 410Ω(Non-
DC-Balanced) Output Resistors
♦5V Tolerant LVTTL/LVCMOS Data Inputs
♦PLL Requires No External Components
♦Up to 1.785Gbps Throughput
♦LVDS Outputs Meet IEC 61000-4-2 and ISO 10605
Requirements
♦LVDS Outputs Conform to ANSI TIA/EIA-644
LVDS Standard
♦Low-Profile 48-Lead TSSOP and Space-Saving
QFN Packages
♦-40°C to +85°C Operating Temperature Range
♦+3.3V Supply
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2828; Rev 4; 10/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
*Future product—contact factory for availability.
**EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX9209ETM* -40°C to +85°C 48 Thin QFN-EP**
MAX9209EUM -40°C to +85°C 48 TSSOP
MAX9209GUM -40°C to +105°C 48 TSSOP
MAX9213ETM -40°C to +85°C 48 Thin QFN-EP**
MAX9213EUM -40°C to +85°C 48 TSSOP
Pin Configurations appear at end of data sheet.
TxIN 0 - 20 21
TIMING
CONTROL PARALLEL-TO-
SERIAL
CONVERTER
AND
DC-BALANCE
LOGIC
CLOCK
GENERATOR
PLL
7X OR 9X
LVDS DRIVER 0
LVDS DRIVER 1
LVDS DRIVER 2
LVDS CLK
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxCLK OUT+
TxCLK OUT-
DCB/NC
TxCLK IN
MAX9209
MAX9213
Functional Diagram
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC
= +3.3V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND...........................................................-0.5V to +4.0V
LVDS Outputs (TxOUT_, TxCLK OUT_) to GND ...-0.5V to +4.0V
5V Tolerant LVTTL/LVCMOS Inputs
(TxIN_, TxCLK IN, PWRDWN) to GND ..............-0.5V to +6.0V
(DCB/NC) to GND ......................................-0.5V to (VCC + 0.5V)
LVDS Outputs (TxOUT_, TxCLK OUT_)
Short to GND and Differential Short .......................Continuous
Continuous Power Dissipation (TA= +70°C)
48-Pin TSSOP (derate 16mW/°C above +70°C) ....... 1282mW
48-Lead QFN (derate 26.3mW/°C above +70°C) ......2105mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
ESD Protection
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND..............................................................±2kV
IEC 61000-4-2 (RD= 330Ω, CS= 150pF)
Contact Discharge (TxOUT_, TxCLK OUT_) to GND ....±8kV
Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND ..±15kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (TxOUT_, TxCLK OUT_) to GND ....±8kV
Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND ..±25kV
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (TxIN_, TxCLK IN, PWRDWN, DCB/NC)
TxIN_, TxCLK IN, PWRDWN 2.0 5.5
High-Level Input Voltage VIH DCB/NC 2.0 VCC +
0.3
V
Low-Level Input Voltage VIL -0.3 +0.8 V
Input Current IIN V
IN
= hi g h or l ow , P WRDWN = hi g h or l ow -20 +20 µA
Input Clamp Voltage VCL ICL = -18mA -0.9 -1.5 V
LVDS OUTPUTS (TxOUT_, TxCLK OUT)
Differential Output Voltage VOD Figure 1 250 350 450 mV
Change in VOD Between
Complementary Output States ΔVOD Figure 1 2 25 mV
Output Offset Voltage VOS Figure 1 1.125 1.25 1.375 V
Change in VOS Between
Complementary Output States ΔVOS Figure 1 10 30 mV
VOUT+ or VOUT- = 0V or VCC,
non-DC-balanced mode -10 ±5.7 +10
Output Short-Circuit Current IOS VOUT+ or VOUT- = 0V or VCC,
DC-balanced mode -15 ±8.2 +15
mA
VOD = 0V, non-DC-balanced mode
(Note 3) 5.7 10
Magnitude of Differential Output
Short-Circuit Current IOSD
VOD = 0V, DC-balanced mode (Note 3) 8.2 15
mA
78 110 147
DC-balanced mode -40°C to +105°C 78 110 150
292 410 547
Differential Output Resistance RONon-DC-balanced
mode -40°C to +105°C 292 410 564
Ω
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High-Impedance Current IOZ
PWRDWN = low or VCC = 0V,
VOUT+ = 0V or 3.6V, VOUT- = 0V or 3.6V -0.5 ±0.1 +0.5 µA
8MHz MAX9209 40 54
16MHz MAX9209 48 68
34MHz MAX9209 71 90
16MHz MAX9213 46 64
34MHz MAX9213 59 87
DC-balanced mode,
worst-case pattern,
CL = 5pF, Figure 2
66MHz MAX9213 94 108
10MHz MAX9209 30 39
20MHz MAX9209 37 53
33MHz MAX9209 49 70
40MHz MAX9209 56 75
20MHz MAX9213 36 49
33MHz MAX9213 45 62
40MHz MAX9213 49 70
66MHz MAX9213 68 89
Worst-Case Supply Current ICCW
Non-DC-balanced
mode, worst-case
pattern, CL = 5pF,
Figure 2
85MHz MAX9213 83 100
mA
Power-Down Supply Current ICCZ PWRDWN = low 17 50 µA
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC
= +3.3V, TA= +25°C.) (Notes 1, 2)
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values
are at VCC = +3.3V, TA= +25°C.) (Notes 4, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9209 150 280 400
LVDS Low-to-High Transition
Time LLHT Figure 3 MAX9213 150 260 350 ps
MAX9209 150 280 400
LVDS High-to-Low Transition
Time LHLT Figure 3 MAX9213 150 260 350 ps
TxCLK IN Transition Time TCIT Figure 4 4 ns
10MHz MAX9209 N/7 x TCIP
- 0.25 N/7 x TCIP N/7 x TCIP
+ 0.25
20MHz MAX9209 N/7 x TCIP
- 0.15 N/7 x TCIP N/7 x TCIP
+ 0.15
40MHz MAX9209 N/7 x TCIP
- 0.1 N/7 x TCIP N/7 x TCIP
+ 0.1
20MHz MAX9213 N/7 x TCIP
- 0.25 N/7 x TCIP N/7 x TCIP
+ 0.25
40MHz MAX9213 N/7 x TCIP
- 0.15 N/7 x TCIP N/7 x TCIP
+ 0.15
N = 0, 1, 2, 3,
4, 5, 6
non-DC-
balanced mode,
Figure 5 (Note 6)
85MHz MAX9213 N/7 x TCIP
- 0.1 N/7 x TCIP N/7 x TCIP
+ 0.1
8MHz MAX9209 N/9 x TCIP
- 0.25 N/9 x TCIP N/9 x TCIP
+ 0.25
16MHz MAX9209 N/9 x TCIP
- 0.15 N/9 x TCIP N/9 x TCIP
+ 0.15
34MHz MAX9209 N/9 x TCIP
- 0.1 N/9 x TCIP N/9 x TCIP
+ 0.1
16MHz MAX9213 N/9 x TCIP
- 0.25 N/9 x TCIP N/9 x TCIP
+ 0.25
34MHz MAX9213 N/9 x TCIP
- 0.15 N/9 x TCIP N/9 x TCIP
+ 0.15
Output Pulse Position TPPosN
N = 0, 1, 2, 3,
4, 5, 6, 7, 8
DC-balanced
mode, Figure 6
(Note 6)
66MHz MAX9213 N/9 x TCIP
- 0.1 N/9 x TCIP N/9 x TCIP
+ 0.1
ns
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
_______________________________________________________________________________________ 5
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
MAX9209 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
40302010
40
60
80
100
20
050
WORST-CASE
PATTERN
27 - 1 PRBS
MAX9209
DC-BALANCED MODE
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
MAX9209 toc02
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
5040302010
40
60
80
100
20
060
WORST-CASE
PATTERN
27 - 1 PRBS
MAX9209
NON-DC-BALANCED MODE
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY
MAX9209 toc03
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
75604530
40
60
80
100
120
20
15 90
WORST-CASE
PATTERN
27 - 1 PRBS
MAX9213
NON-DC-BALANCED MODE
Typical Operating Characteristics
(VCC = +3.3V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, TA= +25°C, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, DCB/NC = high or low, unless otherwise noted. Typical values
are at VCC = +3.3V, TA= +25°C.) (Notes 4, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TxCLK IN High Time TCIH Figure 7 0.3 x TCIP 0.7 x TC IP ns
TxCLK IN Low Time TCIL Figure 7 0.3 x TCIP 0.7 x TC IP ns
TxIN to TxCLK IN Setup TSTC Figure 7 2.2 ns
TxIN to TxCLK IN Hold THTC Figure 7 0 ns
Non-DC-balanced mode, Figure 8 3.5 4.5 6.0
TxCLK IN to TxCLK OUT Delay TCCD DC-balanced mode, Figure 8 4.7 5.9 7.2 ns
Serializer Phase-Locked Loop Set TPLLS Figure 9 32800 x
TCIP ns
Serializer Power-Down Delay TPDD Figure 10 14 50 ns
TxCLK IN Cycle-to-Cycle Jitter
(Input Clock Requirement) TJIT 2ns
Magnitude of Differential Output
Voltage VOD 595Mbps data rate, worst-case
pattern 250 mV
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VOD, ΔVOD, and ΔVOS.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3: Guaranteed by design.
Note 4: TCIP is the period of TxCLK IN.
Note 5: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 6: Pulse position TPPosN is characterized using 27- 1 PRBS data.
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
6 _______________________________________________________________________________________
MAX9213
EYE DIAGRAM—DC-BALANCED MODE
MAX9209 TOC08
100mV/div
300ps/div
0V
DIFFERENTIAL
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
2m OF CAT-5
UTP CABLE
27 - 1 PRBS PATTERN
100Ω TERMINATION
ALL-CHANNELS
SWITCHING
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE
MAX9209 TOC07
100mV/div
300ps/div
TxCLK IN = 85MHz
DC-COUPLED
0V
DIFFERENTIAL
10m OF CAT-5
UTP CABLE
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
MAX9213
EYE DIAGRAM—DC-BALANCED MODE
MAX9209 TOC09
100mV/div
300ps/div
0V
DIFFERENTIAL
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
5m OF CAT-5
UTP CABLE
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
MAX9213
EYE DIAGRAM—DC-BALANCED MODE
MAX9209 TOC10
100mV/div
300ps/div
0V
DIFFERENTIAL
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
10m OF CAT-5
UTP CABLE
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
604530
40
60
80
100
120
20
15 75
WORST-CASE
PATTERN
27 - 1 PRBS
MAX9213
DC-BALANCED MODE
MAX9209 toc04
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE
MAX9209 TOC05
100mV/div
300ps/div
TxCLK IN = 85MHz
DC-COUPLED
27 - 1 PRBS PATTERN
100Ω TERMINATION
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
2m OF CAT-5
UTP CABLE
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE
MAX9209 TOC06
100mV/div
300ps/div
TxCLK IN = 85MHz
DC-COUPLED
27 - 1 PRBS PATTERN
100Ω TERMINATION
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
5m OF CAT-5
UTP CABLE
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL= 100Ω±1%, CL= 5pF, PWRDWN = high, TA= +25°C, unless otherwise noted.)
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
_______________________________________________________________________________________ 7
Pin Description
PIN
TSSOP TQFN NAME FUNCTION
1, 3, 4, 44, 45, 47, 48, 38, 39, 41, 42, 43, 45, 46 TxIN0–TxIN6 5V Tolerant LVTTL/LVCMOS Channel 0 Data Inputs.
Internally pulled down to GND.
2, 8, 14, 21 2, 8, 15, 44 VCC Digital Supply Voltage
5, 11, 17, 24, 46 5, 11, 18, 40, 47 GND Ground
6, 7, 9, 10, 12, 13, 15 1, 3, 4, 6, 7, 9, 48 TxIN7–TxIN13 5V Tolerant LVTTL/LVCMOS Channel 1 Data Inputs.
Internally pulled down to GND.
16, 18, 19, 20, 22, 23, 25 10, 12, 13, 14, 16, 17, 19 TxIN14–TxIN20 5V Tolerant LVTTL/LVCMOS Channel 2 Data Inputs.
Internally pulled down to GND.
26 20 TxCLK IN 5V Tolerant LVTTL/LVCMOS Parallel Rate Clock Input.
Internally pulled down to GND.
27 21 PWRDWN
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally
pulled down to GND. Outputs are high impedance when
PWRDWN = low or open.
28, 30 22, 24 PLL GND PLL Ground
29 23 PLL VCC PLL Supply Voltage
31, 36, 42 25, 30, 36 LVDS GND LVDS Ground
32 26 TxCLK OUT+ Noninverting LVDS Parallel Rate Clock Output
33 27 TxCLK OUT- Inverting LVDS Parallel Rate Clock Output
34 28 TxOUT2+ Noninverting Channel 2 LVDS Serial Data Output
35 29 TxOUT2- Inverting Channel 2 LVDS Serial Data Output
37 31 LVDS VCC LVDS Supply Voltage
38 32 TxOUT1+ Noninverting Channel 1 LVDS Serial Data Output
39 33 TxOUT1- Inverting Channel 1 LVDS Serial Data Output
40 34 TxOUT0+ Noninverting Channel 0 LVDS Serial Data Output
41 35 TxOUT0- Inverting Channel 0 LVDS Serial Data Output
43 37 DCB/NC
LVTTL/LVCMOS DC-Balance Programming Input:
MAX9209: pulled up to VCC
MAX9213: pulled up to VCC
See Table 1.
— EP EP Exposed Paddle. Solder to ground.
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
8 _______________________________________________________________________________________
VOS(-) VOS(+) VOS(-)
VOD(+)
VOD(-) VOD(-)
TxOUT_- OR TxCLK OUT-
TxOUT_+ OR TxCLK OUT+
ΔVOS = |VOS(+) - VOS(-)|
(TxOUT_+) - (TxOUT_-) OR
(TxCLK OUT+) - (TxCLK OUT-)
ΔVOD = |VOD(+) - VOD(-)|
0V
TCIP
TxCLK IN
ODD TxIN
EVEN TxIN
TxOUT_+ OR
TxCLK OUT+
CL
CL
RL
TxOUT_- OR
TxCLK OUT-
80% 80%
20% 20%
LLHT LHLT
(TxOUT_+) - (TxOUT_-) OR
(TxCLK OUT+) - (TxCLK OUT-)
Figure 2. Worst-Case Test Pattern
Figure 3. LVDS Output Load and Transition Times
Figure 1. LVDS Output DC Parameters
90%
10%
90%
10%
VIH
TxCLK IN VIL
TCITTCIT
Figure 4. Clock Transition Time Waveform
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
_______________________________________________________________________________________ 9
Detailed Description
The MAX9209 operates at a parallel clock frequency of
8MHz to 34MHz in DC-balanced mode and 10MHz to
40MHz in non-DC-balanced mode. The MAX9213 oper-
ates at a parallel clock frequency of 16MHz to 66MHz
in DC-balanced mode and 20MHz to 85MHz in non-
DC-balanced mode.
DC-balanced or non-DC-balanced operation is con-
trolled by the DCB/NC pin (see Table 1). In non-DC-
balanced mode, each channel serializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are serialized every clock cycle (7 data bits + 2 DC-bal-
ance bits). The highest data rate in DC-balanced mode
for the MAX9213 is 66MHz x 9 = 594Mbps. In non-DC-
balanced mode, the maximum data rate is 85MHz x 7 =
595Mbps. A bit time is 1 divided by the data rate, for
example, 1 / 595Mbps = 1.68ns.
DC Balance
Through data coding, the DC-balance circuits limit the
imbalance of ones and zeros transmitted on each chan-
nel. If +1 is assigned to each binary one transmitted
and -1 is assigned to each binary zero transmitted, the
variation in the running sum of assigned values is
called the digital sum variation (DSV). The maximum
DSV for the MAX9209/MAX9213 data channels is 10. At
most, 10 more zeros than ones, or 10 more ones than
zeros, are transmitted. The maximum DSV for the clock
channel is 5. Limiting the DSV and choosing the correct
coupling capacitors maintain differential signal amplitude
and reduce jitter due to droop on AC-coupled links.
TxIN15 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
TxIN8 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7
TxIN1 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0
CYCLE N - 1 CYCLE N
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TxCLK OUT
(DIFFERENTIAL)
TxOUT2
(SINGLE ENDED)
TxOUT1
(SINGLE ENDED)
TxOUT0
(SINGLE ENDED)
Figure 5. Non-DC-Balanced Mode LVDS Output Pulse Position Measurement
DEVICE DCB/NC OPERATING
MODE
OPERATING
FREQUENCY
(MHz)
High or open DC balanced 8 to 34
MAX9209 Low Non-DC
balanced 10 to 40
High or open DC balanced 16 to 66
MAX9213 Low Non-DC
balanced 20 to 85
Table 1. DC-Balance Programming
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
10 ______________________________________________________________________________________
DCA2 DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
DCA1 DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7
DCA0 DCB0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0
CYCLE N - 1 CYCLE N
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TxCLK OUT
(DIFFERENTIAL)
TxOUT2
(SINGLE ENDED)
TxOUT1
(SINGLE ENDED)
TxOUT0
(SINGLE ENDED)
DCA2 DCB2
DCA1 DCB1
DCA0 DCB0
TPPos7
TPPos8
TCIP
TCIH TCIL
THTCTSTC
SETUP 1.5V1.5V HOLD
2.0V 1.5V 0.8V
TxIN 0:20
TxCLK IN
TxCLK OUT+
TxCLK IN
TCCD
TxCLK OUT-
1.5V
DIFFERENTIAL 0
Figure 6. DC-Balanced Mode LVDS Output Pulse Position Measurement
Figure 7. Setup and Hold, High and Low Times
Figure 8. Clock-In to Clock-Out Delay
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________ 11
To obtain DC balance on the data channels, the paral-
lel input data is inverted or not inverted, depending on
the sign of the digital sum at the word boundary. Two
complementary bits are appended to each group of 7
parallel input data bits to indicate to the MAX9210/
MAX9214 deserializers whether the data bits are invert-
ed (Figure 11). The deserializer restores the original
state of the parallel data. The LVDS clock signal alter-
nates duty cycles of 4/9 and 5/9, which maintains DC
balance. Figure 12 shows the non-DC-balanced mode
inputs mapped to LVDS outputs.
DCA0
DCB1DCA1
DCB2DCA2
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN2TxIN3TxIN4DCA0 TxIN5TxIN6DCB0
TxIN9TxIN10TxIN11DCA1 TxIN12TxIN13DCB1
TxIN16TxIN17TxIN18DCA2 TxIN19TxIN20DCB2
TxIN0TxIN1
TxIN7TxIN8
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
DCB0
TxCLK OUT-
TxOUT1
TxOUT0
TxOUT2
TxIN1
TxIN8
TxIN15
TxIN0
TxIN7
TxIN14
TxCLK OUT+
Figure 11. DC-Balanced Mode Inputs Mapped to LVDS Outputs
2.0V
3.0V
HIGH-Z DIFFERENTIAL 0
3.6V
VOD = 0
VCC
TxOUT_, TxCLK OUT
TxCLK IN
PWRDWN
TPPLS
Figure 9. PLL Set Time
TxOUT_, TxCLK OUT
TxCLK IN
PWRDWN
HIGH-Z
0.8V
TPDD
Figure 10. Power-Down Delay
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
12 ______________________________________________________________________________________
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode volt-
age range by AC-coupling. AC-coupling increases the
common-mode voltage range of an LVDS receiver to
nearly the voltage rating of the capacitor. The typical
LVDS driver output is 350mV centered on an offset volt-
age of 1.25V, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately ±1V common-
mode difference between the driver and receiver on a
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V -
0V = 1.075V). Figure 13 shows the DC-coupled link,
non-DC-balanced mode.
TxIN1
TxIN7TxIN8
TxIN14TxIN15
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN0TxIN1TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN7TxIN8TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN0TxIN1
TxIN7TxIN8
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxCLK OUT+
TxIN0
TxCLK OUT-
TxOUT1
TxOUT0
TxOUT2
Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
1:7
77
RT =
100Ω
RT =
100Ω
RT =
100Ω
RT =
100Ω
7:1
7:1
1:7
77
7:1 1:7
77
PLL PLL
MAX9209
MAX9213
MAX9210
MAX9214
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
RO
RO
RO
RO
Figure 13. DC-Coupled Link, Non-DC-Balanced Mode
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________ 13
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than ±1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the dif-
ferential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
5V Tolerant Inputs
All signal and control inputs except DCB/NC are 5V tol-
erant and are internally pulled down to GND. The
DCB/NC pin has a pullup on the MAX9209/MAX9213.
DCB/NC Pin Default Conditions
The MAX9209/MAX9213 have programmable DC bal-
ance/non-DC balance. See Table 1 for DCB/NC default
settings and operating modes.
(7 + 2):1 1:(9 - 2)
77
RT =
100Ω
RT =
100Ω
RT =
100Ω
RT =
100Ω
(7 + 2):1 1:(9 - 2)
77
(7 + 2):1 1:(9 - 2)
77
PLL PLL
MAX9209
MAX9213
MAX9210
MAX9214
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT
SERIALIZER INSTEAD OF DESERIALIZER.
RO
RO
RO
RO
Figure 14. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
14 ______________________________________________________________________________________
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (RT), the LVDS driver
output resistor (RO), and the series AC-coupling capac-
itors (C). The RC time constant for two equal-value
series capacitors is (C x (RT + RO)) / 2 (Figure 14). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO)) / 4 (Figure 15).
RTis required to match the transmission line imped-
ance (usually 100Ω) and ROis determined by the LVDS
driver design, with a minimum value of 78Ω(see the DC
Electrical Characteristics table). This leaves the capaci-
tor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = -(2 x tBx DSV) / (ln (1 - D) x (RT+ RO)) (Eq 1)
where:
C = AC-coupling capacitor (F)
tB= bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
RT= termination resistor (Ω)
(7 + 2):1 1:(9 - 2)
77
RT =
100Ω
RT =
100Ω
RT =
100Ω
RT =
100Ω
(7 + 2):1 1:(9 - 2)
77
(7 + 2):1 1:(9 - 2)
77
PLL PLL
MAX9209
MAX9213
MAX9210
MAX9214
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
RO
RO
RO
RO
Figure 15. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________ 15
RO= output resistance (Ω)
Equation 1 is for two series capacitors (Figure 14). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 15).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = -(2 x tBx DSV) / (ln (1 - D) x (RT+ RO))
C = -(2 x 13.9ns x 10) / (ln (1 - .02) x (100Ω+ 78Ω))
C = 0.0773µF
Jitter due to droop is proportional to the droop and
transition time:
tJ= tTx D (Eq 2)
where:
tJ= jitter (s)
tT= transition time (s) (0% to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tJ= 1ns x 0.02
tJ= 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 15) is:
C = -(4 x tBx DSV) / (ln (1 - D) x (RT+ RO)) (Eq 3)
Integrated Termination
The MAX9209/MAX9213 have an integrated output ter-
mination resistor across each of the four LVDS outputs.
These resistors damp reflections from induced noise and
mismatches between the transmission line impedance
and termination resistor at the deserializer input. In DC-
balanced mode, the differential output resistance is part
of the RC time constant. In non-DC-balanced mode, the
output termination is increased to 410Ω(typ) to reduce
power. In power-down mode (PWRDWN = low) or when
the power supply is off, the output resistor is switched
out and the LVDS outputs are high impedance.
PWRDWN
and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated output termination resistors, puts the LVDS
outputs in high impedance, and reduces supply current
to 50µA or less. Driving PWRDWN high starts the PLL
lock to the input clock and switches in the output termi-
nation resistors. The LVDS outputs are not driven until
the PLL locks. The differential output resistance pulls
the outputs together and the LVDS outputs are high
impedance to ground. If the power supply is turned off,
the output resistors are switched out and the LVDS out-
puts are high impedance.
PLL Lock Time
The PLL lock time is set by an internal counter. The maxi-
mum time to lock is 32,800 clock periods. Power and
clock should be stable to meet the lock-time specifica-
tion. When the PLL is locking, the LVDS outputs are not
active and have a differential output resistance of RO.
Power-Supply Bypassing
There are separate power domains for LVDS, PLL, and
digital circuits. Bypass each LVDS VCC, PLL VCC, and
VCC pin with high-frequency surface-mount ceramic
0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smallest value capacitor
closest to the supply pin.
LVDS Outputs
The LVDS outputs are current sources. The voltage
swing is proportional to the load impedance. The out-
puts are rated for a differential load of 100Ω±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS input and LVDS output sig-
nals separated to prevent crosstalk. A four-layer PCB
with separate layers for power, ground, LVDS outputs,
and digital signals is recommended.
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
16 ______________________________________________________________________________________
ESD Protection
The MAX9209/MAX9213 ESD tolerance is rated for IEC
61000-4-2, Human Body Model and ISO 10605 stan-
dards. IEC 61000-4-2 and ISO 10605 specify ESD toler-
ance for electronic systems. The IEC 61000-4-2
discharge components are CS= 150pF and RD= 330Ω
(Figure 16). For IEC 61000-4-2, the LVDS outputs are
rated for ±8kV contact and ±15kV air discharge. The
Human Body Model discharge components are CS=
100pF and RD= 1.5kΩ(Figure 17). For the Human Body
Model, all pins are rated for ±2kV contact discharge. The
ISO 10605 discharge components are CS= 330pF and
RD= 2kΩ(Figure 18). For ISO 10605, the LVDS outputs
are rated for ±8kV contact and ±25kV air discharge.
CS
150pF STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50Ω TO 100Ω
RD
330Ω
Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MΩ
RD
1.5kΩ
CS
100pF
Figure 17. Human Body ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50Ω TO 100Ω
RD
2kΩ
CS
330pF
Figure 18. ISO 10605 Contact Discharge ESD Test Circuit
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________ 17
LVDS GND
TxOUT0-
TxOUT1-
TxOUT1+
TxOUT2-
TxOUT2+
TxCLK OUT-
LVDS GND
TxCLK OUT+
LVDS VCC
LVDS GND
TxOUT0+
TxIN9
TxIN10
GND
TxIN11
TxIN12
VCC
TxIN13
TxIN15
TxIN14
VCC
TxIN8 1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TxIN19
GND
TxIN20
PWRDWN
PLL GND
PLL VCC
PLL GND
TxIN18
VCC
TxIN17
TxIN16
GND
TxIN6
TxIN5
VCC
TxIN4
TxIN3
TxIN2
GND
TxIN1
DCB/NC
TxIN0
TxIN7
THIN QFN
MAX9209
MAX9213
TxCLK IN
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
TxIN3
TxIN2
GND
TxIN1TxIN6
TxIN5
VCC
TxIN4
TOP VIEW
MAX9209
MAX9213
TxIN0
DCB/NC
LVDS GND
TxOUT0-VCC
TxIN8
TxIN7
GND
TxOUT0+
TxOUT1-TxIN10
TxIN9
38
37
36
35
34
33
32
31
30
29
TxOUT1+
LVDS VCC
LVDS GND
TxOUT2-
TxOUT2+
TxCLK OUT-
TxCLK OUT+
LVDS GND
PLL GND
PLL VCC
11
12
13
14
15
16
17
18
19
VCC
TxIN12
TxIN11
GND
TxIN15
GND
TxIN14
TxIN13
TxIN17
TxIN16
20
21
TxIN18
VCC
22
28
27
PLL GND
PWRDWN
TSSOP
23
GND
TxIN19
24
26
25
TxCLK IN
TxIN20
GND EXPOSED PAD
Pin Configurations
Chip Information
MAX9209 TRANSISTOR COUNT: 9458
MAX9213 TRANSISTOR COUNT: 9458
PROCESS: CMOS
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
18 ______________________________________________________________________________________
48L TSSOP.EPS
NOTES:
1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE.
3. CONTROLLING DIMENSION: MILLIMETERS.
4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED (48L), EE (56L).
5. "N" REFERS TO NUMBER OF LEADS.
6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL
PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE
FROM (-C-) IN THE DIRECTION INDICATED.
7. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
8. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
SECTION C-C
DETAIL A
N
SIDE VIEW
TOP VIEW
C
L
1
HE
e
D
b
A
A2 A1
BOTTOM VIEW
c
0.25
(
)b1
b
c1
BASE METAL
c
END VIEW
SEATING
PLANE
SEE DETAIL A
PARTING
LINE
WITH PLATING
L
PACKAGE OUTLINE,
21-0155 1
1
C
48 & 56L TSSOP, 6.1mm BODY
AAA
23
A
MARKING
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________ 19
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
32, 44, 48L QFN.EPS
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
20 ______________________________________________________________________________________
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
3 6/07 — 1–5, 9, 14, 15, 18,
19, 20
4 10/07 Removed all references to MAX9211 and MAX9215. 1–20
Revision History
