UDA1361TS/N1,112 - NXP

DATA SH EET

Product specification

Supersedes data of 2001 Jan 17 2002 Nov 25

INTEGRATED CIRCUITS

UDA1361TS

96 kHz sampling 24-bit stereo audio

ADC

2002 Nov 25 2

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio

ADC UDA1361TS

FEATURES

General

•Low power cons umption

•256, 384, 512 and 768f s system clock

•2.4 to 3.6 V power supply

•Supports sampling frequency of 5 to 110 kHz

•Small package size (SSOP16)

•Integrated high-pass filter to cancel DC offset

•Power-down mode

•Supports 2 V (RMS) input signals

•Easy application

•Master or slave operation.

Multiple format output interface

•I2S-bus and MSB-justified form at compatible

•Up to 24 significant bits serial output.

Advanced audio configuration

•Stereo single-end ed input configuration

•High linearity, dyn a m ic ra ng e an d l ow di sto rtion.

GENERAL DESCRIPTION

The UDA1361TS is a single chip stereo Analog-to-Digital

Converter (ADC) employ ing bitstream conversion

techniques. The low pow er consumption and low voltag e

requirements make the device eminently suitable for use in

low-voltage low -p o we r po rtable digital audio eq uipment

which incorporates recording functions.

The UDA1361TS supports the I2S-bus data format and the

MSB-justified data format with word lengths of up to

24 bits.

ORDERING INFORMATION

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

UDA1361TS SSOP16 plastic shrink small outline pack ag e; 16 leads; body width 4.4 mm SOT36 9-1

2002 Nov 25 3

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA analog supply voltage 2.4 3.0 3.6 V

VDDD digital supply voltage 2.4 3.0 3.6 V

IDDA analog supply current fs=48kHz

operating mode −10.5 −mA

Power-down mode −0.5 −mA

IDDD digital supply current fs=48kHz

operating mode −3.5 −mA

Power-down mode −0.45 −mA

Tamb ambient temperature −40 −+85 °C

Analog

Vi(rms) input voltage (RMS value) at 0 dB(FS) equivalent −1.1 −V

at −1 dB(FS) signal output −1.0 −V

(THD + N)/S total harmonic distortion-plus-noise

to signal ratio fs=48kHz

at −1dB −−88 −83 dB

at −60 dB; A-weighted −−40 −34 dB

fs=96kHz

at −1dB −−85 −80 dB

at −60 dB; A-weighted −−40 −37 dB

S/N signal-to-noise ratio Vi= 0 V; A-weighted

fs=48kHz −100 −dB

fs=96kHz −100 −dB

αcs channel separation −100 −dB

2002 Nov 25 4

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

BLOCK DIAGRAM

handbook, full pagewidth

UDA1361TS

MGT451

VINL ADC

ΣΔ

DIGITAL

INTERFACE DC-CANCELLATION

FILTER

DECIMATION

FILTER CLOCK

CONTROL

VINR ADC

ΣΔ

DATAO 11

BCK 12

6SFOR

7PWON

14 MSSEL

10 VSSD

9VDDD

VSSA

VRP

VRN

Vref

SYSCLK

VDDA

Fig.1 Block diagram.

PINNING

SYMBOL PIN DESCRIPTION

VINL 1 left chan nel input

Vref 2 reference voltage

VINR 3 right channel input

VRN 4 negative reference voltage

VRP 5 positive reference voltage

SFOR 6 data format selection input

PWON 7 power control input

SYSCLK 8 system clock 256, 384, 512 or 768fs

VDDD 9 digital supply voltage

VSSD 10 digital ground

BCK 11 bit clock input/output

WS 12 word select input/output

DATAO 13 data output

MSSEL 14 master/slave select

VSSA 15 analog ground

VDDA 16 analog supply voltage

handbook, halfpage

UDA1361TS

MGT452

VINL

Vref

VINR

VRN

VRP

SFOR

PWON

SYSCLK VDDD

VSSD

BCK

DATAO

MSSEL

VSSA

VDDA

Fig.2 Pin configuration.

2002 Nov 25 5

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

FUNCTIONAL DESCRIPTION

System clock

The UDA1361TS accommodates master and slave

modes. The system devices must provide the system clock

regardless of master or slave mode. In the master mode a

system clock frequency of 256fs is requir ed . In the sl ave

mode a system frequency of 256, 384, 512 or 768fs is

automatically detected ( fo r a s ystem clock of 768fs the

sampling freque ncy must be limited to 55 kHz). The

system clock must be locked in frequency to the digital

interface input signals.

Input level

The overall system gain is prop o rtional to VDDA, or more

accurately the potential difference between the reference

voltages VVRP and VVRN. The −1 dB input level at which

THD + N /S is specified co rresponds to −1dB(FS) digital

output (relative to the full-scale swing). With an input gain

switch, the input level can be calculated as follows:

at 0 dB gain:

at 6 dB gain:

In applications where a 2 V (RMS) input si gnal is used, a

12 kΩ resistor mus t be connected in series with the input

of the ADC. This forms a voltage divider together with the

internal ADC resistor and ensures that only 1 V (RMS)

maximum is input to the IC.

Using this application for a 2 V (RMS) input signal, the gain

switch must be set to 0 dB. When a 1 V (RMS) input signal

is input to the ADC in the same application the gain switch

must be set to 6 dB.

An overview of the maximum input voltage allowed against

the presence of an external resistor and the setting of the

gain switch is given in Table 1. Th e power supply voltag e

is assumed to be 3 V.

Table 1 Application modes using input gain stage

Multiple format output interface

The serial interface provides the following data output

formats in both maste r an d sla ve mod es

(see Figs 3, 4 and 5):

•I2S-bus with data word length of up to 24 bits

•MSB-justified serial format with data word length of up to

24 bits.

The master mode drives pins WS (word selec t; 1fs) an d

BCK (bit clock; 64fs). WS and BCK are received in slave

mode.

Table 2 Master/slave select

Table 3 Select dat a for mat

Decimation filter

The decimation from 64fs is performed in two stages. The

first stage realizes a 4th-order sinx/x characterist ic. This

filter decreases the sample rate by 8.

The second stage, a FIR filter, consists of 3 half-band

filters, each decimating by a factor of 2.

Vi1 dB–()

VVRP VVRN

–

---------------------------------- V (RMS)==

Vi1 dB–()

VVRP VVRN

–

23×

---------------------------------- V (RMS)==

RESISTOR

(12 kΩ)INPUT GAIN

SWITCH

MAXIMUM

INPUT

VOLTAGE

(RMS)

Present 0 dB 2 V

Present 0 dB 1 V

Absent 0 dB 1 V

Absent 6 dB 0.5 V

MSSEL MASTER/SLAVE

SELECT

Lslave mode

H master mode

M (reserved for digital test)

SFOR DATA FORMAT

2S-bus data format

H MSB-justified data format

M (reserved for analog test)

2002 Nov 25 6

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

Table 4 Decimation filter characteristic

DC cancellation filter

A IIR high-pass filter is provide d to remove unwanted

DC components. The filter character istics are given in

Table 5.

Table 5 DC cancellation filter characteristic

Mute

On recovery from Power-down, the seri al data output

DATAO is held LOW until valid data is available from the

decimation filter. This time tracks with the sampling

frequency:

, t = 256 ms when fs=48kHz.

Power-down mode/input voltage control

The PWON pin can control the power savi ng together with

the optional gain switch for 2 or 1 V (RMS) input.

The UDA1361TS supports 2 V (RMS) input using a series

resistor of 12 kΩ. For the definition of the pin se ttings for

1 o r 2 V (RMS) mode, it is assumed th at this resistor is

present as a defa ult co mponent.

Table 6 Power-down/input voltage control

ITEM CONDITION VALUE (dB)

Pass-band rip p l e 0 to 0.45fs±0.01

Pass-band droop 0.45fs−0.2

Stop band >0.55 fs−70

Dynamic range 0 to 0. 45 fs>135

ITEM CONDITION VALUE (dB)

Pass-band rip p l e −none

Pass-band ga in −0

Droop at 0.00045fs−0.031

Attenuation

at DC at 0.00000036fs>40

Dynamic range 0 to 0. 45fs>135

PWON POWER-DOWN OR GAIN

L Power-down mode

M 0 dB gain

H 6 dB gain

t12288

----------------

Serial interface formats

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MGT453

MSB-JUSTIFIED FORMAT

WS LEFT RIGHT

321321

MSB B2 MSBLSB LSB MSB B2B2

≥8≥8

BCK

DATA

WS LEFT RIGHT

321321

MSB B2 MSBLSB LSB MSBB2

≥8≥8

BCK

DATA

INPUT FORMAT I2S-BUS

Fig.3 Serial interface formats.

2002 Nov 25 7

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

LIMITING VALUES

In accordance with the Absolute Max imum Rating System (IEC 60134).

Notes

1. All supply conn ec tions must be made to the s ame power supply.

2. ESD behaviour is te sted in accordance with JEDEC II standard:

a) Human Body Model (HBM); equivalent to discharging a 100 pF capaci tor through a 1.5 kΩ series resistor.

b) Machine Model (MM); equivalent to discharging a 200 pF c apacitor through a 0.75 μH series inductor.

THERMAL CHARACTE RISTICS

DC CHARACTERISTICS

VDDD =V

DDA =3V; T

amb =25°C; all voltages referenced to ground (pins 10 and 15); unles s otherwise specified .

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage note 1 −4.0 V

Txtal(max) maximum crystal temperature −150 °C

Tstg storage temperature −65 +125 °C

Tamb ambient temperature −40 +85 °C

Ves electrostatic handling voltage HBM; note 2 −3000 +3000 V

MM; note 2 −300 +300 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 130 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA analog supply voltage note 1 2.4 3.0 3.6 V

VDDD digital supply voltage note 1 2.4 3.0 3.6 V

IDDA analog supply c urrent fs=48kHz

operating mode −10.5 −mA

Power-down mode −0.5 −mA

fs=96kHz

operating mode −10.5 −mA

Power-down mode −0.5 −mA

IDDD digital su pp ly current fs=48kHz

operating mode −3.5 −mA

Power-down mode −0.45 −mA

fs=96kHz

operating mode −7.0 −mA

Power-down mode −0.65 −mA

2002 Nov 25 8

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

Note

1. All power supply connections mus t b e connected to the same external power supply unit.

Digital input pin (SYSCLK)

VIH HIGH-level input voltage 2.0 −5.5 V

VIL LOW-level input voltage −0.5 −+0.8 V

|ILI|input leakage current −−1μA

Ciinput capacitance −−10 pF

Digital 3-level input pins (PWON, SFOR, MSSEL)

VIH HIGH-level input voltage 0.9VDD −VDD +0.5 V

VIM MIDDLE-level input

voltage 0.4VDD −0.6VDD V

VIL LOW-level input voltage −0.5 −+0.4 V

Digital input/output pins (BCK, WS)

VIH HIGH-level input voltage 2.0 −5.5 V

VIL LOW-level input voltage −0.5 −+0.8 V

|ILI|input leakage current −−1μA

Ciinput capacitance −−10 pF

VOH HIGH-level output voltage IOH =−2 mA 0.85VDDD −−V

VOL LOW-level output voltage IOL =2mA −−0.4 V

Digital output pin (DATAO)

VOH HIGH-level output voltage IOH =−2mA 0.85V

DDD −−V

VOL LOW-level output voltage IOL =2mA −−0.4 V

Analog

Vref reference voltage with respect to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V

Riinput resistance −12 −kΩ

Ciinput capacitance −20 −pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2002 Nov 25 9

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

AC CHARACTERISTICS (ANALOG )

VDDD =V

DDA =3V; f

i= 1 kHz; Tamb =25°C; all voltages referenced to ground (pins 10 and 15); unless otherwise

specified.

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Vi(rms) input voltage (RMS value) at 0 dB(FS) equivalent 1.1 −V

at −1 dB(FS) signal output 1.0 −V

⎪ΔVi⎪unbalance between channe ls <0.1 0.4 dB

(THD + N)/S total harmonic

distortion-plus-noise to signal

ratio

fs=48kHz

at −1dB −88 −83 dB

at −60 dB; A-weighted −40 −34 dB

fs=96kHz

at −1dB −85 −80 dB

at −60 dB; A-weighted −40 −37 dB

S/N signal-to-noise ratio Vi= 0 V; A-weighted

fs=48kHz 100 −dB

fs=96kHz 100 −dB

αcs channel separation 100 −dB

PSRR power supply rejection ratio fripple =1kHz; V

ripple = 30 mV (p-p) 30 −dB

2002 Nov 25 10

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

AC CHARACTERISTICS (DIGITAL)

VDDD =V

DDA = 2.4 to 3.6 V; Tamb =−40 to +85 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise

specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing

Tsys system clock cycle fsys = 256fs35 88 780 ns

fsys = 384fs23 59 520 ns

fsys = 512fs17 44 390 ns

fsys = 768fs17 30 260 ns

tCWL LOW-level system clock pulse width 0.40Tsys −0.60Tsys ns

tCWH HIGH-level system clock pulse width 0.40Tsys −0.60Tsys ns

Serial data timing; see Figs 4 and 5

Tcy(CLK)(bit) bit clock period ; master mode 64fs64fs64fsHz

; slave mode −−64fsHz

tBCKH bit clock H IGH time 50 −−ns

tBCKL bit clock LOW time 50 −−ns

trrise time −−20 ns

tffall time −−20 ns

td(o)(D)(BCK) data output delay time

(from BCK falling edge) −−40 ns

td(o)(D)(WS) d ata output de lay time

(from WS edge) MSB-justified format −−40 ns

th(o)(D) data output hold time 0 −−ns

tr(WS) word select rise time −−20 ns

tf(WS) word select fall time −−20 ns

fWS word select period 111f

td(WS)(BCK) word select delay from BCK master mode −40 −+40 ns

tsu(WS) word select set-up time slave mode 20 −−ns

th(WS) word select hold time slave mode 10 −−ns

cy 1

Tcy

--------

cy 1

Tcy

--------

2002 Nov 25 11

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

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MGT454

td(o)(D)(BCK)

td(WS)(BCK)

Tcy(CLK)(bit)

BCK

DATAO

th(o)(D)

tBCKH

tBCKL

Fig.4 Serial interface master mode timing.

handbook, full pagewidth

MGT455

th(WS) tsu(WS)

td(o)(D)(BCK)

td(o)(D)(WS) th(o)(D)

tBCKL

Tcy(CLK)(bit)

BCK

DATAO

tBCKH

Fig.5 Serial interface slave mode timing.

2002 Nov 25 12

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

APPLICATION INFORMATION

The application information illustrated in Fig.6, is an optimum application environment. Simplification is possible at the

cost of some performan ce degradation.

handbook, full pagewidth

VDDD

X4-1

116

MGU297

UDA1361TS

R12

47 kΩ

1 nF

(63 V)

C11

47 μF

(16 V)

R13

47 kΩ

X4-2

X4-3

VDDD

X2-1 R4

47 kΩ

X2-2

X2-3

VDDD

VDDA

X3-1

47 kΩ

X3-2

X1-1

X1-4

X1-2

X1-3

X1-5

X1-6

X1-7

X1-9

X1-10

X1-8

X3-3

VDDA

R10

47 Ω

SYSCLK

R11

47 Ω

L1 BLM32A07

L2 BLM32A07

1 nF

(63 V) 47 μF

(16 V)

47 μF

(16 V)

47 μF

(16 V)

100 μF

(16 V)

100 μF

(16 V)

47 μF

(16 V)

100 nF

(63 V)

100 nF

(63 V)

47 μF

(16 V)

C10

100 nF

(63 V)

100 nF

(63 V)

C12

220 Ω

1 Ω

Fig.6 Application diagra m.

The value of capacitors C11 and C12 can be reduced. Note that changing their value will change the cut-off frequency determined by the capacitor

value and the12 kΩ input resistance of the ADC.

2002 Nov 25 13

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 1.4

1.2 0.32

0.20 0.25

0.13 5.3

5.1 4.5

4.3 0.65 6.6

6.2 0.65

0.45 0.48

0.18 10

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

0.75

0.45

SOT369-1 MO-152 99-12-27

03-02-19

yHE

detail X

vMA

(A )

0.25

16 9

pin 1 index

0 2.5 5 mm

scale

SOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369

-1

max.

1.5

2002 Nov 25 14

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth acco un t of sold er ing ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method tha t is idea l for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspen sion of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-s yringe dispensing before package placement.

Several methods exist for reflowing; for example,

convection or convection/infrare d heating in a conveyor

type oven. Through put times (preheating, soldering a nd

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatur es range from

215to250°C. The top-surface temperature of the

packages sh ould preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal res ults:

•Use a double-wa ve soldering method comprising a

turbulent wave with high up ward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitc h (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axi s is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footp rint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board .

The footprint must incorporate solder thieves at the

downstream end.

•For packages with leads on four sides, the footprint must

be plac ed at a 45° angle to the transp ort direction of the

printed-circuit board. The footprint must incor porate

solder thieves downstream and at th e side corners.

During placement and before soldering, the package must

be fixed with a droplet of adh esive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one ope ration within 2 to 5 seconds between

270 and 320 °C.

2002 Nov 25 15

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy

from your NXP Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with res pect to time) and body size of th e package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Pac kin g Methods”.

3. These packages are not suitable for wave soldering . On versions with the heatsin k on the bottom side, the solder

cannot pene trat e bet ween the p rinte d-cir cui t boar d and the h eats ink . On ve rsio ns with the h eats ink on th e top sid e,

the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be p lace d at a 45° angle to the solder wave direction.

The package footprint must incorporate so lder thieves down stream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable fo r SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or sma ller than 0.5 mm.

PACKAGE(1) SOLDERING METHOD

WAVE REFLOW(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

HVSON, SMS not suitable(3) suitable

PLCC(4), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(4)(5) suitable

SSOP, TSSOP, VSO not recommended(6) suitable

2002 Nov 25 16

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

DATA SHEET STATUS

Notes

1. Please consult the most recently issued document befor e initiating or completing a design.

2. The product s ta tus of device(s ) described in this do cument may have ch anged since this document was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This document contains data from the objective specification for product

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Prod uc tio n This document contains the product spe cific ation.

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sale of NXP Semiconductors.

Right to make changes ⎯ NXP Semiconductors

reserves the right to make changes to information

published in this doc ument, including without limitation

specifications and product descriptions, at any time and

without notice. This document supersedes and replaces all

information supplied prior to the publication hereof.

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equipment, nor in applications where failure or malfunction

of an NXP Semiconductors product can reasonably be

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accepts no liability for inclusion and/or use of NXP

Semiconductor s pr oducts in such equipme nt or

application s and therefore such inclusion and /or use is at

the customer’s own risk.

Applications ⎯ Applications that are described herein for

any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or

warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of

their applications and products using NXP

Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or

customer product design. It is customer’s sole

responsibility to determine whether the NXP

Semiconductors pro du ct is su itable and fit for the

customer’s applications and products planned, as well as

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design and opera t ing saf eg ua rd s to minimize the risks

associated with their applications an d products.

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to any default, damage, costs or problem which is based

on any weakne ss or default in t he customer’s applic ations

or products, or the application or use by customer’s third

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necessary testing for the customer’s applications and

products using NXP Semiconductors products in order to

avoid a default of the applic ations and the products or of

the application or use by customer’s third party

customer(s). NXP does not accept any liability in this

respect.

2002 Nov 25 17

NXP Semiconductors Product specification

96 kHz sampling 24-bit stereo audio ADC UDA1361TS

Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to

the device. Limiting values are stress ratings only and

(proper) operation of the device at these or any other

conditions abo ve those given in the Recommended

operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will

permanently and irreversibly affect the quality and

reliability of the device.

Terms and conditions of commercial sale ⎯ NXP

Semiconductors products are sold s ubject to the general

terms and conditio ns of commercial sale, as published at

http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written ind i vidual agreemen t. In cas e an

individual agreeme nt is co nc luded only the terms and

conditions of the resp ective agreement shall app ly. NXP

Semiconductors hereby expressly objects to a pply i ng the

customer’s general terms and conditions with regard to the

purchase of NXP Semicon ductors produc ts by customer.

No offer to sell or license ⎯ Nothing in this document

may be interpreted or construed as an offer to sell products

that is open for acceptance or the grant, conveyance or

implication of any license under any copyrights, patents or

other industrial or intellectual proper ty rights.

Export control ⎯ This document as well as the item(s)

described he re in may be subject to export con tro l

regulations. Export might require a prior authorization from

national auth or itie s.

Quick refer ence data ⎯ The Quick reference data is an

extract of th e product data given in the Limiting values an d

Characteristics sections of this document, and as such is

not complete, exhaus tive or legally binding.

Non-automotive qualified products ⎯ Unless this data

sheet expressly states that this specific NXP

Semiconductors product is au tomotive qualified, the

product is not suitable for automotive use. It is neither

qualified nor te sted in accordanc e with automot ive testing

or application requirements. NXP Semiconductors accepts

no liability for inclusion and/or use of non-automotive

qualified prod ucts in automotive equip m en t or

applications.

In the event that customer uses the product for design-in

and use in automotive applications to automotive

specifications and standards, customer (a) shall use the

product without NXP Semiconductors’ warranty of the

product for such au t omo tive applications, use and

specifications, and (b) whenever customer uses the

product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be so lely at

customer’s own ris k, and (c) customer fully indemnifies

NXP Semiconductors for any liability, damages or failed

product clai ms r esult ing fr om custo mer desi gn an d us e o f

the product for automotive ap plic ations beyond NXP

Semiconductors ’ st andard warranty and NXP

Semiconductors’ product specifications.

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product

solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Contact information

For additional information p lease visit: http://www.nxp.com

For sales offices addresses send e-mail to: salesaddresses@nxp.com

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information pr e sent ed in this document does not form p art of any quotation or co nt ra ct, is b elieve d to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or in tellectual property rights.

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

definitions and disclaimer s. No changes were made to the technical content, except for package outline

drawings which were updated to the latest version.

Printed in The Netherlands 753503/02/pp18 Date of release: 2002 Nov 25 Document order number: 9397 750 10479