pee 28 199 Philips Components-Signetics Document No. 27C040 eeu Ne. 4 MEG CMOS EPROM (512K x 8) ~ Date of Issue | November 1990 , Status Objective Specification Memory Products DESCRIPTION FEATURES PIN CONFIGURATIONS The 27C040 CMOS EPROM is a 4,194,304 bit SV read only memory organized as 524,288 words of 8 bits each. It employs advanced CMOS Low power consumption 100A standby current @ Quick pulse programming algorithm circuitry for systems requiring low for high speed production power, high performance speeds, and programming immunity from noise. The 27C040 has High-performance speed non-muhiplexed addressing interface. The 27C040 is available in a ceramic ~ 150ns maximum access time Noise immunity features: windowed DIP and a plastic DIP. ~ #10% Voc toler The 270040 can be programmed on ~ Maximum latch-up immunity through industry standard EPROM programmers, using the intelligent algorithm or quick pulse programming techniques. Epitaxial processing BLOCK DIAGRAM DATA OUTPUTS 00- O7 DE ! OUTPUT ENABLE PIN DESCRIPTION xs een cume OenPeT QUEERS Ao-A18 | Address 00-07 | Outputs , Y DECODER Y-GATING OE Ouiput Enable CE Chip Enable NC No Connection AO- AW X DECODER cot MATRIX GND Ground Ts Vep Program voltage Voc Power supply DU Don't Use Philips Components | | [PHILIPS = | PHILIPSPhilips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 ORDERING INFORMATION DESCRIPTION ORDER CODE 32-Pin Ceramic Dual In-Line with quartz window 27C040-15 FA 32-Pin Ceramic Dual In-Line with quartz window 27C040-20 FA 32-Pin Plastic Dual In-Line 27C040-15 N 32-Pin Plastic Dual In-Line 27C040-20 N ABSOLUTE MAXIMUM RATINGS! 2 SYMBOL PARAMETER RATING UNIT Tstg Storage temperature range -65 to +125 C Vi, Vo Voltage inputs and outputs -0.6 to (Voc + 1) Vv Vu Voltage on Ag (during intelligent identifier interrogation) 0.6 to +13.0 Vv Vpp Voltage on Vpp pin (during programming) -0.6 to +14.0 Vv Voc Supply voltage -0.6 to +7.0 Vv NOTES: 1. Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. All voltages are with respect to network ground. OPERATING TEMPERATURE RANGE PARAMETER RATING (C) . . COMMERCIAL Operating temperature range: Tamp 0 to +70 November 1990 2Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 DEVICE OPERATION! MODE CE OE Ay Ao Vpp Vec OUTPUTS Read Vir Vit x? x Voc 5.0V Dour Output disable Vic Vin X xX Veco 5.0V Hi-Z Standby Vin X xX xX Voc 5.0V Hi-Z Programming Vit Vin x x Vpp Voc Dw Program Verify Vin Vit xX x Vpp Voeo5 Dout Program Inhibit Vin X x xX Vpp Voc5 Hi-Z Intelligent Manufacturer Vic Vit Vi Vit Veco 5.0V F5 (HEX) Identifier Device* Vir Vit vis Vi Voc 5.0V 3E (HEX) NOTES: 1. All voltages are with respect to network ground. 2. Xcan be Vit or Vin. 3. Vu = 12.0V +0.5V, Voc = 5.0V + 0.5V. 4. At -A8,A10-A18 = Vy. 5. See DC Programming Characteristics for Voc and Vpp voltages. READ MODE: 27C040 The 27C040 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output enable (OE) is the output control and should be used to gate data from the output pins. Data is available at the outputs after a delay of tog from the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc - tog. STANDBY MODE: The 27C040 can be placed in the standby mode which reduces the maximum Icc of the device by applying a Vy, to the TE pin. When in the standby mode, the outputs are in a high impedance state, independent of the OE input. November 1990 OUTPUT OR-TIEING 2 LINE OUTPUT CONTROL: The 27C040 may be used in larger memory systems. A two line control function has been provided to allow for: - The lowest possible memory power con- sumptions and, - Complete assurance that bus contention will not occur. To use this feature, CE should be decoded and used as the primary device selecting function, and OE should be made a common connection to ail devices in the array and connected to the read line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. SYSTEM CONSIDERATIONS: During the switch between active and standby power conditions, transient current peaks are produced on the rising and falling edges of chip enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. A 0.1pF ceramic capacitor (high frequency low-inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7pF bulk eletrolytic capacitor should be used between Voc and GND for every eight (8) devices. The location of the capacitor should be close to where the power supply is connected to the array.Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 DC ELECTRICAL CHARACTERISTICS Over operating temperature range, +4.5V < Voc < +5.5V SYMBOL PARAMETER TEST CONDITIONS UMITS UNIT MIN | TYP> | MAX Input current Iya Leakage High Vy = 5.5V = Voc 0.01 1.0 pA In Leakage Low Vi. = OV 0.01 -1.0 pA lpp Vpp read Vpp = Voc 10 pA Output current lo Leakage OE or CE = Vin, Vout = 5.5V = Vog -10.0 10.0 pA los Short circuit: Vout = OV 100 mA Supply current loc TIL | Operating (TTL inputs)* & Ven Von on ' Tone 50 mA leg CMOS | Operating (CMOS inputs). & Inputs Yon OND vO vom A 20 mA Isg TTL Standby (TTL inputs)* CE = Vy, 1 mA Isa CMOS | Standby (CMOS inputs) CE = Vy 100 pA Input voltage Va Low (TTL) Vpp = Voc 05 0.8 Vv Vi Low (CMOS) Vpp = Voc -.02 0.2 Vv View High (TTL) Vpp = Voc 2.0 Voc + 0.5 Vv Vin High (CMOS) Vpp = Voc Voc - 0.2 Veg + 0.2 Vv Vpp Read? (Operating) Vog - 0.7 Voc Vv Output voltage* Vor Low Io, = 2.1MA 0.45 Vv Vou High low = -2.5mA 3.5 Vv Capacitance T,.4, = 25C Cw Address and control Voc = 5.0V, f = 1.0MHz 6 pF Court Outputs Vin = OV, Vout = OV 12 pF NOTES: _ . Minimum DC input voltage is -0.5V. During transitions the inputs may undershoot to -2.0V for periods less than 20ns. All voltages are with respect to network ground. Typical limits are at Voc = 5V, Tarp = 25C. TTL inputs: Spec Vx, Vz, levels. CMOS inputs: GND 40.2V to Voc 40.2V. TE is Voc +0.2V. All other inputs can have any value within spec. Maximum active power usage is the sum of Ipp + loc and is measured at a frequency of 6.7MHz. Test one output at a time, duration should not exceed 1 second. Vpp may be one diode voltage drop below Vc, and can be connected directly to Voc. Guaranteed by design, not 100% tested. DONA BWPPhilips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 AC ELECTRICAL CHARACTERISTICS Over operating temperature range, +4.5V < Voc < +5.5V, Ry, = 6609, C, = 100pF UMITs SYMBOL To FROM 27C040-15 27C040-20 UNIT MIN | MAX | MIN | MAX Access time! tace Output Address 150 200 ns tcc Output CE 150 200 ns tog? Output OE 60 70 ns Disable time tor Output Hi-Z OE 50 60 ns ton Output Hold Address, CE or OF 0 0 ns NOTES: 1. AC characteristics are tested at Vi, = 2.4V and Vi_ = 0.45V. Timing measurements made at Vo, = 0.8V and Voy = 2.0V: Input rise and fall times (10% to 90%) = 20ns. 2. Guaranteed by design, not 100% tested. 3. OE may be delayed up to tog - tog after the falling edge of CE without impact on tc. AC VOLTAGE WAVEFORMS y ce eoee , te___-> CE = 8800 _/ te tor tace tou"} OUTPUT tid Li f f p f AAAS cece Ke Vin Vin. Vis Vw Hz VALID OUTPUT 5 __ Vie AC TESTING LOAD CIRCUIT AL it 2 November 1990 5Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 27C040 PROGRAMMING INFORMATION Complete programming system specifications for both the intelligent programming method and for the quick-pulse programming method are available upon request from Signetics. Signetics encourages the purchase of programming equipment from a manufacturer who has a full line of programming products to offer. Signetics also encourages the manufacturers of 27C040 programming equipment to submit their equipment for verification of electrical parameters and programming procedures. Information on manufacturers offering equipment certified by Signetics is available upon request from Signetics Memory Marketing. PROGRAMMING THE 27C040 Caution: Exceeding 14.0V on Vpp pin may permanently damage the 27C040. Initially, all bits of the 27C040 are in the "1" State. Data is introduced by selectively programming 0"s into the desired bit locations. Although only 0"s will be programmed, both 1s and "0s can be present in the data word. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are standard TTL logic levels. QUICK-PULSE PROGRAMMING ALGORITHM Signetics plastic EPROMs can be programmed using the quick-pulse programming algorithm to substantially reduce the throughput time in the production environment. This algorithm typically allows plastic devices to be programmed in under twelve seconds, a significant improvement over previous algorithms. Actual programming time is a function of the PROM programming equipment being used. The quick-pulse programming algorithm uses initial pulses of 100ps followed by a byte verification to determine when the address byte has been successfully programmed. Up to 25 100j1s pulses per byte are provided before a failure is recognized (refer to the following pages for algorithm specifications). November 1990 ERASURE CHARACTERISTICS The erasure characteristics of the 27C040 are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 - 4000 A range. Data shows that constant exposure to room level fluorescent lighting could erase the typical 27C040 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. if the 270040 is to be exposed to these types of lighting conditions for extended periods of time, opaque labals should be placed over the window to prevent unintentional erasure. The recommended erasure procedure for the 27C040 is exposure to shortwave ultra- violet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000. W/cm? power rating. The 27C040 should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a 27C040 can be exposed to without damage is 7258Wsec/cm? (1 week @ 12000,.Wicm?}. Exposure of these CMOS EPROMs to high intensity UV light for longer periods may cause permanent damage. INTELLIGENT PROGRAMMING ALGORITHM The 27C040 intelligent programming algorithms rapidly program CMOS EPROMs using an efficient and reliable method particularly suited to the production programming environment. Actual programming times may vary due to differences in programming equipment. The intelligent identifier also provides the reading out of a binary code from an EPROM that will identify its manufacturer and type. This is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25 + 5C ambient temperature range that is required when programming the 27C040. To activate this mode, the programming equipment must force 11.5V to 12.5V on address AQ of the 27C040. Two bytes may then be read from the device outputs by toggling address line AO from V_ to Viy. The TE, OE and all other address lines must be at V,_ during interrogation. The identifier information for Signetics 27C040 is as follows: When AO = Ve data is Manufacturer 15 HEX) When AO = Vg data is Product SEWex) Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. The programming algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial PGM pulse(s) is 1ms, which is then followed by a longer overprogram pulse of 3Xms. X is an iteration counter and is equal to the number of the initial 1ms pulses applied to a particular location before a correct verify occurs. Up to 25 ims pulses per byte are provided for before the overprogram pulse is applied (refer to the following pages for algorithm specifications). CMOS NOISE CHARACTERISTICS Special epitaxial processing techniques have enabled Signetics to build CMOS with features that add to system reliability. These include input/output protection to latch-up for stresses up to 100mA on Address and Data pins that range from -1V to (Voc + 1V). in addition, the Vpp (Programming) pin is designed to resist latch-up to the 14V maximum device limit. SIGNETICS DISCOURAGES THE CONSTRUCTION AND USE OF HOMEMADE PROGRAMMING EQUIPMENT In order to consistently achieve excellent programming yields, periodic calibration of the programming equipment is required. Consult the equipment manufacturer for the recommended calibration interval. Signetics warranty for programmability extends only to product that has been programmed on certified equipment that has been serviced to the manufacturers recommendation.Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 INTELLIGENT PROGRAMMING ALGORITHM DC PROGRAMMING CHARACTERISTICS Tam = 25C +5C, Vog = 6.0V 40.25V, Vpp = 12.5V 40.5V SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN MAX h Input current (all inputs) Vin = Vic or Vin 1.0 pA Vit Input low level (all inputs) 0.1 0.8 Vv Vin Input high level 2.4 65 Vv VoL Output low voltage during verify lo, = 2.1mMA 0.45 Vv Vou Output high voltage during verify lon = -2.5mA 3.5 Vv loco Voc supply current 00-15 =OmA 50 mA Ippe Vpp supply current (program) CE = Vit 50 mA AC PROGRAMMING CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN TYP MAX tas Address setup time 2 ps toes - OE setup time 2 ps tos Data setup time 2 ps ta Address hold time 0 ps tou Data hold time 2 ps tore? DE high to output float delay 0 130 ns typs Vpp setup time 2 ps tyes Voc setup time 2 ps tces CE setup time 2 us tpw TE initial program pulse width Note 1 0.95 1.0 1.05 ms topw TE overprogram pulse width Note 2 2.85 78.75 ms toe Data valid from OF 150 ps AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) 0 eee ee nee e enn ee ee ee eee e eee ene EE eee 20ns Input Pulse Levels . 0... eee ee en teen teen eee beeen ene rep eee e eee e nena ee eneee 0.45V to 2.4V input Timing Reference Level . 0.6... ce en eee eee eee e be cette beeen ene een 0.8V and 2.0V Output Timing Reference Level .. 2... ce ee eee ene e eee ee ener n ete b betes eeeee 0.8V and 2.0V NOTES: 1. Initial program pulse width tolerance is 1ms +5%. 2. The length of the overprogram pulse may vary from 2.85msec to 78.75msec as a function of iteration counter value X. 3. The parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven see timing diagram. 4. During programming, a 0. 1pf capacitor is required from Vpp to GND node, to suppress voltage transients that can damage the device. November 1990 7Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 27C040 INTELLIGENT PROGRAMMING ALGORITHM WAVEFORMS PROGRAM PRAM lg READ VERIFY WH ADDRESS ADDRESS STABLE ADDRESS VALID Vi le tas or) | * taco> Wn DATA DATAIN DATA OUT VAUD STABLE VAUD OUTPUT taH - Lf [veg 7 rte Cae - WY \ | November 1990 8Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 INTELLIGENT PROGRAMMING ALGORITHM FLOWCHART DEVICE FAILED November 1990Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 QUICK PULSE PROGRAMMING ALGORITHM DC PROGRAMMING CHARACTERISTICS Tamb = 25C +5C, Voc = 6.25V +0.25V, Vpp = 12.75V 10.25V SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN MAX hh Input current (all inputs) Vin = Vic or Vin 1.0 pA Vir Input low level (all inputs) 0.1 0.8 Vv Vin Input high level 2.4 65 Vv VoL Output low voitage during verify lo. = 2.1mMA 0.45 Vv Vou Output high voltage during verify lon = -2.5mA 3.5 v lece Voc supply current OO - 15 =0mA 50 mA Ippo Vpp supply current (program) CE = Vi 50 mA AC PROGRAMMING CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN TYP MAX tas Address setup time 2 ps toes OE setup time 2 ps tos Data setup time 2 ps tay Address hold time 0 ps tou Data hold time 2 ps tore? OE high to output fioat delay 0 130 ns tvrs Vpp setup time 2 ps twos Voc setup time 2 ps teow CE initial program puise width Note 1 095 0.100 | 0.105 ms topw TE overprogram puise width Note 2 2.85 78.8 ms tor Data valid from OE 150 ps AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) 20... e eee n eee e nee e ete e rete eenebeeneneensnetnsevebenennes 20ns Input Pulse Levels 0.0 cence een eee cee n eee e ete e been eben eet bntntbebncneeenberens 0.45V to 2.4V Input Timing Reference Level 6.6... ccc cece cence nee n enc ee nee eben bbe eb bbb ebb b bbe bbnn ys 0.8V and 2.0V Output Timing Reference Level 0.0.0... c cece ce nett n eee ee bee eve e bbb bbb be bn bbb bbb bbb ed 0.8V and 2.0V NOTES: 1. Initial program pulse width tolerance is ims 5%. 2. The length of the overprogram pulse may vary from 2.85msec to 78.75msec as a function of iteration counter value X, 3. The parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven see timing diagram. 4. During programming, a 0. 1yf capacitor is required from Vpp to GND node, to suppress voitage transients that can damage the device. November 1990 10Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 QUICK PULSE PROGRAMMING ALGORITHM WAVEFORMS PROGRAM. PROGRAM VERIFY >} ~ READ VERIFY Vin ADDRESS ADDRESS STABLE ADDRESS VALID Vi L. tas Orr | * tacc } Vin DATA DATA IN DATA out VAUD STABLE VALID OUTPUT v n taH i. ~ Lf [ves eee Voc 7 a a | / Vin SOL pw * toes Vin November 1990 11Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 270040 QUICK PULSE PROGRAMMING ALGORITHM FLOWCHART START ADDRESS FIRST LOCATION Voc = 6.250 Vpp = 12.75V PROGRAM ONE 100)s PULSE +) FAIL INCREMENT ADDRESS DEVICE FAILED November 1990 12Philips ComponentsSignetics Memory Products 4 MEG CMOS EPROM (512K x 8) Objective Specification 270040 32-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F}) PACKAGE .098 (2.49) (___ .098 (2.49) | 040 (1.02} 7] 040 (1.02) ale SEE NOTE 6 ADRAA MAM AM ALAS A MH NOTES: y 1. CONTROLLING DIMENSION: INCHES. MILLIMETERS ARE SHOWN IN PARENTHESIS. N 2. DIMENSION AND TOLERANCING PER ANSI Y14.5M-1982. / 3. *T,"D", ANDE* ARE REFERANCE DATUMS ON THE \ \ 598 (15.19) BODY AND INCLUDE ALLOWANCE FOR GLASS OVERRUN a) \ ' $a 03.06) AND MENISCUS ON THE SEAL LINE, AND LID TO BASE \ 1 MISMATCH. \ 7 4. THESE DIMENSIONS MEASURED WITH THE LEADS weer CONSTRAINED TO BE PERPENDICULAR TO PLANE T. \ 2 SE Sa Sass EN ENE ron (] PWV Ae 6. DENOTES WINDOW LOCATION FOR EPROM PRODUCTS. wt 100 (2.54) BSC 4.875 (42.55) 7.640 (41.66) __. .070 (1.78) 820 (15.75) 050 (1.27) 500 (14.99) (NOTE 4) i A75 (4.45) 1 225 (5.72) 145 (3.68) +-+ MAX. " 165 (4.19) 055 (1 ) , . 7125 (3.18) 020 (51 , " i ij S88) ry as x) | 023 (.58) a a Fs oer LOL EPO Lovo 250 @] rota (NOTE 4) 695 (17.65) 600 (15.24) 853-1468 00351 FR3 November 1990 13Philips ComponentsSignetics Memory Products Objective Specification 4 MEG CMOS EPROM (512K x 8) 27C040 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative of in Design Tray change ir ry anne thet nee on Speateatons for product development. Specifications This data sheet contains preliminary data, and supplementary data will be published at a later date. Preliminary Specification Preproduction Product Signetics reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Signetics reserves the to make changes at any time Product Specification Ful Production without ausion In sede ts Krptove design tnd apply the bast pocebie product uv Signetics reserves the right to make changes without notice in the products, including circuits, standard calls, and/or software, described or contained herein, in order to improve design and/or performance. Signetics assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work infringement, unless otherwise specified. Applications that are described herein for any of these prod- ucts are for ilustrative purposes only. Signetics makes no representation or warranty that such applications will be suitable for the spacified use without further testing or modification. LIFE SUPPORT APPLICATIONS Signetics Products are not designed for use in life support appliances, devices, or systems where malfunction of a Signetics Product can reasonably be expected to result in a personal injury. Signetics customers using or selling Signetics Products for use in such applications do so at their own risk, and agree to fully indemnify Signetics for any damages resulting from such improper use or sale. Signetics Company Signetics registers eligible circuits under a e 811 East Arques Avenue the Semiconductor Chip Protection Act. Si netics P.O. Box 3409 @Copyright 1990 NAPC. Sunnyvale, California 94088-3400 All rights reserved. Printed in U.S.A. 0 division of North American Philios Corporation Telephone 408/991-2000 98-6232-040 0S82N/4W/FP/1290 \4 JAN 2 2 198t VL R November 1990