LP5904TME-2.6/NOPB - Texas Instruments High-Performance Analog

VIN

VEN

GND

VOUT OUTPUT

1 PF

1.0 PF

INPUT

ENABLE

GND

LP5904

SVA-30110401

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

Ultra Low Noise, 200 mA Linear Regulator for RF/Analog

Circuits - Requires No Bypass Capacitor

Check for Samples: LP5904

1FEATURES PACKAGE

• Stable with 1.0 µF Ceramic Input and Output • 4-Bump DSBGA (lead free)

Capacitors 0.815 mm × 0.815 mm × 0.600 mm

• No Noise Bypass Capacitor Required DESCRIPTION

• Remote Output Capacitor Placement The LP5904 is a linear regulator capable of supplying

• Thermal-overload and Short-circuit Protection 200 mA output current. Designed to meet the

• –40°C to +125°C Junction Temperature Range requirements of RF/ Analog circuits, the LP5904

for Operation device provides low noise, high PSRR, low quiescent

current, and low line transient response figures. Using

APPLICATIONS new innovative design techniques the LP5904 offers

class-leading device noise performance without a

• Cellular Phones noise bypass capacitor and the ability for remote

• PDA Handsets output capacitor placement. An active pulldown circuit

with a 280Ωresistor is wired from the output to

• Wireless LAN Devices ground pins to quickly discharge output when the

device is disabled (VEN = low).

KEY SPECIFICATIONS The device is designed to work with a 1.0 µF input

• Input Voltage Range … 2.2V to 5.5V and a 1.0 µF output ceramic capacitor. (No Bypass

• Output Voltage Range … 1.2V to 4.4V Capacitor is required.)

• Output Current … 200 mA The device is available in a DSBGA package. For

• Low Output Voltage Noise at other package options contact your local TI sales

200 mA … 6.5µVRMS office.

• PSRR … 78 dB at 1kHz This device is available between 1.2V and 4.4V in

• Output Voltage Tolerance … ± 2% 25 mV steps. Please contact Texas Instruments

Sales for specific voltage option needs.

• Virtually Zero IQ (Disabled) … <1 µA

• Very Low IQ (Enabled) … 11 µA

• Startup Time … 85 µs

• Low Dropout … 95 mV typ

TYPICAL APPLICATION CIRCUIT

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

B2B1

A2A1 VOUT

GND

VIN

VEN

B2 B1

A2 A1

VOUT

GND

VIN

VEN

TOP VIEW BOTTOM VIEW

SVA-30110402

LP5904

SNVS637G –MARCH 2011–REVISED APRIL 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAMS

Note: The actual physical placement of the package marking will vary from part to part. The package marking “A”

designates the date code, and will vary in production.

Figure 1. 4-Bump Thin DSBGA Package

Package Number YFQ0004AAA

PIN DESCRIPTIONS

PIN DESCRIPTION

NAME NO.

A1 VIN Input voltage supply. A 1.0 µF capacitor should be connected at this input.

Output voltage. A 1.0 µF Low ESR capacitor should be connected to this pin. Connect this output to

A2 VOUT the load circuit. An internal 280Ωdischarge resistor prevents a charge remaining on VOUT when

disabled.

Enable input; disables the regulator when ≤0.4V. Enables the regulator when ≥1.2V. An internal 1MΩ

B1 VEN pulldown resistor connects this input to ground.

B2 GND Common ground.

ORDERING INFORMATION

DSBGA PACKAGE (LEAD FREE)(1)

SUPPLIED AS

OUTPUT VOLTAGE (V) 250 TAPE AND REEL 3000 TAPE AND REEL

1.2 LP5904TME-1.2/NOPB LP5904TMX-1.2/NOPB

1.8(2) LP5904TME-1.8/NOPB LP5904TMX-1.8/NOPB

2.5(2) LP5904TME-2.5/NOPB LP5904TMX-2.5/NOPB

2.6(2) LP5904TME-2.6/NOPB LP5904TMX-2.6/NOPB

2.8 LP5904TME-2.8/NOPB LP5904TMX-2.8/NOPB

2.85 LP5904TME-2.85/NOPB LP5904TMX-2.85/NOPB

3.0(2) LP5904TME-3.0/NOPB LP5904TMX-3.0/NOPB

3.1 LP5904TME-3.1/NOPB LP5904TMX-3.1/NOPB

3.2(2) LP5904TME-3.2/NOPB LP5904TMX-3.2/NOPB

3.4(2) LP5904TME-3.4/NOPB LP5904TMX-3.4/NOPB

(1) Contact your local TI Sales Office for availability of other voltage options.

(2) Not yet released — contact TI sales office for sample availability.

Product Folder Links: LP5904

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

ABSOLUTE MAXIMUM RATINGS(1)(2)(3)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VIN Input Voltage –0.3 6.0 V

VOUT Output Voltage –0.3 to (VIN + 0.3V) 6.0 V

VEN Enable Input Voltage –0.3 to (VIN + 0.3V) 6.0 V

Continuous Power Dissipation(4) Internally Limited

Junction Temperature (TJMAX) 150 °C

Storage Temperature Range –65 150 °C

Maximum Lead Temperature (Soldering, 10 sec.) 260 °C

Human Body Model 2 kV

ESD Rating(5) Machine Model 200 V

(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics tables.

(3) All voltages are with respect to the potential at the GND pin.

(4) Internal thermal shutdown circuitry protects the device from permanent damage.

(5) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. The machine model is a 200 pF

capacitor discharged directly into each pin. MIL-STD-883 3015.7

OPERATING RATINGS(1)(2)

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VIN Input Voltage Range 2.2 5.5 V

VEN Enable Voltage Range 0 to (VIN + 0.3) 5.5 V

Recommended Load Current(3) 0 200 mA

TJJunction Temperature Range –40 +125 °C

TAAmbient Temperature Range(3) –40 +85 °C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See applications section.

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

JEDEC Board (DSBGA)(2) 119.6 °C/W

θJA Junction to Ambient Thermal Resistance(1) 4L Cellphone Board (DSBGA) 186.5 °C/W

(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(2) Detailed description of the board can be found in JESD51-7

Product Folder Links: LP5904

LP5904

SNVS637G –MARCH 2011–REVISED APRIL 2013

www.ti.com

ELECTRICAL CHARACTERISTICS(1)(2)

Limits in standard typeface are for TA= 25°C. Limits in boldface type apply over the full operating junction temperature range

(–40°C ≤TJ≤+125°C). Unless otherwise noted, specifications apply to the LP5904 Typical Application Circuit with: VIN = VOUT

(NOM) + 1.0V, VEN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, IOUT = 1.0 mA.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN Input Voltage 2.2 5.5 V

VIN = (VOUT(NOM) + 1.0V) to 5.5V,

Output Voltage Tolerance –2 2 %

IOUT = 1mA to 200 mA

VIN = (VOUT(NOM) + 1.0V) to 5.0V, 0.06

IOUT = 1 mA

ΔVOUT Line Regulation %/V

VIN = (VOUT(NOM) + 1.0V) to 5.5V, 0.16

IOUT = 1 mA

Load Regulation IOUT = 1mA to 200 mA 0.002 %/mA

Load Current See (3) 0 200

ILOAD mA

Maximum Output Current 200

VEN = 1.2V, IOUT = 0 mA 11 20

IQQuiescent Current(4) VEN = 1.2V, IOUT = 200 mA 250 325 µA

VEN = 0.3V (Disabled) 0.2 1.0

IGGround Current(5) IOUT = 0 mA (VEN = 1.2V) 12.2 µA

IOUT = 100 mA 45

VDO Dropout Voltage(6) mV

IOUT = 200 mA 95 150

ISC Short Circuit Current Limit See (7) 220 450 mA

f = 100 Hz, IOUT = 10 mA 88

f = 1 kHz, IOUT = 10 mA 80

Power Supply Rejection

PSRR f = 10 kHz, IOUT = 10 mA 70 dB

Ratio(8) f = 100 kHz, IOUT = 10 mA 50

f = 2MHz, IOUT = 10 mA 30

IOUT = 1mA 10

BW = 10 Hz to 100

eNOutput Noise Voltage(8) µVRMS

kHz IOUT = 200 mA 6.5

Temperature 160

TSHUTDOWN Thermal Shutdown °C

Hysteresis 15

VIL Low Input Threshold (VEN) VIN = 2.2V to 5.5V 0.4 V

VIH High Input Threshold (VEN) VIN = 2.2V to 5.5V 1.2 V

VEN = 5.5V and VIN = 5.5V 5.5

IEN Input Current at VEN Pin(9) µA

VEN = 0.0V and VIN = 5.5V 0.001

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most

likely norm.

(3) The device maintains a stable, regulated output voltage without a load current.

(4) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(5) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.

(6) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value. This specification does not apply for input voltages below 2.2V.

(7) Short Circuit Current is measured with VOUT pulled to 0V and VIN worst case = 5.5V.

(8) This specification is ensured by design.

(9) There is a 1MΩresistor between VEN and ground on the device.

Product Folder Links: LP5904

OUTIN

A special integrated filter

for noise suppression

Bandgap

1.2V

FILTER

REFERENCE

VREFC

VEN

280W

SVA-30110406

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

ELECTRICAL CHARACTERISTICS(1)(2) (continued)

Limits in standard typeface are for TA= 25°C. Limits in boldface type apply over the full operating junction temperature range

(–40°C ≤TJ≤+125°C). Unless otherwise noted, specifications apply to the LP5904 Typical Application Circuit with: VIN = VOUT

(NOM) + 1.0V, VEN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, IOUT = 1.0 mA.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TRANSIENT CHARACTERISTICS

VIN = (VOUT(NOM) + 1.0V) to (VOUT(NOM) + 1.6V) in 30 µs, –2

IOUT = 1mA

Line Transient(10) mV

VIN = (VOUT(NOM) + 1.6V) to (VOUT(NOM) + 1.0V) in 30 µs, 2

IOUT = 1mA

ΔVOUT IOUT = 1mA to 200 mA in 10 µs –50

Load Transient(10) mV

IOUT = 200 mA to 1mA in 10 µs 50

Overshoot on Startup(10) Stated as a percentage of nominal VOUT 2%

Turn-on Time To 95% of VOUT(NOM) 85 300 µs

(10) This specification is ensured by design.

OUTPUT AND INPUT CAPACITORS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN(1) TYP MAX UNIT

CIN Input Capacitance(2) 0.5 1.0

Capacitance for stability µF

COUT Output Capacitance(2) 0.5 1.0 10

ESR Output/Input Capacitance(2) 5 500 mΩ

(1) Note: The minimum capacitance should be greater than 0.5 μF over the full range of operating conditions. The capacitor tolerance

should be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should

be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended

however capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions.

(2) This specification is ensured by design.

BLOCK DIAGRAM

Product Folder Links: LP5904

3.5 4.0 4.5 5.0 5.5

2.740

2.760

2.780

2.800

2.820

2.840

VOUT(V)

VIN(V)

50 A

500 A

1mA

10 mA

100 mA

200 mA

SVA

0 50 100 150 200

2.740

2.760

2.780

2.800

2.820

2.840

VOUT(V)

IOUT(mA)

VIN = 3.8V

VIN = 5.0V

VIN = 5.5V

0 50 100 150

LOAD CURRENT (mA)

-1.000%

VOUT VARIATION

100oC

200

-0.5000%

0.000%

0.500%

1.000%

-40oC

25oC85oC

SVA-30110403

0 50 100 150 200 250 300

100

150

200

250

300

350

GROUND CURRENT (A)

IOUT(mA)

VIN = 3.0V

VIN = 3.8V

VIN = 4.2V

VIN = 5.5V

2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7

IQ(A)

VIN(V)

Dropout Region

SVA-30110460

0 50 100 150 200 250

100

150

200

250

GROUND CURRENT (A)

IOUT(mA)

-40°C

25°C

85°C

125°C

SVA

LP5904

SNVS637G –MARCH 2011–REVISED APRIL 2013

www.ti.com

TYPICAL CHARACTERISTICS

Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN= 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA= 25°C.

IqGround Current

vs vs

VIN IOUT

Figure 2. Figure 3.

Ground Current VOUT Variation

vs vs

IOUT IOUT

Figure 4. Figure 5.

VOUT VOUT

vs vs

VIN IOUT

Figure 6. Figure 7.

Product Folder Links: LP5904

VIN

VOUT

10 mV/

DIV

1V/DIV

40 Ps/DIV

SVA-30110412

SVA-30110445

VOUT

SVA-30110444

SVA-30110443

0 20 40 60 80 100120140160180200

2.740

2.760

2.780

2.800

2.820

2.840

VOUT(V)

IOUT(mA) OVER TEMPERATURE

-40°C

25°C

85°C

100°C

SVA-30110442

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

TYPICAL CHARACTERISTICS (continued)

Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN= 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA= 25°C.

VOUT

IOUT Startup, No Load

Figure 8. Figure 9.

Startup, Load = 28ΩStartup, Load = 14Ω

Figure 10. Figure 11.

Load Transient, Line Transient

Load = 1mA to 200mA, VOUT = 2.8V Load = 1mA, VOUT = 2.8 at VIN Rising Edge

Figure 12. Figure 13.

Product Folder Links: LP5904

SVA-30110446

10 100 1000 10000 100000

.001

.01

V/¥(Hz)

FREQUENCY (Hz)

Load = 0mA

Load = 1mA

Load = 50mA

0 50 100 150 200

100

120

DROPOUT (mV)

IOUT(mA)

SVA-30110466

VIN

VOUT

10 mV/

DIV

1V/DIV

40 Ps/DIV

SVA-30110415

VIN

VOUT

10 mV/

DIV

1V/DIV

40 Ps/DIV

SVA-30110414

VIN

VOUT

10 mV/

DIV

1V/DIV

40 Ps/DIV

SVA-30110413

LP5904

SNVS637G –MARCH 2011–REVISED APRIL 2013

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN= 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA= 25°C.

Line Transient Line Transient

Load = 1mA, VOUT = 2.8 at VIN Falling Edge Load = 200 mA, VOUT = 2.8 at VIN Rising Edge

Figure 14. Figure 15.

Dropout Voltage

Line Transient vs

Load = 200 mA, VOUT = 2.8 at VIN Falling Edge Load Current

Figure 16. Figure 17.

Output Noise Spectral Density,

PSRR VOUT = 2.8V

Figure 18. Figure 19.

Product Folder Links: LP5904

VEN =

VIN

VOUT

IOUT

10 Ps/DIV

2A/DIV

1V/DIV

SVA-30110422

VEN =

VIN

VOUT

IOUT

10 Ps/DIV

2A/DIV

1V/DIV

SVA-30110421

VOUT

VEN

IOUT

200 Ps/DIV

1V/DIV

1A/DIV

1V/DIV

SVA-30110419

VOUT

VEN

IOUT

200 Ps/DIV

1V/DIV

1A/DIV

1V/DIV

SVA-30110420

VEN =

VIN

VOUT

IIN

20 Ps/DIV

1V/DIV

2A/DIV

SVA-30110416

VOUT

VEN

IOUT

200 Ps/DIV

1V/DIV

1A/DIV

1V/DIV

SVA-30110418

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

TYPICAL CHARACTERISTICS (continued)

Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN= 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA= 25°C.

Turn On Time, 1 mA Load Turn OFF Time, no Load,

VOUT = 2.8V, VIN = 3.93V (Battery) VOUT = 3.3V

Figure 20. Figure 21.

Turn OFF Time, 1 mA Load Turn OFF Time, 200 mA Load

VOUT = 3.3V VOUT = 3.3V

Figure 22. Figure 23.

Turn OFF Time, VEN = VIN at No Load Turn OFF Time, VEN = VIN at 200 mA

VOUT = 3.3V VOUT = 3.3V

Figure 24. Figure 25.

Product Folder Links: LP5904

VIN

VOUT

IIN

20 ms/DIV

1V/DIV

0 mA/

DIV

1V/DIV

SVA-30110417

IIN

40 ms/DIV

1A/DIV

VEN = VIN = VOUT +1

VOUT

1V/DIV

SVA-30110427

VOUT

IIN

20 ms/DIV

1A/DIV

1V/DIV

VEN

SVA-30110425

VOUT

IIN

20 ms/DIV

1A/DIV

1V/DIV

VEN

SVA-30110426

VOUT

IIN

20 Ps/DIV

2A/DIV

1V/DIV

1V/DIV VEN

SVA-30110424

VOUT

IIN

20 Ps/DIV

2A/DIV

1V/DIV

1V/DIV VEN

SVA-30110423

LP5904

SNVS637G –MARCH 2011–REVISED APRIL 2013

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN= 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA= 25°C.

Inrush, VIN = (VOUT(NOM)) + 1V, Inrush, VIN = (VOUT(NOM)) + 1V,

VOUT = 3.3V, IOUT = 100 µA VOUT = 3.3V, IOUT = 200 mA

Figure 26. Figure 27.

VEN Ramp Down VEN Ramp Down

vs vs

VOUT at 1mA Load VOUT = 3.3V VOUT at 200 mA Load VOUT = 3.3V

Figure 28. Figure 29.

Supply Ramping VEN = VIN = (VOUT + 1V)

Inrush, VIN Ramp at 1mA Load vs

VOUT = 2.8V, VIN = 3.8V, TRISE = 100 ms VOUT at IOUT = 200 mA, VOUT = 3.3V

Figure 30. Figure 31.

Product Folder Links: LP5904

SVA-30110409

SVA-30110405

IIN

40 ms/DIV

1A/DIV

VOUT

VEN

1V/DIV

SVA-30110430

IIN

40 ms/DIV

1A/DIV

VEN = VIN = VOUT +1

VOUT

1V/DIV

SVA-30110428

IIN

40 ms/DIV

1A/DIV

VOUT

VEN

1V/DIV

SVA-30110429

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

TYPICAL CHARACTERISTICS (continued)

Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN= 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA= 25°C.

VEN Ramping

Supply Ramping VEN = VIN = (VOUT + 1V) vs

vs VOUT at IOUT = 100 µA,

VOUT at IOUT = 100 µA, VOUT = 3.3V VIN = (VOUT + 1V), VOUT = 3.3V

Figure 32. Figure 33.

VEN Ramping

VOUT at IOUT = 200 mA, High Inrush due to Fast Power-On (VIN = VEN)

VIN = (VOUT + 1V), VOUT = 3.3V Such as in Hot-Plug

Figure 34. Figure 35.

No Inrush Current in Normal Power-On due to

System Capacitance Showing VIN Ramping

Figure 36.

Product Folder Links: LP5904

D IN OUT OUT

P = (V V) I- ´

(JMAX A

T T

P-

LP5904

SNVS637G –MARCH 2011–REVISED APRIL 2013

www.ti.com

APPLICATION INFORMATION

POWER DISSIPATION AND DEVICE OPERATION

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from

the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power

dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces

between the die and ambient air. As stated in the Operating Ratings (1), the allowable power dissipation for the

device in a given package can be calculated using the equation:

(1)

The actual power dissipation across the device can be represented by the following equation:

(2)

This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage

drop across the device, and the continuous current capability of the device. These two equations should be used

to determine the optimum operating conditions for the device in the application.

EXTERNAL CAPACITORS

Like any low-dropout regulator, the LP5904 requires external capacitors for regulator stability. The LP5904 is

specifically designed for portable applications requiring minimum board space and smallest components. These

capacitors must be correctly selected for good performance.

INPUT CAPACITOR

An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the

output capacitor for good load transient performance. At least a 1.0 µF capacitor has to be connected between

the LP5904 input pin and ground for stable operation over full load current range. Basically, it is ok to have more

output capacitance than input, as long as the input is at least 1.0 µF.

This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

NOTE

Important: To ensure stable operation it is essential that good PCB practices are

employed to minimize ground impedance and keep input inductance low. If these

conditions cannot be met, or if long leads are to be used to connect the battery or other

power source to the LP5904, then it is recommended to increase the input capacitor to at

least 10 µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current

when connected to a low-impedance source of power (like a battery or a very large

capacitor). If a tantalum capacitor is used at the input, it must be specified by the

manufacturer to have a surge current rating sufficient for the application. There are no

requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but

tolerance and temperature coefficient must be considered when selecting the capacitor to

ensure the capacitance will remain 1.0 µF ±30% over the entire operating temperature

range.

OUTPUT CAPACITOR

The LP5904 is designed specifically to work with a very small ceramic output capacitor, typically 1.0 µF. A

ceramic capacitor (dielectric types X5R or X7R) in the 0.5 µF to 10 µF range, and with ESR between 5mΩto 500

mΩ, is suitable in the LP5904 application circuit. For this device the output capacitor should be connected

between the VOUT pin and a good ground connection.

(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-

OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance

of the part/package in the application θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See

APPLICATION INFORMATION.

Product Folder Links: LP5904

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as

attractive for reasons of size and cost (see CAPACITOR CHARACTERISTICS below).

The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value

that is within the range 5mΩto 500 mΩfor stability.

REMOTE CAPACITOR OPERATION

The LP5904 requires at least a 1µF capacitor at output pin, but there is no strict requirements about the location

of the capacitor in regards the LDO output pin. In practical designs the output capacitor may be located some 5-

10 cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if

there is already respective capacitor(s) in the system (like a capacitor at the input of supplied part). The Remote

Capacitor feature helps user to minimize the number of capacitors in the system.

As a good design practice, it is good to keep the wiring parasitic inductance at a minimum, which means to use

as wide as possible traces from the LDO output to the capacitor(s), keeping the LDO trace layer as close as

possible to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many as

possible vias between the connection layers. The recommendation is to keep parasitic wiring inductance less

than 35 nH. For the applications with fast load transients, it is recommended to use an input capacitor equal to or

larger to the sum of the capacitance at the output node for the best load transient performance.

CAPACITOR CHARACTERISTICS

The LP5904 is designed to work with ceramic capacitors on the input and output to take advantage of the

benefits they offer. For capacitance values in the range of 0.5 µF to 10 µF, ceramic capacitors are the smallest,

least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise.

The ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩto 40 mΩ, which easily meets the ESR

requirement for stability for the LP5904.

The temperature performance of ceramic capacitors varies by type and manufacturer. Most large value ceramic

capacitors (≥2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the

capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.

A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable

and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than

ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance

and voltage ratings in the 0.5 µF to 10 µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about

2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.

NO-LOAD STABILITY

The LP5904 will remain stable and in regulation with no external load.

ENABLE CONTROL

The LP5904 may be switched ON or OFF by a logic input at the ENABLE pin. A high voltage at this pin will turn

the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3nA.

However, if the application does not require the shutdown feature, the VEN pin can be tied to VIN to keep the

regulator output permanently on.

A 1MΩpulldown resistor ties the VEN input to ground, this ensures that the device will remain off when the

enable pin is left open circuit. To ensure proper operation, the signal source used to drive the VEN input must be

able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics

section under VIL and VIH.

DSBGA MOUNTING

The DSBGA package requires specific mounting techniques, which are detailed in Texas Instruments Application

Note AN-1112 (SNVA009).

Product Folder Links: LP5904

LP5904

SNVS637G –MARCH 2011–REVISED APRIL 2013

www.ti.com

For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the

DSBGA device.

DSBGA LIGHT SENSITIVITY

Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as

halogen lamps can affect electrical performance if they are situated in proximity to the device.

Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the

fluorescent lighting used inside most buildings has very little effect on performance.

Product Folder Links: LP5904

LP5904

www.ti.com

SNVS637G –MARCH 2011–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision F (April 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 14

Product Folder Links: LP5904

PACKAGE OPTION ADDENDUM

www.ti.com 26-Nov-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP5904SP-2.8/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SP-2.85/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SP-3.0/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SP-3.1/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SP-3.3/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SP-4.4/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-1.2/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-1.8/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-2.8/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-2.85/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-3.0/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-3.1/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-3.3/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904SPX-4.4/NOPB NRND USON NLB 4 TBD Call TI Call TI

LP5904TME-1.2/NOPB NRND DSBGA YFQ 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TME-1.5/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TME-1.8/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TME-2.5/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TME-2.7/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TME-2.8/NOPB NRND DSBGA YFQ 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TME-2.85/NOPB NRND DSBGA YFQ 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TME-3.0/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TME-3.1/NOPB NRND DSBGA YFQ 4 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TME-3.3/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TME-3.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TME-4.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-0B/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

PACKAGE OPTION ADDENDUM

www.ti.com 26-Nov-2013

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP5904TMX-1.2/NOPB NRND DSBGA YFQ 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TMX-1.5/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-1.8/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-2.5/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-2.7/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-2.8/NOPB NRND DSBGA YFQ 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TMX-2.85/NOPB NRND DSBGA YFQ 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TMX-3.0/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-3.1/NOPB NRND DSBGA YFQ 4 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125

LP5904TMX-3.3/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-3.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

LP5904TMX-4.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 26-Nov-2013

Addendum-Page 3

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP5904TME-1.2/NOPB DSBGA YFQ 4 250 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

LP5904TME-2.8/NOPB DSBGA YFQ 4 250 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

LP5904TME-2.85/NOPB DSBGA YFQ 4 250 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

LP5904TME-3.1/NOPB DSBGA YFQ 4 250 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

LP5904TMX-1.2/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

LP5904TMX-2.8/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

LP5904TMX-2.85/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

LP5904TMX-3.1/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP5904TME-1.2/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5904TME-2.8/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5904TME-2.85/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5904TME-3.1/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0

LP5904TMX-1.2/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

LP5904TMX-2.8/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

LP5904TMX-2.85/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

LP5904TMX-3.1/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 2

MECHANICAL DATA

NLB0004A

www.ti.com

SPD04A (Rev A)

TOP SIDE OF PACKAGE

BOTTOM SIDE OF PACKAGE

MECHANICAL DATA

YFQ0004xxx

www.ti.com

TMD04XXX (Rev A)

0.600±0.075

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

4215073/A 12/12

D: Max =

E: Max =

0.84 mm, Min =

0.78 mm

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