PIC18F4331-I/ML - Microchip Technology

 2010 Microchip Technology Inc. DS30500B-page 1

PIC18F2331/2431/4331/4431

1.0 DEVICE OVERVIEW

This docume nt includes the program ming sp ecifications

for the following devices :

• PIC18F2331

• PIC18F2431

• PIC18F4331

• PIC18F4431

2.0 PROGRAMMING OVERVIEW

OF THE PIC18FXX 31

PIC18FXX3 1 devi ces c an be pro gramm ed usi ng eith er

the high voltage In-Circuit Serial ProgrammingTM

(ICSPTM) method, or the low voltage ICSP method.

Both of these c an be d one with the de vi ce in the us ers ’

system. The low volt a ge ICSP m etho d is sli ght ly dif f er-

ent than the high voltage method, and these differ-

ences are noted where applicable. This programming

specification applies to PIC18FXX31 devices in all

package types.

2.1 Hardware Requirements

In High Voltage IC SP mode , the PIC 18 FXX31 requ ire s

two programmable power supplies: one for VDD and

one for MCLR/VPP. Both supplies should have a

minimum resolution of 0.25V. Refer to Section 6.0 for

additional hardware parameters.

2.1.1 LOW VOLTAGE ICSP

PROGRAMMING

In Low Voltage ICSP mode, the PIC18FXX31 can be

programmed using a VDD source in the operating

range. This only means that MCLR/VPP does not have

to be brought to a different voltage but can instead be

left at the normal operating voltage. Refer to

Section 6.0 for additional hardware parameters.

2.2 Pin Diagrams

The pin diagrams for the PIC18FXX31 family are

shown in Figure 2-1, Figure 2-2, and Figure 2-3. The

pin desc riptions of these dia grams do not represent the

complete functionality of the device types. Users

should refer to the appropriate device data sheet for

complete pin descriptions.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX31

Pin Name During Programming

Pin Name Pin Type Pin Description

MCLR/VPP VPP P Program mi ng Enab le

VDD(2) VDD P Power S upply

VSS(2) VSS P Ground

AVDD AVDD P Analog Power Supply

AVSS AVSS P Analog Ground

RB5 PGM I Low Voltage ICSP™ Input when LVP Configuration bit equals ‘1’ (1)

RB6 SCLK I Serial Clock

RB7 SDATA I/O Serial Data

Legend: I = Input, O = Output, P = Power

Note 1: See Section 5.3 for more detail.

2: All power supply and ground must be connected, including AVDD and AVSS.

Flash Microcontroller Programming Specification

PIC18F2331/2431/4331/4431

DS30500B-page 2  2010 Microchip Technology Inc.

FIGURE 2-1: PIN DIAGRAMS

40-Pin PDIP

28-Pin SDIP, SOIC

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CAP1/INDX

RA3/AN3/VREF+/CAP2/QEA

RA4/AN4/CAP3/QEB

AVDD

AVSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI/T5CKI/INT0

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM(1)

RB4/KBI0/PWM5

RB3/PWM3

RB2/PWM2

RB1/PWM1

RB0/PWM0

VDD

VSS

RC7/RX/DT/SDO

RC6/TX/CK/SS

RC5/INT2/SCK/SCL

RC4/INT1/SDI/SDA

• 1

PIC18F2331/2431

Note 1: Low voltage programming must be enabled.

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM(2)

RB4/KBI0/PWM5

RB3/PWM3

RB2/PWM2

RB1/PWM1

RB0/PWM0

VDD

VSS

RD7/PWM7

RD6/PWM6

RD5/PWM4(4)

RD4/FLTA(3)

RC7/RX/DT/SDO(1)

RC6/TX/CK/SS

RC5/INT2/SCK(1)/SCL(1)

RC4/INT1/SDI(1)/SDA(1)

RD3/SCK/SCL

RD2/SDI/SDA

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CAP1/INDX

RA3/AN3/VREF+/CAP2/QEA

RA4/AN4/CAP3/QEB

RA5/AN5/LVDIN

RE0/AN6

RE1/AN7

RE2/AN8

AVDD

AVSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2/FLTA

RC2/CCP1/FLTB

RC3/T0CKI(1)/T5CKI(1)/INT0

RD0/T0CKI/T5CKI

RD1/SDO

PIC18F4331/4431

Note 1: RC3 is the alternate pin for T0CKI/T5CKI, RC4 is the alternate pin for SDI/SDA, RC5 is the alternate pin

for SCK/SCL.

2: Low voltage programming must be enabled.

3: RD4 is the alternate pin for FLTA.

4: RD5 is the alternate pin for PWM4.

 2010 Microchip Technology Inc. DS30500B-page 3

PIC18F2331/2431/4331/4431

FIGURE 2-2: PIN DIAGRAMS (CONTINUED)

44-Pin TQFP

PIC18F4331

RA3/AN3/VREF+/CAP2/QEB

RA2/AN2/VREF-/CAP1/INDX

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM(2)

RB4/KBI0/PWM5

RC6/TX/CK/SS

RC5/INT2/SCK(1)/SCL(1)

RC4/INT1/SDI(1)/SDA(1)

RD3/SCK/SCL

RD2/SDI/SDA

RD1/SDO

RD0/T0CKI/T5CKI

RC3/T0CKI(1)/T5CKI(1)/INT0

RC2/CCP1/FLTB

RC1/T1OSI/CCP2/FLTA

RC0/T1OSO/T1CKI

OSC2/CLKO/RA6

OSC1/CLKI/RA7

AVSS

AVDD

RE2/AN8

RE1/AN7

RE0/AN6

RA5/AN5/LVDIN

RA4/AN4/CAP3/QEB

RC7/RX/DT/SDO(1)

RD4/FLTA(3)

RD5/PWM4(4)

RD6/PWM6

RD7/PWM7

VSS

VDD

RB0/PWM0

RB1/PWM1

RB2/PWM2

RB3/PWM3

PIC18F4431

Note 1: RC3 is the alternate pin for T0CKI/T5CKI, RC4 is the alternate pin for SDI/SDA, RC5 is the alternate pin

for SCK/SCL.

2: Low voltage programming must be enabled.

3: RD4 is the alternate pin for FLTA.

4: RD5 is the alternate pin for PWM4.

PIC18F2331/2431/4331/4431

DS30500B-page 4  2010 Microchip Technology Inc.

FIGURE 2-3: PIN DIAGRAMS (CONTINUED)

44-Pin QFN

PIC18F4331

RA3/AN3/VREF+/CAP2/QEA

RA2/AN2/VREF-/CAP1/INDX

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

RB3/PWM3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PWM4/PGM(2)

RB4/KBI0/PWM5

RC6/TX/CK/SS

RC5/INT2/SCK(1)/SCL(1)

RC4/INT1/SDI(1)/SDA(1)

RD3/SCK/SCL

RD2/SDI/SDA

RD1/SDO

RD0/T0CKI/T5CKI

RC3/T0CKI(1)/T5CKI(1)/INT0

RC2/CCP1/FLTB

RC1/T1OSI/CCP2/FLTA

RC0/T1OSO/T1CKI

OSC2/CLKO/RA6

OSC1/CLKI/RA7

VSS

VDD

RE2/AN8

RE1/AN7

RE0/AN6

RA5/AN5/LVDIN

RA4/AN4/CAP3/QEB

RC7/RX/DT/SDO(1)

RD4/FLTA(3)

RD5/PWM4(4)

RD6/PWM6

RD7/PWM7

VSS

VDD

AVDD

RB0/PWM0

RB1/PWM1

RB2/PWM2

PIC18F4431

AVSS

Note 1: RC3 is the alternate pin for T0CKI/T5CKI, RC4 is the alternate pin for SDI/SDA, RC5 is the alternate pin

for SCK/SCL.

2: Low voltage programming must be enabled.

3: RD4 is the alternate pin for FLTA.

4: RD5 is the alternate pin for PWM4.

 2010 Microchip Technology Inc. DS30500B-page 5

PIC18F2331/2431/4331/4431

2.3 Memory Map

The code memory sp ace extend s from 0000h to 3FFFh

(16 Kbytes) in four 4-Kbyte blocks. Addresses 0000h

through 01FFh, however, define a “Boot Block” region

that is treated separately from Block 0. All of these

blocks define code protection boundaries within the

code memory space.

In contra st, code memory panels are defined in 8-Kbyte

boundaries. Panels are discussed in greater detail in

Section 3.2.

TABLE 2-2: IMPLEMENTATION OF CODE

MEMORY

FIGURE 2-4: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXX31 DEVICES

Device Code Memory Size (Bytes)

PIC18F2331 000000h - 001FFFh (8K)

PIC18F4331

PIC18F2431 000000h - 003FFFh (16K)

PIC18F4431

000000h

1FFFFFh

3FFFFFh

003FFFh

Note: Sizes of memory areas not to scale.

Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

MEMORY SIZE/DEVICE

8Kbytes

(PIC18FX331) Address

Range

16 Kbytes

(PIC18FX431) Address

Range

Block Code

Protection

Controlled By:

Boot Block 0000h

0FFFh Boot Block 0000h

01FFh CPB, W RTB, EBTRB

Block 0 0200h

0FFFh Block 0 0200h

0FFFh CP0, WRT0, EBTR0

Block 1 1000h

1FFFh Block 1 1000h

1FFFh CP1, WRT1, EBTR1

Unimplemented

Read as ‘0’

Block 2 2000h

2FFFh CP2, WRT2, EBTR2

3FFFh Block 3 3000h

3FFFh CP3, WRT3, EBTR3

PIC18F2331/2431/4331/4431

DS30500B-page 6  2010 Microchip Technology Inc.

In addition to the code memory space, there are three

blocks in the configuration and ID space that are acces-

sible to the user through table reads and table writes.

Their locations in the memory map are shown in

Figure 2-5.

Users may store identification information (ID) in eight

ID registers. These ID registers are mapped in

addresses 200000h thro ugh 200007h. The ID locations

read out n ormally even aft er code protection is applied.

Locations 300000h through 30000Dh are reserved for

the configuration bits. These bits select various device

options and are described in Section 5.0. These

configuration bits read out normally even after code

protection.

Locatio ns 3FFFF Eh and 3FFF FFh are res erved fo r the

device ID bits. Thes e bits may be us ed by the program-

mer to identify what device type is being programmed

and are described in Section 5.0. These device ID bits

read out normal ly even af te r code protec tio n.

2.3.1 M EMORY ADDR ESS POINTER

Memory in the addres s space 000000 0h to 3FFFFFh is

addressed via the table pointer which is comprised of

three pointe r regis ters :

• TBLPTRU, at RAM address 0FF8h

• TBLPTRH, at RAM address 0FF7h

• TBLPTRL, at RAM address 0FF6h

The 4-bit command, ‘0000’ (core instruction), is used to

load the table pointer prior to using many read or write

operations.

FIGURE 2-5: CONFIGURATION AND ID LOCATIONS FOR PIC18FXX31 DEVICES

TBLPTRU TBLPTRH TBLPTRL

Addr[21:16] Addr[15:8] Addr[7:0]

ID Location 1 200000h

ID Location 2 200001h

ID Location 3 200002h

ID Location 4 200003h

ID Location 5 200004h

ID Location 6 200005h

ID Location 7 200006h

ID Location 8 200007h

CONFIG1L 300000h

CONFIG1H 300001h

CONFIG2L 300002h

CONFIG2H 300003h

CONFIG3L 300004h

CONFIG3H 300005h

CONFIG4L 300006h

CONFIG4H 300007h

CONFIG5L 300008h

CONFIG5H 300009h

CONFIG6L 30000Ah

CONFIG6H 30000Bh

CONFIG7L 30000Ch

CONFIG7H 30000Dh

Device ID1 3FFFFE h

Device ID2 3FFFFFh

Note: Sizes of memory areas are not to scale.

000000h

1FFFFFh

3FFFFFh

01FFFFh Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

2FFFFFh

 2010 Microchip Technology Inc. DS30500B-page 7

PIC18F2331/2431/4331/4431

2.4 High Level Overview of the

Programming Process

Figure 2-7 shows the high level overview of the pro-

gramming process. First, a bulk erase is performed.

Next, the code memory, ID locations, and data

EEPROM are programmed. These memories are then

verified to ensure that programming was successful. If

no errors are detected, the configuration bits are then

programmed and verified.

2.5 Entering High Voltage ICSP

Program/Verify Mode

The High Voltage ICSP Program/Verify mode is

entered by holding SCLK and SDATA low and then

raising MCLR/VPP to VIHH (high voltage). Once in this

mode, the code memory, data EEPROM, ID locations,

and configuration bits can be accessed and

programmed in serial fas hion.

The sequ en ce that ente rs t he d ev ic e in to th e Pro gram /

Verify mode places all unused I/Os in the high

impedance state.

2.5.1 ENTERING LOW VOLTAGE ICSP

PROGRAM/VERIFY MODE

When the LVP c onfi gu ratio n bit is ‘1’ (see Sec tion 5.3),

the Low Voltage ICSP mode is enabled. Low Voltage

ICSP Progra m/V erify mod e is entered b y holding SCLK

and SDATA l ow, placing a lo gic h igh on PGM, and the n

raising MCLR/VPP to VIH. In this mode, the RB5/PGM

pin is dedicated to the programming function and

ceases to be a general purpose I/O pin.

The sequ en ce that ente rs t he d ev ic e in to th e Pro gram /

Verify mode places all unused I/Os in the high

impedance state.

FIGURE 2-6: ENTERING HIGH

VOLTAGE PROGRAM/

VERIFY MODE

FIGURE 2-7: HIGH LEVEL

PROGRAMMING FLOW

FIGURE 2-8: ENTERING LOW

VOLTAGE PROGRAM/

VERIFY MODE

MCLR/VPP

P12

SDATA

SDATA = Input

SCLK

VDD

D110

P13

Start

Program Memory

Program IDs

Program Data

Verify Program

Veri fy IDs

Verify Data

Program

Configuration Bits

Verify

Configuration Bits

Done

Perform Bulk

Erase

MCLR/VPP

P12

SDATA

SDATA = Input

SCLK

PGM

P15

VDD

VIH

PIC18F2331/2431/4331/4431

DS30500B-page 8  2010 Microchip Technology Inc.

2.6 Serial Program/Verify Operation

The SCLK pin is used as a clock input pin and the

SDATA pin is used for enterin g comm and bits and da ta

input/output during serial operation. Commands and

data are transmitted on the rising edge of SCLK,

latched on the falling edge of SCLK, and are Least

Significant bit (LSb) first.

2.6.1 4-BIT COMMANDS

All instructions are 20 bits, consisting of a leading 4-bit

command followed by a 16-bit operand, which depends

on the type of command being executed. To input a

command, SCLK is cycled four times. The commands

needed for programming and verification are shown in

Table 2-3.

Depending on the 4-bit command, the 16-bit operand

represents 16 bits of input data, or 8 bits of input data

and 8 bits of output data.

Throughout this specification, commands and data are

presented as illustrated in Table 2-4. The 4-bit

command is shown MSb first. The command operand,

or “Data Payload”, is shown <MSB><LSB>. Figure 2-9

demonstrates how to serially present a 20-bit

command/operand to the device.

2.6.2 CORE INSTRUCTION

The core instruction passes a 16-bit instruction to the

CPU core for execution. This is needed to setup

TABLE 2-3: COMMANDS FOR

PROGRAMMING

TABLE 2-4: SAMPLE COMMAND

SEQUENCE

FIGURE 2-9: TABLE WRITE, POST-INCREMENT TIMING (1101)

Description 4-Bit

Command

Core Instruction

(Shift in16-bit instruction) 0000

Shift out TABLAT register 0010

Table Read 1000

Table Read, post-inc rem en t 1001

Table Read, post-dec rem en t 1010

Table Read, pre-in cre men t 1011

Table Write 1100

Table Write, post-increment by 2 1101

Table Write, pos t-de crement by 2 1110

Table Write, start programming 1111

4-Bit

Command Data

Payload Core Instruction

1101 3C 40 Table Write,

post-increment by 2

1234

SCLK P5

SDATA

SDATA = Input

5678 1234

P5A

910 11 13 15 161412

Fetch Next 4-bit Command

1011

1234

nnnn

P2 P2A

000000 010001111 0

04C3

4-bit Command 16-bit Data Payload

P2B

 2010 Microchip Technology Inc. DS30500B-page 9

PIC18F2331/2431/4331/4431

3.0 DEVICE PROGRAMMING

3.1 High Voltage ICSP Bulk Erase

Erasing code or data EEPROM is accomplished by

writing an “erase option” to address 3C0004h. Code

memory may be erased portions at a time, or the user

may era se th e entir e devi ce in one a ction . “Bulk Erase”

operations will also clear any code protect settings

associated with the memory block erased. Erase

options are detailed in Table 3-1.

TABLE 3-1: BULK ERASE OPTIONS

The actual bulk erase function is a self-timed operation.

Once the erase has started (falling edge of the 4th

SCLK after the NOP command), serial execution will

cease until the erase completes (parameter P11). Dur-

ing this time, SCLK may continue to toggle but SDATA

must be held low.

The code s equence to er ase the entire devic e is shown

in Table 3-2 and the flowchart is shown in Figure 3-1.

TABLE 3-2: BULK ERASE COMMAND

SEQUENCE

FIGURE 3-1: BULK ERASE FLOW

FIGURE 3-2: BULK ERASE TIMING

Description Data

Chip Erase 80h

Erase Data EEPROM 81h

Erase Boot Block 83h

Erase Block 1 88h

Erase Block 2 89h

Erase Block 3 8Ah

Erase Block 4 8Bh

Note: A bulk erase is the only way to reprogram

code protect bits from an on-state to an

off-state.

Non-code protect bits are not returned to

default settings by a bulk erase. These bits

should be programmed to ones, as out-

lined in Section 3.6, “Configuration Bits

Programming”.

4-Bit

Command Data

Payload Core Instruction

0000

1100

0000

0E 3C

6E F8

0E 00

6E F7

0E 04

6E F6

00 80

00 00

MOVLW 3Ch

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 04h

MOVWF TBLPTRL

Write 80h TO 3C0004h to

eras e enti re de vice .

NOP

Hold SDATA low until

erase completes.

Start

Done

Write 80h

to Erase

Entire Device

Load Address

Poi n te r to

3C0004h

Delay P11+P10

Time

1234 121516 123

SCLK

P5 P5A

SDATA

SDATA = Input

00011

P11

P10

Erase Time

00 0 000 0 0

1 2 15 16

123

P5A

0000

4-bit Command 4-bit Command 4-bit Comm an d

16-bit

Data Payload

16-bit

Data Payload 16-bit

Data Payload

PIC18F2331/2431/4331/4431

DS30500B-page 10  2010 Microchip Technology Inc.

3.1.1 LOW VOLTAGE ICSP BULK ER ASE

When using low voltage ICSP, the part must be sup-

plied by the voltage specified in parameter #D111 if a

bulk erase is to be executed. All other bulk erase det ails

as described above apply.

If it is determined that a program memory erase must

be performed at a supply voltage below the bulk erase

limit, refer to the erase methodology described in

Sections 3.1.2 and 3.2.2.

If it is determined that a data EEPROM erase must be

performed at a supply voltage below the bulk erase

limit, follow the methodology described in Section 3.3

and write ones to the array.

3.1.2 ICSP MULTI-PANEL SINGLE ROW

ERASE

Irrespective of whether high or low voltage ICSP is

used, it is possible to erase single row (64 bytes of

data) in all panels at once. For example, in the case of

a 16-Kbyte device (4 panels), 512 bytes through 64

bytes i n each p anel can be era se d s im ul taneou sl y d ur-

ing ea ch erase s eq uen ce. In this c as e, th e off set o f th e

erase within each panel is the same (see Figure 3-5).

Multi-panel single row erase is enabled by appropri-

ately configuring the Programming Control register

located at 3C0006h.

The multi-panel single row erase duration is externally

timed and is controlled by SCLK. After a “Start Pro-

grammi ng” c om man d is is sue d (4-b it, ‘1111’), a NOP is

issued, where the 4th SCLK is held high for the

duration of the programming time, P9.

Aft er SCLK i s b roug ht l ow, the progra mm ing se quence

is terminated. SCLK must be held low for the time spec-

ified by parameter P10 to allow high voltage discharge

of the memory array.

The code sequence to program a PIC18FXX31 device

is shown in Table 3-3. The flowchart shown in

Figure 3-3 depicts the logic necessary to completely

erase a PIC18FXX 31 device. The timing diagram that

details the “Start Programming” command, and

parameters P9 and P10 is shown in Figure 3-6.

Note: The TBLPTR register must contain the

same offset value when initiating the pro-

gramming sequence as it did when the

write buffers were loaded.

 2010 Microchip Technology Inc. DS30500B-page 11

PIC18F2331/2431/4331/4431

TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE

FIGURE 3-3: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW

4-Bit

Command Data Payload Core Instruction

Step 1: Direct access to config memory.

0000

8E A6

8C A6

86 A6

BSF EECON1, EEPGD

BSF EECON1, CFGS

BSF EECON1, WREN

Step 2: Configure device for multi-panel writes.

0000

1100

0E 3C

6E F8

0E 00

6E F7

0E 06

6E F6

00 40

MOVLW 3Ch

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 06h

MOVWF TBLPTRL

Write 40h to 3C0006h to enable multi-panel erase.

Step 3: Direct access to code memory and enable erase.

0000

8E A6

9C A6

88 A6

6A F8

6A F7

6A F6

BSF EECON1, EEPGD

BCF EECON1, CFGS

BSF EECON1, FREE

CLRF TBLPTRU

CLRF TBLPTRH

CLRF TBLPTRL

Step 4: Erase single row of all panels at an offset.

1111

0000

00 00

Write 2 dummy bytes and start programming.

NOP - hold SCLK high for time P9.

Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.

Done

Start

Delay P9 + P10

Time for Erase

to Occ u r

All

Panels

Done?

Yes

Addr = 0

Configure

Device for

Multi-Panel Erase

Addr = Addr + 64

Start Erase Sequence

and hold SCLK High

Until Done

PIC18F2331/2431/4331/4431

DS30500B-page 12  2010 Microchip Technology Inc.

3.2 Code Memory Programming

Programming code memory is accomplished by first

loading dat a int o the appro priate wr ite bu ffe rs an d then

initiating a programming sequence. Each panel in the

code memory space (see Figure 2-4) has an 8-byte

deep w rite buffer that must be load ed pri or to init iat ing

a write sequence. The actual memory write sequence

takes the contents of these buffers and programs the

associated EEPROM code memory.

Typically, all of th e pro gram buf fe rs are w ritten in para l-

lel (Multi-Panel Write mode). In o ther words, in the case

of a 16-Kbyte device (2 panels with an 8-byte buffer per

panel), 16 bytes will be simultaneously programmed

during each programming sequence. In this case, the

offset of the write within each panel is the same (see

Figure 3-4). Multi-Panel Write mode is enabled by

appropriately configuring the Programming Control

The programming duration is externally timed and is

controlled by SCLK. After a “Start Programming” com-

mand is issued (4-bit command, ‘1111’), a NOP is

issued, where the 4th SCLK is held high for the

duration of the programming time, P9.

Aft er SCLK i s b roug ht l ow, the progra mm ing se quence

is terminated. SCLK must be held low for the time spec-

ified by parameter P10 to allow high voltage discharge

of the memory array.

The code sequence to program a PIC18FXX31 device

is shown in Table 3-4. The flowchart shown in

Figure 3-5 depicts the logic necessary to completely

write a PIC18FXX31 device. The timing diagram that

details the “Start Programming” command, and

parameters P9 and P10, is shown in Figure 3-6.

FIGURE 3-4: ERASE AND WRITE BOUNDARIES

Note: The TBLPTR register must contain the

same offset value when initiating the pro-

gramming sequence as it did when the

write buffers were loaded.

TBLPTR<2:0> = 0

TBLPTR<2:0> = 1

TBLPTR<2:0> = 2

TBLPTR<2:0> = 3

TBLPTR<2:0> = 4

TBLPTR<2:0> = 5

TBLPTR<2:0> = 6

TBLPTR<2:0> = 7

Offset = TBLPTR<12:3>

TBLPTR<21:13> = 0

Offset = TBLPTR<12:6>

Panel 1

Erase Region

(64 bytes)

8-byte Write Buffer

TBLPTR<2:0> = 0

TBLPTR<2:0> = 1

TBLPTR<2:0> = 2

TBLPTR<2:0> = 3

TBLPTR<2:0> = 4

TBLPTR<2:0> = 5

TBLPTR<2:0> = 6

TBLPTR<2:0> = 7

Offset = TBLPTR<12:3>

TBLPTR<21:13> = 1

Offset = TBLPTR<12:6>

Panel 2

Erase Region

(64 bytes)

8-byte Write Buffer

Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.

 2010 Microchip Technology Inc. DS30500B-page 13

PIC18F2331/2431/4331/4431

TABLE 3-4: WRITE CODE MEMORY CODE SEQUENCE

4-Bit

Command Data Payload Core Instruction

Step 1: Direct access to config memory.

0000

8E A6

8C A6

86 A6

BSF EECON1, EEPGD

BSF EECON1, CFGS

BSF EECON1, WREN

Step 2: Configure device for multi-panel writes.

0000

1100

0E 3C

6E F8

0E 00

6E F7

0E 06

6E F6

00 40

MOVLW 3Ch

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 06h

MOVWF TBLPTRL

Write 40h to 3C0006h to enable multi-panel writes.

Step 3: Direct access to code memory.

0000

0000 8E A6

9C A6 BSF EECON1, EEPGD

BCF EECON1, CFGS

Step 4: Load write buffer for Panel 1.

0000

1101

1100

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2

Write 2 bytes

Step 5: Repeat for Panel 2.

Step 6: Repeat for all but the last panel (N – 1).

Step 7: Load write buffer for last panel.

0000

1101

1111

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

00 00

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2

Write 2 bytes and start programming

NOP - hold SCLK high for time P9

To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented by 8 in each panel at each iteration of

the loop.

PIC18F2331/2431/4331/4431

DS30500B-page 14  2010 Microchip Technology Inc.

FIGURE 3-5: PROGRAM CODE MEMORY FLOW

FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)

Start Write Sequence

All

Locations

Done?

Done

Start

Yes

Delay P9+P10 Time

for Wr i te to O c cu r

Load 8 Bytes

to Panel N Write

Buffer at <Addr>

All

Panel Buffers

Written?

Yes

and Hold SCLK

High until Done

N = 1

LoopCount = 0

Configure

Device for

Multi-Panel Writes

N = 1

LoopCount =

LoopCount + 1

N = N + 1

Panel Base Address =

(N – 1) x 2000h

Addr = Panel Base Address

+ (8 x LoopCount)

1234 1 2 15 16 123 4

SCLK P5A

SDATA

SDATA = Input

1111

34 65

P10

Programming Time

nnn nn n n 0 0

000

16-bit

Data Payload

4-bit Comman d 16-bit Dat a Payload 4-bit Command

 2010 Microchip Technology Inc. DS30500B-page 15

PIC18F2331/2431/4331/4431

3.2.1 SINGLE PANEL PROGRAMMING

The programming example presented in Section 3.2

utilizes multi-panel programming. This technique

greatly decreases the tot al amount of t ime necessary to

completely program a device and is the recommended

method of com pl etel y prog ram mi ng a devi ce .

There m ay be situatio ns , h ow ev er, wher e i t i s adv an ta-

geous to limit writes to a single panel. In such cases,

the user only needs to disable the multi-panel write

feature of the device by appropriately configuring the

Programming Control register located at 3C0006h.

The single panel that will be written will automatically

be enabled based on the value of the table pointer.

3.2.2 MODIFYING CODE MEMORY

All of the programming examples up to this point have

assum ed tha t the dev ic e has bee n bulk er ased prior to

programming (see Section 3.1). It may be the case,

however, that the user wishes to modify only a section

of an already programmed device.

The minim um am ount of dat a that c an be wri tten to the

device is 8 bytes. This is accomplished by placing the

device i n Single Pan el Wr ite m ode (s ee Sec ti on 3.2. 1),

loading the 8-byte write buffer for the panel, and then

initiating a write sequence. In this case, however, it is

assumed that the address space to be written already

has data in it (i.e., it is not blank).

The minimum amount of code memory that may be

erased at a given time is 64 bytes. Again, the device must

be placed in Single Panel Write mode. The EECON1

space prior to writing the data.

When using the EECON1 register to act on code

memory, the EEPGD bit must be set (EECON1<7> = 1)

and the CFGS bit must be cleared (EECON1<6> = 0).

The WREN bit must be set (EECON1<2> = 1) to

enable writes of any sort (e.g., erases), and this must

be done prior to initiating a write sequence. The FREE

bit must be set (EECON1<4 > = 1) in order to erase the

program space being pointed to by the table pointer.

The erase sequence is initiated by the setting the WR

bit (EECON1 <1> = 1). It is stro ngly recommended that

the WREN bit be set only w hen absol ute ly neces s ary.

To help prevent inadvertent writes when using the

EECON1 re gister , EECON2 is used to “ena ble” the WR

bit. This register must be sequentially loaded with 55h

and then AAh, immediately prior to asserting the WR bit

in order for the write to occur.

The erase will begin on the falling edge of the 4th SCLK

after the WR bit is set. After the erase sequence termi-

nates, SCLK must still be held low for the time specified

by parameter #P10 to allow high voltage discharge of

the memory array.

Note: Even though multi-panel writes are dis-

abled, the user must still fill the 8-byte

write buffer for the given panel.

PIC18F2331/2431/4331/4431

DS30500B-page 16  2010 Microchip Technology Inc.

TABLE 3-5: MODIFYING CODE MEMORY

4-Bit

Command Data Payload Core Instruction

Step 1: Direct access to config memory.

0000

0000 8E A6

8C A6 BSF EECON1, EEPGD

BSF EECON1, CFGS

Step 2: Configure device for single panel writes.

0000

1100

0E 3C

6E F8

0E 00

6E F7

0E 06

6E F6

00 00

MOVLW 3Ch

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 06h

MOVWF TBLPTRL

Write 00h to 3C0006h to enable single panel writes.

Step 3: Direct access to code memory.

0000

0000 8E A6

9C A6 BSF EECON1, EEPGD

BCF EECON1, CFGS

Step 4: Set the table pointer for the block to be erased.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[8:15]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[8:15]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 5: Enable memory writes and set up an erase.

0000

0000 84 A6

88 A6 BSF EECON1, WREN

BSF EECON1, FREE

Step 6: Perform required sequence.

0000

0E 55

6E A7

0E AA

6E A7

MOVLW 55h

MOVWF EECON2

MOVLW 0AAh

MOVWF EECON2

Step 7: Initiate erase.

0000

0000 82 A6

00 00 BSF EECON1, WR

NOP

Step 8: Wait for P11+P10 and then disable writes.

0000 94 A6 BCF EECON1, WREN

Step 9: Load write buffer for panel. The correct panel will be selected based on the table pointer.

0000

1101

1111

0000

0E <Addr[8:15]>

6E F7

0E <Addr[7:0]>

6E F6

00 00

MOVLW <Addr[8:15]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2

Write 2 bytes and start programming

NOP - hold SCLK high for time P9

To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.

 2010 Microchip Technology Inc. DS30500B-page 17

PIC18F2331/2431/4331/4431

3.3 Data EEPROM Programming

Data EEPROM is accessed one byte at a time via an

Address Poin ter (register pair EEADR:EEADRH) and a

data latch (EEDA TA). Dat a EEPROM is written by loa d-

ing EEADR:EEADRH with the desired memory loca-

tion, EEDATA with the data to be written, and initiating

a memory write by appropriately configuring the

EECON1 and EECON2 registers. A byte write auto-

matically erases the location and writes the new data

(erase-before-write).

When using the EECON1 register to perform a data

EEPROM write, both the EEPGD and CFGS bits must

be cleared (EECON1<7:6> = 00). The WREN bit must

be set (EEC ON1< 2> = 1) to enable writes of any sort,

and this must be done prior to initiating a write

sequen ce. The write sequence is initiated by setting the

WR bit (EECON1<1> = 1). It is strongl y recom me nde d

that the WREN bit be set only when absolutely

necessary.

To help prevent inadvertent writes when using the

EECON1 re gister , EECON2 i s used to “enable ” the WR

bit. This register must be sequentially loaded with 55h

and then AAh, immediately pri or to asserting the WR bit

in order for the write to occur.

The write begins on the falling edge of the 4th SCLK

after the WR bit is set. It ends when the WR bit is

cleared by hardware.

After the programming sequence terminates, SCLK

must still be held low for the time specified by

parameter P10 to allow high voltage discharge of the

memory array.

FIGURE 3-7: PROGRAM DATA FLOW

FIGURE 3-8: DATA EEPROM WRITE TIMING

Start

St ar t Write

Set Data

Done

Yes

Done

Enable Write

Unlock Sequence

55h - EECON2

AAh - EECON2

Sequence

Set Address

WR bit

Clear ? No

Yes

SCLK

SDATA

SDATA = Input

0000

BSF EECON1, WR

4-bit Command

1234 121516

P5 P5A

P10

Poll WR bit, Repeat until Clear 16-bit Data

Payload

1234 121516 123

P5 P5A

41 2 15 16

P5 P5A

0000

MOVF EECON1, W, 0

4-bit Command

0000

4-bit Command Shift Out Data

MOVWF TABLAT

SCLK

SDATA

(see below)

(see Figu re 4-4 )

SDATA = Input SDATA = Output

Poll WR bit

PIC18F2331/2431/4331/4431

DS30500B-page 18  2010 Microchip Technology Inc.

TABLE 3-6: PROGRAMMING DATA MEMORY

4-Bit

Command Data Payload Core Instruction

Step 1: Direct access to data EEPROM .

0000

0000 9E A6

9C A6 BCF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Set the data EEPROM Address P ointer.

0000

0E <Addr>

6E A9

OE <AddrH>

6E AA

MOVLW <Addr>

MOVWF EEADR

MOVLW <AddrH>

MOVWF EEADRH

Step 3: Load the data to be written.

0000

0000 0E <Data>

6E A8 MOVLW <Data>

MOVWF EEDATA

Step 4: Enable memory writes.

0000 84 A6 BSF EECON1, WREN

Step 5: Perform required sequence.

0000

0E 55

6E A7

0E AA

6E A7

MOVLW 0X55

MOVWF EECON2

MOVLW 0XAA

MOVWF EECON2

Step 6: Initiate write.

0000 82 A6 BSF EECON1, WR

Step 7: Poll WR bit, repeat until the bit is clear.

0000

0010

50 A6

6E F5

MOVF EECON1, W, 0

MOVWF TABLAT

Shift out data(1)

Step 8: Disable writes.

0000 94 A6 BCF EECON1, WREN

Repeat steps 2 through 8 to write more data.

Note 1: See Figure 4-4 for details on shift out data timing.

 2010 Microchip Technology Inc. DS30500B-page 19

PIC18F2331/2431/4331/4431

3.4 ID Location Programming

The ID locations are programmed much like the code

memory except that multi-panel writes must be dis-

abled. The sin gle p anel that will be writ ten wil l autom at-

ically be enabled based on the value of the table

pointer. The ID registers are mapped in addresses

200000h through 200007h. These locations read out

normally even after code protect ion.

Table 3-7 demonst rates the cod e sequence requ ired to

write the ID locations.

TABLE 3-7: WRITE ID SEQUENCE

In order to modif y the ID l ocations , refer to the me thod-

ology described in Section 3.2.2, “Modifying Code

Memory”. As with code memory, the ID locations must

be erased before modifi ed.

Note: Even though multi-panel writes are dis-

abled, t he user mus t still fil l the 8-byte data

buffer for the panel.

4-Bit

Command Dat a Payload Core Instruction

Step 1: Direct access to config memory.

0000

0000 8E A6

8C A6 BSF EECON1, EEPGD

BSF EECON1, CFGS

Step 2: Configure device for single panel writes.

0000

1100

0E 3C

6E F8

0E 00

6E F7

0E 06

6E F6

00 00

MOVLW 3Ch

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 06h

MOVWF TBLPTRL

Write 00h to 3C0006h to enable single panel writes.

Step 3: Direct access to code memory.

0000

0000 8E A6

9C A6 BSF EECON1, EEPGD

BCF EECON1, CFGS

Step 4: Load write buffer. Panel will be automatically determined by address.

0000

1101

1111

0000

0E 20

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

MOVLW 20h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 00h

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2

Write 2 bytes and start programming

NOP - hold SCLK high for time P9

PIC18F2331/2431/4331/4431

DS30500B-page 20  2010 Microchip Technology Inc.

3.5 Boot Block Programming

The boot block segment is programmed in exactly the

same manner as the ID locations (see Section 3.4).

Multi-panel writes must be disabled so that only

address es in the rang e 000 0h to 01 FFh wil l be wr itte n.

The code sequence detailed in Table 3-7 should be

used, ex cept t hat the addres s dat a use d in “Step 2” will

be in the range 000000h to 0001FFh.

3.6 Configuration Bits Programming

Unlike code memory, the configuration bits are

programmed a byte at a time. The “Table Write, Begin

Programming” 4-bit command (1111) is used but only

8 bits of the following 16-bit payload will be written. The

LSB of the payload will be written to even addresses,

and the MSB will be wr itten to odd addresses. The c ode

sequence to program two consecutive configuration

locations is shown in Table 3-8.

TABLE 3-8: SET ADDRESS POINTER TO CONFIGURATION LOCATION

FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW

4-Bit

Command Dat a Payload Core Instruction

Step 1: Direct access to config memory.

0000

0000 8E A6

8C A6 BSF EECON1, EEPGD

BSF EECON1, CFGS

Step 2: Position the program counter(1).

0000

0000 EF 00

F8 00 GOTO 100000h

Step 3(2): Set table pointer for config byte to be written. Write even/odd addresses.

0000

1111

0000

1111

0000

0E 30

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

2A F6

00 00

MOVLW 30h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPRTH

MOVLW 00h

MOVWF TBLPTRL

Load 2 bytes and start programming

NOP - hold SCLK high for time P9

INCF TBLPTRL

Load 2 bytes and start programming

NOP - hold SCLK high for time P9

Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of

code protection logic may prevent further table write. To avoid this situation, move the program counter outside the

code protection area (e.g., GOTO 100000h).

2: Enabling the write protection of configuration bit s (WRTC = 0 in CONFIG6H) will prevent further writing of configuration

bits. Always write all the configuration bits before enabling the write protection for configuration bits.

Load Even

Configuration

Start

Program Program

MSB

Done

Delay P9 Time

for Writ e

Delay P9 Time

for Wr i te

LSB

Load Odd

Configuration

Address Address

Done

Start

 2010 Microchip Technology Inc. DS30500B-page 21

PIC18F2331/2431/4331/4431

4.0 READING THE DEVICE

4.1 Read Code Memory, ID Locations,

and Configurati on Bits

Code memory is accessed one byte at a time via the

4-bit command, ‘1001’ (table read, post-increment).

The conte nt s of memory pointe d to by the t able po inter

(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the

table latch and then serially output on SDATA.

The 4-bit command is shifted in LSb first. The table

read is executed during the next 8 clocks, then shifted

out on SDATA during the last 8 clocks, LSb to MSb. A

delay of P6 mu st be introduc ed af ter the fall ing edg e of

the 8th SCLK of the operand to allow SDATA to transi-

tion from an input to an output. During this time, SCLK

must be held low (see Figure 4-1). This operation also

increments the table pointer by one, po inting to the next

byte in code memory for the next read.

This technique will work to read any memory in the

000000h to 3FFFFF h a ddre ss s pace, s o i t a ls o a ppl ie s

to the reading of the ID and Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)

4-Bit

Command Data Payload Core Instruction

Step 1: Set table pointer.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW Addr[21:16]

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 2: Read memory into table latch and then shift out on SDATA, LSb to MSb.

1001 00 00 TBLRD *+

1234

SCLK P5

SDATA

SDATA = Input

Shift Data Out

SDATA = Output

5678 1234

P5A

910 11 13 15 161412

Fetch Next 4-bit Command

1001

SDATA = Input

LSb MSb

123456

1234

nnnn

P14

PIC18F2331/2431/4331/4431

DS30500B-page 22  2010 Microchip Technology Inc.

4.2 Verify Code Memory and ID

Locations

The veri fy step invo lves read ing back the code memo ry

space and comparing against the copy held in the pro-

gramme r’s buf fer. Memory reads occ ur a singl e byte at

a time, so two bytes must be read to compare against

the word in the programmer’s buffer. Refer to

Section 4.1 for implementation details of reading code

memory.

The table pointer must be manually set to 200000h

(base add ress of the ID loc ations) on ce the code mem-

ory has been verified. The post-increment feature of

the t able read 4-b it command ma y not be used to incre-

ment the t able pointe r beyond the co de memory sp ace.

In a 16-Kbyte device, for example, a post-increment

read of address 3FFFh w il l wrap the table poi nter b ac k

to 0000h, rather than point to unimplemented address

4000h.

FIGURE 4-2: VERIFY CODE MEMORY FLOW

Read Low Byte

Read High byte

Does

Word = Expect

Data? Failure,

Report

Error

All

Code Memory

Verified?

Yes

Set Po i nter = 0

Start

Set Pointer = 200000h

Yes

Read Low Byte

Read High byte

Does

Word = Expect

Data? Failure,

Report

Error

All

ID Locations

Verified?

Yes

Done

Yes

 2010 Microchip Technology Inc. DS30500B-page 23

PIC18F2331/2431/4331/4431

4.3 Verify Configuration Bits

A configuration address may be read and output on

SDATA via the 4-bit command, ‘1001’. Configuration

data is read and written in a byte-wise fashion, so it is

not nec essary t o merg e two by tes into a word p rior to a

compare. The result may then be immediately

compared to the appropriate configuration data in the

programmer’s memory for verification. Refer to

Section 4.1 for implementation details of reading

configu r ati on data.

4.4 Read Data EEPROM Memory

Data EEPROM is accessed one byte at a time via an

Address Poin ter (register pair EEADR:EEADRH) and a

data latch (EEDATA). Dat a EEPROM is read by loading

EEADR:EEADRH with the desired memory location

and initi ating a m emory read by approp riat ely con figur-

ing the EECON1 register. The data will be loaded into

EEDATA, where it may be se rially outpu t on SDATA via

the 4- bit com mand, ‘0010’ (Shif t O ut Dat a H oldin g reg-

ister). A delay of P6 must be i ntroduced af ter t he fal ling

edge of the 8th SCLK of the op erand to allow SDATA to

transition from an input to an output. During this time,

SCLK must be held low (see Figure 4-4).

The command sequence to read a single byte of data

is shown in Table 4-2.

FIGURE 4-3: READ DATA E EPROM

FLOW

Start

Set

Address

Read

Byte

Done

Yes

Done

Move to TABLAT

Shift Ou t D a ta

PIC18F2331/2431/4331/4431

DS30500B-page 24  2010 Microchip Technology Inc.

TABLE 4-2: READ DATA EEPROM MEMORY

FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)

4-Bit

Command Data Payload Core Instruction

Step 1: Direct access to data EEPROM .

0000

0000 9E A6

9C A6 BCF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Set the data EEPROM Address P ointer.

0000

0E <Addr>

6E A9

OE <AddrH>

6E AA

MOVLW <Addr>

MOVWF EEADR

MOVLW <AddrH>

MOVWF EEADRH

Step 3: Initiate a memory read.

0000 80 A6 BSF EECON1, RD

Step 4: Load data into the Serial Data Holding register.

0000

0010

50 A8

6E F5

MOVF EEDATA, W, 0

MOVWF TABLAT

Shift Out Data(1)

Note 1: The <LSB> is undefined. The <MSB> is the data.

1234

SCLK P5

SDATA

SDATA = Input

Shift Data Out

SDATA = Output

5678 1234

P5A

91011 13 15161412

Fetch Next 4-bit Command

0100

SDATA = Input

LSb MSb

123456

1234

nnnn

P14

 2010 Microchip Technology Inc. DS30500B-page 25

PIC18F2331/2431/4331/4431

4.5 Verify Data EEPROM

A data EEPROM add res s may b e re ad via a se qu enc e

of core instructions (4-bit command, ‘0000’) and then

output on SDATA via the 4-bit command, ‘0010’ (Shift

Out Data Holding register). The result may then be

immediately compared to the appropriate data in the

programmer’s memory for verification. Refer to

Section 4.4 for implementation details of reading data

EEPROM.

4.6 Blank Check

The term “Blank C heck” me ans to ve rify that the device

has no p ro gra mm ed m em ory ce lls . Al l me mo rie s must

be verif ied: code me mory, data EEPROM, ID locations ,

and configuration bits. The Device ID registers

(3FFFFEh:3FFFFFh) should be ignored.

A “blank” or “erased” memory cell will read as a ‘1’. So,

“Blank Checking” a device merely means to verify that

all bytes read as FFh except the configuration bits.

Unused (reserved) configuration bits will read ‘0’ (pro-

grammed). Refer to Table 5-2 and Table 5-3 for blank

configuration expect data for the various PIC18FXX31

devices.

Given that “Blank Checking” is merely code and data

EEPROM verification with FFh expect data, refer to

Section 4.4 a nd Secti on 4.2 for impl emen tati on det ails .

FIGURE 4-5: BLANK CHECK FLOW

Yes

Start

Blank Check Device

Device

Blank? Continue

Abort

PIC18F2331/2431/4331/4431

DS30500B-page 26  2010 Microchip Technology Inc.

5.0 CONFIGURATION WORD

The PIC18FXX31 devices have several configuration

words. These bits can be set or cleared to select vari-

ous device configurations. All other memory areas

should be programmed and verified prior to setting con-

figuration words. These bits may be read out normally

even after read or code protection.

5.1 ID Locations

A user may sto re ide ntif ic atio n inf orm atio n (ID ) in eig ht

ID locations mapped in 200000h:200007h. It is recom-

mended that the Most Significant nibble of each ID be

0Fh. In doing so, if the user code inadvertently tries to

execute from the ID space, the ID data will execute as

NOP.

5.2 Device ID W ord

The device ID word for the PIC18FXX31 is located at

3FFFFEh:3FFFFFh. These bits may be used by the

programmer to identify what device type is being

programmed and read out normally even after code or

read protect ion .

5.3 Low Voltage Programming (LVP)

Bit

The LVP bit in Configuration register, CONFIG4L,

enables low voltage ICSP programming. The LVP bit

defaults to a ‘1’ from the factory.

If Low V ol tage Program ming mode is no t used, the L V P

bit can be pro grammed to a ‘0’ and RB5/PGM becomes

a digital I/O pi n. Ho wev er, the LVP b it may o nly b e p ro-

grammed by entering the High Voltage ICSP mode,

where M CLR/VPP is raised to VIHH. Once the LVP bit i s

progra mmed to a ‘0’, only t he Hi gh Voltage ICSP mod e

is available and only the High Voltage ICSP mode can

be used to program the device.

TABLE 5-1: DEVICE ID VALUES

Note 1: The normal ICSP mode is always avail-

able, regardless of the state of the LVP

bit, by applying VIHH to the MCLR/VPP

pin.

2: While in Low Voltage ICSP mode, the

RB5 pin can no longer be used as a

general purp os e I/O.

Device Device ID Value

DEVID2 DEVID1

PIC18F2331 08h E0h

PIC18F2431 08h C0h

PIC18F4331 08h A0h

PIC18F4431 08h 80h

Note: The ‘x’s in DEVID1 contain the device revision code.

 2010 Microchip Technology Inc. DS30500B-page 27

PIC18F2331/2431/4331/4431

TABLE 5-2: PIC18FX431 CONFIGURATION BITS AND DEVICE IDS

TABLE 5-3: PIC18FX331 CONFIGURATION BITS AND DEVICE IDS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogrammed

Value

300001h CONFIG1H IESO FCMEM ——FOSC3FOSC2FOSC1FOSC01100 1111

300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN 0000 1111

300003h CONFIG2H —— WINEN WDPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 0011 1111

300004h CONFIG3L ——T5RENHPOL LPOL PWMPIN — — 0011 1100

300005h CONFIG3H MCLRE —— EXCLKMX PWM4MX SSPMX —FLTAMX1001 1101

300006h CONFIG4L DEBUG — — — —LVP —STVREN1000 0101

300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 0000 1111

300009h CONFIG5H CPD CPB — — — — — — 1100 0000

30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 0000 1111

30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 1110 0000

30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 0000 1111

30000Dh CONFIG7H —EBTRB — — — — — — 0100 0000

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1

3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.

Shaded cells are unimplemented, read as ‘0’.

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogrammed

Value

300001h CONFIG1H IESO FCMEM ——FOSC3FOSC2FOSC1FOSC01100 1111

300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN 0000 1111

300003h CONFIG2H —— WINEN WDPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 0011 1111

300004h CONFIG3L ——T5RENHPOL LPOL PWMPIN — — 0011 1100

300005h CONFIG3H MCLRE —— EXCLKMX PWM4MX SSPMX —FLTAMX1001 1101

300006h CONFIG4L DEBUG — — — —LVP —STVREN1000 0101

300008h CONFIG5L — — — — — —CP1CP00000 0011

300009h CONFIG5H CPD CPB — — — — — — 1100 0000

30000Ah CONFIG6L — — — — — — WRT1 WRT0 0000 0011

30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 1110 0000

30000Ch CONFIG7L — — — — — —EBTR1EBTR00000 0011

30000Dh CONFIG7H —EBTRB — — — — — — 0100 0000

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1

3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.

Shaded cells are unimplemented, read as ‘0’.

PIC18F2331/2431/4331/4431

DS30500B-page 28  2010 Microchip Technology Inc.

TABLE 5-4: PIC18FXX31 CONFIGURATION BIT DESCRIPTIONS

Bit Name Configuration

Words Description

IESO CONFIG1H Internal External Switch Over bit

1 = Internal External Switch Over mode enabled

0 = Internal External Switch Over mode disabled

FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

FOSC<3:0> CONFIG1H Oscillator Selection bits

11xx = External RC oscillator, CLKO function on RA6

101x = External RC oscillator, CLKO function on RA6

1001 = Internal RC oscillator, CLKO function on RA6, and port function on RA7

1000 = Internal RC oscillator, port function on RA6, and port function on RA7

0111 = External RC oscillator, port function on RA6

0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)

0101 = EC oscillator, port function on RA6

0100 = EC oscillator, CLKO function on RA6

0011 = External RC oscillator, CLKO function on RA6

0010 = HS oscillator

0001 = XT oscillator

0000 = LP oscillator

BORV<1:0> C ONFIG2L Brown-out Reset Vo ltage bits

11 =V

BOR set to 2.0V

10 =V

BOR set to 2.7V

01 =V

BOR set to 4.2V

00 =V

BOR set to 4.5V

BOREN CONFIG2L Brown-out Reset Enable bit

1 = Brown-out Reset enabled

0 = Disabled

PWRTEN CONFIG2L Power-up Timer Enable bit

1 = PWRT disabled

0 = Enabled

Note 1: Polarity control bits HPOL and LPOL define PWM signal output active and inactive states, PWM states

generated by the fault inputs or PWM manual override.

2: PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices.

3: When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices)

and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is

defined by HPOL and LPOL.

4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’).

5: For PIC18FX431 devices only.

 2010 Microchip Technology Inc. DS30500B-page 29

PIC18F2331/2431/4331/4431

WINEN CONFIG2H Watchdog Timer Window Enable bit

1 = Enable window comp ari so n

0 = Disable window comparison

WDPS<3:0> CONFIG2H Watchdog Timer Postscale Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

WDTEN CONFIG2H Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on the SWDTEN bit in WDTCON register)

GPTREN CONFIG3L GPT Reset upon CAP1 Special Event Trigger bit

1 = Special Event Reset enable (RESEN in TMR5CON register) is inactive.

0 = Special Event Reset enable (RESEN in TMR5CON register) is active and

can enable the special event trigger signal from IC1 to reset the TMR5 time

base.

HPOL(1) CONFIG3L High Side Transistors Polarity bit (i.e., Odd PWM Output Polarity Control bit )

1 = PWM 1, 3, 5, and 7 are active high (default)

0 = PWM 1, 3, 5, and 7 are active low

LPOL(1) CONFIG3L Low Side Transistors Polarity bit (i.e., Even PWM Output Polarity Control bit)

1 = PWM 0, 2, 4, and 6 are active high (default)

0 = PWM 0, 2, 4, and 6 are active low

PWMPIN(2) CONFIG3L PWM Output Pins RESET State Control bit

1 = PWM outputs disabled upon RESET (default)

0 = PWM outputs drive active states upon RESET(3)

TABLE 5-4: PIC18FXX31 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

Note 1: Polarity control bits HPOL and LPOL define PWM signal output active and inactive states, PWM states

generated by the fault inputs or PWM manual override.

2: PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices.

3: When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices)

and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is

defined by HPOL and LPOL.

4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’).

5: For PIC18FX431 devices only.

PIC18F2331/2431/4331/4431

DS30500B-page 30  2010 Microchip Technology Inc.

MCLRE CONFIG3H MCLR Pin Enable bit

1 = MCLR pin enabled; RE3 input pin disabled

0 = RE3 input pin enabled; MCLR disabled

EXCLKMX(4) CONFIG3H TMR0/GPCKI External Clock Mux bit

1 = TMR0/T5CKI external clock input is multiplexed with RC3

0 = TMR0/T5CKI external clock input is multiplexed with RD0

PWM4MX(4) CONFIG3H PWM4 Mux bit

1 = PWM4 output is multiplexed with RB5

0 = PWM4 output is multiplexed with RD5

SSPMX(4) CONFIG3H SSP I/O Mux bit

1 = SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4,

respectively. SDO output is multiplexed with RC7.

0 = SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2,

respectively. SDO output is multiplexed with RD1.

FLTAMX(4) CONFIG3H FLTA Mux bit

1 = FLTA input is multiplexed with RC1

0 = FLTA input is multiplexed with RD4

BKBUG CONFIG4L Background Debugger Enable bit

1 = Background debugger disabled (RB6,RB7 have I/O port function)

0 = Background debugger functions enabled (RB6, RB7 have ICSP serial

communication function)

LVP CONFIG4L Low Voltage Programming Enable bit

1 = Low voltage programming enabled

0 = Low voltage programming disabled

STVREN CONFIG4L Stack Overflow Reset Enable bit

1 = RESET on stack overflow/underflow enabled

0 = RESET on stack overflow/underflow disabled

CP3(5) CONFIG5L Code Protecti on bit

1 = Block 3 (003000h-003FFFh) not code protected

0 = Block 3 (003000h-003FFFh) code protected

CP2(5) CONFIG5L Code Protecti on bit

1 = Block 2 (002000h-002FFFh) not code protected

0 = Block 2 (002000h-002FFFh) code protected

CP1 CONFIG5L Code Protection bit

1 = Block 1 (001000h-001FFFh) not code protected

0 = Block 1 (001000h-001FFFh) code protected

CP0 CONFIG5L Code Protection bit

1 = Block 0 (000200h-000FFFh) not code protected

0 = Block 0 (000200h-000FFFh) code protected

TABLE 5-4: PIC18FXX31 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

Note 1: Polarity control bits HPOL and LPOL define PWM signal output active and inactive states, PWM states

generated by the fault inputs or PWM manual override.

2: PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices.

3: When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices)

and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is

defined by HPOL and LPOL.

4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’).

5: For PIC18FX431 devices only.

 2010 Microchip Technology Inc. DS30500B-page 31

PIC18F2331/2431/4331/4431

CPD CONFIG5H Code Protection bit Data EEPROM

1 = Data EEPROM not code protected

0 = Data EEPROM code protected

CPB CONFIG5H Code Protection bit

1 = Boot block (000000-0001FFh) not code protected

0 = Boot block (000000-0001FFh) code protected

WRT3(5) CONFIG6L Write Protect i on bit

1 = Block 3 (003000h-003FFFh) not write protected

0 = Block 3 (003000h-003FFFh) write protected

WRT2(5) CONFIG6L Write Protect i on bit

1 = Block 2 (002000h-002FFFh) not write protected

0 = Block 2 (002000h-002FFFh) write protected

WRT1 CONFIG6L Write Protec tion bit

1 = Block 1 (001000h-001FFFh) not write protected

0 = Block 1 (001000h-001FFFh) write protected

WRT0 CONFIG6L Write Protec tion bit

1 = Block 0 (000200h-000FFFh) not write protected

0 = Block 0 (000200h-000FFFh) write protected

WRTD CONFIG6H Write Protection bit Data EEPROM

1 = Data EEPROM not write protected

0 = Data EEPROM write protected

WRTB CONFIG6H Write Protectio n bit

1 = Boot block (000000h-0001FFh) not write protected

0 = Boot block (000000h-0001FFh) write protected

WRTC CONFIG6H Write Protection bi t(1)

1 = Configuration registers (300000h-3000FF) not write protected

0 = Configuration registers (300000h-3000FF) write protected

TABLE 5-4: PIC18FXX31 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

Note 1: Polarity control bits HPOL and LPOL define PWM signal output active and inactive states, PWM states

generated by the fault inputs or PWM manual override.

2: PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices.

3: When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices)

and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is

defined by HPOL and LPOL.

4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’).

5: For PIC18FX431 devices only.

PIC18F2331/2431/4331/4431

DS30500B-page 32  2010 Microchip Technology Inc.

EBTR3(5) CONFIG7L Table Read Pr otection bit

1 = Block 3 (003000h-003FFFh) not protected from table reads executed in

other blocks

0 = Block 3 (003000h-003FFFh) protected f rom tab le read s executed in other

blocks

EBTR2(5) CONFIG7L Table Read Pr otection bit

1 = Block 2 (002000h-002FFFh) not protected from table reads executed in

other blocks

0 = Block 2 (002000h-002FFFh) protected f rom tab le read s executed in other

blocks

EBTR1 CONFIG7L Table Read Protection bit

1 = Block 1 (001000h-001FFFh) not protected from table reads executed in

other blocks

0 = Block 1 (001000h-001FFFh) protected f rom tab le read s executed in other

blocks

EBTR0 CONFIG7L Table Read Protection bit

1 = Block 0 (000200h-000FFFh) not protected from table reads executed in

other blocks

0 = Block 0 (000200h-000FFFh) protected f rom tab le read s executed in other

blocks

EBTRB CONFIG 7H Table Read Protection bit

1 = Boot block (000000h-0001FFh) not protected from table reads executed in

other blocks

0 = Boot block (000000h-0001FFh) protected from table reads executed in

other blocks

DEV<2:0> DEVID1 Device ID bits

These bits are used with the DEV<10:3> bits in the Device ID Register 2 to

identify the part number.

REV<4:0> DEVID1 Revision ID bits

These bits are used to indicate the device revision.

DEV<10:3> DEVID2 Device ID bits

These bits are used with the DEV<2:0> bits in the Device ID Register 1 to

identify the part number.

TABLE 5-4: PIC18FXX31 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

Note 1: Polarity control bits HPOL and LPOL define PWM signal output active and inactive states, PWM states

generated by the fault inputs or PWM manual override.

2: PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices.

3: When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices)

and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is

defined by HPOL and LPOL.

4: This bit is reserved on PIC18F2X31 devices and should be maintained set (i.e., equal to ‘1’).

5: For PIC18FX431 devices only.

 2010 Microchip Technology Inc. DS30500B-page 33

PIC18F2331/2431/4331/4431

5.4 Embedding Configuration Word

Info rmation in th e H E X Fi le

To allow portability of code, a PIC18FXX31 program-

mer is required to read the co nfiguration word loc ations

from the HEX file. If configuration word information is

not present in the HEX file, then a simple warning mes-

sage should be issued. Similarly, while saving a HEX

file, all configuration word information must be

included. An option to not include the configuration

word information may be provided. When embedding

configu ration word information in the HEX file, it shoul d

start at address 300000h.

Microchip Technology Inc. feels strongly that this

featur e is imp orta nt for th e bene fit of t he end cu stome r.

5.5 Checksum Comput ation

The check s um is cal cu lat ed by sum mi ng the foll owing:

• The conte nts of all code memory locat ions

• The configuration word, appropriately masked

• ID locations

The Least Significant 16 bits of this sum are the

checksum.

Table 5-5 (pages 34 through 36) describes how to

calculate the checksum for each device.

Note 1: The checksum calculation differs depend-

ing on the code protect setting. Since the

code memory locations read out differ-

ently depending on the code protect set-

ting, the table describes how to

manipulate the actual code memory val-

ues to simulate the values that would be

read from a protected device. When cal-

culatin g a chec ksum by readi ng a dev ice,

the entire code memory can simply be

read and summed. The configuration

word and ID locations can always be

read.

PIC18F2331/2431/4331/4431

DS30500B-page 34  2010 Microchip Technology Inc.

TABLE 5-5: CHECKSUM COMPUTATION

Device Code

Protect Checksum Blank

Value

0xAA at 0

and Max

Address

PIC18F2331

None SUM(0000:01FF)+SUM(0200:0FFF)+SUM(1000:1FFF)+

(CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 00C0)+(CONFIG10 & 0003)+(CONFIG11 & 00E0)+

(CONFIG12 & 0003)+(CONFIG13 & 0040)

E464 E3BA

Boot

Block SUM(0200:0FFF)+SUM(1000:1FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 000F)+(CONFIG3 & 003F)+

(CONFIG4 & 003C)+(CONFIG5 & 009D)+(CONFIG6 & 0085)+

(CONFIG7 & 0000)+(CONFIG8 & 0003)+(CONFIG9 & 00C0)+

(CONFIG10 & 0003)+(CONFIG11 & 00E0)+(CONFIG12 & 0003)+

(CONFIG13 & 0040)+SUM(IDs)

E640 E5F5

Boot

Block/

Block 0

(CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 00C0)+(CONFIG10 & 0003)+(CONFIG11 & 00E0)+

(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

043D 0447

All (CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 00C0)+(CONFIG10 & 0003)+(CONFIG11 & 00E0)+

(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

043D 0447

Legend: Item Description

CFGW = Configuration Word

SUM[a:b] = Sum of locations, a to b inclusive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+ = Addition

& = Bit-wise AND

 2010 Microchip Technology Inc. DS30500B-page 35

PIC18F2331/2431/4331/4431

PIC18F2431

None SUM(0000:01FF)+SUM(0200:0FFF)+SUM(1000:1FFF)+

SUM(2000:2FFF)+SUM(3000:3FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 000F)+(CONFIG3 & 003F)+

(CONFIG4 & 003C)+(CONFIG5 & 009D)+(CONFIG6 & 0085)+

(CONFIG7 & 0000)+(CONFIG8 & 000F)+(CONFIG9 & 00C0)+

(CONFIG10 & 000F)+(CONFIG11 & 00E0)+(CONFIG12 & 000F)+

(CONFIG13 & 0040)

C488 C3DE

Boot

Block SUM(0200:0FFF)+SUM(1000:1FFF)+SUM(2000:2FFF)+

SUM(3000:3FFF)+(CONFIG0 & 0000)+(CONFIG1 & 00CF)+

(CONFIG2 & 000F)+(CONFIG3 & 003F)+(CONFIG4 & 003C)+

(CONFIG5 & 009D)+(CONFIG6 & 0085)+(CONFIG7 & 0000)+

(CONFIG8 & 000F)+(CONFIG9 & 00C0)+(CONFIG10 & 000F)+

(CONFIG11 & 00E0)+(CONFIG12 & 000F)+(CONFIG13 & 0040)+

SUM(IDs)

C668 C61D

Boot

Block/

Block 0

SUM(2000:2FFF)+SUM(3000:3FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 000F)+(CONFIG3 & 003F)+

(CONFIG4 & 003C)+(CONFIG5 & 009D)+(CONFIG6 & 0085)+

(CONFIG7 & 0000)+(CONFIG8 & 000F)+(CONFIG9 & 00C0)+

(CONFIG10 & 000F)+(CONFIG11 & 00E0)+(CONFIG12 & 000F)+

(CONFIG13 & 0040)+SUM(IDs)

E465 E41A

All (CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 000F)+

(CONFIG9 & 00C0)+(CONFI G10 & 000F)+(CONFIG11 & 00E0)+

(CONFIG12 & 000F)+(CONFIG13 & 0040)+SUM(IDs)

0459 0463

TABLE 5-5: CHECKSUM COMPUTATION (CONTINUED)

Device Code

Protect Checksum Blank

Value

0xAA at 0

and Max

Address

Legend: Item Description

CFGW = Configuration Word

SUM[a:b] = Sum of locations, a to b inclusive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+ = Addition

& = Bit-wise AND

PIC18F2331/2431/4331/4431

DS30500B-page 36  2010 Microchip Technology Inc.

PIC18F4331

None SUM(0000:01FF)+SUM(0200:0FFF)+SUM(1000:1FFF)+

(CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 0003)+(CONFIG10 & 00E0)+(CONFIG11 & 0003)+

(CONFIG12 & 0040)+(CONFIG13 & 0000)

E3A4 E2FA

Boot

Block SUM(0200:0FFF)+SUM(1000:1FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 000F)+(CONFIG3 & 003F)+

(CONFIG4 & 003C)+(CONFIG5 & 009D)+(CONFIG6 & 0085)+

(CONFIG7 & 0000)+(CONFIG8 & 0003)+(CONFIG9 & 0003)+

(CONFIG10 & 00E0)+(CONFIG11 & 0003)+(CONFIG12 & 0040)+

(CONFIG13 & 0000)+SUM(IDs)

E5C3 E578

Boot

Block/

Block 0/

Block 1

(CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 0003)+(CONFIG10 & 00E0)+(CONFIG11 & 0003)+

(CONFIG12 & 0040)+(CONFIG13 & 0000)+SUM(IDs)

03C0 03CA

All (CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 0003)+(CONFIG10 & 00E0)+(CONFIG11 & 0003)+

(CONFIG12 & 0040)+(CONFIG13 & 0000)+SUM(IDs)

03C0 03CA

TABLE 5-5: CHECKSUM COMPUTATION (CONTINUED)

Device Code

Protect Checksum Blank

Value

0xAA at 0

and Max

Address

Legend: Item Description

CFGW = Configuration Word

SUM[a:b] = Sum of locations, a to b inclusive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+ = Addition

& = Bit-wise AND

 2010 Microchip Technology Inc. DS30500B-page 37

PIC18F2331/2431/4331/4431

5.6 Embedding Data EEPROM

Info rmation In th e H E X Fi le

To allow portability of code, a PIC18FXX31 program-

mer i s re qui red to r ead th e da ta EEP RO M in form ati on

from the HEX file. If data EEPROM information is not

present, a simple warning message should be issued.

Similarly, when saving a HEX file, all data EEPROM

information must be included. An option to not include

the dat a EEPROM informat ion may be provided . When

embedding data EEPROM information in the HEX file,

it should start at address F00000h.

Microchip Technology Inc. believes that this feature is

important for the benefit of the end customer.

PIC18F4431

None SUM(0000:01FF)+SUM(0200:0FFF)+SUM(1000:1FFF)+

SUM(2000:2FFF)+SUM(3000:3FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 000F)+(CONFIG3 & 003F)+

(CONFIG4 & 003C)+(CONFIG5 & 009D)+(CONFIG6 & 0085)+

(CONFIG7 & 0000)+(CONFIG8 & 000F)+(CONFIG9 & 00C0)+

(CONFIG10 & 000F)+(CONFIG11 & 00E0)+(CONFIG12 & 000F)+

(CONFIG13 & 0040)

C488 C3DE

Boot

Block SUM(0200:0FFF)+SUM(1000:1FFF)+SUM(2000:2FFF)+

SUM(3000:3FFF)+(CONFIG0 & 0000)+(CONFIG1 & 00CF)+

(CONFIG2 & 000F)+(CONFIG3 & 003F)+(CONFIG4 & 003C)+

(CONFIG5 & 009D)+(CONFIG6 & 0085)+(CONFIG7 & 0000)+

(CONFIG8 & 000F)+(CONFIG9 & 00C0)+(CONFIG10 & 000F)+

(CONFIG11 & 00E0)+(CONFIG12 & 000F)+(CONFIG13 & 0040)+

SUM(IDs)

C668 C61D

Boot

Block/

Block 0/

Block 1

SUM(2000:2FFF)+SUM(3000:3FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 000F)+(CONFIG3 & 003F)+

(CONFIG4 & 003C)+(CONFIG5 & 009D)+(CONFIG6 & 0085)+

(CONFIG7 & 0000)+(CONFIG8 & 000F)+(CONFIG9 & 00C0)+

(CONFIG10 & 000F)+(CONFIG11 & 00E0)+(CONFIG12 & 000F)+

(CONFIG13 & 0040)+SUM(IDs)

E465 E41A

All (CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 000F)+

(CONFIG3 & 003F)+(CONFIG4 & 003C)+(CONFIG5 & 009D)+

(CONFIG6 & 0085)+(CONFIG7 & 0000)+(CONFIG8 & 000F)+

(CONFIG9 & 00C0)+(CONFI G10 & 000F)+(CONFIG11 & 00E0)+

(CONFIG12 & 000F)+(CONFIG13 & 0040)+SUM(IDs)

0459 0463

TABLE 5-5: CHECKSUM COMPUTATION (CONTINUED)

Device Code

Protect Checksum Blank

Value

0xAA at 0

and Max

Address

Legend: Item Description

CFGW = Configuration Word

SUM[a:b] = Sum of locations, a to b inclusive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+ = Addition

& = Bit-wise AND

PIC18F2331/2431/4331/4431

DS30500B-page 38  2010 Microchip Technology Inc.

6.0 AC/DC CHARACTERISTICS

TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE

Standard Operatin g Conditions

Operating Temperature: 10C to 50C unless otherwise in dicated

Param

No. Sym Characteristic Min Max Units Conditions

D110 VIHH High Voltage Programming Voltage on

MCLR/VPP 9.00 13.25 V

D110A VIHLLow Volt age Program mi ng Voltage on

MCLR/VPP 2.00 5.50 V

D111 VDD Supply Voltage during programming 2.00 5.50 V Normal

programming

4.50 5.50 V Bulk erase

operations

D112 IPP Programming Current on MCLR/VPP — 300 A

D113 IDDP Supply Current during programming — 5 mA

D031 VIL Input Low Voltag e VSS 0.2 VSS V

D041 VIH Input High Voltage 0.8 VDD VDD V

D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA

D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA

D012 CIO Capacitive Loading on I/O pin (SDATA) — 50 pF To meet AC

specifications

P2 Tsclk Serial Clock (SCLK) period 100 — ns VDD = 5.0V

1—sVDD = 2.0V

P2A TsclkL Serial Clock (SCLK) Low Time 40 — ns VDD = 5.0V

400 — ns VDD = 2.0V

P2B TsclkH Serial Clock (SCLK) High Time 40 — ns VDD = 5.0V

400 — ns VDD = 2.0V

P3 Tset1 Input Data Setup Time to serial clock 15 — ns

P4 Thld1 Input Data Hold Time from SCLK 15 — ns

P5 Tdly1 Delay between 4-bit command and

command operand 20 — ns

P5A Tdly1a Delay between 4-bit command

operand and next 4-bit command 20 — ns

P6 Td ly2 Delay be tween last SCLK  of

command byte to first SCLK  of read

of data word

20 — ns

P9 Tdly5 SCLK High Time

(minimum programming time) 1—ms

P10 Tdly6 SCLK Low Time after programming

(high voltage discharge time) 5—s

P11 Tdly7 Delay to allow self-timed data write or

bulk erase to occur 10 — ms

P12 Thld2 Input Data Hold Time from

MCLR/VPP 2—s

P13 Tset2 VDD Setup Time to MCLR/VPP 100 — ns

P14 Tvalid Data Out Valid from SCLK 10 — ns

P15 Tset3 PGM Setup Time to MCLR/VPP 2—s

 2010 Microchip Technology Inc. DS30500B-page 39

Information contained in this publication regarding device

applications a nd the lik e is provided only f or yo ur convenience

and may be supers ed ed by u pda t es . I t is y o u r r es ponsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Contr ol

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI-TIDE, In - Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Cert ified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, UniWinDriver, WiperLock and ZENA

are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and ds PIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS30500B-page 40  2010 Microchip Technology Inc.

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