MICRF220
300MHz to 450MHz, 3.3V ASK/OOK Receiver
with RSSI and Squelch
com
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.
August 2010 9-082610-A
RadioTech@micrel.com
M999
General Description
The MICRF220 is a 300MHz to 450MHz super-
heterodyne, image-reject, RF receiver with automatic
gain control, ASK/OOK demodulator, analog RSSI
output, and integrated squelch features. It only requires
a crystal and a minimum number of external components
to implement. The MICRF220 is ideal for low-cost, low-
power, RKE, TPMS, and remote actuation applications.
The MICRF220 achieves −110dBm sensitivity at a bit
rate of 1kbps with 0.1% BER. Four demodulator filter
bandwidths are selectable in binary steps from 1625Hz
to 13kHz at 433.92MHz, allowing the device to support
bit rates up to 20kbps. The device operates from a
supply voltage of 3.0V to 3.6V, and typically consumes
4.3mA of supply current at 315MHz and 6.0mA at
433.92MHz. A shutdown mode reduces supply current to
0.1A typical. The squelch feature decreases the activity
on the data output pin until valid bits are detected while
maintaining overall receiver sensitivity.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
• –110dBm sensitivity at 1kbps with 0.1% BER
• Supports bit rates up to 20kbps at 433.92MHz
• 25dB image-reject mixer
• No IF filter required
• 60dB analog RSSI output range
• 3.0V to 3.6V supply voltage range
• 4.3mA supply current at 315MHz
• 6.0mA supply current at 434MHz
• 0.1µA supply current in shutdown mode
• Data output squelch until valid bits detected
• 16-pin QSOP package (4.9mm x 6.0mm)
• −40˚C to +105˚C temperature range
• 3kV HBM ESD Rating
Ordering Information
Part Number Temperature Range Package
MICRF220AYQS –40°C to +105°C 16-Pin QSOP
Typical Application
or (408) 944-0800
433.92MHz, 1kbps Operation
Micrel, Inc. MICRF220
August 2010 2 M9999-082610-A
Pin Configuration
MICRF220AYQS
Pin Description
Pin
Number
Pin
Name Pin Function
1 RO1
Reference resonator connection to the Pierce oscillator. May also be driven by external reference signal of
200mVp-p to 1.5V p-p amplitude maximum. Internal capacitance of 7pF to GND during normal operation.
2 GNDRF Ground connection for ANT RF input. Connect to PCB ground plane.
3 ANT
Antenna Input: RF Signal Input from Antenna. Internally AC coupled. It is recommended to use a matching
network with an inductor-to-RF ground to improve ESD protection.
4 GNDRF Ground connection for ANT RF input. Connect to PCB ground plane.
5 VDD
Positive supply connection for all chip functions. Bypass with 0.1F capacitor located as close to the VDD pin
as possible.
6 SQ
Squelch Control Logic-Level Input. An internal pull-up (5A typical) pulls the logic-input HIGH when the device
is enabled. A logic LOW on SQ squelches, or reduces, the random activity on DO pin when there is no RF
input signal.
7 SEL0
Demodulator Filter Bandwidth Select Logic-Level Input. This pin has an internal pull-up (3A typical) when the
chip is on. Use in conjunction with SEL1 to control demodulation bandwidth.
8 SHDN
Shutdown Control Logic-Level Input. A logic-level LOW enables the device. A logic-level HIGH places the
device in low-power shutdown mode. An internal pull-up (5A typical) pulls the logic input HIGH.
9 GND Ground connection for all chip functions except for RF input. Connect to PCB ground plane.
10 DO
Data Output. Demodulated data output. A current limited CMOS output during normal operation, 25k pull-
down is present when device is in shutdown.
11 SEL1
Demodulator Filter Bandwidth Select Logic-Level Input. This pin has an internal pull-up (3A typical) when the
chip is on. Use in conjunction with SEL0 to Demodulation bandwidth.
12 CTH
Demodulation Threshold Voltage Integration Capacitor. Connect a 0.1F capacitor from CTH pin-to-GND to
provide a stable slicing threshold.
13 CAGC
AGC Filter Capacitor. Connect a capacitor from this pin to GND. Refer to the AGC Loop and CAGC section for
information on the capacitor value.
14 RSSI
Received Signal Strength Indicator. The voltage on this pin is an inversed amplified version of the voltage on
CAGC. Output is from a switched capacitor integrating op amp with 250 typical output impedance.
15 NC No Connect. Leave this pin floating.
16 RO2
Reference resonator connection to the Pierce oscillator. Internal capacitance of 7pF to GND during normal
operation.
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August 2010 3 M9999-082610-A
Absolute Maximum Ratings(1)
Supply Voltage (VDD).................................................. +5V
ANT, SQ, SEL0, SEL1,
SHDN DC Voltage. .................... −0.3V to VDD + 0.3V
Junction Temperature ...........................................+150ºC
Lead Temperature (soldering, 10sec.)..................+300°C
Storage Temperature .............................−65ºC to +150°C
Maximum Receiver Input Power ......................... +10dBm
ESD Rating(3).................................................... 3kV HBM
Operating Ratings(2)
Supply Voltage (VDD) ............................. +3.0V to +3.6V
Ambient Temperature (TA)..................–40°C to +105°C
ANT, SQ, SEL0, SEL1,
SHDN DC Voltage ................ ....−0.3V to VDD + 0.3V
Maximum Input RF Power.................................. 0 dBm
Receive Modulation Duty Cycle .......................20~80%
Frequency Range.......................... 300MHz to 450MHz
Electrical Characteristics
VDD = 3.3V, VSHDN = GND = 0V, SQ = open, CCAGC = 4.7µF, CCTH = 0.1µF, unless otherwise noted. Bold values indicate
–40°C TA 105°C. “Bit rate” refers to the encoded bit rate throughout this datasheet (see Note 4).
Parameter Condition Min. Typ. Max. Units
Continuous Operation, fRF = 315MHz 4.3
Operating Supply Current Continuous Operation, fRF = 433.92MHz 6.0 mA
Shutdown Current VSHDN = VDD 0.1 µA
Receiver
433.92MHz, VSEL1 = VSEL0 = 0V, BER = 1% −112.5
433.92MHz, VSEL1 = VSEL0 = 0V,
BER = 0.1% −110
315MHz, VSEL1 = 0V, VSEL0 = 3.3V,
BER = 1% −112.5
Conducted Receiver
Sensitivity@1kbps (Note 5)
315MHz, VSEL1 = 0V, VSEL0 = 3.3V,
BER = 0.1% −110
dBm
Image Rejection fIMAGE = fRF – 2fIF 25 dB
fRF = 315MHz 0.85
IF Center Frequency (fIF) fRF = 433.92MHz 1.18 MHz
fRF = 315MHz 235
−3dB IF Bandwidth fRF = 433.92MHz 330 kHz
−40dBm RF input level 1.15
CAGC Voltage Range −100dBm RF input level 1.55
V
Reference Oscillator
fRF = 315 MHz 9.81713
Reference Oscillator
Frequency fRF = 433.92 MHz 13.52313 MHz
Reference Buffer Input
Impedance RO1 when driven externally 1.6 k
Reference Oscillator Bias
Voltage RO2 1.15 V
Reference Oscillator Input
Range External input, AC couple to RO1 0.2 1.5 VP-P
Reference Oscillator Source
Current VRO1 = 0V 300 µA
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August 2010 4 M9999-082610-A
Electrical Characteristics (Continued)
Parameter Condition Min. Typ. Max. Units
Demodulator
fREF = 9.81713MHz 165
CTH Source Impedance,
Note 6 fREF = 13.52313MHz 120 k
CTH Leakage Current In
CTH Hold Mode
TA = +25ºC
TA = +105ºC 1
10 nA
Digital / Control Functions
DO Pin Output Current As output source @ 0.8 VDD
As output sink @ 0.2 VDD 300
680 µA
Output Rise Time 600
Output Fall Time
15pF load on DO pin, transition time
between 0.1xVDD and 0.9xVDD 200
ns
Input High Voltage SHDN, SEL0, SEL1, SQ 0.8VDD V
Input Low Voltage SHDN, SEL0, SEL1, SQ 0.2VDD V
Output Voltage High DO 0.8VDD V
Output Voltage Low DO 0.2VDD V
RSSI
−110dBm RF input level 0.5
RSSI DC Output Voltage
Range −50dBm RF input level 2.0
V
RSSI Output Current 5kΩ load to GND, −50dBm RF input level 400
µA
RSSI Output Impedance 250
RSSI Response Time VSEL0 = VSEL1 = 0V, RF input power stepped
from no input to −50dBm 10
ms
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside of its operating rating.
3. Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute maximum rating may damage the device.
4. Encoded bit rate is 1/(shortest pulse duration) that appears at MICRF220 DO pin.
5. In an ON/OFF keyed (OOK) signal, the signal level goes between a “mark” level (when the RF signal is ON) and a “space” level (when the RF
signal is OFF). Sensitivity is defined as the input signal level when “ON” necessary to achieve a specified BER (bit error rate). BER measured with
the built-in BERT function in Agilent E4432B using the PN9 sequence. Sensitivity measurement values are obtained using an input matching
network corresponding to 315MHz or 433.92MHz.
6. CTH source impedance is inversely proportional to the reference frequency. In production testing, the typical source impedance value is verified
with 12MHz reference frequency.
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Typical Characteristics
VDD = 3.3V, TA = +25ºC, BER measured with PN9 sequence, unless otherwise noted.
Current vs. Receiver
Frequency
3.5
4.0
4.5
5.0
5.5
6.0
6.5
300 325 350 375 400 425 450
Receiver Frequency (MHz)
Current (mA)
Current vs. Supply Voltage
f
RF
= 433.92MHz
4.5
5.0
5.5
6.0
6.5
7.0
7.5
3.0 3.2 3.4 3.6
Supply Voltage (V)
Current vs. Supply Voltage
f
RF
= 315MHz
3.5
4.0
4.5
5.0
3.0 3.2 3.4 3.6
Supply Voltage (V)
+105ºC
+105ºC
Current (mA)
Current (mA)
+25ºC
+25ºC
-40ºC
-40ºC
CAGC Voltage vs. Input
Power
1.0
1.2
1.4
1.6
1.8
2.0
-125 -100 -75 -50 -25 0
Input Power (dBm)
BER vs. Input Power
VSEL1 = VSEL0 = 0V
0.1
1
10
-116 -115 -114 -113 -112 -111 -110
Input Power (dBm)
RSSI vs. Input Power
0.0
0.5
1.0
1.5
2.0
2.5
-125 -100 -75 -50 -25 0
Input Power (dBm)
CAGC Voltage (V)
+105ºC
-40ºC
+25ºC
RSSI Voltage (V)
+105ºC
-40ºC
+25ºC
433.92MHz
BER (%)
315MHz
`
PN9 sequence
at 1kbps
Sensitivity at 1% BER
V
SEL1
= V
SEL0
= 0V
-116
-114
-112
-110
-108
-106
-104
-102
-100
-98
Sensitivity (dBm)
024681012
Bit Rate (kbps)
315MHz
433.92MHz
Sensitivity at 1% BER
V
SEL1
= 0V, V
SEL0
= 3.3V
-114
-112
-110
-108
-106
-104
-102
-100
Sensitivity (dBm)
036912151821
Bit Rate (kbps)
315MHz
433.92MHz
Sensitivity at 1% BER
V
SEL1
= 3.3V, V
SEL0
= 0V
-112
-110
-108
-106
-104
-102
-100
-98
Sensitivity (dBm)
0 10203040
Bit Rate (kbps)
315MHz
433.92MHz
Micrel, Inc. MICRF220
August 2010 6 M9999-082610-A
Typical Characteristics (Continued)
VDD = 3.3V, TA = +25ºC, BER measured with PN9 sequence, unless otherwise noted.
Sensitivity at 1% BER
V
SEL1
= 3.3V, V
SEL0
= 3.3V
-110
-108
-106
-104
-102
-100
-98
01020304050
Bit Rate (kbps)
Bandpass Filter Attenuation
fXTAL = 13.52313MHz
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
433.6 433.8 434.0 434.2
Input Frequency (MHz)
Attenuation (dB)
Bandpass Filter Attenuation
f
XTAL
= 9.81713MHz
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
Attenuation (dB)
Sensitivity (dBm)
315MHz
433.92MHz
314.8 314.9 315.0 315.1 315.2
Input Frequency (MHz)
Sensitivity for 1% BER vs
Frequency
f
XTAL
= 13.52313MHz
-120
-110
-100
-90
-80
-70
-60
-50
-40
Sensitivity (dBm)
419 424 429 434 439 444 449
Input Frequency (MHz)
Sensitivity for 1% BER vs
Frequency
f
XTAL
= 9.81713MHz
-120
-110
-100
-90
-80
-70
-60
-50
-40
Sensitivity (dBm)
304 309 314 319 324
Input Frequency (MHz)
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August 2010 7 M9999-082610-A
Functional Diagram
Figure 1. Simplified Block Diagram
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August 2010 8 A M9999-082610-
Functional Description
The simplified block diagram (Figure 1) illustrates the basic
structure of the MICRF220 receiver. It is made up of four
sub-blocks:
• UHF Down-Converter
• ASK/OOK Demodulator
• Reference and Control logic
• Squelch Control
Outside the device, the MICRF220 receiver requires just a
few components to operate: a capacitor from CAGC to
GND, a capacitor from CTH-to-GND, a reference crystal
resonator with associated loading capacitors, LNA input
matching components, and a power-supply decoupling
capacitor.
Receiver Operation
UHF Downconverter
The UHF down-converter has six sub-blocks: LNA, mixers,
synthesizer, image reject filter, band pass filter and IF
amplifier.
LNA
The RF input signal is AC-coupled into the gate of the LNA
input device. The LNA configuration is a cascoded
common source NMOS amplifier. The amplified RF signal
is then fed to the RF ports of two double balanced mixers.
Mixers and Synthesizer
The LO ports of the mixers are driven by quadrature local
oscillator outputs from the synthesizer block. The local
oscillator signal from the synthesizer is placed on the low
side of the desired RF signal (Figure 2). The product of the
incoming RF signal and local oscillator signal will yield the
IF frequency, which will be demodulated by the detector of
the device. The image reject mixer suppresses the image
frequency which is below the wanted signal by two times
the IF frequency. The local oscillator frequency (fLO) is set
to 32 times the crystal reference frequency (fREF) via a
phase-locked loop synthesizer with a fully-integrated loop
filter:
fLO = 32 x fREF Eq. 1
MICRF220 uses an IF frequency scheme that scales the IF
frequency (fIF) with fREF according to:
fIF = fREF x 1000
87 Eq. 2
Therefore, the reference frequency fREF needed for a given
desired RF frequency (fRF) is approximately:
fREF = fRF / (32 + 1000
87 ) Eq. 3
Figure 2. Low-Side Injection Local Oscillator
Image-Reject Filter and Band-Pass Filter
The IF ports of the mixer produce quadrature-down
converted IF signals. These IF signals are low-pass filtered
to remove higher-frequency products prior to the image
reject filter where they are combined to reject the image
frequency. The IF signal then passes through a third order
band pass filter. The IF bandwidth is 330kHz @
433.92MHz, and will scale with RF operating frequency
according to:
BWIF = BWIF@433.92 MHz ×
⎟
⎠
⎞
⎝433.92
(MHz) Freq Operating
⎜
⎛ Eq. 4
These filters are fully integrated inside the MICRF220.
After filtering, four active gain controlled amplifier stages
enhance the IF signal to its proper level for demodulation.
ASK/OOK Demodulator
The demodulator section is comprised of detector,
programmable low pass filter, slicer, and AGC comparator.
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August 2010 9 M9999-082610-A
Detector and Programmable Low-Pass Filter
The demodulation starts with the detector removing the
carrier from the IF signal. Post detection, the signal
becomes baseband information. The low-pass filter further
enhances the baseband signal. There are four selectable
low-pass filter BW settings; 1625Hz, 3250Hz, 6500Hz, and
13000Hz for 433.92MHz operation. The low-pass filter BW
is directly proportional to the crystal reference frequency,
and hence RF Operating Frequency. Filter BW values can
be easily calculated by direct scaling. Equation 5 illustrates
filter Demod BW calculation:
BWOperating Freq = BW@433.92MHz ×
⎟
⎠
⎞
⎜
⎝
⎛
433.92
(MHz) Freq Operating Eq. 5
It is very important to choose the baseband bandwidth
setting suitable for the data rate to minimize bit error rate.
Use the operating curves that show BER vs. bit rates for
different SEL1, SEL0 settings as a guide.
This low-pass filter -3dB corner, or the demodulation BW,
is set at 13000Hz @ 433.92MHz as default (assuming both
SEL0 and SEL1 pins are floating, internal pull-up resistors
set the voltage to VDD). The low-pass filter can be hardware
set by external pins SEL0 and SEL1. Table 2 demonstrates
the scaling for 315MHz RF frequency:
VSEL1 V
SEL0 Low-Pass
Filter BW
Maximum Encoded
Bit Rate
GND GND 1625Hz 2.5kbps
GND VDD 3250Hz 5kbps
VDD GND 6500Hz 10kbps
VDD V
DD 13000Hz 20kbps
Table 1. Low-Pass Filter Selection @ 434MHz RF Input
VSEL1 V
SEL0 Low-Pass
Filter BW
Maximum Encoded
Bit Rate
GND GND 1170Hz 1.8kbps
GND VDD 2350Hz 3.6kbps
VDD GND 4700Hz 7.2kbps
VDD V
DD 9400Hz 14.4kbps
Table 2. Low-Pass Filter Selection @ 315MHz RF Input
Slicer and CTH
The signal prior to the slicer, labeled “Audio Signal” in
Figure 1, is still baseband analog signal. The data slicer
converts the analog signal into ones and zeros based upon
50% of the slicing threshold voltage built up in the CTH
capacitor. After the slicer, the signal is demodulated OOK
digital data. When there is only thermal noise at ANT pin,
the voltage level on CTH pin is about 650mV. This voltage
starts to drop when there is RF signal present. When the
RF signal level is greater than −100dBm, the voltage is
about 400mV.
The value of the capacitor from CTH pin to GND is not
critical to the sensitivity of MICRF220, although it should be
large enough to provide a stable slicing level for the
comparator. The value used in the evaluation board of
0.1F is good for all bit rates from 500bps to 20kbps.
CTH Hold Mode
If the internal demodulated signal (DO′ in Figure 1) is at
logic LOW for more than about 4msec, the chip
automatically enters CTH hold mode, which holds the
voltage on CTH pin constant even without RF input signal.
This is useful in a transmission gap, or “deadtime”, used in
many encoding schemes. When the signal reappears, CTH
voltage does not need to re-settle, improving the time to
output with no pulse width distortion, or time to good data
(TTGD).
AGC Loop and CAGC
The AGC comparator monitors the signal amplitude from
the output of the programmable low-pass filter. The AGC
loop in the chip regulates the signal at this point to be at a
constant level when the input RF signal is within the AGC
loop dynamic range (about −115dBm to −40dBm).
When the chip first turns on, the fast charge feature
charges the CAGC node up with 120µA typical current.
When the voltage on CAGC increases, the gains of the
mixer and IF amplifier go up, increasing the amplitude of
the audio signal (as labeled in Figure 1), even with only
thermal noise at the LNA input. The fast-charge current is
disabled when the audio signal crosses the slicing
threshold, causing DO’ to go high, for the first time.
When an RF signal is applied, a fast attack period ensues,
when 600µA current discharges the CAGC node to reduce
the gain to a proper level. Once the loop reaches
equilibrium, the fast attack current is disabled, leaving only
15µA to discharge CAGC or 1.5µA to charge CAGC. The
fast attack current is enabled only when the RF signal
increases faster than the ability of the AGC loop to track it.
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The value of CAGC impacts the time to good data (TTGD),
which is defined as the time when signal is first applied, to
when the pulse width at DO is within 10% of the steady
state value. The optimal value of CAGC depends upon the
setting of the SEL0 and SEL1 pins. A smaller CAGC value
does NOT always result in a shorter TTGD. This is due to
the loop dynamics, the fast discharge current being 600µA,
and the charge current being only 1.5µA. For example, if
VSEL0 = VSEL1 = 0V, the low pass filter bandwidth is set to a
minimum and CAGC capacitance is too small, TTGD will
be longer than if CAGC capacitance is properly chosen.
This is because when RF signal first appears, the fast
discharge period will reduce VCAGC very fast, lowering the
gain of the mixer and IF amplifier. But since the low pass
filter bandwidth is low, it takes too long for the AGC
comparator to see a reduced level of the audio signal, so it
can not stop the discharge current. This causes an
undershoot in CAGC voltage and a corresponding
overshoot in RSSI voltage. Once CAGC undershoots, it
takes a long time for it to charge back up because the
current available is only 1.5µA.
Table 3 lists the recommended CAGC values for different
SEL0 and SEL1 settings.
VSEL1 V
SEL0 CAGC value
0V 0V 4.7F
0V VDD 2.2F
VDD 0V 1F
VDD V
DD 0.47F
Table 3. Minimum Suggested CAGC Values
Figure 3 illustrates what occurs if CAGC capacitance is too
small for a given SEL1, SEL0 setting. Here, VSEL1 = 0V,
VSEL0 = VDD, the capacitance on CAGC pin is 0.47F, and
the RF input level is stepped from no signal to −100dBm.
RSSI voltage is shown instead of CAGC voltage because
RSSI is a buffered version of CAGC (with an inversion and
amplification). Probing CAGC directly can affect the loop
dynamics through resistive loading from a scope probe,
especially in the state where only 1.5A is available,
whereas probing RSSI does not. When RF signal is first
applied, RSSI voltage overshoots due to the fast discharge
current on CAGC, and the loop is too slow to stop this fast
discharge current in time. Since the voltage on CAGC is
too low, the audio signal level is lower than the slicing
threshold (voltage on CTH), and DO pin is low. Once the
fast discharge current stops, only the small 1.5µA charge
current is available in settling the AGC loop to the correct
level, causing the recovery from CAGC undershoot/RSSI
overshoot condition to be slow. As a result, TTGD is about
9.1ms.
Figure 3. RSSI Overshoot and Slow TTGD (9.1ms)
Figure 4 shows the behavior with a larger capacitor on
CAGC pin (2.2F), VSEL1 = 0V, and VSEL0 = VDD. In this
case, VCAGC does not undershoot (RSSI does not
overshoot), and TTGD is relatively short at 1ms.
Figure 4. Proper TTGD (1ms) with Sufficient CAGC
Reference Oscillator
The reference oscillator in the MICRF220 (Figure 5) uses a
basic Pierce crystal oscillator configuration with MOS
transconductor to provide negative resistance. Though the
MICRF220 has built-in load capacitors for the crystal
oscillator, the external load capacitors are still required for
tuning it to the right frequency. RO1 and RO2 are external
pins of the MICRF220 to connect the crystal to the
reference oscillator.
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August 2010 11 M9999-082610-A
V BIAS
RO2
R
RO1
C
C
Figure 5. Reference Oscillator Circuit
Reference oscillator crystal frequency can be calculated
according to Equation 3. For example, if fRF = 433.92MHz,
fREF = 13.52313MHz. Table 4 lists the values of reference
frequencies at different popular RF frequencies. To
operate the MICRF220 with minimum offset, use proper
loading capacitance recommended by the crystal
manufacturer.
RF Input Frequency (MHz) Reference Frequency (MHz)
315.0 9.81713*
390.0 12.15446
418.0 13.02708
433.92 13.52313*
*Empirically derived, slightly different from Equation 3.
Table 4. Reference Frequency Examples
Squelch Operation
When squelch function is enabled by tying the SQ pin low,
the chip will monitor incoming pulse width before allowing
activity on DO pin. The pulse width is set by SEL1 and
SEL0 pins as shown in Table 5, and is inversely
proportional to frequency. When there is no input signal
and squelch is not enabled (SQ pin left floating), voltage on
DO chatters due to random noise as shown in Figure 6. If
SQ pin is tied low, the activity on DO pin is much reduced
as shown in Figure 7.
Figure 6. Data Out Pin with No Squelch (VSQ = VDD)
When squelch function is enabled by tying the SQ pin low,
the chip will monitor incoming pulse width before allowing
activity on DO pin. The pulse width is set by SEL1 and
SEL0 pins as shown in Table 5, and is inversely
proportional to frequency. When there is no input signal
and squelch is not enabled (SQ pin left floating), voltage on
DO chatters due to random noise as shown in Figure 6. If
SQ pin is tied low, the activity on DO pin is much reduced
as shown in Figure 7.
Figure 7. Data Out Pin with Squelch (VSQ = 0V)
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August 2010 12 M9999-082610-A
VSEL1 V
SEL0 Pulse Width at
315MHz (μs)
Pulse Width at
433.92MHz
(μs)
0V 0V 420 305
0V VDD 210 152
VDD 0V 105 76
VDD V
DD 53 38
When four or less out of eight pulses (at DO′signal labeled
in Figure 1) are good, the DO output is squelched. If good
pulse count increases to seven or more in any eight
sequential pulses, squelch is disabled, thereby allowing
data to output at DO pin. A good pulse has a duration that
is greater than the values listed in Table 5, and it can be a
high or a low pulse. For other frequencies pulse times are
calculated as follows:
Table 5. Pulse Width Settings in Squelch
PW = PW@433.92 MHz × ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
Freq(MHz) Operating
433.92 Eq. 6
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Application Information
Figure 8. MICRF220 EV Board Application Example
Micrel, Inc. MICRF220
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Supply Voltage Ramping
When supply voltage is initially applied, it should rise
monotonically from 0V to 3.3V to ensure proper startup
of the crystal oscillator and the PLL. It should not have
multiple bounces across 2.6V, which is the threshold of
the undervoltage lockout (UVLO) circuit inside
MICRF220.
Antenna and RF Port Connections
Figure 8 shows the schematic of the MICRF220
Evaluation Board. Figures 9 thru 11 depict PCB images.
This evaluation board is a good starting point for the
prototyping of most applications. The evaluation board
offers two options of injecting the RF input signal:
through a PCB antenna or through a 50Ω SMA
connector. The SMA connection allows for conductive
testing, or an external antenna.
Low-Noise Amplifier Input Matching
Capacitor C3 and inductor L2 form the “L” shape input
matching network to the SMA connector. The capacitor
cancels out the inductive portion of the net impedance
after the shunt inductor, and provides additional
attenuation for low-frequency outside band noise. The
inductor is chosen to over resonate the net capacitance
at the pin, leaving a net-positive reactance and
increasing the real part of the impedance. It also
provides additional ESD protection for the antenna pin.
The input impedance of the device is listed in Table 6 to
aid calculation of matching values. Note that the net
impedance at the pin is easily affected by component
pads parasitic due to the high input impedance of the
device. The numbers in Table 6 does NOT include trace
and component pad parasitic capacitance, which total
about 0.75pF on the evaluation board.
The matching components to the PCB antenna (L3 and
C9) were empirically derived for best over-the-air
reception range.
Frequency (MHz) Z Device (Ω)
315 23 − j290
390 14 – j230
418 17 – j216
433.92 12 – j209
Table 6. Input Impedance for the Most Used Frequencies
Crystal Selection
The crystal resonator provides a reference clock for all
the device internal circuits. Crystal tolerance needs to
be chosen such that the down-converted signal is
always inside the IF bandwidth of MICRF220. From this
consideration, the tolerance should be ±50ppm on both
the transmitter and the MICRF220 side. ESR should be
less than 300, and the temperature range of the crystal
should match the range required by the application.
With the Abracon crystal listed in the Bill of Materials, a
typical MICRF220 crystal oscillator still starts up at
105ºC with additional 400 series resistance.
The oscillator of the MICRF220 is a Pierce-type
oscillator. Good care must be taken when laying out the
printed circuit board. Avoid long traces and place the
ground plane on the top layer close to the REFOSC pins
RO1 and RO2. When care is not taken in the layout, and
the crystals used are not verified, the oscillator may not
start or takes longer to start. Time-to-good-data will be
longer as well.
PCB Considerations and Layout
Figures 9 thru 11 illustrate the MICRF220 Evaluation
Board layout. The Gerber files provided are
downloadable from the Micrel website and contain the
remaining layers needed to fabricate this board. When
copying or making one’s own boards, make the traces
as short as possible. Long traces alter the matching
network and the values suggested are no longer valid.
Suggested matching values may vary due to PCB
variations. A PCB trace 100 mils (2.5mm) long has about
1.1nH inductance. Optimization should always be done
with exhaustive range tests. Make sure the individual
ground connection has a dedicated via rather then
sharing a few of ground points by a single via. Sharing
ground via will increase the ground path inductance.
Ground plane should be solid and with no sudden
interruptions. Avoid using ground plane on top layer next
to the matching elements. It normally adds additional
stray capacitance which changes the matching. Do not
use Phenolic materials as they are conductive above
200MHz. Typically, FR4 or better materials are
recommended. The RF path should be as straight as
possible to avoid loops and unnecessary turns.
Separate ground and VDD lines from other digital or
switching power circuits (such microcontroller…etc).
Known sources of noise should be laid out as far as
possible from the RF circuits. Avoid unnecessary wide
traces which would add more distribution capacitance
(between top trace to bottom GND plane) and alter the
RF parameters.
Micrel, Inc. MICRF220
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Figure 9. MICRF220 EV Board Assembly
Figure 10. MICRF220 EV Board Top Layer
Figure 11. MICRF220 EV Board Bottom Layer
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MICRF220 Evaluation Board (433.92MHz) Bill of Materials
Item Part Number Manufacturer Description
C3 GRM1885C1H1R2CZ01 Murata(1) 1.2pF 100V, ±0.25pF, 0603
C4 GRM21BR60J475KE01L Murata(1) 4.7F 6.3V, 0805
C5, C6 GRM188R71E104KA01D Murata(1) 0.1F 25V, 0603
C7, C12, JP3 NP
C9 GRM1885C1H1R5CZ01 Murata(1) 1.5pF, 100V, ±0.25pF, 0603
C10, C11 GRM1885C1H100JA01D Murata(1) 10pF 50V, 0603
J2 NP, SMA, Edge Conn.
J3 571-41031480 AMPMODU Breakaway Headers 40 P(6pos)
R/A HEADER GOLD
JP1, JP2 CRCW04020000Z Vishay(2) 0, 0402
L2 LQG18HN39NJ00 Murata(1) 39nH, ± 5%, 0603
L3 LQG18HN33NJ00 Murata(1) 33nH, ± 5%, 0603
R3 CRCW0402100KFKEA 100k, 0402
R4 NP
Y1 ABLS-13.52313MHz-10J4Y Abracon(3) 13.52313MHz, HC49/US
Y2 DSX321GK-13.52313MHz KDS(4) NP, (13.52313MHz, −40°C to +105°C), DSX321GK
U1 MICRF220AYQS Micrel, Inc.(5) 300MHz to 450MHz, 3.3V ASK/OOK Receiver with RSSI and
Squelch
Notes:
1. Murata: www.murata.com.
2. Vishay: www.vishay.com.
3. Abracon: www.abracon.com.
4. KDS: www.kds.info/index_en.htm.
5. Micrel, Inc.: www.micrel.com.
Micrel, Inc. MICRF220
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MICRF220 Evaluation Board (315MHz) Bill of Materials
Item Part Number Manufacturer Description
C3 GRM1885C1H1R5CZ01 Murata(1) 1.5pF 100V, ±0.25pF, 0603
C4 GRM21BR60J475KE01L Murata(1) 4.7F 6.3V, 0805
C5, C6 GRM188R71E104KA01D Murata(1) 0.1F 25V, 0603
C7, C12, JP3 NP
C9 GRM1885C1H1R2CZ01 Murata(1) 1.2pF, 100V, ±0.25pF, 0603
C10, C11 GRM1885C1H100JA01D Murata(1) 10pF 50V, 0603
J2 NP, SMA, Edge Conn.
J3 571-41031480 Mouser(2) AMPMODU Breakaway Headers 40 P(6pos) R/A HEADER
GOLD
JP1, JP2 CRCW04020000Z Vishay(3) 0, 0402
L2, L3 LQG18HN68NJ00 Murata(1) 68nH, ±5%, 0603
R3 CRCW0402100KFKEA 100k, 0402
R4 NP
Y1 ABLS-9.81713MHz-10J4Y Abracon(4) 9.81713MHz, HC49/US
Y2 DSX321GK-9.81713MHz KDS(5) NP, (9.81713MHz, −40°C to +105°C), DSX321GK
U1 MICRF220AYQS Micrel, Inc.(6) 300MHz to 450MHz, 3.3V ASK/OOK Receiver with RSSI and
Squelch
Notes:
1. Murata: www.murata.com.
2. Mouser: www.mouser.com.
3. Vishay: www.vishay.com.
4. Abracon: www.abracon.com.
5. KDS: www.kds.info/index_en.htm.
6. Micrel, Inc.: www.micrel.com.
Micrel, Inc. MICRF220
Package Information
QSOP16 Package Type (AQS16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 US
A
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical impla
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
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August 2010 18 M9999-082610-A
