SPICE Device Model SUD70N02-03P Vishay Siliconix N-Channel 20-V (D-S) 175C MOSFET CHARACTERISTICS * N- and P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72407 30-Jul-03 www.vishay.com 1 SPICE Device Model SUD70N02-03P Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Symbol Test Conditions Simulated Data Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250A 1.7 V On-State Drain Currenta ID(on) VDS = 5V, VGS = 10V 1788 A VGS = 10V, ID = 20A 0.0024 Drain-Source On-State Resistancea rDS(on) VGS = 10V, ID = 20A, TJ = 125C 0.0034 VGS = 10V, ID = 20A, TJ = 175C 0.0040 VGS = 4.5V, ID = 20A 0.0040 gfs VDS = 15V, ID = 20A 67 VSD IS = 50A, VGS = 0V 0.93 1.2 4790 5100 1517 1650 Parameter Measured Data Unit Static Forward Transconductancea Forward Voltage Dynamic a 0.0026 0.0042 S V b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 634 800 Total Gate Chargec Qg 40 40 Gate-Source Chargec Qgs 14 14 13 c VGS = 0V, VDS = 10V, f = 1 MHz VDS = 10V, VGS = 4.5V, ID = 50A Gate-Drain Charge Qgd 13 Turn-On Delay Timec td(on) 11 15 tr 14 11 30 45 32 15 Rise Timec Turn-Off Delay Timec Fall Timec td(off) tf VDD = 10V, RL = 0.20 ID 50A, VGEN = 10V, RG = 2.5 Pf NC Ns Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 72407 30-Jul-03 SPICE Device Model SUD70N02-03P Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 72407 30-Jul-03 www.vishay.com 3