FIN3385 / FIN3383 / FIN3384 / FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Features Description The FIN3385 and FIN3383 transform 28-bit wide parallel LVTTL (Low-Voltage TTL) data into four serial LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 28 bits of input LVTTL data are sampled and transmitted. Low Power Consumption 20MHz to 85MHz Shift Clock Support 1V Common-Mode Range around 1.2V Narrow Bus Reduces Cable Size and Cost High Throughput (up to 2.38Gbps) Internal PLL with No External Component Compatible with TIA/EIA-644 Specification 56-Lead TSSOP Package The FIN3386 and FIN3384 receive and convert the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the serializers and deserializers available. For the FIN3385, at a transmit clock frequency of 85MHz, 28-bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Operating Part Number Temperature Range Eco Status Package Packing Method FIN3383MTDX FIN3384MTDX FIN3385MTDX -10 to +70C 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,6.1mm Wide RoHS Tape and Reel FIN3386MTDX For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Table 1. Display Panel Link Serializer / Deserializer Chip Matrix Part CLK Frequency LVTTL In LVDS Out FIN3385 85 28 4 FIN3383 66 28 4 FIN3386 FIN3384 LVDS In LVTTL Out 85 4 28 66 4 28 (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 Package 56 TSSOP www.fairchildsemi.com FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer July 2009 Figure 1. FIN3385 and FIN3383 Transmitter Functional Diagram FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Block Diagrams Figure 2. FIN3386 and FIN3384 Receiver Functional Diagram (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 www.fairchildsemi.com 2 Truth Table Pin Configuration Inputs Outputs TxIn TxCLKIn /PwrDn(1) TxOut TxCLKOut Active Active HIGH LOW/ HIGH LOW/ HIGH Active LOW/ HIGH/ High Impedance HIGH LOW/ HIGH Don't Care(2) Floating Active HIGH LOW LOW/ HIGH Floating Floating HIGH LOW Don't Care(2) Don't Care Don't Care LOW High Impedance High Impedance Notes: 1. The outputs of the transmitter or receiver remains in a high-impedance state until VCC reaches 2V. 2. TxCLKOut settles at a free-running frequency when the part is powered up, /PwrDn is HIGH, and the TxCLKIn is a steady logic level (LOW / HIGH / High-Impedance). Figure 3. FIN3383 and FIN3385 (28:4 Transmitter) Pin Assignment Pin Definitions Pin Names I/O Types Number of Pins TxIn I 28/21 Description of Signals LVTTL Level Input TxCLKIn I 1 TxOut+ O 4/3 Positive LVDS Differential Data Output LVTTL Level Clock Input, the rising edge is for data strobe TxOut- O 4/3 Negative LVDS Differential Data Output TxCLKOut+ O 1 Positive LVDS Differential Clock Output TxCLKOut- O 1 Negative LVDS Differential Clock Output R_FB I 1 Rising Edge Data Strobe: Assert HIGH (VCC) Falling Edge Data Strobe: Assert LOW (Ground) /PwrDn I 1 LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in high-impedance state PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Output LVDS GND I 3 Ground Pins for LVDS Output VCC I 3 Power Supply Pins for LVTTL Input GND I 5 Ground Pin for LVTTL Input (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Transmitters www.fairchildsemi.com 3 Pin Configuration Figure 4. FIN3386 and FIN3384(28:4 Receiver) Pin Assignment Pin Definitions Pin Names I/O Types Number of Pins Description of Signals RxIn I 4/3 Negative LVDS Differential Data Output RxIn+ I 4/3 Positive LVDS Differential Data Output RxCLKIn- I 1 Negative LVDS Differential Data Input RxCLKIn+ I 1 Positive LVDS Differential Clock Input RxOut O 28/21 RxCLKOut- O 1 LVTTL Level Data Output, goes HIGH for /PwrDn LOW LVTTL Clock Output /PwrDn I 1 LVTTL Level Input. Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Input LVDS GND I 3 Ground Pins for LVDS Input VCC I 4 Power Supply for LVTTL Output GND I 5 Ground Pins for LVTTL Output (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Receivers www.fairchildsemi.com 4 The outputs of the transmitter remain in the high-impedance state until the power supply reaches 2V. The following table shows the operation of the transmitter during power-up and power-down and operation of the /PwrDn pin. Transmitter PwrDn Normal VCC <2V >2V >2V >2V TxIN Don't Care Don't Care Active Active TxOUT High Impedance High Impedance Active Don't Care TxCLKIn Don't Care Don't Care Active LOW/HIGH/ High Impedance TxCLKOut High Impedance High Impedance Active Note 3 /PwrDn LOW LOW HIGH HIGH >2V >2V HIGH Notes: 3. If the transmitter is powered up, /PwrDn is inactive HIGH, and the clock input goes to any state LOW, HIGH, or high-impedance; the internal PLL goes to a known low frequency and stays until the clock starts normal operation again. Receiver /PwrDn RxIn Don't Care Don't Care Active Active Note 4 Note 4 RxOut High Impedance LOW LOW/HIGH Last Valid State HIGH Last Valid State RxCLKIn Don't Care Don't Care Active Note 4 Note 4 Note 4 RxCLKOut High Impedance Note 5 Active Note 5 Note 5 Note 5 /PwrDn LOW LOW HIGH HIGH HIGH HIGH VCC <2V <2V <2V <2V <2V <2V Notes: 4. If the input is terminated and un-driven (high-impedance) or shorted or open (fail-safe condition). 5. For /PwrDn or fail-safe condition the RxCLKOut pin goes LOW for Panel Link devices and HIGH for channel link devices. 6. Shorted means ( inputs are shorted to each other, or inputs are shorted to each other and ground or VCC, or either inputs are shorted to ground or VCC) with no other current/voltage sources (noise) applied. If the VID is still in the valid range (greater than 100mV) and VCM is in the valid range (0V to 2.4V), the input signal is still recognized and the part responds normally. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Transmitter and Receiver Power-Up / Power-Down Operation Truth Tables www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Power Supply Voltage Min. Max. Unit -0.3 +4.6 V VID_TTL TTL/CMOS Input/Output Voltage -0.5 +4.6 V VIO_LVDS LVDS Input/Output Voltage -0.3 +4.6 V IOSD LVDS Output Short-Circuit Current TSTG Storage Temperature Range Continuous +150 C TJ Maximum Junction Temperature +150 C TL Lead Temperature, Soldering, 4 Seconds +260 C ESD -65 Human Body Model, JESD22A114 (1.5k,100pF) I/O to GND >10.0 All Pins >6.5 kV >400 Machine Model, JESD22-A115 (0, 200pF) V Note: 7. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Supply Voltage TA Operating Temperature VCCNPP Maximum Supply Noise Voltage (8) Min. Max. Unit 3.0 3.6 V -10 +70 C 100 mVPP Note: 8. 100mV VCC noise should be tested for frequency at least up to 2MHz. All the specifications should be met under such a noise. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Absolute Maximum Ratings www.fairchildsemi.com 6 Typical values are at TA=25C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating temperatures ranges, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units Transmitter LVTTL Input Characteristics VIH Input HIGH Voltage 2.0 VCC V VIL Input LOW Voltage GND 0.8 V VIK Input Clamp Voltage -0.79 -1.50 V IIN Input Current 1.8 10.0 IIK=-18mA VIN=0.4V to 4.6V VIN=GND -10 0 A (9) Transmitter LVDS Output Characteristics VOD VOD VOS VOS Output Differential Voltage 250 VOD Magnitude Change from Differential LOW-to-HIGH RL=100, Figure 5 Offset Voltage 1.125 Offset Magnitude Change from Differential LOW-to-HIGH 1.250 450 mV 35 mV 1.375 V 25 IOS Short-Circuit Output Current VOUT=0V IOZ Disabled Output Leakage Current DO=0V to 4.6V, /PwrDn=0V mV -3.5 -5.0 mA 1 10 A 32.5MHz 31.0 49.5 40MHz 32.0 55.0 66MHz 37.0 60.5 85MHz 42.0 66.0 Transmitter Supply Current ICCWT ICCPDT ICCGT 28:4 Transmitter Power Supply Current (10) for Worst-Case Pattern (with Load) RL=100 Figure 8 Powered-Down Supply Current /PwrDn=0.8V 28:4 Transmitter Supply Current for 16 (10) Grayscale Figure (11) 23 10.0 55.0 32.5MHz 29.0 41.8 40MHz 30.0 44.0 66MHz 35.0 49.5 85MHz 39.0 55.0 mA A mA Notes: 9. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltages are referenced to ground unless otherwise specified (except VOD and VOD). 10. The power supply current for both transmitter and receiver can vary with the number of active I/O channels. 11. The 16-grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Transmitter DC Electrical Characteristics www.fairchildsemi.com 7 Typical values are at TA=25C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating temperatures ranges, unless otherwise specified. Symbol Parameter Conditions tTCP Transmit Clock Period tTCH Transmit Clock (TxCLKIn) HIGH Time tTCL Transmit Clock LOW Time tCLKT TxCLKIn Transition Time (Rising and Falling) tJIT TxCLKIn Cycle-to-Cycle Jitter tXIT TxIn Transition Time Figure 9 (10% to 90%) Figure 10 Min. Typ. Max. Units 11.76 T 50.00 ns 0.35 0.50 0.65 T 0.35 0.50 0.65 T 1.0 6.0 ns 3.0 1.5 6.0 ns 0.75 1.50 ns 0.75 1.50 ns LVDS Transmitter Timing Characteristics tTLH Differential Output Rise Time (20% to 80%) tTHL Differential Output Fall Time (20% to 80%) tSTC TxIn Setup to TxCLNIn tHTC TxIn Holds to TxCLNIn tTPDD tTCCD Figure 8 Figure 9 f=85MHz ns 0 ns (12) Transmitter Power-Down Delay Figure 14 Transmitter Clock Input to Clock Output Delay (TA=25C and with VCC=3.3V) Figure 13 Transmitter Output Data Jitter (f=40MHz) 2.5 100 ns 2.8 5.5 6.8 ns -0.25 0 0.25 ns (13) tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 a-0.25 a a+0.25 ns tTPPB2 Transmitter Output Pulse Position of Bit 2 2a-0.25 2a 2a+0.25 ns tTPPB3 Transmitter Output Pulse Position of Bit 3 3a-0.25 3a 3a+0.25 ns tTPPB4 Transmitter Output Pulse Position of Bit 4 4a-0.25 4a 4a+0.25 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.25 5a 5a+0.25 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.25 6a 6a+0.25 ns Transmitter Output Data Jitter (f=65MHz) Figure 20 1 a= f x7 (13) tTPPB0 Transmitter Output Pulse Position of Bit 0 -0.2 0 0.2 ns tTPPB1 Transmitter Output Pulse Position of Bit 1 a-0.2 a a+0.2 ns tTPPB2 Transmitter Output Pulse Position of Bit 2 2a-0.2 2a 2a+0.2 ns tTPPB3 Transmitter Output Pulse Position of Bit 3 3a-0.2 3a 3a+0.2 ns tTPPB4 Transmitter Output Pulse Position of Bit 4 4a-0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.2 6a 6a+0.2 ns Figure 20 1 a= f x7 Continued on following page... (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Transmitter AC Electrical Characteristics www.fairchildsemi.com 8 Over supply voltage and operating temperature ranges, unless otherwise specified. Transmitter Output Data Jitter (f=85MHz) (13) tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 a-0.2 tTPPB2 Transmitter Output Pulse Position of Bit 2 2a-0.2 tTPPB3 Transmitter Output Pulse Position of Bit 3 3a-0.2 tTPPB4 Transmitter Output Pulse Position of Bit 4 tTPPB5 Transmitter Output Pulse Position of Bit 5 tTPPB6 Transmitter Output Pulse Position of Bit 6 tJCC tTPLLS -0.2 FIN3385 Transmitter Clock Out Jitter, Cycle-to-Cycle Figure 20 Transmitter Phase Lock Loop Set Time 0.2 ns a a+0.2 ns 2a 2a+0.2 ns 3a 3a+0.2 ns 4a-0.2 4a 4a+0.2 ns 5a-0.2 5a 5a+0.2 ns 6a-0.2 6a 6a+0.2 ns f=40MHz 350 370 f=65MHz 210 230 110 150 Figure 20 1 a= f x7 (14) f=85MHz Figure 26 (13) 0 10 ps ms Notes: 12. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle 10ms after VCC reaches 3V and /PwrDn pin is above 1.5V. 13. This output data pulse position works for both transmitters for TTL inputs, except the LVDS output bit mapping difference (see Figure 18). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle delay is guaranteed when the MSB is output from transmitter. 14. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter of less than 2ns. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Transmitter AC Electrical Characteristics www.fairchildsemi.com 9 Typical values are at TA=25C and with VCC=3.3V. Minimum and maximum values are over supply voltage and operating temperature ranges unless otherwise specified. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltages are referenced to ground unless otherwise specified (except VOD and VOD). Symbol Parameter Conditions Min. Typ. Max. Units LVTTL/CMOS DC Characteristics VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage GND 0.8 V VOH Output High Voltage IOH=-0.4mA VOL Output Low Voltage IOL=2mA VIK Input Clamp Voltage IIK=-18mA IIN Input Current VIN=0V to 4.6V IOFF Input/Output Power-Off Leakage Current VCC=0V, All LVTTL Inputs / Outputs 0V to 4.6V IOS Output Short-Circuit Current VOUT=0V 2.7 3.3 V 0.06 0.30 -0.79 -1.50 V 10 A 10 A -120 m 100 mV -10 -60 V Receiver LVDS Input Characteristics VTH Differential Input Threshold HIGH Figure 6, Table 2 VTL Differential Input Threshold LOW Figure 6, Table 2 -100 VICM Input Common Mode Range Figure 6, Table 2 0.05 IIN Input Current mV 2.35 VIN=2.4V, VCC=3.6V or 0V 10 VIN=0V, VCC=3.6V or 0V 10 V A Receiver Supply Current 4:28 Receiver Power Supply Current for Worst Case (15) Pattern with Load ICCWR ICCPDT 3:21 Receiver Power Supply Current for Worst Case (15) Pattern with Load Powered-Down Supply Current (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 CL=8pF, Figure 7 32.5MHz 70 40MHz 75 66MHz 114 85MHz 135 32.5MHz 49 60 40MHz 53 65 66MHz 78 100 85MHz 90 115 NA 55 /PwrDn=0.8V (RxOut stays LOW) mA A FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Receiver DC Electrical Characteristics www.fairchildsemi.com 10 Typical values are at TA=25C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating temperatures ranges, unless otherwise specified. Symbol Parameter tRCOP Receiver Clock Output (RxCLKOut) Period tRCOL RxCLKOut LOW Time tRCOH RxCLKOut HIGH Time Conditions Figure 12 Rising Edge Strobe f=85MHz Min. Typ. Max. Units 11.76 T 50.00 4.0 5.0 6.0 ns 4.5 5.0 6.5 ns tRSRC RxOut Valid Prior to RxCLKOut 3.5 ns tRHRC RxOut Valid After RxCLKOut 3.5 ns tROLH Output Rise Time (20% to 80%) tROHL Output Rise Time (80% to 20%) tRCCD Receiver Clock Input to Clock Output (16) Delay TA=25C and VCC=3.3V Figure 24 tRPPD Receiver Power-Down Delay Figure 17 tRSPB0 Receiver Input Strobe Position of Bit 0 0.49 tRSPB1 Receiver Input Strobe Position of Bit 1 2.17 tRSPB2 Receiver Input Strobe Position of Bit 2 2.0 3.5 1.8 3.5 5.0 7.5 ns 1.0 s 0.84 1.19 ns 2.52 2.87 ns 3.85 4.20 4.55 ns 5.53 5.88 6.23 ns CL=8pF, Figure 8 Figure 21 f=85MHz 3.5 ns tRSPB3 Receiver Input Strobe Position of Bit 3 tRSPB4 Receiver Input Strobe Position of Bit 4 7.21 7.56 7.91 ns tRSPB5 Receiver Input Strobe Position of Bit 5 8.89 9.24 9.59 ns tRSPB6 Receiver Input Strobe Position of Bit 6 10.57 10.92 11.27 ns (17) tRSKM RxIN Skew Margin tRPLLS Receiver Phase Lock Loop Set Time Figure 21 Figure 21 290 ps 10 ms Notes: 15. The power supply current for the receiver can be different with the number of I/O channels. 16. Total channel latency from serializer to deserializer is (T + tTCCD). There is a clock period. 17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Receiver DC Electrical Characteristics (Continued) www.fairchildsemi.com 11 Symbol tRCOP Parameter Receiver Clock Output (RxCLKOut) Period tRCOL RxCLKOut LOW Time tRCOH RxCLKOut HIGH Time tRSRC RxOUT Valid Prior to RxCLKOut tRHRC tRCOL Conditions Figure 12 Min. Typ. Max. Units 15 T 50 ns 10.0 11.0 10.0 12.2 6.5 11.6 RxOUT Valid After RxCLKOut 6.0 11.6 RxCLKOut LOW Time 5.0 6.3 9.0 5.0 7.6 9.0 4.5 7.3 4.0 6.3 tRCOH RxCLKOut HIGH Time tRSRC RxOUT Valid Prior to RxCLKOut tRHRC RxOUT Valid After RxCLKOut Figure 12 Rising Edge Strobe f=40MHz Figure 12 Rising Edge (18) Strobe f=66MHz (18) ns tROLH Output Rise Time (20% to 80%) tROHL Output Fall Time (20% to 80%) tRCCD Receiver Clock Input to Clock Output (19) Delay Figure 14 TA=25C and VCC=3.3v tRPDD Receiver Power-Down Delay Figure 17 tRSPB0 Receiver Input Strobe Position of Bit 0 tRSPB1 Receiver Input Strobe Position of Bit 1 4.5 5.0 5.8 tRSPB2 Receiver Input Strobe Position of Bit 2 8.10 8.50 9.15 tRSPB3 Receiver Input Strobe Position of Bit 3 11.6 11.9 12.6 tRSPB4 Receiver Input Strobe Position of Bit 4 15.1 15.6 16.3 tRSPB5 Receiver Input Strobe Position of Bit 5 18.8 19.2 19.9 tRSPB6 Receiver Input Strobe Position of Bit 6 22.5 22.9 23.6 tRSPB0 Receiver Input Strobe Position of Bit 0 0.7 1.1 1.4 tRSPB1 Receiver Input Strobe Position of Bit 1 2.9 3.3 3.6 tRSPB2 Receiver Input Strobe Position of Bit 2 5.1 5.5 5.8 7.3 7.7 8.0 CL=8pF Figure 12 3.5 1.00 Figure 21 f=40MHz Figure 21 f=66MHz 2.0 5.0 1.8 5.0 5.0 7.5 ns 1.0 s 1.40 Receiver Input Strobe Position of Bit 3 tRSPB4 Receiver Input Strobe Position of Bit 4 9.5 9.9 10.2 tRSPB5 Receiver Input Strobe Position of Bit 5 11.7 12.1 12.4 tRSPB6 Receiver Input Strobe Position of Bit 6 13.9 14.3 14.6 tRSKM RxIn Skew Margin tRPLLS Receiver Phase Lock Loop Set Time f=40MHz, Figure 21 490 f=66MHz, Figure 21 400 Figure 15 ns 2.15 tRSPB3 (20) ns ns ns ps 10.0 ms Notes: 18. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes through +0.8V. 19. Total channel latency from serializer to deserializer is (T + tCCD) (2*T + tRCCD). There is the clock period. 20. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum / maximum bit position. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Receiver AC Electrical Characteristics (66MHz) www.fairchildsemi.com 12 Figure 5. Differential LVDS Output DC Test Circuit Notes: A: For all input pulses, tR or tF<=1ns. B: CL includes all probe and jig capacitance. Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and Transition Time Test Circuit Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) Resulting Differential Input Voltage (mV) Resulting Common Mode Input Voltage (V) VIA VIB VID VICM 1.25 1.15 100 1.20 1.15 1.25 -100 1.20 2.40 2.30 100 2.35 2.30 2.40 -100 2.35 0.10 0 100 0.05 0 0.10 -100 0.05 1.50 0.90 600 1.20 0.90 1.50 -600 1.20 2.40 1.80 600 2.10 1.80 2.40 -600 2.10 0.60 0 600 0.30 0 0.60 -600 0.30 (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Test Circuits www.fairchildsemi.com 13 Figure 7. Worst-Case Test Pattern Note: 21. The worst-case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or failing edge data strobe. Figure 8. Transmitter LVDS Output Load and Transition Times Figure 9. Transmitter Setup/Hold and HIGH/LOW Times (Rising-Edge Strobe) Figure 10. Transmitter Input Clock Transition Time FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer AC Loadings and Waveforms Figure 11. Transmitter Outputs Channel-to-Channel Skew (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 www.fairchildsemi.com 14 Figure 12. Receiver Setup/Hold and HIGH/LOW Times Note: 22. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes through +0.8V. Figure 13. Transmitter Clock-In to Clock-Out Delay (Rising-Edge Strobe) Figure 14. Receiver Clock-In to Clock-Out Delay (Falling-Edge Strobe) FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer AC Loadings and Waveforms (Continued) Figure 15. Receiver Phase Lock Loop Set Time (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 www.fairchildsemi.com 15 Figure 16. Transmitter Power-down Delay Figure 17. Receiver Power-Down Delay Figure 18. 28 Parallel LVTTL Inputs Mapped to Four Serial LVDS Outputs Note: 23. The information in this diagram shoes the difference between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is output from the transmitter. FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer AC Loadings and Waveforms (Continued) Figure 19. 21 Parallel LVTTL Inputs Mapped to Three Serial Outputs Note: 24. This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 www.fairchildsemi.com 16 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer AC Loadings and Waveforms (Continued) Figure 20. Transmitter Output Pulse Bit Position Figure 21. Receiver Input Bit Position Figure 22. Receiver LVDS Input Skew Margin Note: 25. tRSKM is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI). The minimum and maximum pulse position values are based on the bit position of each of the seven bits within the LVDS data stream across PVT (Process, Voltage Supply, and Temperature). (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 www.fairchildsemi.com 17 Figure 23. Transmitter Clock Out Jitter Measurement Setup Note: 26. Test setup used considers no requirement for separation of RMS and deterministic jitter. Other hardware setup, such as Wavecrest boxes, can be used if no M1 software is available, but the test methodology in Figure 24 should be followed. Figure 24. Timing Diagram of Transmitter Clock Input with Jitter Note: 27. This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with worst jitter 3ns (cycle-to-cycle) clock input. The specific test methodology is as follows: 28. Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to the right +3ns when data is HIGH. 29. The 3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst-case of clock-edge jump (3ns) from graphical controllers. Cycle-tocycle jitter at TxCLKOut pin should be measured cross VCC range with 100mV noise (VCC noise frequency <2MHz). (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer AC Loadings and Waveforms (Continued) www.fairchildsemi.com 18 Figure 25. "16 Grey-Scale" Test Pattern Note: 30. The 16-grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. Figure 26. Transmitter Phase-Lock-Loop Time (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer AC Loadings and Waveforms (Continued) www.fairchildsemi.com 19 A 56 51 34 29 1 6 23 28 6.15 7.6 9.125 B 8.10 1.45 4.05 0.2 C B A 0.30 0.50 0.1 C -C- 0.50 0.10 A B C 0.25 MTD56REV3 Figure 27. 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,6.1mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Physical Dimensions www.fairchildsemi.com 20 FIN3385/FIN3383/FIN3384/FIN3386 -- Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer 21 www.fairchildsemi.com (c) 2003 Fairchild Semiconductor Corporation FIN3383/3384/3385/3386 * Rev. 1.0.4