INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock FEATURES * * * * * * * * * * Real time clock keeps tracks of hundredths of seconds, minutes, hours, days, date of the months, and years. Watch function is transparent to RAM operation. Data Retention over 10 years in absence of power. 512K x 8 NV SRAM directly replaces volatile static RAM or EEPROM. Embedded lithium energy cell maintains calendar operation and retains RAM data. Standard 32 pin DIP JEDEC Pinout. Month and year determine the number of days in each month Full +10% operating range. Operating temperature range 0oC to 70oC. Available in 120 ns access time. Functional Description The IM 1251Y 4096K NV SRAM with Phantom Clock is a fully static nonvolatile RAM organized as 512K words by 8 bits with a built-in real time clock. This `NV SRAM' has all the normal characteristics of a CMOS static RAM with an important benefit of data being retained in the absence of power. Data retention current is so small that a miniature lithium cell contained within the package provides an energy source to preserve data. Protection against data loss has also been incorporated to maintain data integrity during power on/off conditions. The Phantom Clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month and year information. The date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock operates in either 24hour or 12-hour format with an AM/PM indicator. Pin configuration A18/RST A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PIN NAMES A0-A18 CE GND I/O0-I/O-7 Vcc WE OE RST Address Inputs Chip Enable Ground Input/Output Power(+5V) Write Enable Output Enable Reset INNOVATIVE MICROTECHNOLOGY INC.Phone/Fax-440-322-8083.Website:www.innovativemicrotechnology.com INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock READ MODE The IM 1251Y performs a read cycle whenever WE high and CE low. The unique address specified by the 19 address inputs A0-A18 defines which of the 4,194,304 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within access time tACC after the last address input is stable, provided that CE and OE access times are satisfied. If OE or CE access times are not satisfied, data access will be measured from the limiting parameter (tCO or tOE), rather than address. The state of the eight data I/O lines is controlled by the OE and CE control signals. The data lines may be in an indeterminate state between tOH and tAA but the data lines will always have valid data at tAA. WRITE MODE The IM 1251Y is in the write mode whenever CE and WE inputs are held low. The latter occurring falling edge of either CE or WE determines the start of a write cycle. A write is terminated by the earlier rising edge of CE or WE. The address must be held valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another Read or Write cycle can be initiated. CE or WE is high during power on to perfect memory after Vcc reaches Vcc (min) but before the processor stabilizes. DATA RETENTION The IM 1251Y provides full functional capability for Vcc greater than 4.75V and write protects at 4.5V. Data is retained in the absence of Vcc without any additional support circuitry. The SRAM constantly monitors Vcc. The moment Vcc decays, the RAM automatically write protects itself. All inputs to the RAM become "don't care" and all outputs are in high impedance-state. As Vcc falls below approximately 3.0V the power switching circuit connects the lithium energy source to RAM to retain data. During power-on, when Vcc rises above approximately 3.0V the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc becomes greater than 4.5V. Maximum Ratings Operating Temperature....0oC to 70oC Storage Temperature.......0oC to 70oC Soldering Temperature And Time......................260oC for 10 sec Supply Voltage................-0.5V to 7.0V Input Voltage..................-0.5V to 7.0V Input/ Output Voltage.......-0.5V to Vcc + 0.3V Power Dissipation............1.0W Recommended D.C. Operating Conditions Parameter Symbol Min. Supply Voltage Vcc 4.5 Gnd 0 Typ 5.0 - Max. 5.5 0 Unit V V Input Voltage Vcc +0.3 0.8 V V VIH 2.2 3.5 VIL 0 - INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock PHANTOM CLOCK OPEARTION PHANTOM CLOCK REGISTER INFORMATION Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on I/ O0. All access which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 read or write cycles either extract or update data in the Phantom Clock, and memory access is inhibited. Initially, a read cycle to any memory location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the Phantom Clock. However, write cycle generated to gain access to the Phantom Cycle are also writing data to a location in the mated RAM. When the first write cycle is executed it is compared to bit 0 of the 64-bit comparison register, If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register have been matched. With a correct match for 64-bits the Phantom Clock is enabled and data transfer to or from the timekeeping register can proceed. The next 64-cycles will cause the Phantom Clock to either receive or transmit data on I/O0, depending the level of the OE pin or the WE. The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Phantom Clock registers, each register must be handled in - groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. AM/PM 12/24 MODE Bit 7of the hours register is defined as the 12-or24 hour mode selectbit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit(20-23 hours). INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock PHANTOM CLOCK REGISTER DEFINTION 7 BYTE 0 5 4 3 2 1 HEX VALUE 0 C5 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 3A 1 0 1 0 0 0 1 1 A3 0 1 0 1 1 1 0 0 5C 1 1 0 0 0 1 0 1 C5 0 0 1 1 1 0 1 0 BYTE 1 BYTE 2 6 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 1 1 0 0 0 1 0 1 0 1 0 1 1 1 0 0 3A A3 5C INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock OSCILATTOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET bit is set to logic0, A low input on the RESET pin will cause the Phantom Clock to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to a logic 1. PHANTOM CLOCK REGISTER DEFINTION RANGE (BCD) REGISTER 0.1 SEC 0 1 10 SEC 0 SECONDS 10 MIN 2 0 3 12/24 0 4 0 0 5 0 0 6 0 0 7 0.01 SEC 10 10YEAR A/P OSC 00-59 MINUTES 00-59 HR HOUR 01-12 00-23 RST DAY 01-07 DATE 01-13 MONTH 01-12 10 DATE 0 00-99 10 MONTH YEAR 00-99 INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock DC ELECTRICAL CHARACTERISTICS (00C TO 700C; Vcc = 5V + 10%) PARAMETER SYMBOL Input Leakage Current MIN TYP MAX UNITS IIL -1.0 +1.0 A I/O Leakage Current CE > VIH < Vcc IIO -1.0 +1.0 A Output Current @ 2.4V IOH -1.0 Output Current @ 0.4V IOL Standby Current CE = 2.25V ICCS1 5.0 10 mA Standby Current CE = Vcc- 0.5V ICCS2 3.0 5.0 mA Operating Current tCYC = 120ns ICC01 85 mA mA 2.0 mA Notes 1. Typical values are measured at Ta = 25OC and Vcc = 5V Capacitance Parameter Description Test conditons Min. Typ Max Unit CI CI/O Input capacitance I/O capacitance Vi =0V VIO = 0V - 5 5 10 10 pF pF INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock Switching Characteristics over the operating range Parameter Description Min tRC tACC tOE tCO tCOE tOD tOH Read cycle time 120 Address access time Output enable access time CE to output valid OE or CE to output valid 5 Output High Z from Deselection Output hold from adds change 5 tWC tAW tWP tWR tODW tOEW tDS tDH Write cycle time Address setup time Write pulse-width Write recovery time Output High Z from WE Output Active from WE Input data setup time Input data hold time Max 120 60 120 40 Unit ns ns ns ns ns ns ns 120 0 90 20 ns ns ns ns 40 ns 5 50 20 ns ns ns POWER DOWN/POWER UP TIMING PARAMETER CE at VIH before power-down SYMBOL tPD MIN TYP MAX UNITS 0 us Vcc Slow from 4.5 V to 0V (CE at VIH) tF 300 us Vcc Slow from 0V to 4.5 V (CE at VIH) tR 0 us CE at VIH after Power-Up tREC 2 ms INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS(00C TO 700C,Vcc= 4.5 TO 5.5V) PARAMETER SYMBOL MIN Read Cycle Time CE Access Time OE Access Time CE to Output Low Z OE to Output Low Z CE to Output High Z OE to Output High Z Read Recovery t RC t CO tOE tCOE tOEE tOD tODO tRR 120 Write Cycle Time Write Pulse Width Write Recovery Data Setup Time Data Hold Time CE Pulse Width RESET Pulse Width CE High to Power-Fail tWC tWP tWR tDS tDH tCW tRST tPF 120 100 20 40 10 100 200 TYP MAX 100 100 10 10 40 40 20 0 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock READ CYCLE tRC VIH ADDRESSES VIH VIL VIL tOH tACC VIH CE VIH VIL tOD tCO VIH OE VIH VIL tOD tCOE DOUT VOH VOH tCOF OUTPUT DATA VALID VOL VOL WRITE CYCLE 1 tWC ADDRESSES VIH VIH VIL VIL tAW VIH CE VIL VIL tWR tWP VIH WE VIL VIL tODW tOEW High Impedance DOUT tDS VIH DIN VIH Data In Stable VIL VIL RESET FOR PHATOM CLOCK RST tDH1 tRST INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock WRITE CYCLE 2 tWC ADDRESSES VIH VIH VIL VIL tWR2 tAW tWP VIH VIH CE VIL VIL VIL VIL VIH WE tODW tCOE DOUT tDH tDS VIH DIN VIH Data In Stable VIL VIL Read cycle to Phantom Clock tCOE tCO tRR CE tOD tOE OE tODO tOEE tCOE Q Output Data Valid INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock Write Cycle to Phantom Clock tWC OE=VIH tWR tWP WE tWR tCW CE tDH tDH tDS D FIG. D TION Data IN Stable POWER - DOWN/ POWER -ON CONDI- 4.75V -------------------------------------------------------------------------------------------------- tF tR 3.2V ---------------------------------------------------------------------------------------------------- tPD LI Cell Leakage Current tREC Data Retention Time tDR INNOVATIVE IM1251 4096K NV SRAM with Phantom Clock INNOVATIVE IM 1251 Serial RTC + SRAM mm - yy B J H A C F G D DIM IN INCHES MIN. MAX. A B C D E F G H J 1.54 0.72 0.415 0.13 0.021 0.16 0.11 0.63 0.012 1.52 0.695 0.395 0.1 0.015 0.12 0.09 0.59 0.008 E