TLC2543CDBR - Texas Instruments

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12-Bit-Resolution A/D Converter

10-µs Conversion Time Over Operating

Temperature

11 Analog Input Channels

3 Built-In Self-Test Modes

Inherent Sample-and-Hold Function

Linearity Error . . . ±1 LSB Max

On-Chip System Clock

End-of-Conversion Output

Unipolar or Bipolar Output Operation

(Signed Binary With Respect to 1/2 the

Applied Voltage Reference)

Programmable MSB or LSB First

Programmable Power Down

Programmable Output Data Length

CMOS Technology

Application Report Available†

description

The TLC2543C and TLC2543I are 12-bit, switched-

capacitor, successive-approximation, analog-to-

digital converters. Each device, with three control

inputs [chip select (CS), the input-output clock, and

the address input (DATA INPUT)], is designed for

communication with the serial port of a host processor

or peripheral through a serial 3-state output. The

device allows high-speed data transfers from the

host.

In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel

multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The

sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high

to indicate that conversion is complete. The converter incorporated in the device features differential

high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry

from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating

temperature range.

The TLC2543C is characterized for operation from TA = 0°C to 70°C. The TLC2543I is characterized for

operation from T A = –40°C to 85°C. The TLC2543M is characterized for operation from T A = –55°C to 125°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

GND

VCC

EOC

I/O CLOCK

DATA INPUT

DATA OUT

REF+

REF–

AIN10

AIN9

(TOP VIEW)

DB, DW, J, OR N PACKAGE

3 2 1 20 19

910111213

I/O CLOCK

DATA INPUT

DATA OUT

AIN3

AIN4

AIN5

AIN6

AIN7

FN PACKAGE

(TOP VIEW)

AIN1

AIN0

AIN10

REF –

AIN2

EOC

AIN8

GND

AIN9 VCC

REF+

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

TASMALL OUTLINE PLASTIC CHIP

CARRIER CERAMIC DIP PLASTIC DIP

(DB)†(DW)†(FN)†(J) (N)

0°C to 70°C TLC2543CDB TLC2543CDW TLC2543CFN —TLC2543CN

–40°C to 85°C TLC2543IDB TLC2543IDW TLC2543IFN —TLC2543IN

–55°C to 125°C— — — TLC2543MJ —

†Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543IDBR, TLC2543CDWR, TLC2543IDWR, TLC2543CFNR, or

TLC2543IFNR.

functional block diagram

14-Channel

Analog

Multiplexer

Sample-and-

Hold

Function

12-Bit

Analog-to-Digital

Converter

(Switched Capacitors)

Self-Test

Reference

Output

Data

12-to-1 Data

Selector and

Driver

Control Logic

and I/O

Counters

Input Address

REF+ REF–

DATA

OUT

DATA

INPUT

I/O CLOCK

EOC

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

14 13

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

AIN0 – AIN10 1–9,

11, 12 IAnalog input. These 1 1 analog-signal inputs are internally multiplexed. The driving source impedance should

be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input

voltage into a capacitance of 60 pF.

CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DA T A OUT,

DA T A INPUT, and I/O CLOCK. A low-to-high transition disables DA T A INPUT and I/O CLOCK within a setup

time.

DATA INPUT 17 I Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.

The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK.

After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order .

DATA OUT 16 O The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS

is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state

and is driven to the logic level corresponding to the MSB/LSB† value of the previous conversion result. The

next falling edge of I/O CLOCK drives DA T A OUT to the logic level corresponding to the next MSB/LSB, and

the remaining bits are shifted out in order.

EOC 19 O End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and

remains low until the conversion is complete and the data is ready for transfer.

GND 10 Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage

measurements are with respect to GND.

I/O CLOCK 18 I Input/output clock. I/O CLOCK receives the serial input and performs the following four functions:

1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK

with the multiplexer address available after the fourth rising edge.

2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input

begins charging the capacitor array and continues to do so until the last falling edge of the I/O

CLOCK.

3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on

the falling edge of I/O CLOCK.

4. It transfers control of the conversion to the internal state controller on the falling edge of the last

I/O CLOCK.

REF+ 14 I Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The

maximum input voltage range is determined by the difference between the voltage applied to this terminal and

the voltage applied to the REF– terminal.

REF–13 I Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–.

VCC 20 Positive supply voltage

†MSB/LSB = Most significant bit / least significant bit

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise

noted)†

Supply voltage range, VCC (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Positive reference voltage, Vref+ V

CC + 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Negative reference voltage, Vref– –0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current, II (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current, II (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLC2543C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC2543I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC2543M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTE 1: All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, VCC 4.5 5 5.5 V

Positive reference voltage, V ref+ (see Note 2) VCC V

Negative reference voltage, V ref– (see Note 2) 0 V

Differential reference voltage, Vref+ – Vref– (see Note 2) 2.5 VCC VCC+0.1 V

Analog input voltage (see Note 2) 0 VCC V

High-level control input voltage, VIH VCC = 4.5 V to 5.5 V 2 V

Low-level control input voltage, VIL VCC = 4.5 V to 5.5 V 0.8 V

Clock frequency at I/O CLOCK 0 4.1 MHz

Setup time, address bits at DATA INPUT before I/O CLOCK↑, tsu(A) (see Figure 4) 100 ns

Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4) 0 ns

Hold time, CS low after last I/O CLOCK↓, th(CS) (see Figure 5) 0 ns

Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5) 1.425 µs

Pulse duration, I/O CLOCK high, twH(I/O) 120 ns

Pulse duration, I/O CLOCK low, twL(I/O) 120 ns

T ransition time, I/O CLOCK high to low, tt(I/O) (see Note 4 and Figure 6) 1µs

T ransition time, DATA INPUT and CS, tt(CS) 10 µs

TLC2543C 0 70

Operating free-air temperature, TATLC2543I –40 85 °C

TLC2543M –55 125

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied

to REF– convert as all zeros (000000000000).

3. T o minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control

input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed.

4. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of

normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data acquisition applications

where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TLC2543C, TLC2543I

UNIT

PARAMETER

TEST

CONDITIONS

MIN TYP†MAX

UNIT

VOH

High level out

ut voltage

VCC = 4.5 V, IOH = –1.6 mA 2.4

High

level

output

voltage

VCC = 4.5 V to 5.5 V, IOH = –20 µA VCC–0.1

VOL

Low level out

ut voltage

VCC = 4.5 V, IOL = 1.6 mA 0.4

Low

level

output

voltage

VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1

IOZ

h-impedance off-state output VO = VCC, CS at VCC 1 2.5

µA

current VO = 0, CS at VCC 1–2.5 µ

IIH High-level input current VI = VCC 1 2.5 µA

IIL Low-level input current VI = 0 1–2.5 µA

ICC Operating supply current CS at 0 V 1 2.5 mA

ICC(PD) Power-down current For all digital inputs,

0 ≤VI ≤ 0.5 V or VI ≥ VCC – 0.5 V 4 25 µA

Selected channel leakage

Selected channel at VCC,Unselected channel at 0 V 1

Selected

channel

leakage

current Selected channel at 0 V,

Unselected channel at VCC –1µA

Maximum static analog

reference current into REF+ Vref+ = VCC, Vref– = GND 1 2.5 µA

Input Analog inputs 30 60 p

icapacitance Control inputs 5 15

†All typical values are at VCC = 5 V, TA = 25°C.

electrical characteristics over recommended operating free-air temperature range,

VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TLC2543M

UNIT

PARAMETER

TEST

CONDITIONS

MIN TYP†MAX

UNIT

VOH

High level out

ut voltage

VCC = 4.5 V, IOH = –1.6 mA 2.4

High

level

output

voltage

VCC = 4.5 V to 5.5 V, IOH = –20 µA VCC–0.1

VOL

Low level out

ut voltage

VCC = 4.5 V, IOL = 1.6 mA 0.4

Low

level

output

voltage

VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1

IOZ

h-impedance off-state output VO = VCC, CS at VCC 1 2.5

µA

current VO = 0, CS at VCC 1–2.5 µ

IIH High-level input current VI = VCC 1 10 µA

IIL Low-level input current VI = 0 1–10 µA

ICC Operating supply current CS at 0 V 1 2.5 mA

ICC(PD) Power-down current For all digital inputs,

0 ≤VI ≤ 0.5 V or VI ≥ VCC – 0.5 V 4 25 µA

Selected channel leakage

Selected channel at VCC,Unselected channel at 0 V 10

Selected

channel

leakage

current Selected channel at 0 V,

Unselected channel at VCC –10 µA

Maximum static analog

reference current into REF+ Vref+ = VCC, Vref– = GND 1 2.5 µA

Input Analog inputs 30 60 p

icapacitance Control inputs 5 15

†All typical values are at VCC = 5 V, TA = 25°C.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range,

VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

ELLinearity error (see Note 5) See Figure 2 ±1 LSB

EDDifferential linearity error See Figure 2 ±1 LSB

EOOffset error (see Note 6) See Note 2 and

Figure 2 ±1.5 LSB

EGGain error (see Note 6) See Note 2 and

Figure 2 ±1 LSB

ETTotal unadjusted error (see Note 7) ±1.75 LSB

DATA INPUT = 1011 2048

Self-test output code (see Table 3 and Note 8) DATA INPUT = 1100 0

DATA INPUT = 1101 4095

t(conv) Conversion time See Figures 9–14 8 10 µs

tcTotal cycle time (access, sample, and conversion) See Figures 9–14

and Note 9

10 + total

I/O CLOCK

periods +

td(I/O-EOC)

µs

tacq Channel acquisition time (sample) See Figures 9–14

and Note 9 4 12 I/O

CLOCK

periods

tvValid time, DATA OUT remains valid after I/O CLOCK↓See Figure 6 10 ns

td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 150 ns

td(I/O-EOC) Delay time, last I/O CLOCK↓ to EOC↓See Figure 7 1.5 2.2 µs

td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB/LSB) See Figure 8 100 ns

tPZH, tPZL Enable time, CS↓ to DATA OUT (MSB/LSB driven) See Figure 3 0.7 1.3 µs

tPHZ, tPLZ Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 70 150 ns

tr(EOC) Rise time, EOC See Figure 8 15 50 ns

tf(EOC) Fall time, EOC See Figure 7 15 50 ns

tr(bus) Rise time, data bus See Figure 6 15 50 ns

tf(bus) Fall time, data bus See Figure 6 15 50 ns

td(I/O-CS) Delay time, last I/O CLOCK↓ to CS↓ to abort conversion

(see Note 10) 5µs

†All typical values are at TA = 25°C.

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that

applied to REF– convert as all zeros (000000000000).

5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified

gain point after the of fset error has been adjusted to zero. Of fset error is the difference between the actual midstep value and the

nominal midstep value at the offset point.

7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

8. Both the input address and the output codes are expressed in positive logic.

9. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 7).

10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs

of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether

the conversion is aborted or the conversion results are valid.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

0.1 µF

10 µFC3

470 pF

50 Ω

15 V

50 Ω

–15 V

VIAIN0–AIN10

TLC2543

10 Ω

10 µFC3

470 pF

0.1 µF

LOCATION

DESCRIPTION

OP27

10-µF 35-V tantalum capacitor

0.1-µF ceramic NPO SMD capacitor

470-pF porcelain Hi-Q SMD capacitor

PART NUMBER

—

AVX 12105C104KA105 or equivalent

Johanson 201S420471JG4L or equivalent

Figure 1. Analog Input Buffer to Analog Inputs AIN0–AIN10

EOC

CL = 50 pF 12 kΩ

DATA OUT

Test Point VCC

RL = 2.18 kΩ

CL = 100 pF 12 kΩ

Test Point VCC

RL = 2.18 kΩ

Figure 2. Load Circuits

DATA

OUT

2.4 V

0.4 V

90%

10%

tPZH, tPZL tPHZ, tPLZ

0.8 V 2 V

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

DATA INPUT

th(A)

0.8 V

2 V

I/O CLOCK

Data

Valid

tsu(A)

0.8 V

Figure 4. DATA INPUT and I/O CLOCK

Voltage Waveforms

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Last

Clock

CS 0.8 V 2 V

0.8 V

tsu(CS)

0.8 V

I/O CLOCK

th(CS)

NOTE A: To ensure full conversion accuracy , it is recommended that no input signal change

occurs while a conversion is ongoing.

Figure 5. CS and I/O CLOCK Voltage Waveforms

0.4 V

2.4 V 0.4 V

2.4 V

2 V 0.8 V

I/O CLOCK

DATA OUT

tt(I/O)

0.8 V

2 V

tr(bus), tf(bus)

td(I/O-DATA)

tt(I/O)

0.8 V

I/O CLOCK Period

Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms

Last

Clock 0.8 V

2.4 V 0.4 V

tf(EOC)

td(I/O-EOC)

I/O CLOCK

EOC

Figure 7. I/O CLOCK and EOC Voltage Waveforms

0.4 V

2.4 V

EOC

td(EOC-DATA)

Valid MSB

DATA OUT

0.4 V 2.4 V

tr(EOC)

Figure 8. EOC and DATA OUT Voltage Waveforms

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎÎÎÎ

ÎÎÎ

ÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval InitializeInitialize

MSB LSB

Previous Conversion Data

MSB LSB

B7 B6 B5 B4 C7

B11A11 A10 A9 A8 A7 A6 A5 A4 A1 A0 Hi-Z State

1 2 3 4 5 6 7 8 11 12 1

I/O

CLOCK

DATA

OUT

DATA

INPUT

EOC

(see Note A)

B3 B2 B1 B0

ÎÎÎ

ÎÎ

t(conv)

NOTE A: T o minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.

Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 9. Timing for 12-Clock Transfer Using CS With MSB First

ÎÎÎ

ÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B7 B6 B5 B4 C7

B11A11 A10 A9 A8 A7 A6 A5 A4 A1 A0 Low Level

1 2 3 4 5 6 7 8 11 12 1

I/O

CLOCK

DATA

OUT

DATA

INPUT

EOC

Initialize

(see Note A)

B3 B2 B1 B0

ÎÎ

t(conv)

NOTE A: T o minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.

Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎÎ

ÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B7 B6 B5 B4 C7

B7A7 A6 A5 A4 A3 A2 A1 A0

12345678 1

I/O CLOCK

DATA OUT

DATA INPUT

EOC

Initialize

ÎÎÎÎÎÎ

Hi-Z

(see Note A)

B3 B2 B1 B0

ÎÎ

t(conv)

NOTE A: T o minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.

Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 11. Timing for 8-Clock Transfer Using CS With MSB First

ÎÎ

ÎÎÎ

ÎÎ

Access Cycle B Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B7 B6 B5 B4 C7

B7A7 A6 A5 A4 A3 A2 A1 A0 Low Level

12345678 1

I/O CLOCK

DATA OUT

DATA INPUT

EOC

Initialize

(see Note A)

ÎÎ

B3 B2 B1 B0

ÎÎ

t(conv)

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

NOTE A: T o minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.

Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

ÎÎ

ÎÎÎ

ÎÎ

A/D Conversion

Interval

Initialize

MSB LSB

B7 B6 B5 B4 C7

B15A15 A14 A13 A12 A11 A10 A9 A8 A1 A0

1 2 3 4 5 6 7 8 15 16 1

I/O

CLOCK

DATA

OUT

DATA

INPUT

EOC

Initialize

ÎÎÎÎÎÎÎ

Hi-Z State

(see Note A)

B3 B2 B1 B0

Access Cycle B Sample Cycle B

Previous Conversion Data

ÎÎ

t(conv)

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

NOTE A: T o minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.

Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 13. Timing for 16-Clock Transfer Using CS With MSB First

ÎÎ

ÎÎÎÎ

A/D Conversion

Interval

Initialize

MSB LSB

B7 B6 B5 B4 C7

B15A15 A14 A13 A12 A11 A10 A9 A8 A1 A0

1 2 3 4 5 6 7 8 15 16 1

I/O

CLOCK

DATA

OUT

DATA

INPUT

EOC

Low Level

(see Note A)

B3 B2 B1 B0

Sample Cycle B

Access Cycle B

Previous Conversion Data

ÎÎ

t(conv)

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

NOTE A: T o minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.

Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the

high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DAT A INPUT

and removes DATA OUT from the high-impedance state.

The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7–D4), a 2-bit data length

select (D3–D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are

applied to DA T A INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the

input data register.

During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data

the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge

of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last

falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.

converter operation

The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle and 2) the

actual conversion cycle.

I/O cycle

The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending

on the selected output data length.

During the I/O cycle, the following two operations take place simultaneously.

An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is

shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first

eight clocks during 12- or 16-clock I/O transfers.

The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the

first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output

data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the

first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.

conversion cycle

The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to

I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the

analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when

conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O

cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

power up and initialization

After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data

should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O

cycle. The first conversion after the device has returned from the power-down state may not read accurately

due to internal device settling.

Table 1. Operational Terminology

Current (N) I/O cycle The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks

the digital result from the previous conversion from DATA OUT

Current (N) conversion cycle The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the

last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output

Current (N) conversion result The current conversion result is serially shifted out on the next I/O cycle.

Previous (N–1) conversion cycle The conversion cycle just prior to the current I/O cycle

Next (N+1) I/O cycle The I/O period that follows the current conversion cycle

Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during

the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even

when this corrupts the output data from the previous conversion. The current conversion is begun

immediately after the twelfth falling edge of the current I/O cycle.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

data input

The data input is internally connected to an 8-bit serial-input address and control register . The register defines

the operation of the converter and the output data length. The host provides the data word with the MSB first.

Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data input-register

format).

Table 2. Input-Register Format

INPUT DATA BYTE

FUNCTION SELECT

ADDRESS BITS L1 L0 LSBF BIP

FUNCTION

SELECT

(MSB) D6 D5 D4 D3 D2 D1 D0

(LSB)

Select input channel

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

Select test voltage

(Vref+ – Vref–)/2

V ref–

V ref+

Software power down 1110

Output data length

8 bits

12 bits

16 bits

X†

Output data format

MSB first

LSB first (LSBF) 0

Unipolar (binary) 0

Bipolar (BIP) 2s complement 1

†X represents a do not care condition.

data input address bits

The four MSBs (D7 – D4) of the data register address one of the 11 input channels, a reference-test voltage,

or the power-down mode. The address bits affect the current conversion, which is the conversion that

immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+ – Vref–.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

data output length

The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is

valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the

current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can

be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.

With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current

conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly

12 bits long for proper synchronization, even when this means corrupting the output data from a previous

conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.

With bits D3 and D2 set to 1 1, the 16-bit data-length mode is selected, which allows convenient communication

with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial

data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must

be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the

previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current

I/O cycle.

With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit

serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream

during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even

when this means corrupting the output data from the previous conversion. The four LSBs of the conversion

result are truncated and discarded. The current conversion is started immediately after the eighth falling edge

of the current I/O cycle.

Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict

with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when

the data format is selected to be least significant bit first, since at the time the data length change becomes

effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.

In actual operation, when different data lengths are required within an application and the data length is changed

between two conversions, no more than one conversion result can be corrupted and only when it is shifted out

in LSB-first format.

sampling period

During the sampling period, one of the analog inputs is internally connected to the capacitor array of the

converter to store the analog input signal. The converter starts sampling the selected input immediately after

the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge

of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge

of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK

falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has

begun. After EOC goes low , the analog input can be changed without affecting the conversion result. Since the

delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be

digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.

After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC

goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the

influence of external digital noise.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

data register, LSB first

D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is reset

to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of

MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one

data direction to another, the current I/O cycle is never disrupted.

data register, bipolar format

D0 (BIP) in the input data register controls the binary data format used to represent the conversion result. When

D0 is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the

conversion result of an input voltage equal to Vref– is a code of all zeros (000 . . . 0), the conversion result of

an input voltage equal to V ref+ is a code of all ones (111 . . . 1), and the conversion result of (Vref + + Vref–)/2

is a code of a one followed by zeros (100 ...0).

When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally , conversion

of an input voltage equal to Vref– is a code of a one followed by zeros (100 . . . 0), conversion of an input voltage

equal to V ref+ is a code of a zero followed by all ones (011 . . . 1), and the conversion of (V ref+ + V ref–)/2 is a

code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the

unipolar format in that the MSBs are always each other’s complement.

Selection of the unipolar or bipolar format always af fects the current conversion cycle, and the result is output

during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the

current I/O cycle is not affected.

EOC output

The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During

the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high

until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs

after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input

data register. After the EOC signal goes low, the analog input signal can be changed without affecting the

conversion result.

The EOC signal goes high again after the conversion is completed and the conversion result is latched into the

output data register . The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.

On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low . When

CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the

falling edge of CS.

data format and pad bits

D3 and D2 of the input data register determine the number of significant bits in the digital output that represent

the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines

the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.

The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of

the internal result are discarded to provide a faster one-byte transfer . When a 12-bit transfer is used, all bits are

transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion

result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are

zeros.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

data format and pad bits (continued)

When CS is held low continuously, the first data bit of the newly completed conversion occurs on DATA OUT

on the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes

low and the serial output is forced to a setting of 0 until EOC goes high again.

When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS.

On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next

bit in the serial conversion result until the required number of bits has been output.

chip-select input (CS)

CS enables and disables the device. During normal operation, CS should be low . Although the use of CS is not

necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data

transfer of several devices sharing the same bus.

When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing

its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK

is inhibited, thus preventing any further change in the internal state.

When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce

time before the reset operation takes effect. After CS is debounced low , I/O CLOCK must remain inactive (low)

for a minimum time before a new I/O cycle can start.

CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough

before the end of the current conversion cycle, the previous conversion result is saved in the internal output

buffer and shifted out during the next I/O cycle.

power-down features

When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles,

the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse.

During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed,

and the internal output buffer keeps the previous conversion cycle data results provided that all digital inputs

are held above VCC – 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be

completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,

the converter normally begins in the power-down mode. The device remains in the power-down mode until a

valid input address (other than 1110) is clocked in. Upon completion of that I/O cycle, a normal conversion is

performed with the results being shifted out during the next I/O cycle.

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

analog input, test, and power-down mode

The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer

according to the input addresses shown in T ables 2, 3, and 4. The input multiplexer is a break-before-make type

to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on

the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held

on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then

sampled and converted in the same manner as the external analog inputs. The first conversion after the device

has returned from the power-down state may not read accurately due to internal device settling.

Table 3. Analog-Channel-Select Address

ANALOG INPUT

SELECTED

VALUE SHIFTED INTO

DATA INPUT

SELECTED

BINARY HEX

AIN0 0000 0

AIN1 0001 1

AIN2 0010 2

AIN3 0011 3

AIN4 0100 4

AIN5 0101 5

AIN6 0110 6

AIN7 0111 7

AIN8 1000 8

AIN9 1001 9

AIN10 1010 A

Table 4. Test-Mode-Select Address

INTERNAL

SELF-TEST

VOLTAGE

VALUE SHIFTED INTO

DATA INPUT UNIPOLAR OUTPUT

RESULT (HEX)‡

VOLTAGE

SELECTED†BINARY HEX

RESULT

(HEX)‡

Vref+ – Vref–

21011 B 800

Vref–1100 C 000

Vref+ 1101 D FFF

†Vref+ is the voltage applied to REF+, and Vref– is the voltage applied to REF–.

‡The output results shown are the ideal values and may vary with the reference stability

and with internal offsets.

Table 5. Power-Down-Select Address

INPUT COMMAND VALUE SHIFTED INTO

DATA INPUT RESULT

BINARY HEX

Power down 1110 E ICC ≤ 25 µA

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously .

This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)

voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and

the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks

at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF –. When the voltage at the

summing node is greater than the trip point of the threshold detector (approximately 1/2 VCC), a bit 0 is placed

in the output register and the 4096-weight capacitor is switched to REF–. When the voltage at the summing node

is less than the trip point of the threshold detector , a bit 1 is placed in the register and this 4096-weight capacitor

remains connected to REF+ through the remainder of the successive-approximation process. The process is

repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are

determined. With each step of the successive-approximation process, the initial charge is redistributed among

the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.

reference voltage inputs

The two reference inputs used with the device are the voltages applied to the REF+ and REF– terminals. These

voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale

reading respectively. These voltages and the analog input should not exceed the positive supply or be lower

than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the

input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower

than REF– terminal voltage. SC

Threshold

Detector

Node 4096

REF–

REF+

4096

To Output

Latches

REF–

REF+

REF–

REF+

REF–

REF+

REF–

REF+

REF–

REF+

REF–

REF+

REF–

112481610242048

Figure 15. Simplified Model of the Successive-Approximation System

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

100000000000

011111111111

000000000010

000000000001

000000000000

111111111110

0 0.0024 2.4564 2.4576 2.4588

Digital Output Code

100000000001

111111111101

111111111111

4.9128 4.9140 4.9152

2048

2047

4094

Step

2049

4093

4095

0.0006

VI – Analog Input Voltage – V

VZT = VZS + 1/2 LSB

VZS

See Notes A and B

4.9134

0.0012

VFT = VFS – 1/2 LSB

VFS

VFSnom

NOTES: A. This curve is based on the assumption that Vref+ and Vref– have been adjusted so that the voltage at the transition from digital 0

to 1 (VZT) is 0.0006 V and the transition to full scale (VFT) is 4.9134 V. 1 LSB = 1.2 mV.

B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is

the step whose nominal midstep value equals zero.

Figure 16. Ideal Conversion Characteristics

Processor Control

Circuit

Analog

Inputs

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

I/O CLOCK

DATA INPUT

DATA OUT

EOC

REF+

REF–

GND

TLC2543

To Source

Ground

5-V DC Regulated

Figure 17. Serial Interface

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079F – DECEMBER 1993 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 V to

VS within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

)

Where: Rt = Rs + ri

1–e–tc

RtCi

The final voltage to 1/2 LSB is given by

(2)VC (1/2 LSB) = VS – (VS/8192)

Equating equation 1 to equation 2 and solving for time tc gives

)

and tc (1/2 LSB) = Rt × Ci × ln(8192) (4

)

*ǒ

8192

Ǔ+

1–e–tc

RtCi

Therefore, with the values given, the time for the analog input signal to settle is

(5)

tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(8192)

This time must be less than the converter sample time shown in the timing diagrams.

Rsri

VSVC

60 pF Max

1 kΩ Max

Driving Source†TLC2543

VI= Input Voltage at AIN

VS= External Driving Source Voltage

Rs= Source Resistance

ri= Input Resistance

Ci= Input Capacitance

VC= Capacitance Charging Voltage

†Driving source requirements:

•Noise and distortion for the source must be equivalent to the

resolution of the converter.

•Rs must be real at the input frequency.

Figure 18. Equivalent Input Circuit Including the Driving Source

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

5962-9688601QRA ACTIVE CDIP J 20 1 TBD Call TI Call TI

TLC2543CDB ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CDBG4 ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CDBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI

TLC2543CDBR ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CDW ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CDWR ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543CFN ACTIVE PLCC FN 20 46 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM

TLC2543CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM

TLC2543CFNR ACTIVE PLCC FN 20 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM

TLC2543CFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM

TLC2543CN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

TLC2543CNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

TLC2543IDB ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543IDBG4 ACTIVE SSOP DB 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TLC2543IDBR ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543IDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543IDW ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543IDWR ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2543IFN ACTIVE PLCC FN 20 46 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM

TLC2543IFNG3 ACTIVE PLCC FN 20 46 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM

TLC2543IFNR OBSOLETE PLCC FN 20 TBD Call TI Call TI

TLC2543IN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

TLC2543INE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

TLC2543MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

TLC2543MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 3

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC2543, TLC2543M :

•Catalog: TLC2543

•Automotive: TLC2543-Q1, TLC2543-Q1

•Enhanced Product: TLC2543-EP, TLC2543-EP

•Military: TLC2543M

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLC2543CDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

TLC2543IDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLC2543CDBR SSOP DB 20 2000 367.0 367.0 38.0

TLC2543IDBR SSOP DB 20 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MPLC004A – OCTOBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

4040005/B 03/95

20 PIN SHOWN

0.026 (0,66)

0.032 (0,81)

D2/E2

0.020 (0,51) MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

D2/E2

0.013 (0,33)

0.021 (0,53)

Seating Plane

MAX

D2/E2

0.219 (5,56)

0.169 (4,29)

0.319 (8,10)

0.469 (11,91)

0.569 (14,45)

0.369 (9,37)

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.008 (0,20) NOM

1.158 (29,41)

0.958 (24,33)

0.756 (19,20)

0.191 (4,85)

0.141 (3,58)

MIN

0.441 (11,20)

0.541 (13,74)

0.291 (7,39)

0.341 (8,66)

E1E

MINMAXMIN

PINS

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

84 1.185 (30,10)

0.985 (25,02)

0.785 (19,94)

D/E

0.395 (10,03)

0.495 (12,57)

1.195 (30,35)

0.995 (25,27)

0.695 (17,65)

0.795 (20,19)

NO. OF D1/E1

0.350 (8,89)

0.450 (11,43)

1.150 (29,21)

0.950 (24,13)

0.650 (16,51)

0.750 (19,05)

0.004 (0,10)

0.007 (0,18)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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