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FEATURES DESCRIPTION
APPLICATIONS
VDD
SCLA0
GND
Output
Buffer
Power-Down
Control Logic Resistor
Network
Ref (+) Ref(−)
8-Bit
DAC
I2C
Control
Logic
DAC
Register
Power-On
Reset
VOUT
SDA
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
+2.7 V to +5.5 V, I
2
C INTERFACE, VOLTAGE OUTPUT,8-BIT DIGITAL-TO-ANALOG CONVERTER
•Micropower Operation: 125 µA @ 3 V
The DAC5571 is a low-power, single-channel, 8-bit•Fast Update Rate: 188 KSPS
buffered voltage output DAC. Its on-chip precisionoutput amplifier allows rail-to-rail output swing to be•Power-On Reset to Zero
achieved. The DAC5571 utilizes an I
2
C-compatible,•+2.7-V to +5.5-V Power Supply
two-wire serial interface that operates at clock rates•Specified Monotonic by Design
up to 3.4 Mbps with address support of up to two•I
2
C™ Interface up to 3.4 Mbps
DAC5571s on the same data bus.•On-Chip Output Buffer Amplifier, Rail-to-Rail
The output voltage range of the DAC is 0 V to V
DD
.Operation
The DAC5571 incorporates a power-on-reset circuit•Double-Buffered Input Register
that ensures that the DAC output powers up at zero•Address Support for up to Two DAC5571s
volts and remains there until a valid write to thedevice takes place. The DAC5571 contains a•Small 6 Lead SOT 23 Package
power-down feature, accessed via the internal control•Operation From –40 °C to 105 °C
register, that reduces the current consumption of thedevice to 50 nA at 5 V.
The low-power consumption of this part in normal•Process Control
operation makes it ideally suited for portable battery•Data Acquistion Systems
operated equipment. The power consumption is less•Closed-Loop Servo Control
than 0.7 mW at V
DD
= 5 V reducing to 1 µW in•PC Peripherals power-down mode.•Portable Instrumentation
DAC7571/6571/5571 are 12/10/8-bit, single-channelI
2
C DACs from the same family. DAC7574/6574/5574and DAC7573/6573/5573 are 12/10/8-bitquad-channel I
2
C DACs. Also see DAC8571/8574 forsingle/quad-channel, 16-bit I
2
C DACs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.I
2
C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PIN CONFIGURATIONS
A0
SCL
SDA
6
5
4
1
2
3
VOUT
GND
VDD
D571
1
2
3
6
5
4
YMLL
(TOP VIEW)
(BOTTOM VIEW)
Lot Trace Code
ABSOLUTE MAXIMUM RATINGS
(1)
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
SPECIFIED TEM- PACKAGE ORDERING NUM-PRODUCT PACKAGE DESIG- TRANSPORT MEDIAPERATURE RANGE MARKING BERNATOR
DAC5571IDBVT 250-Piece Small Tape and ReelDAC5571 SOT23-6 DBV –40°C to +105°C D571
DAC5571IDBVR 3000-Piece Tape and Reel
PIN DESCRIPTION (SOT23-6)
PIN NAME DESCRIPTION
1 V
OUT
Analog output voltage from DACGround reference point for all2 GND
circuitry3 V
DD
Analog Voltage Supply Input4 SDA Serial Data Input5 SCL Serial Clock Input6 A0 Device Address SelectLOT Year (3 = 2003); Month (1–9 = JAN–SEP; A=OCT,TRACE B=NOV, C=DEC); LL– Random code generatedCODE: when assembly is requested
UNITS
V
DD
to GND – 0.3 V to +6 VDigital input voltage to GND –0.3 V to +V
DD
+0.3 VV
OUT
to GND – 0.3 V to +V
DD
+0.3 VOperating temperature range –40 °C to +105 °CStorage temperature range –65 °C to +150 °CJunction temperature range (T
J
max) +150 °CPower dissipation (T
J
max - T
A
)R
ΘJA
Thermal impedance, R
ΘJA
240 °C/WLead temperature, soldering Vapor phase (60s) 215 °CInfrared (15s) 220 °C
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.
2
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ELECTRICAL CHARACTERISTICS
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
V
DD
= +2.7 V to +5.5 V; R
L
= 2 k Ωto GND; C
L
= 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted.
DAC5571PARAMETER CONDITIONS UNITSMIN TYP MAX
STATIC PERFORMANCE
(1)
Resolution 8 BitsRelative accuracy ±0.5 LSBDifferential nonlinearity Assured monotonic by design ±0.25 LSBZero code error 5 20 mVFull-scale error All ones loaded to DAC register -0.15 -1.25 % of FSRGain error ±1.25 % of FSRZero code error drift ± 7 µV/°CGain temperature coefficient ± 3 ppm of FSR/ °C
OUTPUT CHARACTERISTICS
(2)
Output voltage range 0 V
DD
V1/4 Scale to 3/4 scale change (400
H
to C00
H
) ;Output voltage settling time 6 8 µsR
L
=∞Slew rate 1 V/µsR
L
=∞470 pFCapacitive load stability
R
L
= 2 k Ω1000 pFCode change glitch impulse 1 LSB Change around major carry 20 nV-sDigital feedthrough 0.5 nV-sDC output impedance 1 ΩV
DD
= +5 V 50 mAShort-circuit current
V
DD
= +3 V 20 mAComing out of power-down mode, V
DD
= +5 V 2.5 µsPower-up time
Coming out of power-down mode, V
DD
= +3 V 5 µs
LOGIC INPUTS
(3)
Input current ±1 µAV
IN
L, Input low voltage V
DD
= +3 V 0.3×V
DD
VV
IN
H, Input high voltage V
DD
= +5 V 0.7×V
DD
VPin capacitance 3 pF
POWER REQUIREMENTS
V
DD
2.7 5.5 VI
DD
(normal operation) DAC active and excluding load currentV
DD
= +3.6 V to +5.5 V V
IH
= V
DD
and V
IL
= GND 155 200 µAV
DD
= +2.7 V to +3.6 V V
IH
= V
DD
and V
IL
= GND 125 160 µAI
DD
(all power-down modes)V
DD
= +3.6 V to +5.5 V V
IH
= V
DD
and V
IL
= GND 0.2 1 µAV
DD
= +2.7 V to +3.6 V V
IH
= V
DD
and V
IL
= GND 0.05 1 µA
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, V
DD
= +5 V 93 %
(1) Linearity calculated using a reduced code range of 3 to 253; output unloaded.(2) Specified by design and characterization, not production tested.(3) Specified by design and characterization, not production tested.
3
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TIMING CHARACTERISTICS
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
f
SCL
SCL Clock Frequency Standard mode 100 kHzFast mode 400 kHzHigh-speed mode, C
B
- 100 pF max 3.4 MHzHigh-Speed mode, C
B
- 400 pF max 1.7 MHzt
BUF
Bus Free Time Between a STOP Standard mode 4.7 µsand START Condition
Fast mode 1.3 µst
HD
; t
STA
Hold Time (Repeated) START Standard mode 4.0 µsCondition
Fast mode 600 nsHigh-speed mode 160 nst
LOW
LOW Period of the SCL Clock Standard mode 4.7 µsFast mode 1.3 µsHigh-speed mode, C
B
- 100 pF max 160 nsHigh-speed mode, C
B
- 400 pF max 320 nst
HIGH
HIGH Period of the SCL Clock Standard mode 4.0 µsFast mode 600 nsHigh-speed mode, C
B
- 100 pF max 60 nsHigh-speed mode, C
B
- 400 pF max 120 nst
SU
; t
STA
Setup Time for a Repeated Standard mode 4.7 µsSTART Condition
Fast mode 600 nsHigh-speed mode 160 nst
SU
; t
DAT
Data Setup Time Standard mode 250 nsFast mode 100 nsHigh-speed mode 10 nst
HD
; t
DAT
Data Hold Time Standard mode 0 3.45 µsFast mode 0 0.9 µsHigh-speed mode, C
B
- 100 pF max 0 70 nsHigh-speed mode, C
B
- 400 pF max 0 150 nst
RCL
Rise Time of SCL Signal Standard mode 1000 nsFast mode 20 + 0.1C
B
300 nsHigh-speed mode, C
B
- 100 pF max 10 40 nsHigh-speed mode, C
B
- 400 pF max 20 80 nst
RCL1
Rise Time of SCL Signal After a Standard mode 1000 nsRepeated START Condition and
Fast mode 20 + 0.1C
B
300 nsAfter an Acknowledge BIT
High-speed mode, C
B
- 100 pF max 10 80 nsHigh-speed mode, C
B
- 400 pF max 20 160 nst
FCL
Fall Time of SCL Signal Standard mode 300 nsFast mode 20 + 0.1C
B
300 nsHigh-speed mode, C
B
- 100 pF max 10 40 nsHigh-speed mode, C
B
- 400 pF max 20 80 nst
RDA
Rise Time of SDA Signal Standard mode 1000 nsFast mode 20 + 0.1C
B
300 nsHigh-speed mode, C
B
- 100 pF max 10 80 nsHigh-speed mode, C
B
- 400 pF max 20 160 nst
FDA
Fall Time of SDA Signal Standard mode 300 nsFast mode 20 + 0.1C
B
300 nsHigh-speed mode, C
B
- 100 pF max 10 80 nsHigh-speed mode, C
B
- 400 pF max 20 160 ns
4
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TYPICAL CHARACTERISTICS: V
DD
= +5 V
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
0 32 64 96 128 160 192 224 256
Digital Input Code
VDD = 5 V at 25°C
LE − LSBDLE − LSB
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
0 32 64 96 128 160 192 224 256
VDD = 5 V at −40°C
Digital Input Code
LE − LSBDLE − LSB
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
0 32 64 96 128 160 192 224 256
Digital Input Code
VDD = 5 V at 105°C
LE − LSB
DLE − LSB
−16
−8
0
8
16
0 32 64 96 128 160 192 224 256
Digital Input Code
VDD = 5 V, TA = 25°C
Output Error − mV
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
TIMING CHARACTERISTICS (continued)SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
t
SU
; t
STO
Setup Time for STOP Condition Standard mode 4.0 µsFast mode 600 nsHigh-speed mode 160 nsC
B
Capacitive Load for SDA and SCL 400 pFt
SP
Pulse Width of Spike Suppressed Fast mode 50 nsHigh-speed mode 10 nsV
NH
Noise Margin at the HIGH Level Standard mode 0.2V
DD
Vfor Each Connected Device
Fast mode(Including Hysteresis)
High-speed modeV
NL
Noise Margin at the LOW Level for Standard mode 0.1V
DD
VEach Connected Device
Fast mode(Including Hysteresis)
High-speed mode
At T
A
= +25°C, +V
DD
= +5 V, unless otherwise noted.
LINEARITY ERROR AND LINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs vsCODE (-40°C) CODE (+25°C )
Figure 1. Figure 2.
LINEARITY ERROR AND ABSOLUTE ERRORDIFFERENTIAL LINEARITY ERRORvsCODE (+105°C)
Figure 3. Figure 4.
5
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−30
−20
−10
0
10
20
30
−50−40−30−20 −10 0 10 20 30 40 50 60 70 80 90 100 110
VDD = 5 V
T − Temperature − C
Zero-Scale Error
−30
−20
−10
0
10
20
30
−50 −40 −30−20 −10 0 10 20 30 40 50 60 70 80 90 100 110
VDD = 5 V
Full-Scale Error − mV
T − Temperature − C
0
VOUT (V)
ISOURCE/SINK (mA)
5 10 15
5
4
3
2
1
0
DAC Loaded with FFH
DAC Loaded with 00H
0
100
200
300
400
500
0 2 32 64 96 128 160 192 224 252 255
Code
VDD = 5 V
IDD Aµ − Supply Current −
0
50
100
150
200
250
300
−50 −40−30 −20−10 0 10 20 30 40 50 60 70 80 90 100110
VDD = 5 V
− Supply Current −
IDD Aµ
T − Temperature − C
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)At T
A
= +25°C, +V
DD
= +5 V, unless otherwise noted.
ZERO-SCALE ERROR FULL-SCALE ERRORvs vsTEMPERATURE TEMPERATURE
Figure 5. Figure 6.
I
DD
HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY
Figure 7. Figure 8.
SUPPLY CURRENT SUPPLY CURRENTvs vsCODE TEMPERATURE
Figure 9. Figure 10.
6
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0
50
100
150
200
250
300
2.7 3.2 3.7 4.2 4.7 5.2 5.7
− Supply Current −
IDD Aµ
VDD − Supply Voltage − V
2.7
IDD (nA)
VDD (V)
3.2 3.7 4.2 4.7 5.2 5.7
100
90
80
70
60
50
40
30
20
10
0
+25°C
–40°C
+105°C
CLK (5V/div)
VOUT (1V/div)
Time (1µs/div)
Full−Scale Code Change
00Hto FFH
Output Loaded with
2k and 200pF to GNDΩ
0
IDD (µA)
VLOGIC (V)
1 2 3 4 5
2500
2000
1500
1000
500
0
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)At T
A
= +25°C, +V
DD
= +5 V, unless otherwise noted.
SUPPLY CURRENT POWER-DOWN CURRENTvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 11. Figure 12.
SUPPLY CURRENT FULL-SCALE SETTLING TIMEvsLOGIC INPUT VOLTAGE
Figure 13. Figure 14.
7
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Time (1 s/div)
CLK (5V/div)
VOUT (1V/div)
Full−Scale Code Change
FFHto 00H
Output Loaded with
2k and 200pF to GNDΩ
µ
Time (1 s/div)
CLK (5V/div)
VOUT (1V/div)
Half−Scale Code Change
40Hto C0H
Output Loaded with
2k and 200pF to GNDΩ
µ
Time ( s/div)
CLK (5V/div)
VOUT (1V/div)
Half−Scale Code Change
C0Hto 40 H
Output Loaded with
2kΩand 200pF to GND
1m
1µ
Time (20µs/div)
Loaded with 2kΩ to VDD.
VDD (1V/div)
VOUT (1V/div)
Time (0.5 s/div)
Loaded with 2k
and 200pF to GND.
Code Change:
80Hto 7FH
VOUT (20mV/div)
Ω
µ
Time (5µs/div)
CLK (5V/div)
V
OUT
(1V/div)
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)At T
A
= +25°C, +V
DD
= +5 V, unless otherwise noted.
FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME
Figure 15. Figure 16.
HALF-SCALE SETTLING TIME POWER-ON RESET TO 0V
Figure 17. Figure 18.
EXITING POWER DOWN CODE CHANGE GLITCH(80
H
Loaded)
Figure 19. Figure 20.
8
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TYPICAL CHARACTERISTICS: V
DD
= +2.7 V
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
0 32 64 96 128 160 192 224 256
Digital Input Code
VDD = 2.7 V at −40°C
LE − LSBDLE − LSB
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
0 32 64 96 128 160 192 224 256
Digital Input Code
LE − LSB
DLE − LSB
VDD = 2.7 V at 25°C
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
0 32 64 96 128 160 192 224 256
Digital Input Code
VDD = 2.7 V at 105°C
LE − LSBDLE − LSB
−16
−8
0
8
16
032 64 96 128 160 192 224 256
Digital Input Code
Output Error − mV
VDD = 2.7 V TA = 25°C
−50 −30 −10 10 30 50 70 90 110
−30
−20
−10
0
10
20
30 VDD = 5 V
VDD = 2.7 V
Full-Scale Error − mV
T − Temperature − C
−30
−20
−10
0
10
20
30
−50 −30 −10 10 30 50 70 90 110
VDD = 2.7 V
Zero-ScalenError − mV
T − Temperature − C
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
At T
A
= +25°C, +V
DD
= +2.7 V, unless otherwise noted.
LINEARITY ERROR AND LINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs vsCODE (-40°C) CODE (+25°C)
Figure 21. Figure 22.
LINEARITY ERROR AND ABSOLUTE ERRORSDIFFERENTIAL LINEARITY ERRORvsCODE (+105°C)
Figure 23. Figure 24.
ZERO-SCALE ERROR FULL-SCALE ERRORvs vsTEMPERATURE TEMPERATURE
Figure 25. Figure 26.
9
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0
500
1000
1500
2000
2500
80
90
100
110
120
130
140
150
160
170
180
190
200
VDD = 2.7 V
IDD − Supply Current − A
f − Frequency − Hz
0
VOUT (V)
ISO U RC E /S IN K (mA)
5 10 15
3
2
1
0
DAC Loaded with FFH
DAC Loaded with 00H
VDD = +3V
0
100
200
300
400
500
0 2 32 64 96 128 160 192 224 252 255
VDD = 2.7 V
Code
IDD Aµ − Supply Current −
0
50
100
150
200
250
300
−50 −30 −10 10 30 50 70 90 110
VDD = 2.7 V
− Supply Current −IDD Aµ
T − Temperature − C
Time (1 s/div)
CLK (2.7V/div)
VOUT (1V/div)
Full−Scale Code Change
00Hto FFH
Output Loaded with
2k and 200pF to GNDΩ
µ
0
IDD (µA)
VLOGIC (V)
1 2 3 4 5
2500
2000
1500
1000
500
0
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: V
DD
= +2.7 V (continued)At T
A
= +25°C, +V
DD
= +2.7 V, unless otherwise noted.
I
DD
HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY
Figure 27. Figure 28.
SUPPLY CURRENT SUPPLY CURRENTvs vsCODE TEMPERATURE
Figure 29. Figure 30.
SUPPLY CURRENT FULL SCALE SETTLING TIMEvsLOGIC INPUT VOLTAGE
Figure 31. Figure 32.
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Time (1 s/div)
CLK (2.7V/div)
VOUT (1V/div) Full−Scale Code Change
FFHto 00H
Output Loaded with
2k and 200pF to GNDΩ
µ
Time (1s/div)
CLK (2.7V/div)
VOUT (1V/div)
Half−Scale Code Change
40Hto C0H
Output Loaded with
2Ωand 200pFto GND
k
Time (1 s/div)
CLK (2.7V/div)
VOUT (1V/div)
Half−Scale Code Change
C0Hto 40H
Output Loaded with
2k and 200pF to GNDΩ
µ
POWER-ON RESET to 0V
Time (20µs/div)
Time (0.5s/div)
Loaded with 2k
and 200pF to GND.
Code Change:
80Hto 7FH.
VOUT (20mV/div)
H
Time (5µs/div)
CLK (2.7V/div)
V
OUT
(1V/div)
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
TYPICAL CHARACTERISTICS: V
DD
= +2.7 V (continued)At T
A
= +25°C, +V
DD
= +2.7 V, unless otherwise noted.
FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME
Figure 33. Figure 34.
HALF-SCALE SETTLING TIME POWER-ON RESET 0 V
Figure 35. Figure 36.
EXITING-POWER DOWN (80
H
Loaded) CODE CHANGE GLITCH
Figure 37. Figure 38.
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THEORY OF OPERATION
D/A SECTION
REF (+)
REF (-)
Resistor
String Output
Amplifier
VOUT
GND
VDD
DAC Register
VOUT 

RESISTOR STRING
VDD To Output
Amplifier
R
R R RGND
OUTPUT AMPLIFIER
I
2
C Interface
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
The architecture of the DAC5571 consists of a string DAC followed by an output buffer amplifier. Figure 39shows a block diagram of the DAC architecture.
Figure 39. R-String DAC Architecture
The input coding to the DAC5571 is unsigned binary, which gives the ideal output voltage as:
where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255.
The resistor string section is shown in Figure 40 . It is basically a divide-by-2 resistor, followed by a string ofresistors, each of value R. The code loaded into the DAC register determines at which node on the string thevoltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to theamplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
Figure 40. Resistor String
The output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, whichgives an output range of 0 V to V
DD
. It is capable of driving a load of 2 k Ωin parallel with 1000 pF to GND. Thesource and sink capabilities of the output amplifier can be seen in the typical characteristics curves. The slewrate is 1 V/µs with a half-scale settling time of 7 µs with the output unloaded.
I
2
C is a two-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the busis idle, both SDA and SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus throughopen drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,controls the bus. The master is responsible for generating the SCL signal and device addresses. The master alsogenerates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/ortransmits data on the bus under control of the master device.
The DAC5571 works as a slave and supports the following data transfer modes, as defined in the I
2
C-Bus
12
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F/S-Mode Protocol
HS-Mode Protocol
Start
Condition
SDA
Stop
Condition
SDA
SCL
S P
SCL
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
THEORY OF OPERATION (continued)Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The datatransfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode inthis document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to asHS-mode. The DAC5571 supports 7-bit addressing; 10-bit addressing and general call address are notsupported.
•The master initiates data transfer by generating a start condition. The start condition is when a high-to-lowtransition occurs on the SDA line while SCL is high, as shown in Figure 41 . All I
2
C-compatible devices shouldrecognize a start condition.•The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bitR/ W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data conditionrequires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42 ). All devicesrecognize the address sent by the master and compare it to their internal fixed addresses. Only the slavedevice with a matching address generates an acknowledge (see Figure 43 ) by pulling the SDA line lowduring the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that acommunication link with a slave has been established.•The master generates further SCL cycles to either transmit data to the slave (R/ W bit 1) or receive data fromthe slave (R/ W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. Soan acknowledge signal can either be generated by the master or by the slave, depending on which one is thereceiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as longas necessary.
•To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from lowto high while the SCL line is high (see Figure 41 ). This releases the bus and stops the communication linkwith the addressed slave. All I
2
C compatible devices must recognize the stop condition. On the receipt of astop condition, all devices know that the bus is released, and they wait for a start condition followed by amatching address.
•When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.•The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge theHS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbpsoperation.
•The master then generates a repeated start condition (a repeated start condition has the same timing as thestart condition). After this repeated start condition, the protocol is the same as F/S-mode, except thattransmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all theinternal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeatedstart conditions should be used to secure the bus in HS-mode.
Figure 41. START and STOP Conditions
13
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Change of Data Allowed
Data Line
Stable;
Data Valid
SDA
SCL
Not Acknowledge
Acknowledge
1 2 8 9
Clock Pulse for
Acknowledgement
S
START
Condition
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK 1 2 3 - 8 9
ACK
Address
R/W
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
THEORY OF OPERATION (continued)
Figure 42. Bit Transfer on the I
2
C Bus
Figure 43. Acknowledge on the I
2
C Bus
Figure 44. Bus Protocol
14
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DAC5571 I
2
C Update Sequence
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
THEORY OF OPERATION (continued)
The DAC5571 requires a start condition, a valid I
2
C address, a control-MSB byte, and an LSB byte for a singleupdate. After the receipt of each byte, DAC5571 acknowledges by pulling the SDA line low during the high periodof a single clock pulse. A valid I
2
C address selects the DAC5571. The CTRL/MSB byte sets the operationalmode of the DAC5571, and the four most significant bits. The DAC5571 then receives the LSB byte containingfour least significant data bits followed by four don't care bits. DAC5571 performs an update on the falling edgeof the acknowledge signal that follows the LSB byte.
For the first update, DAC5571 requires a start condition, a valid I
2
C address, a CTRL/MSB byte, an LSB byte.For all consecutive updates, DAC5571 needs a CTRL/MSB byte, and an LSB byte.
Using the I
2
C high-speed mode (f
scl
= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other thanthe first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte,acknowledge signal), at 188.88 KSPS. Using the fast mode (f
scl
= 400 kHz), clock running at 400 kHz, maximumDAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC5571 releases the I
2
C bus andawaits a new start condition.
Address Byte
MSB LSB
100110A0 0
The address byte is the first byte received following the START condition from the master device. The first sixbits (MSBs) of the address are factory preset to 100110. The next bit of the address is the device select bit A0.The A0 address input can be connected to V
DD
or digital GND, or can be actively driven by TTL/CMOS logiclevels. The device address is set by the state of this pin during the power-up sequence of the DAC5571. Up totwo devices (DAC5571) can be connected to the same I
2
C-Bus without requiring additional glue logic.
Broadcast Address Byte
MSB LSB
10010000
Broadcast addressing is also supported by DAC5571. Broadcast addressing can be used for synchronouslyupdating or powering down multiple DAC5571 devices. Using the broadcast address, DAC5571 respondsregardless of the state of the address pin A0.
Control - Most Significant Byte
Most Significant Byte CTRL/MSB[7:0] consists of two zeros, two power-down bits, and four most significant bitsof 8-bit unsigned binary D/A conversion data.
Least Significant Byte
Least Significant Byte LSB[7:0] consists of the four least significant bits of the 8-bit unsigned binary D/Aconversion data, followed by four don't care bits. DAC5571 updates at the falling edge of the acknowledge signalthat follows the LSB[0] bit.
15
www.ti.com
SLAVE ADDRESS R/W A Ctrl/MS-Byte A LS-Byte A/A P
”0” (write) Data T ransferred
(n* Words + Acknowledge)
Word = 16 Bit
From Master to DAC5571
From DAC5571 to Master
A = Acknowledge (SDA LOW)
A=Not Acknowledge (SDA HIGH)
S = START Condition
Sr = Repeated START Condition
P= STOP Condition
DAC5571 I2C-SLAVE ADDRESS:
1 0 0 1 1 0 A0 R/W
MSB LSB
Factory Preset
A0 = I2C Address Pin
Standard- and Fast-Mode:
S
HS-Master Code R/W A Ctrl/MS-Byte A LS-Byte A/A P
”0” (write) Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
High-Speed Mode (HS Mode):
S A Sr Slave Address
HS Mode Continues
F/S-Mode HS Mode F/S Mode
Sr Slave Address
0 0 0 0 1 X X R/W
MSB LSB
HS-Mode Master Code:
0 0 PD1 PD0 D7 D6 D5 D4
MSB LSB
Ctrl/MS-Byte:
D3 D2 D1 D0 X X X X
MSB LSB
LS-Byte:
D7 − D0 = Data Bits
’0’ = Write to DAC5571
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
Figure 45. Master Transmitter Addressing DAC5571 as a Slave Receiver With a 7-Bit Address
16
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POWER-ON RESET
POWER-DOWN MODES
Resistor
String DAC
Power-Down
VOUT
Amplifier
Resistor
Network
Circuitry
CURRENT CONSUMPTION
DRIVING RESISTIVE AND CAPACITIVE LOADS
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
The DAC5571 contains a power-on reset circuit that controls the output voltage during power up. On power up,the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a validwrite sequence is made to the DAC. This is useful in applications where it is important to know the state of theDAC output while it is in the process of powering up.
The DAC5571 contains four separate modes of operation. These modes are programmable via two bits (PD1and PD0). Table 1 shows how the state of these bits correspond to the mode of operation.
Table 1. Modes of Operation for the DAC5571
PD1 PD0 OPERATING MODE
0 0 Normal Operation0 1 1k Ωto AGND, PWD1 0 100 k Ωto AGND, PWD1 1 High Impedance, PWD
When both bits are set to zero, the device works normally with normal power consumption of 150 µA at 5 V.However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not onlydoes the supply current fall but the output stage is also internally switched from the output of the amplifier to aresistor network of known values. This has the advantage that the output impedance of the device is known whilein power-down mode. There are three different options: The output is connected internally to AGND through a1-k Ωresistor, a 100-k Ωresistor, or it is left open-circuited (high impedance). The output stage is illustrated inFigure 46 .
Figure 46. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DACregister are unaffected when in power down. The time required to exit power down is typically 2.5 µs for AV
DD
=5 V and 5 µs for AV
DD
= 3 V. See the Typical Characteristics section for more information.
The DAC5571 typically consumes 150 µA at V
DD
= 5 V and 120 µA at V
DD
= 3 V. Additional current consumptioncan occur due to the digital inputs if V
IH
<< V
DD
. For most efficient power operation, CMOS logic levels arerecommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200 nA.
The DAC5571 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offsetand gain error margins, the DAC5571 can operate rail-to-rail when driving a capacitive load. When the outputs ofthe DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB outputstage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearityperformance of the DAC. This may occur within approximately the top 20 mV of the DAC's digital input-to-voltageoutput transfer characteristic.
17
www.ti.com
OUTPUT VOLTAGE STABILITY
APPLICATIONS
USING REF02 AS A POWER SUPPLY FOR THE DAC5571
REF02
15 V
5 V
1.14 mA
A0
SCL
SDA
I2C
Interface
VOUT = 0 V to 5 V
DAC5571
LAYOUT
DAC5571
SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005
The DAC5571 exhibits excellent temperature stability of 5 ppm/ °C typical output voltage drift over the specifiedtemperature range of the device. This enables the output voltage to stay within a ±25- µV window for a ±1 °Cambient temperature change. Combined with good dc noise performance and true 8-bit differential linearity, theDAC5571 becomes a perfect choice for closed-loop control applications.
Due to the extremely low supply current required by the DAC5571, a possible configuration is to use a REF02+5-V precision voltage reference to supply the required voltage to the DAC5571's supply input as well as thereference input, as shown in Figure 47 . This is especially useful if the power supply is quite noisy or if the systemsupply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC5571.If the REF02 is used, the current it needs to supply to the DAC5571 is 140 µA typical. When a DAC output isloaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5-mWload on a given DAC output) is: 140 µA + (5 mW/5 V) = 1.14 mA.
The load regulation of the REF02 is typically (0.005% ×V
DD
)/mA, which results in an error of 0.285 mV for the1.14-mA current drawn from it. This corresponds to a 0.015 LSB error for a 0-V to 5-V output range.
Figure 47. REF02 as Power Supply to DAC5571
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated powersupplies.
The power applied to V
DD
should be well regulated and low noise. Switching power supplies and dc/dcconverters often has high-frequency glitches or spikes riding on the output voltage. In addition, digitalcomponents can create similar high-frequency spikes as their internal logic switches states. This noise can easilycouple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, V
DD
should be connected to a +5-V power supply plane or trace that is separatefrom the connection for digital logic until they are connected at the power entry point. In addition, the 1- µF to10- µF and 0.1- µF bypass capacitors are strongly recommended. In some situations, additional bypassing may berequired, such as a 100- µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—alldesigned to essentially low-pass filter the +5-V supply, removing the high-frequency noise.
18
PACKAGE OPTION ADDENDUM
www.ti.com 22-Oct-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC5571IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
DAC5571IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
DAC5571IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
DAC5571IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC5571IDBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
DAC5571IDBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC5571IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
DAC5571IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jul-2011
Pack Materials-Page 2
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