LT1016IS8#PBF - Linear Technology

LT1016

APPLICATIO S

FEATURES

DESCRIPTIO

TYPICAL APPLICATION

The LT

1016 is an UltraFast 10ns comparator that inter-

faces directly to TTL/CMOS logic while operating off either

±5V or single 5V supplies. Tight offset voltage specifica-

tions and high gain allow the LT1016 to be used in

precision applications. Matched complementary outputs

further extend the versatility of this comparator.

A unique output stage provides active drive in both direc-

tions for maximum speed into TTL/CMOS logic or passive

loads, yet does not exhibit the large current spikes found

in conventional output stages. This allows the LT1016 to

remain stable with the outputs in the active region which,

greatly reduces the problem of output “glitching” when the

input signal is slow moving or is low level.

The LT1016 has a LATCH pin which will retain input data

at the outputs, when held high. Quiescent negative power

supply current is only 3mA. This allows the negative

supply pin to be driven from virtually any supply voltage

with a simple resistive divider. Device performance is not

affected by variations in negative supply voltage.

Linear Technology offers a wide range of comparators in

addition to the LT1016 that address different applications.

See the Related Parts section on the back page of the data

sheet.

■

High Speed A/D Converters

■

High Speed Sampling Circuits

■

Line Receivers

■

Extended Range V-to-F Converters

■

Fast Pulse Height/Width Discriminators

■

Zero-Crossing Detectors

■

Current Sense for Switching Regulators

■

High Speed Triggers

■

Crystal Oscillators

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

UltraFast

(10ns typ)

■

Operates Off Single 5V Supply or ±5V

■

Complementary Output to TTL

■

Low Offset Voltage

■

No Minimum Input Slew Rate Requirement

■

No Power Supply Current Spiking

■

Output Latch Capability

UltraFast Precision

10ns Comparator

–

LT1016

10MHz TO 25MHz

(AT CUT)

22Ω

820pF

200pF

–

LATCH

GND

OUTPUT

1016 TA1a

TIME (ns)

1016 TA2b

20 020

THRESHOLD

100mV STEP

5mV OVERDRIVE

OUT

1V/DIV

Response Time

10MHz to 25MHz Crystal Oscillator

UltraFast is a trademark of Linear Technology Corporation.

LT1016

Positive Supply Voltage (Note 5) ............................... 7V

Negative Supply Voltage ............................................ 7V

Differential Input Voltage (Note 7) ........................... ±5V

+IN, –IN and LATCH ENABLE Current (Note 7) .. ±10mA

Output Current (Continuous) (Note 7) ................ ±20mA

ORDER PART

NUMBER

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UUW

(Note 1)

Operating Temperature Range

LT1016I ...............................................–40∞C to 85∞C

LT1016C .................................................. 0∞C to 70∞C

Storage Temperature Range ................. –65∞C to 150∞C

Lead Temperature (Soldering, 10 sec).................. 300∞C

JMAX

= 100∞C, q

= 130∞C/W (N8)

Consult LTC marketing for parts specified with wider operating temperature ranges.

ORDER PART

NUMBER

S8 PART

MARKING

1016

1016I

LT1016CS8

LT1016IS8

JMAX

= 110∞C, q

= 120∞C/W

TOP VIEW

+IN

–IN

–

Q OUT

GND

LATCH

ENABLE

N8 PACKAGE

8-LEAD PDIP

–

TOP VIEW

Q OUT

GND

LATCH

ENABLE

V+

+IN

–IN

V–

S8 PACKAGE

8-LEAD PLASTIC SO

–

LT1016CN8

LT1016IN8

LT1016

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Input offset voltage is defined as the average of the two voltages

measured by forcing first one output, then the other to 1.4V. Input offset

current is defined in the same way.

Note 3: Input bias current (I

) is defined as the average of the two input

currents.

Note 4: t

and Dt

cannot be measured in automatic handling

equipment with low values of overdrive. The LT1016 is sample tested with

a 1V step and 500mV overdrive. Correlation tests have shown that t

and

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25∞C. V+ = 5V, V– = 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.

LT1016C/I

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Offset Voltage R

£ 100W (Note 2) 1.0 ±3mV

●3.5 mV

Input Offset Voltage Drift ●4mV/∞C

Input Offset Current (Note 2) 0.3 1.0 mA

●0.3 1.3 mA

Input Bias Current (Note 3) 5 10 mA

●13 mA

Input Voltage Range (Note 6) ●–3.75 3.5 V

Single 5V Supply ●1.25 3.5 V

CMRR Common Mode Rejection –3.75V £ V

£ 3.5V ●80 96 dB

PSRR Supply Voltage Rejection Positive Supply 4.6V £ V

£ 5.4V ●60 75 dB

LT1016C

Positive Supply 4.6V £ V

£ 5.4V ●54 75 dB

LT1016I

Negative Supply 2V £ V

–

£ 7V ●80 100 dB

Small-Signal Voltage Gain 1V £ V

OUT

£ 2V 1400 3000 V/V

Output High Voltage V

≥ 4.6V I

OUT

=1mA ●2.7 3.4 V

OUT

= 10mA ●2.4 3.0 V

Output Low Voltage I

SINK

= 4mA ●0.3 0.5 V

SINK

= 10mA 0.4 V

Positive Supply Current ●25 35 mA

–

Negative Supply Current ●35 mA

LATCH Pin Hi Input Voltage ●2.0 V

LATCH Pin Lo Input Voltage ●0.8 V

LATCH Pin Current V

LATCH

= 0V ●500 mA

Propagation Delay (Note 4) DV

= 100mV, OD = 5mV 10 14 ns

●16 ns

= 100mV, OD = 20mV 9 12 ns

●15 ns

Differential Propagation (Note 4) DV

= 100mV, 3 ns

Delay OD = 5mV

Latch Setup Time 2ns

limits shown can be guaranteed with this test if additional DC tests

are performed to guarantee that all internal bias conditions are correct. For

low overdrive conditions V

is added to overdrive. Differential

propogation delay is defined as: Dt

= t

PDLH

– t

PDHL

Note 5: Electrical specifications apply only up to 5.4V.

Note 6: Input voltage range is guaranteed in part by CMRR testing and in

part by design and characterization. See text for discussion of input

voltage range for supplies other than ±5V or 5V.

Note 7: This parameter is guaranteed to meet specified performance

through design and characterization. It has not been tested.

LT1016

TYPICAL PERFOR A CE CHARACTERISTICS

Gain Characteristics

Propagation Delay vs Input

Overdrive

Propagation Delay vs Load

Capacitance

Propagation Delay vs Source

Resistance

Propagation Delay vs Supply

Voltage

Propagation Delay vs

Temperature

Latch Set-Up Time vs

Temperature

Output Low Voltage (VOL) vs

Output Sink Current

Output High Voltage (VOH) vs

Output Source Current

OVERDRIVE (mV)

TIME (ns)

040

1016 G02

10 20 30 50

= ±5V

= 25°C

STEP

= 100mV

LOAD

= 10pF

OUTPUT LOAD CAPACITANCE (pF)

TIME (ns)

040

1016 G03

10 20 30 50

= ±5V

= 25°C

OUT

= 0

STEP

= 100mV

OVERDRIVE = 5mV

PDHL

PDLH

POSITIVE SUPPLY VOLTAGE (V)

4.4

TIME (ns)

4.6 4.8 5.0 5.2

1016 G05

5.4 5.6

FALLING EDGE t

PDHL

RISING EDGE t

PDLH

–

= –5V

= 25°C

STEP

= 100mV

OVERDRIVE = 5mV

LOAD

= 10pF

JUNCTION TEMPERATURE (°C)

–50

TIME (ns)

025 75

1016 G06

–25 0 50 100 125

FALLING OUTPUT tPDHL

RISING OUTPUT tPDLH

VS = ±5V

OVERDRIVE = 5mV

STEP SIZE = 100mV

CLOAD = 10pF

JUNCTION TEMPERATURE (°C)

–50

TIME (ns)

–2

–4

–6 25 75

1016 G07

–25 0 50 100 125

VS = ±5V

IOUT = 0V

OUTPUT SINK CURRENT (mA)

OUTPUT VOLTAGE (V)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

016

1016 G08

4261014 18

812 20

= 125°C

= –55°C

= 25°C

= ±5V

= 30mV

OUTPUT SOURCE CURRENT (mA)

OUTPUT VOLTAGE (V)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0 16

1016 G09

4261014 18

812 20

= 125°C

= –55°C

= 25°C

= ±5V

= –30mV

DIFFERENTIAL INPUT VOLTAGE (mV)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

OUTPUT VOLTAGE (V)

1016 G01

–2.5 –1.5 –0.5 0.5 1.5 2.5

= 125°C

= –55°C

= 25°C

= ±5V

OUT

= 0

SOURCE RESISTANCE (Ω)

0 500

TIME (ns)

1k 2k1.5k 2.5k 3k

1016 G04

STEP SIZE = 800mV

400mV

200mV

100mV

VS = ±5V

TJ = 25°C

OVERDRIVE = 20mV

EQUIVALENT INPUT

CAPACITANCE IS ≈ 3.5pF

CLOAD = 10pF

LT1016

TYPICAL PERFOR A CE CHARACTERISTICS

Negative Supply Current vs

Temperature

Positive Supply Current vs

Switching Frequency

Positive Supply Current vs

Positive Supply Voltage

Common Mode Rejection vs

Frequency

Positive Common Mode Limit vs

Temperature

Negative Common Mode Limit vs

Temperature

LATCH Pin Threshold vs

Temperature

LATCH Pin Current* vs

Temperature

JUNCTION TEMPERATURE (°C)

–50

CURRENT (mA)

025 75

1016 G10

–25 0 50 100 125

VS = ±5V

IOUT = 0

SUPPLY VOLTAGE (V)

CURRENT (mA)

245

1016 G11

13 678

TJ = 125°C

TJ = –55°C

–

= 0V

VIN = 60mV

IOUT = 0

TJ = 25°C

SWITCHING FREQUENCY (MHz)

CURRENT (mA)

010 100

1016 G12



TJ = –55°C

TJ = 25°C

TJ = 125°C

VS = ±5V

VIN = ±50mV

IOUT = 0

FREQUENCY (Hz)

10k

REJECTION RATIO (dB)

120

110

100

40 100k 1M 10M

1016 G13

= ±5V

= 2V

P-P

= 25°C

JUNCTION TEMPERATURE (°C)

–50

INPUT VOLTAGE (V)

025 75

1016 G14

–25 0 50 100 125

= ±5V*

*SEE APPLICATION INFORMATION

FOR COMMON MODE LIMIT WITH

VARYING SUPPLY VOLTAGE.

JUNCTION TEMPERATURE (°C)

–50

INPUT VOLTAGE (V)

–1

–2

–3

–4 25 75

1016 G15

–25 0 50 100 125

= ±5V*

= SINGLE 5V SUPPLY

*SEE APPLICATION INFORMATION

FOR COMMON MODE LIMIT WITH

VARYING SUPPLY VOLTAGE.

JUNCTION TEMPERATURE (°C)

–50

VOLTAGE (V)

2.6

2.2

1.8

1.4

1.0

0.6

0.2 25 75

1016 G16

–25 0 50 100 125

OUTPUT UNAFFECTED

OUTPUT LATCHED

= ±5V

JUNCTION TEMPERATURE (°C)

–50

CURRENT (µA)

300

250

200

150

100

025 75

1016 G17

–25 0 50 100 125

= ±5V

LATCH

= 0V

*CURRENT COMES OUT OF

LATCH PIN BELOW THRESHOLD

LT1016

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Common Mode Considerations

The LT1016 is specified for a common mode range of

–3.75V to 3.5V with supply voltages of ±5V. A more

general consideration is that the common mode range is

1.25V above the negative supply and 1.5V below the

positive supply, independent of the actual supply voltage.

The criteria for common mode limit is that the output still

responds correctly to a small differential input signal.

Either input may be outside the common mode limit (up to

the supply voltage) as long as the remaining input is within

the specified limit, and the output will still respond cor-

rectly. There is one consideration, however, for inputs that

exceed the positive common mode limit. Propagation

delay will be increased by up to 10ns if the signal input is

more positive than the upper common mode limit and then

switches back to within the common mode range. This

effect is not seen for signals more negative than the lower

common mode limit.

Input Impedance and Bias Current

Input bias current is measured with the output held at

1.4V. As with any simple NPN differential input stage, the

LT1016 bias current will go to zero on an input that is low

and double on an input that is high. If both inputs are less

than 0.8V above V

–

, both input bias currents will go to

zero. If either input exceeds the positive common mode

limit, input bias current will increase rapidly, approaching

several milliamperes at V

= V

Differential input resistance at zero differential input

voltage is about 10kW, rapidly increasing as larger DC

differential input signals are applied. Common mode input

resistance is about 4MW with zero differential input

voltage. With large differential input signals, the high input

will have an input resistance of about 2MW and the low

input greater than 20MW.

Input capacitance is typically 3.5pF. This is measured by

inserting a 1k resistor in series with the input and measur-

ing the resultant change in propagation delay.

LATCH Pin Dynamics

The LATCH pin is intended to retain input data (output

latched) when the LATCH pin goes high. This pin will float

to a high state when disconnected, so a flowthrough

condition requires that the LATCH pin be grounded. To

guarantee data retention, the input signal must be valid at

least 5ns before the latch goes high (setup time) and must

remain valid at least 3ns after the latch goes high (hold

time). When the latch goes low, new data will appear at the

output in approximately 8ns to 10ns. The LATCH pin is

designed to be driven with TTL or CMOS gates. It has no

built-in hysteresis.

Measuring Response Time

The LT1016 is able to respond quickly to fast low level

signals because it has a very high gain-bandwidth product

(ª50GHz), even at very high frequencies. To properly

measure the response of the LT1016 requires an input

signal source with very fast rise times and exceptionally

clean settling characteristics. This last requirement comes

about because the standard comparator test calls for an

input step size that is large compared to the overdrive

amplitude. Typical test conditions are 100mV step size

with only 5mV overdrive. This requires an input signal that

settles to within 1% (1mV) of final value in only a few

nanoseconds with no ringing or “long tailing.” Ordinary

high speed pulse generators are not capable of generating

such a signal, and in any case, no ordinary oscilloscope is

capable of displaying the waveform to check its fidelity.

Some means must be used to inherently generate a fast,

clean edge with known final value.

LT1016

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The circuit shown in Figure 1 is the best

electronic

means

of generating a known fast, clean step to test comparators.

It uses a very fast transistor in a common base configura-

tion. The transistor is switched “off” with a fast edge from

the generator and the collector voltage settles to exactly

0V in just a few nanoseconds. The most important feature

of this circuit is the lack of feedthrough from the generator

to the comparator input. This prevents overshoot on the

comparator input that would give a false fast reading on

comparator response time.

To adjust this circuit for exactly 5mV overdrive, V1 is

adjusted so that the LT1016 output under test settles to

1.4V (in the linear region). Then V1 is

changed

–5V to set

overdrive at 5mV.

The test circuit shown measures low to high transition on

the “+” input. For opposite polarity transitions on the

output, simply reverse the inputs of the LT1016.

High Speed Design Techniques

A substantial amount of design effort has made the LT1016

relatively easy to use. It is much less prone to oscillation

and other vagaries than some slower comparators, even

with slow input signals. In particular, the LT1016 is stable

in its linear region, a feature no other high speed compara-

tor has. Additionally, output stage switching does not

appreciably change power supply current, further enhanc-

ing stability. These features make the application of the

50GHz gain-bandwidth LT1016 considerably easier than

other fast comparators. Unfortunately, laws of physics

dictate that the circuit

environment

the LT1016 works in

must be properly prepared. The performance limits of high

speed circuitry are often determined by parasitics such as

stray capacitance, ground impedance and layout. Some of

these considerations are present in digital systems where

designers are comfortable describing bit patterns and

memory access times in terms of nanoseconds. The

LT1016 can be used in such fast digital systems and

Figure 2 shows just how fast the device is. The simple test

circuit allows us to see that the LT1016’s (Trace B)

response to the pulse generator (Trace A) is as fast as a

TTL inverter (Trace C) even when the LT1016 has only

millivolts of input signal! Linear circuits operating with

this kind of speed make many engineers justifiably wary.

Nanosecond domain linear circuits are widely associated

with oscillations, mysterious shifts in circuit characteris-

tics, unintended modes of operation and outright failure to

function.

–

PULSE

–100mV

–3V

–5V

0.1µF

50Ω

25Ω

10Ω

400Ω

130Ω

750Ω

10k

2N3866

V1†

0.01µF

0.01µF**

LT1016

Q10 SCOPE PROBE

(CIN ≈ 10pF)

10 SCOPE PROBE

(CIN ≈ 10pF)

* SEE TEXT FOR CIRCUIT EXPLANATION

** TOTAL LEAD LENGTH INCLUDING DEVICE PIN.

SOCKET AND CAPACITOR LEADS SHOULD BE

LESS THAN 0.5 IN. USE GROUND PLANE

†(VOS + OVERDRIVE) • 1000

1016 F01

Figure 1. Response Time Test Circuit

LT1016

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Other common problems include different measurement

results using various pieces of test equipment, inability to

make measurement connections to the circuit without

inducing spurious responses and dissimilar operation

between two “identical” circuits. If the components used

in the circuit are good and the design is sound, all of the

above problems can usually be traced to failure to provide

a proper circuit “environment.” To learn how to do this

requires studying the causes of the aforementioned

difficulties.

By far the most common error involves power supply

bypassing. Bypassing is necessary to maintain low supply

impedance. DC resistance and inductance in supply wires

and PC traces can quickly build up to unacceptable levels.

This allows the supply line to move as internal current

levels of the devices connected to it change. This will

almost always cause unruly operation. In addition, several

devices connected to an unbypassed supply can “commu-

nicate” through the finite supply impedances, causing

erratic modes. Bypass capacitors furnish a simple way to

eliminate this problem by providing a local reservoir of

energy at the device. The bypass capacitor acts like an

electrical flywheel to keep supply impedance low at high

frequencies. The choice of what type of capacitors to use

for bypassing is a critical issue and should be approached

carefully. An unbypassed LT1016 is shown responding to

a pulse input in Figure 3. The power supply the LT1016

sees at its terminals has high impedance at high fre-

quency. This impedance forms a voltage divider with the

LT1016, allowing the supply to move as internal condi-

tions in the comparator change. This causes local feed-

back and oscillation occurs. Although the LT1016

responds to the input pulse, its output is a blur of 100MHz

oscillation.

Always use bypass capacitors.

Figure 2. LT1016 vs a TTL Gate

Figure 3. Unbypassed LT1016 Response

TRACE A

5V/DIV

TRACE B

5V/DIV

TRACE C

5V/DIV

10ns/DIV

–

OUTPUTS

PULSE

GENERATOR

10Ω

REF

1016 F02

LT1016

TEST CIRCUIT

7404

2V/DIV

100ns/DIV

1016 F03

LT1016

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In Figure 4 the LT1016’s supplies are bypassed, but it still

oscillates. In this case, the bypass units are either too far

from the device or are lossy capacitors.

Use capacitors

with good high frequency characteristics and mount them

as close as possible to the LT1016. An inch of wire

between the capacitor and the LT1016 can cause prob-

lems. If operation in the linear region is desired, the

LT1016 must be over a ground plate with good RF bypass

capacitors (

≥

0.01

F) having lead lengths less than 0.2

inches. Do not use sockets.

In Figure 5 the device is properly bypassed but a new

problem pops up. This photo shows both outputs of the

comparator. Trace A appears normal, but Trace B shows

an excursion of almost 8V—quite a trick for a device

running from a 5V supply. This is a commonly reported

Figure 4. LT1016 Response with Poor Bypassing

Figure 5. Improper Probe Compensation Causes

Seemingly Unexplainable Amplitude Error

Figure 6. Overcompensated or Slow Probes

Make Edges Look Too Slow

2V/DIV

100ns/DIV 1016 F04

TRACE A

2V/DIV

TRACE B

2V/DIV

10ns/DIV

1016 F05

1V/DIV

50ns/DIV 1016 F06

problem in high speed circuits and can be quite confusing.

It is not due to suspension of natural law, but is traceable

to a grossly miscompensated or improperly selected

oscilloscope probe.

Use probes that match your

oscilloscope’s input characteristics and compensate them

properly.

Figure 6 shows another probe-induced problem.

Here, the amplitude seems correct but the 10ns response

time LT1016 appears to have 50ns edges! In this case, the

probe used is too heavily compensated or slow for the

oscilloscope. Never use 1¥ or “straight” probes. Their

bandwidth is 20MHz or less and capacitive loading is high.

Check probe bandwidth to ensure it is adequate for

the measurement. Similarly, use an oscilloscope with

adequate bandwidth.

LT1016

2V/DIV

100ns/DIV

1016 F09

Figure 9. Transition Instabilities Due to No Ground Plane

In Figure 7 the probes are properly selected and applied

but the LT1016’s output rings and distorts badly. In this

case, the probe ground lead is too long. For general

purpose work most probes come with ground leads about

six inches long. At low frequencies this is fine. At high

speed, the long ground lead looks inductive, causing the

ringing shown. High quality probes are always supplied

with some short ground straps to deal with this problem.

Some come with very short spring clips which fix directly

to the probe tip to facilitate a low impedance ground

connection. For fast work, the ground connection to the

probe should not exceed one inch in length.

Keep the

probe ground connection as short as possible.

Figure 8 shows the LT1016’s output (Trace B) oscillating

near 40MHz as it responds to an input (Trace A). Note that

the input signal shows artifacts of the oscillation. This

example is caused by improper grounding of the compara-

tor. In this case, the LT1016’s GND pin connection is

one inch long. The ground lead of the LT1016 must be as

short as possible and connected directly to a low imped-

ance ground point. Any substantial impedance in the

LT1016’s ground path will generate effects like this. The

reason for this is related to the necessity of bypassing the

Figure 7. Typical Results Due to Poor Probe Grounding

Figure 8. Excessive LT1016 Ground Path

Resistance Causes Oscillation

TRACE A

1V/DIV

TRACE B

2V/DIV

100ns/DIV

1016 F08

1V/DIV

20ns/DIV 1016 F07

power supplies. The inductance created by a long device

ground lead permits mixing of ground currents, causing

undesired effects in the device. The solution here is

simple.

Keep the LT1016’s ground pin connection as short

(typically 1/4 inch) as possible and run it directly to a low

impedance ground. Do not use sockets.

Figure 9 addresses the issue of the “low impedance

ground,” referred to previously. In this example, the

output is clean except for chattering around the edges.

This photograph was generated by running the LT1016

without a “ground plane.” A ground plane is formed by

using a continuous conductive plane over the surface of

the circuit board. The only breaks in this plane are for the

circuit’s necessary current paths. The ground plane serves

two functions. Because it is flat (AC currents travel along

the surface of a conductor) and covers the entire area of

the board, it provides a way to access a low inductance

ground from anywhere on the board. Also, it minimizes the

effects of stray capacitance in the circuit by referring them

to ground. This breaks up potential unintended and harm-

ful feedback paths.

Always use a ground plane with the

LT1016 when input signal levels are low or slow moving.

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LT1016

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“Fuzz” on the edges is the difficulty in Figure 10. This

condition appears similar to Figure 10, but the oscillation

is more stubborn and persists well after the output has

gone low. This condition is due to stray capacitive feed-

back from the outputs to the inputs. A 3kW input source

impedance and 3pF of stray feedback allowed this oscilla-

tion. The solution for this condition is not too difficult.

Keep source impedances as low as possible, preferably 1k

or less. Route output and input pins and components away

from each other.

The opposite of stray-caused oscillations appears in

Figure 11. Here, the output response (Trace B) badly lags

the input (Trace A). This is due to some combination of

high source impedance and stray capacitance to ground at

the input. The resulting RC forces a lagged response at the

input and output delay occurs. An RC combination of 2k

source resistance and 10pF to ground gives a 20ns time

constant—significantly longer than the LT1016’s

response time.

Keep source impedances low and mini-

mize stray input capacitance to ground.

Figure 12 shows another capacitance related problem.

Here the output does not oscillate, but the transitions are

discontinuous and relatively slow. The villain of this

situation is a large output load capacitance. This could be

caused by cable driving, excessive output lead length or

the input characteristics of the circuit being driven. In

most situations this is undesirable and may be eliminated

by buffering heavy capacitive loads. In a few circum-

stances it may not affect overall circuit operation and is

tolerable.

Consider the comparator’s output load

characteristics and their potential effect on the circuit. If

necessary, buffer the load.

2V/DIV

50ns/DIV 1016 F10

TRACE A

2V/DIV

TRACE B

2V/DIV

10ns/DIV

1016 F11

Figure 11. Stray 5pF Capacitance from

Input to Ground Causes Delay Figure 12. Excessive Load Capacitance Forces Edge Distortion

Figure 10. 3pF Stray Capacitive Feedback

with 3kW Source Can Cause Oscillation

2V/DIV

100ns/DIV 1016 F12

LT1016

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Another output-caused fault is shown in Figure 13. The

output transitions are initially correct but end in a ringing

condition. The key to the solution here is the ringing. What

is happening is caused by an output lead that is too long.

The output lead looks like an unterminated transmission

line at high frequencies and reflections occur. This ac-

counts for the abrupt reversal of direction on the leading

edge and the ringing. If the comparator is driving TTL this

may be acceptable, but other loads may not tolerate it. In

this instance, the direction reversal on the leading edge

might cause trouble in a fast TTL load.

Keep output lead

lengths short. If they get much longer than a few inches,

terminate with a resistor (typically 250

to 400

200ns-0.01% Sample-and-Hold Circuit

Figure 14’s circuit uses the LT1016’s high speed to

improve upon a standard circuit function. The 200ns

acquisition time is well beyond monolithic sample-and-

hold capabilities. Other specifications exceed the best

commercial unit’s performance. This circuit also gets

around many of the problems associated with standard

sample-and-hold approaches, including FET switch errors

and amplifier settling time. To achieve this, the LT1016’s

high speed is used in a circuit which completely abandons

traditional sample-and-hold methods.

Important specifications for this circuit include:

Acquisition Time <200ns

Common Mode Input Range ±3V

Droop 1mV/ms

Hold Step 2mV

Hold Settling Time 15ns

Feedthrough Rejection >>100dB

When the sample-and-hold line goes low, a linear ramp

starts just below the input level and ramps upward. When

the ramp voltage reaches the input voltage, A1 shuts off

the ramp, latches itself off and sends out a signal indicat-

ing sampling is complete.

–

DELAY

COMP

1N4148

8pF

100Ω

390Ω470Ω100Ω

100Ω300Ω

2N5160

2N2369 Q6

2N2222

2N2907A

5.1k

5.1k 1.5k

0.1µF

1000pF

(POLYSTYRENE)

390Ω

SN7402 SN7402

SN7402

NOW

LT1016

SAMPLE-HOLD

COMMAND (TTL)

OUTPUT

–5V

–15V

INPUT

±3V

220Ω

1.5k

2N2222

LT1009

2.5V

820Ω

1016 F14

2N5486

LATCH

2N2907A

Figure 14. 200ns Sample-and-Hold

Figure 13. Lengthy, Unterminated Output Lines

Ring from Reflections

1V/DIV

50ns/DIV

1016 F13

LT1016

APPLICATIO S I FOR ATIO

WUUU

1.8ms, 12-Bit A/D Converter

The LT1016’s high speed is used to implement a very fast

12-bit A/D converter in Figure 15. The circuit is a modified

form of the standard successive approximation approach

and is faster than most commercial SAR 12-bit units. In

this arrangement the 2504 successive approximation reg-

ister (SAR), A1 and C1 test each bit, beginning with the

MSB, and produce a digital word representing V

’s value.

To get faster conversion time, the clock is controlled by the

window comparator monitoring the DAC input summing

junction. Additionally, the DMOS FET clamps the DAC

output to ground at the beginning of each clock cycle,

shortening DAC settling time. After the fifth bit is con-

verted, the clock runs at maximum speed.

Figure 15. 12-Bit 1.8ms SAR A-to-D

–

LT1021

10V

MSB LSB

PARALLEL

DIGITAL

DATA

OUTPUT

15V

–5V

–15V

R+

R–

GND I

–

COMP AM6012

AM2504

150k

15k

–5V

–15V

2.5k

620Ω*

620Ω*150Ω

0.01µF

Q1 Q2

0V TO 10V

27k

STATUS

1000pF

0.01µF

SD210

CLK GND E S CC

1314 15

19 20

10k** 10k

2.5k**

–

0.1µF10Ω

–5V

0.1µF10Ω

1/2 74S74

1/6 74S04

1/4 74S00

1/4 74S08 1/4 74S08

1/6 74S04

PRS

RST

CLK

CLOCK CONVERT

COMMAND

7.4MHz

IN B

Q74121

1016 F15

Q1 TO Q5 RCA CA3127 ARRAY

1N4148

HP5082-2810

*1% FILM RESISTOR

**PRECISION 0.01%; VISHAY S-102

–

LT1016

10V

LT1016

–

GND

LATCH

V–

5pF

100pF

LT1016

OUTPUTS

10k

74HC04

≈6.2k*

1016 AI02

* SELECT OR TRIM FOR f = 1.00MHz

–

1000pF

2N3906

FULL-SCALE

CALIBRATION

500Ω

LM385

1.23V

–5V

25Ω

2.7k

LT1016

100pF

1N914

470pF

8.2k

START

0µs TO 2.5µs

(MINIMUM

WIDTH ≈ 0.05µs

)

EXT

QA1Q

74121

1016 AI01

= 0V TO 2.5V

Voltage Controlled Pulse Width Generator Single Supply Precision RC 1MHz Oscillator

50MHz Fiber Optic Receiver with Adaptive Trigger

–

LT1220

LT1223

LT1097

LT1016

10k

50Ω

–5V

0.005µF

500pF

22M

22M 0.1µF

330Ω

OUTPUT

1016 AI03

= HP 5082-4204

NPN = 2N3904

PNP = 2N3906

TYPICAL APPLICATIO S

LT1016

APPE DIX A

About Level Shifts

The TTL output of the LT1016 will interface with many

circuits directly. Many applications, however, require some

form of level shifting of the output swing. With LT1016

based circuits this is not trivial because it is desirable to

maintain very low delay in the level shifting stage. When

designing level shifters, keep in mind that the TTL output

of the LT1016 is a sink-source pair (Figure A1) with good

ability to drive capacitance (such as feedforward capaci-

tors).

Figure A2 shows a noninverting voltage gain stage with a

15V output. When the LT1016 switches, the base-emitter

voltages at the 2N2369 reverse, causing it to switch very

quickly. The 2N3866 emitter-follower gives a low imped-

ance output and the Schottky diode aids current sink

capability.

Figure A3 is a very versatile stage. It features a bipolar

swing that may be programmed by varying the output

transistor’s supplies. This 3ns delay stage is ideal for

driving FET switch gates. Q1, a gated current source,

switches the Baker-clamped output transistor, Q2. The

heavy feedforward capacitor from the LT1016 is the key to

low delay, providing Q2’s base with nearly ideal drive. This

capacitor loads the LT1016’s output transition (Trace A,

Figure A4), but Q2’s switching is clean (Trace B, Figure A4)

with 3ns delay on the rise and fall of the pulse.

Figure A5 is similar to Figure A2 except that a sink

transistor has replaced the Schottky diode. The two emit-

ter-followers drive a power MOSFET which switches 1A at

15V. Most of the 7ns to 9ns delay in this stage occurs in

the MOSFET and the 2N2369.

When designing level shifters, remember to use transis-

tors with fast switching times and high f

s. To get the kind

of results shown, switching times in the ns range and f

approaching 1GHz are required.

–

LT1016

0.068µF

GND

LATCH

V–

1MHz TO 10MHz

CRYSTAL

V+

1016 AI04

OUTPUT

–

LT1016

–

LT1193

RESET (NORMALLY OPEN)

900Ω

200Ω

CALIBRATE

1k*

9k*

LOAD

10Ω

CARBON

TRIP SET

0mA TO 250mA = 0V TO 2.5V

28V

2N3866

2N2369

330Ω

2.4k

–5V

33pF 300Ω

* = 1% FILM RESISTOR

A1 AND A2 USE ±5V SUPPLIES

1016 AI05

1MHz to 10MHz Crystal

Oscillator

18ns Fuse with Voltage Programmable Trip Point

TYPICAL APPLICATIO S

LT1016

APPE DIX A

LT1016 OUTPUT

OUTPUT = 0V TO

TYPICALLY 3V TO 4V

1016 FA01

–

LT1016

2N2369 2N3866

1016 fFA02

12pF

HP5082-2810

OUTPUT

NONINVERTING

VOLTAGE GAIN

RISE

= 4ns

FALL

= 5ns

15V

TRACE A

2V/DIV

TRACE B

10V/DIV

(INVERTED)

5ns/DIV

1016 FA04

–

LT1016

2N2369 2N3866

1016 FA05

1k 12pF

NONINVERTING

VOLTAGE GAIN

tRISE = 7ns

tFALL = 9ns

2N5160

POWER FET

15V

Figure A1 Figure A2

Figure A3

Figure A4. Figure A3’s Waveforms Figure A5

–

LT1016

2N2907

2N2369

4.7k 430Ω

1000pF

0.1µF 820Ω

820Ω

OUTPUT

–10V

330Ω

(TYP)

–10V

(TYP)

INPUT

1N4148

1016 FA03

OUTPUT TRANSISTOR SUPPLIES

(SHOWN IN HEAVY LINES)

CAN BE REFERENCED ANYWHERE

BETWEEN 15V AND –15V

INVERTING VOLTAGE GAIN—BIPOLAR SWING

RISE

= 3ns

FALL

= 3ns

HP5082-2810

LT1016

SI PLIFIED SCHE ATIC

800Ω

75Ω

800Ω

75Ω

15pF

15pF 15pF

100pF

50Ω50Ω

Q5 Q6

Q7 Q8

Q9 Q10

Q11

Q12

Q13

Q14

375Ω

350Ω

955Ω

Q15

150Ω150Ω

65Ω1.1k

830Ω

3.5k

1.5k

1.5k 1.5k

210Ω210Ω

3.5k

165Ω165Ω

1.3k 1.8k 1.8k

1.2k

90Ω

670Ω

170Ω

700Ω

170Ω

700Ω

670Ω

90Ω

1.2k 480Ω

490Ω

1.3k

1.3k1.3k

+ INPUT

– INPUT

Q22

Q28

Q32

Q31

Q33

Q35 Q34

Q51

565Ω

Q21

Q23 Q24

Q26

Q27

Q25

Q20

Q19

Q18

Q17

Q16

Q50

Q49

300Ω300Ω

100Ω100Ω

LATCH

–

Q30

Q29

Q40

Q41

Q42

Q44

Q47

Q46

Q45

Q43

Q36

GND

D10

LT1016

PACKAGE DESCRIPTIO

N8 Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

N8 1098

0.100

(2.54)

BSC

0.065

(1.651)

TYP

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

0.020

(0.508)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.125

(3.175)

MIN

12 34

87 65

0.255 ± 0.015*

(6.477 ± 0.381)

0.400*

(10.160)

MAX

0.009 – 0.015

(0.229 – 0.381)

0.300 – 0.325

(7.620 – 8.255)

0.325 +0.035

–0.015

+0.889

–0.381

8.255

()

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

LT1016

PACKAGE DESCRIPTIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

0.016 – 0.050

(0.406 – 1.270)

0.010 – 0.020

(0.254 – 0.508) 45°

0°– 8° TYP

0.008 – 0.010

(0.203 – 0.254)

SO8 1298

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

1234

0.150 – 0.157**

(3.810 – 3.988)

8765

0.189 – 0.197*

(4.801 – 5.004)

0.228 – 0.244

(5.791 – 6.197)

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

LT1016

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear-tech.com

„ LINEAR TECHNOLOGY CORPORATION 1991

sn1016 1016fcs LT/TP 0601 1.5K REV C • PRINTED IN USA

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of LT1016, LT1016 Pinout and Functionality

LT1394 7ns, UltraFast, Single Supply Comparator 6mA, 100MHz Data Rate, LT1016 Pinout and Functionality

LT1671 60ns, Low Power, Single Supply Comparator 450mA, Single Supply Comparator, LT1016 Pinout and Functionality

LT1711/LT1712 Single/Dual 4.5ns 3V/5V/±5V Rail-to-Rail Comparators Rail-to-Rail Inputs and Outputs

LT1713/LT1714 Single/Dual 7ns 3V/5V/±5V Rail-to-Rail Comparators 5mA per Comparator, Rail-to-Rail Inputs and Outputs

LT1715 Dual 150MHz 4ns 3V/5V Comparator 150MHz Toggle Rate, Independent Input/Output Supplies

LT1719/LT1720/LT1721 Single/Dual/Quad 4.5ns 3V/5V Comparators 4mA per Comparator, Ground-Sensing Rail-to-Rail Inputs and Outputs

APPLICATIO S I FOR ATIO

WUUU

1Hz to 10MHz V-to-F Converter

The LT1016 and the LT1122 FET input amplifier combine

to form a high speed V-to-F converter in Figure 16. A

variety of techniques is used to achieve a 1Hz to 10MHz

output. Overrange to 12MHz (V

= 12V) is provided. This

circuit’s dynamic range is 140dB, or seven decades, which

is wider than any commercially available unit. The 10MHz

full-scale frequency is 10 times faster than monolithic

V-to-F’s now available. The theory of operation is based on

the identity Q = CV.

Each time the circuit produces an output pulse, it feeds

back a fixed quantity of charge, Q, to a summing node, S.

The circuit’s input furnishes a comparison current at the

summing node. This difference current is integrated in

A1’s 68pF feedback capacitor. The amplifier controls the

circuit’s output pulse generator, closing feedback loop

around the integrating amplifier. To maintain the sum-

ming node at zero, the pulse generator runs at a frequency

that permits enough charge pumping to offset the input

signal. Thus, the output frequency is linearly related to the

input voltage.

To trim this circuit, apply 6.000V at the input and adjust the

2kW pot for 6.000MHz output. Next, excite the circuit with

a 10.000V input and trim the 20k resistor for 10.000MHz

output. Repeat these adjustments until both points are

fixed. Linearity of the circuit is 0.03%, with full-scale drift

of 50ppm/∞C. The LTC1050 chopper op amp servos the

integrator’s noninverting input and eliminates the need for

a zero trim. Residual zero point error is 0.05Hz/∞C.

Figure 16. 1Hz to 10MHz V-to-F Converter. Linearity is Better Than 0.03% with 50ppm/∞C Drift

–

100Ω

68pF 1.2k

15V

15V 15V

–5V

150pF

10µF

36k 1k

10M

LTC1050

LT1122 A2

LT1016

5pF

0.1µF

4.7µF

10MHz

TRIM

LT1010

5V REF

–

LT1006

OUTPUT

1Hz TO 10MHz

–15V

15pF

(POLYSTYRENE)

INPUT

0V TO 10V

6MHz

TRIM 10k* 100k*

100k*

10k

470Ω

6.8Ω

LT1034-1.2V

LT1034-2.5V

2.2M*

0.02µF

1016 F16

20k

LM134

* = 1% METAL FILM/10ppm/°C

BYPASS ALL ICs WITH 2.2µF ON

EACH SUPPLY DIRECTLY AT PINS



= 2N2369

= 74HC14