K9F2G08U0C-SIB0000 - SAMSUNG

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K9F2G08U0C

Rev. 0.2, May. 2010

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

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All brand names, trademarks and registered trademarks belong to their respective owners.

Advance

2Gb C-die NAND Flash

Single-Level-Cell (1bit/cell)

datasheet

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datasheet FLASH MEMORY

Rev. 0.2

K9F2G08U0C

Advance

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact

the SAMSUNG branch office near your office.

Revision No. History Draft Date Remark Editor

0.0 1. Initial issue Aug. 12, 2009 Advance -

0.1 1. DC Parameter is chagned

2. Typo is modified Dec. 09, 2009 Advance -

0.2 1. Max tR value has changed from 35us to 40us

2. Min tRC/ tWC value has changed from 30ns to 25ns

3. Chapter 2.9, 2.10 AC parameters revised

4. Chapter 2.3 ISB2 MAX value has changed from 50 to 80

5. Chapter 7.0 2plane Erase NOT supported.

6. Chapter 2.8 tDBSY value has changed.

May. 03, 2010 Advance H.K.Kim

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Table Of Contents
datasheet FLASH MEMORY
Rev. 0.2
K9F2G08U0C
0 INTRODUCTION ........................................................................................................................................................4
1 Product List..............................................................................................................................................................4
2 Features...........................................................................................................................................................4
3 General Description.................................................................................................................................................4
4 Pin Configuration (TSOP1)......................................................................................................................................5
4.1Package Dimensions .........................................................................................................................................5
5 Pin Configuration (FBGA)........................................................................................................................................6
5.1Package Dimensions .........................................................................................................................................7
6 Pin Description ........................................................................................................................................................8
0 PRODUCT INTRODUCTION......................................................................................................................................9
1 Absolute Maximum Ratings.....................................................................................................................................10
2 Recommended Operating Conditions .....................................................................................................................10
3 DC And Operating Characteristics(Recommended opera ting conditi ons otherwise noted.)...................................10
4 Valid Block...............................................................................................................................................................11
5 AC Test Condition . .. ................................................................................................................................................11
6 Capacitance(TA=25°C, VCC= 3.3V, f=1.0MHz)......................................................................................................11
7 Mode Selection........................................................................................................................................................11
8 Program / Erase Characteristics........................................................................................................................12
9 AC Timing Characteristics for Command / Address / Data Input ............................................................................12
10 AC Characteristics for Operation...........................................................................................................................13
0 NAND FLASH TECHNICAL NOTES ..........................................................................................................................14
1 Initial Invalid Block(s)...............................................................................................................................................14
2 Identifying Initial Invalid Block(s) .............................................................................................................................14
3 Error In Write Or Read Operation............................................................................................................................15
4 Addressing for Program Operation..........................................................................................................................17
0 SYSTEM INTERFACE USING CE DON’T-CARE. .....................................................................................................18
1 Command Latch Cycle ............................................................................................................................................19
2 Address Latch Cycle................................................................................................................................................19
3 Input Data Latch Cycle............. ... ................................................................... ... ......................................................20
4* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L).......................................................................................20
5  Status Read Cycle..................................................................................................................................................21
6 Read Operation.......................................................................................................................................................21
7 Read Operation(Intercepted by CE)........................................................................................................................22
8 Random Data Output In a Page  ........................ ................... .................... ... ................... ... ...... ...............................23
9 Page Program Operation.........................................................................................................................................24
10 Page Program Operation with Random Data Input.......... .....................................................................................25
11 Copy-Back Program Operation With Random Data Input ....................................................................................26
12 Two- Plane Page Program operatoin ....................................................................................................................27
13 Block Erase Operation...........................................................................................................................................28
14 Read ID Operation.................................................................................................................................................28
0 DEVICE OPERATION ................................................................................................................................................31
1 Page Read ...............................................................................................................................................................31
2 Page Program .........................................................................................................................................................33
3 Copy-back Program.................................................................................................................................................34
4 Read Status.............................................................................................................................................................35
5 Read ID ...................................................................................................................................................................36
6 Reset.......................................................................................................................................................................36
7 READY/BUSY .........................................................................................................................................................37
0  DATA PROTECTION & POWER UP SEQUENCE................................ .................... ................... ... ..........................38
0 BACKWARD COMPATIBILITY INFORMATION.........................................................................................................39

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datasheet FLASH MEMORY

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1.0 INTRODUCTION

1.1 Product List

1.2 Features

1.3 General Description

Offered in 256Mx8bit, the K9F2G08U0C is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-effective solution for

the solid state application market. A program operation can b e performed in typical 250μs on the (2K+64)Byte page and an erase operation can be per-

formed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for

address and data input/output as well as command input. The on-chip write controller automates al l program and erase functions including pulse repeti-

tion, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08U0C′s

extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08U0C is

an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

Part Number Vcc Range Organization PKG Type

K9F2G08U0C-S2.7 ~ 3.6v x8 TSOP1

K9F2G08U0C-H 2.7 ~ 3.6v x8 63 FBGA

• Voltage Supply

- 3.3V device(K9F2G08U0C): 2.70V ~ 3.60V

• Organization

- Memory Cell Array : (256M + 8M) x 8bit

- Data Register : (2K + 64) x 8bit

• Automatic Program and Erase

- Page Program : (2K + 64)Byte

- Block Erase : (128K + 4K)Byte

• Page Read Operation

- Page Size : (2K + 64)Byt e

- Random Read : 40μs(Max.)

- Serial Access : 25ns(Min.)

• Fast Write Cycle Time

- Page Program time : 250μs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

-Endurance & Data Retention : Refor to the gualification report

-ECC regnirement : 1 bit / 528bytes• Command Driven Operation

• Unique ID for Copyright Protection

• Package :

- K9F2G08U0C-SCB0/SIB0 : Pb-FREE PACKAGE

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F2G08U0C-HCB0/HIB0 : Pb-FREE PACKAGE

63 - ball FBGA (9 x 11 / 0.8 mm pitch)

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1.4 Pin Configuration (TSOP1)

K9F2G08U0C-SCB0/SIB0

48-pin TSOP1

Standard Type

12mm x 20mm

N.C

R/B

N.C

Vcc

Vss

N.C

CLE

ALE

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

1.4.1 Package Dimensions

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

Unit :mm/Inch

0.787

0.008

20.00

0.20

#24

0.20

+0.07

-0.03

0.008

+0.003

-0.001

0.50

0.0197

#48

#25

0.488

12.40MAX

12.00

0.472

0.10

0.004 MAX

0.25

0.010

()

0.039

0.002

1.00

0.05

0.002

0.05 MIN

0.047

1.20 MAX

0.45~0.75

0.018~0.030

0.724

0.004

18.40

0.10

0~8

0.010

0.25 TYP

0.125

+0.075

0.035

0.005

+0.003

-0.001

0.50

0.020

()

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1.5 Pin Configuration (FBGA)

K9F2G08U0C-HCB0/HIB0

R/B/WE/CEVssALE/WP

/RE CLE

NCNC

NC NC Vcc

NCNC I/O0

I/O1NC NC Vcc I/O5 I/O7

VssI/O6I/O4I/O3I/O2Vss

NC NC

NC NC NC

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.CN.C

N.C N.C

N.C

3456 1 2

Top View

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1.5.1 Package Dimensions

63-Ball FBGA (measured in millimeters)

9.00±0.10

#A1

Side View

Top View

1.00(Max.)

0.45±0.05

4321

Bottom View

11.00±0.10

63-∅0.45±0.05

0.80 x7= 5.60

11.00±0.10

0.80 x 5= 4.00

0.80

0.25(Min.)

0.10MAX

2.80

2.00

9.00±0.10

(Datum B)

(Datum A)

0.20 M A B

∅

0.80

0.80 x 1 1= 8 .80

0.80 x 9= 7.20

9.00±0.10

2.00

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1.6 Pin Description

NOTE :

Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

Pin Name Pin Function

I/O0 ~ I/O7DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to

high-z when the chip is deselected or when the outputs are disabled.

CLE COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high, commands are

latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising

edge of WE with ALE high.

CE CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does

not return to standby mode in program or erase op eration.

RE READ ENABLE

The RE input is the serial data-out control, and when active drives the da ta onto the I/O bus. Data is valid tREA after the fall-

ing edge of RE which also increments the internal column address counter by one.

WE WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

WP WRITE PROTECT

The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is

reset when the WP pin is active low.

R/B

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read

operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z con-

dition when the chip is deselected or when outputs are disabled.

Vcc POWER

VCC is the power supply for device.

Vss GROUND

N.C NO CONNECTION

Lead is not internally connected.

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2.0 PRODUCT INTRODUCTION

NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities

by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low.

Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address

respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, S t atus Read Command, etc. require just one cycle

bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution..

Page Read and Page Program need the same five address cycles following the r equired command input. In Block Erase operation, however, only the

three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific

commands of the K9G2G08U0C.

[Table 1] Command Sets

NOTE :

1) Random Data Input/Output can be executed in a page.

2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.

Caution :

Any undefined command inputs are prohibited except for above command set of Table 1.

Function 1st Cycle 2nd Cycle Acceptable Command during Busy

Read 00h 30h

Read for Copy Back 00h 35h

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Copy-Back Program 85h 10h

Two-Plane Page Program(2) 80h---11h 81h---10h

Block Erase 60h D0h

Random Data Input(1) 85h -

Random Data Output(1) 05h E0h

Read Status 70h - O

Read Status 2 F1h - O

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2.1 Absolute Maximum Ratings

NOTE :

1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoo t to -2.0V for periods <30ns.

Maximum DC voltage on input/out put pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the cond itions

as detailed in the operation al sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.2 Recommended Operating Conditions

(Voltage reference to GND, K9F2G08U0C-XCB0 :TA=0 to 70°C, K9F2G08U0C-XIB0:TA=-40 to 85°C)

2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.)

NOTE :

1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

2) Typical value is measured at Vcc= 3.3V, TA=25°C. Not 100% tested.

Parameter Symbol Rating Unit

Voltage on any pin relative to VSS

VCC -0.6 to +4.6

VVIN -0.6 to +4.6

VI/O -0.6 to Vcc + 0.3 (< 4.6V)

Temperature Under Bias K9F2G08U0C-XCB0 TBIAS -10 to +125 °C

K9F2G08U0C-XIB0 -40 to +125

Storage Temperature K9F2G08U0C-XCB0 TSTG -65 to +150 °C

K9F2G08U0C-XIB0

Short Circuit Current IOS 5mA

Parameter Symbol 3.3V Unit

Min Typ. Max

Supply Voltage VCC 2.7 3.3 3.6 V

Supply Voltage VSS 000V

Parameter Symbol Test Conditions 3.3V Unit

Min Typ Max

Operating

Current

Page Read with Serial

Access ICC1tRC=25ns

CE=VIL, IOUT=0mA -2035

Program ICC2-

Erase ICC3-

Stand-by Current(TTL) ISB1CE=VIH, WP=0V/VCC --1

Stand-by Current(CMOS) ISB2CE=VCC-0.2, WP=0V/VCC -1080

μA

Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10

Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10

Input High Voltage VIH(1) - 0.8xVcc - Vcc+0.3

Input Low Voltage, All inputs VIL(1) - -0.3 - 0.2xVcc

Output High Voltage Level VOH K9F2G08B0C: IOH=-100μA

K9F2G08U0C: IOH=-400μA2.4 - -

Output Low Voltage Level VOL K9F2G08B0C: IOL=100μA

K9F2G08U0C: IOL=2.1mA --0.4

Output Low Current(R/B)IOL(R/B)K9F2G08B0C: VOL=0.1V

K9F2G08U0C: VOL=0.4V 810-mA

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2.4 Valid Block

NOTE :

1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being us ed. The number of valid blocks is presented with both

cases of invalid blocks considered. Invalid blocks are defined as bl ocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the

attached technical notes for appropriate management of invalid blocks.

2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.

3) The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.

2.5 AC Test Condition

(K9F2G08U0C-XCB0 :TA=0 to 70°C, K9F2G08U0C-XIB0:TA=-40 to 85°C, K9F2G08U0C: Vcc=2.7V~3.6V unless otherwise noted)

2.6 Capacitance(TA=25°C, VCC= 3.3V, f=1.0MHz)

NOTE :

Capacita nce is periodically sampled and not 100% tested.

2.7 Mode Selection

NOTE :

1) X can be VIL or VIH.

2) WP should be biased to CMOS high or CMOS low for standby.

Parameter Symbol Min Typ. Max Unit

K9F2G08U0C NVB 2,008 - 2,048 Blocks

Parameter K9F2G08U0C

Input Pulse Levels 0V to Vcc

Input Rise and Fall Times 5ns

Input and Output Timing Levels Vcc/2

Output Load 1 TTL GATE and CL=50pF

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V - 10 pF

Input Capacitance CIN VIN=0V - 10 pF

CLE ALE CE WE RE WP Mode

HLL HX

Read Mode Command Input

L H L H X Address Input(5clock)

HLL HH

Write Mode Command Input

L H L H H Address Input(5clock)

LLL HH

Data Input

LLLH X Data Output

X X X X H X During Read(Busy)

X X X X X H During Program(Busy)

X X X X X H During Erase(Busy)

XX(1) X X X L Write Protect

XXHXX

0V/VCC(2) Stand-by

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2.8 Program / Erase Characteristics

NOTE :

1) Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.

2) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.

2.9 AC Timing Characteristics for Command / Address / Data Input

NOTE :

1) The transition of the corresponding cont rol pins must occur only once while WE is held low

2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle

Parameter Symbol Min Typ Max Unit

Program Time tPROG -250 750 μs

Dummy Busy time for Two-Plane Page Program tDBSY -2.5 3 μs

Number of Partial Program Cycles Nop - - 4 cycles

Block Erase Time tBERS -210 ms

Parameter Symbol Min Max Unit

CLE Setup Time tCLS(1) 12 -ns

CLE Hold Time tCLH 5-ns

CE Setup Time tCS(1) 20 - ns

CE Hold Time tCH 5-ns

WE Pulse Width tWP 12 -ns

ALE Setup Time tALS(1) 12 -ns

ALE Hold Time tALH 5-

Data Setup Time tDS(1) 12 -ns

Data Hold Time tDH 5-ns

Write Cycle Time tWC 25 -ns

WE High Hold Time tWH 10 - ns

Address to Data Loading Time tADL(2) 100 - ns

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2.10 AC Characteristics for Operation

NOTE :

1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5μs.

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register tR-40 μs

ALE to RE Delay tAR 10 - ns

CLE to RE Delay tCLR 10 - ns

Ready to RE Low tRR 20 - ns

RE Pulse Width tRP 12 -ns

WE High to Busy tWB -100

Read Cycle Time tRC 25 -ns

RE Access Time tREA -20ns

CE Access Time tCEA -25ns

RE High to Output Hi-Z tRHZ -100ns

CE High to Output Hi-Z tCHZ -30ns

CE High to ALE or CLE Don’t Care tCSD 10 -ns

RE High to Output Hold tRHOH 15 - ns

CE High to Output Hold tCOH 15 - ns

RE High Hold Time tREH 15 -ns

Output Hi-Z to RE Low tIR 0-ns

RE High to WE Low tRHW 100 - ns

WE High to RE Low tWHR 60 - ns

Device Resetting Time(Read/Program/Erase) tRST -5/10/500(1) μs

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3.0 NAND FLASH TECHNICAL NOTES

3.1 Initial Invalid Block(s)

[Figure 1] Flow chart to create initial invalid block table

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information

regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices

with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it

is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via

address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte

ECC.

3.2 Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s)

status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at

the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has

been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create

the initial invalid block table via the following suggested flow chart(Figure 1). Any intentional erasure of the original initial invalid block information is pro-

hibited.

*Check "FFh" at the column addres s 2048

Star t

Set Block Address = 0

Check "FFh"

Increment Block Address

Last Block ?

End

Yes

Create (or update) No

Initial

of the 1st and 2nd page in the block

Invalid Block(s) Table

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NAND Flash Technical Notes (Continued)

3.3 Error In Write Or Read Operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following pos-

sible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replace-

ment should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block

replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest

of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verifica-

tion failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those

reclaimed blocks.

ECC

: Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection

Program Flow Chart

Failure Mode Detection and Countermeasure sequence

Write Erase Failure Status Read after Erase --> Block Replacement

Program Failure Status Read after Program --> Block Replacement

Read Single Bit Failure Verify ECC -> ECC Correction

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 80h

Write Address

Write Data

Write 10h

Read Sta tu s R eg ister

Program Completed

or R/B = 1 ?

Program E rror

Yes

: If program operation results in an error, map out

the block including the page in error and copy the

targ et da ta to another bloc k.

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NAND Flash Technical Notes (Continued)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2

Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)

* Step3

Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.

* Step4

Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.

Erase Flow Chart

Star t

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 60h

Write Block Address

Write D0h

Read Status Register

or R/B = 1 ?

Erase Error

Yes

: If erase operation results in an error, map out

the failing block and replace it with another blo ck.

Erase Completed

Yes

Read Flow Chart

Start

Verify ECC

Write 00h

Write Address

Read Data

ECC Generation

Reclaim the Error

Page Read Completed

Yes

Write 30h

Block Replac e m ent

Buffer memory of the controller.

1st Block A

Block B

(n-1)th

nth

(page)

{

∼

1st

(n-1)th

nth

(page)

{

∼

an error occurs. 1

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3.4 Addressing for Program Operation

Within a block, the pages must be programmed con secutively fro m the LSB(least significant bit) page of the block to the MSB( most significant bit) pages

of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.

Therefore, LSB doesn't need to be page 0.

From the LSB page to MSB page

DATA IN: Data (1) Data (64)

(1)

(2)

(3)

(32)

(64)

Data register

Page 0

Page 1

Page 2

Page 31

Page 63

Ex.) Random page program (Prohibition)

DATA IN: Data (1) Data (64)

(2)

(32)

(3)

(1)

(64)

Data register

Page 0

Page 1

Page 2

Page 31

Page 63

[Figure 3] Read Operation with CE don’t-care.

[Figure 2] Program Operation with CE don’t-care.

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datasheet FLASH MEMORY

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4.0 SYSTEM INTERFACE USING CE DON’T-CARE.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are

utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle

time on the order of μ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.

NOTE :

Device I/O DATA ADDRESS

I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

K9F2G08U0C I/O 0 ~ I/O 7 2,112byte A0~A7 A8~A11 A12~A19 A20~A27 A28

tWP

tCH

tCS

Address(5Cycles)80h Data Input

CLE

ALE

Data Input

CE don’t-care

10h

tCEA

out

tREA

I/O

I/Ox

≈

≈≈ ≈ ≈

≈ ≈

≈

Address(5Cycle)00h

CLE

ALE

I/O

Data Output(serial access)

CE don’t-care

R/B

30h

≈ ≈ ≈≈≈≈

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4.1 Command Latch Cycle

CLE

ALE

Command

tCLS

tCS

tCLH

tCH

tWP

tALS tALH

tDS tDH

I/Ox

4.2 Address Latch Cycle

CLE

ALE

Col. Add1

tCS tWC

tWP

tALS

tDS tDH

tALH tALS

tWH

tWC

tWP

tDS tDH

tALH tALS

tWH

tWC

tWP

tDS tDH

tALH tALS

tWH

tDS tDH

tWP

I/Ox

Col. Add2 Row Add1 Row Add2

tWC

tWH

tALH tALS

tDS tDH

Row Add3

tALH

tCLS

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datasheet FLASH MEMORY

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4.3 Input Data Latch Cycle

CLE

DIN 0 DIN 1 DIN final

ALE

tALS

tCLH

tWC

tCH

tDS tDH tDS tDH tDS tDH

tWP

tWH

tWP tWP

≈

I/Ox

≈

4.4* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

R/B

Dout Dout Dout

tRC

tREA

tRR

tRHOH

tREA

tREH tREA tCOH

tRHZ

≈≈≈≈

I/Ox

tCHZ

tRHZ

NOTE :

Transition is measured at ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

tRHOH starts to be valid when fr equency is lower than 33MHz.

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datasheet FLASH MEMORY

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4.5 Status Read Cycle

CLE

Status Output

tCLR

tCLH

tWP tCH

tDS tDH tREA

tIR tRHOH

tCOH

tWHR

tCEA

tCLS

I/Ox

tCHZ

tRHZ

tCS

70h/F1h

4.6 Read Operation

CLE

R/B

ALE

Busy

00h

Col. Add1 Col. Add2 Row Add1

Dout N Dout N+1

Column Address Row Address

tWB tAR

tRtRC tRHZ

tRR

Dout M

tWC

≈≈ ≈

Row Add2

30h

tCLR

I/Ox

Row Add3

tCSD

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datasheet FLASH MEMORY

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4.7 Read Operation(Intercepted by CE)

CLE

R/B

ALE

Busy

00h

Dout N Dout N+1 Dout N+2

Row Address

Column Address

tWB tAR

tCHZ

tRR

tRC

30h

I/Ox

Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

tCOH

tCLR

tCSD

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datasheet FLASH MEMORY

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4.8 Random Data Output In a Page

CLE

R/B

ALE

Busy

00h Dout N Dout N+1

Row Address

Column Address

tWB

tAR

tRR

30h 05h

Column Address

Dout M Dout M+1

I/Ox

Col. Add1 Col. Add2 Row Add1 Row Add2 Col Add1 Col Add2

Row Add3

tCLR

E0h

tWHR

tREAtRC

tRHW

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datasheet FLASH MEMORY

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4.9 Page Program Operation

CLE

R/B

ALE

80h 70h I/O

Din

NDin 10h

SerialData

Input Command Column Address Row Address 1 up to m Byte

Serial Input Program

Command Read Status

Command

I/O

=0 Successful Program

I/O

=1 Error in Program

tPROG

tWB

tWC tWC tWC

≈

I/Ox

Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3

tAD tWHR

NOTE :

tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

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datasheet FLASH MEMORY

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4.10 Page Program Operation with Random Data Input

CLE

R/B

ALE

80h 70h I/O

Din

NDin 10h

Serial Data

Input Command Column Address Row Address Serial Input Program

Command Read Status

Command

tPROG

tWB

tWC tWC

≈≈

≈

85h

Random Data

Input Command Column Address

tWC

Din

JDin

Serial Input

≈≈

I/Ox

Col. Add1 Col. Add2 Row Add1 Row Add2 Col. Add1 Col. Add2

Row Add3

≈

NOTE :

tADL tADL tWHR

tADL is h time from the WE rising edge of final address cycle to the WE risin g edge of first data cycle.

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datasheet FLASH MEMORY

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4.11 Copy-Back Program Operation With Random Data Input

CLE

R/B

ALE

00h I/O

85h

Column Address Row Address

I/O

=0 Successful Progra m

I/O

=1 Error in Pro gram

tPROG

tWB

tWC

≈

Busy

tWB

Busy

≈

10h

Copy-Back Data

Input Command

35h

Column Address Row Address

Data 1 Data N

≈ ≈

I/Ox

Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3

Row Add3

70h

NOTE :

tADL

tWHR

Read Status Command

tADL is the time from the WE rising edge of final addr ess cycle to the WE rising edge of first data cycle.

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4.12 Two- Plane Page Program operatoin

80h

I/O0~7

R/B

11h

Ex.) Two-Plane Page Program

tDBSY

Address & Data Input 81h 10h

Address & Data Input 70h/F1h

tPROG

Col Add1,2 & Row Add 1,2,3

2112 Byte Data

CLE

R/B

ALE

80h Din

NDin 11h

Serial Data

Input Command

Column Address

Program

tDBSY

tWB

tWC

≈≈

≈

Command

(Dummy)

Din

N10h

tPROG

tWB

≈≈

≈

I/O

Program Confirm

Command

(True)

81h

70h/F1h

Page Row Address

I/Ox

≈

1 up to 2112 Byte Data

Serial Input

Din

Read Status Command

DBSY :

typ. 2.5us

max. 3us

Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3

Col Add1,2 & Row Add 1,2,3

2112 Byte Data

A0 ~ A11 : Valid

A12 ~ A17 : Fixed ’Low’

A18 : Fixed ’Low’

A19 ~ A29 : Fixed ’Low’

A0 ~ A11 : Valid

A12 ~ A17 : Valid

A18 : Fixed ’High’

A19 ~ A29 : Valid

NOTE:

Any command between 11h and 81h is prohibited except 70h and FFh.

Note

tWHR

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datasheet FLASH MEMORY

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4.13 Block Erase Operation

CLE

R/B

ALE

60h

Erase Command Read Status

Command I/O

=1 Error in Erase

D0h 70h I/O 0

Busy

tWB tBERS

I/O

=0 Successful Erase

Row Address

tWC

≈

Auto Block Erase

Setup Command

I/Ox

Row Add1 Row Add2 Row Add3

tWHR

4.14 Read ID Operation

CLE

ALE

90h

Read ID Command Maker Code Device Code

00h ECh

REA

Address 1cycle

I/Ox

Device 4th cyc.

Code 3rd cyc. 5th cyc.

Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle

K9F2G08U0C DAh 10h 15h 44h

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datasheet FLASH MEMORY

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ID Definition Table

3rd ID Data

4th ID Data

Description

1st Byte

2nd Byte

3rd Byte

4th Byte

5th Byte

Maker Code

Device Code

Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc

Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum

Plane Number, Plane Size

Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Internal Chip Number

0 0

0 1

1 0

1 1

Cell Type

2 Level Cell

4 Level Cell

8 Level Cell

16 Level Cell

0 0

0 1

1 0

1 1

Number of

Simultaneously

Programmed Pages

0 0

0 1

1 0

1 1

Interleave Program

Between multiple chips Not Support

Support 0

Cache Program Not Support

Support 0

Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Page Size

(w/o redundant area )

1KB

2KB

4KB

8KB

0 0

0 1

1 0

1 1

Block Size

(w/o redundant area )

64KB

128KB

256KB

512KB

0 0

0 1

1 0

1 1

Redundant Area Size

( byte/512byte) 8

16 0

Organization x8

x16 0

Serial Access Minimum

50ns/30ns

25ns

Reserved

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datasheet FLASH MEMORY

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5th ID Data

Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Plane Number

0 0

0 1

1 0

1 1

Plane Size

(w/o redundant Area)

64Mb

128Mb

256Mb

512Mb

1Gb

2Gb

4Gb

8Gb

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Reserved 0 0 0

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5.0 DEVICE OPERATION

[Figure 4] Read Operation

5.1 Page Read

Page read is initiated by writing 00h-30h to the command register alo ng with five address cycles. After initial power up, 00h command is latched. There-

fore only five address cycles and 30h comma nd in itiates that operatio n after initial pow er up. The 2,112 bytes of data within the selected page are trans-

ferred to the data registers in less than 40μs(tR). The system controller can detect the comp letion of this data transfer(tR) by analyzing the output of R/B

pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing RE . The repetitive high to

low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address

of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated

multiple times regardless of how many times it is done in a page.

Address(5Cycle)00h

Col. Add.1,2 & Row Add.1,2,3

Data Output(Serial Access)

Data Field Spare Field

CLE

ALE

R/B

30h

I/Ox

≈≈≈≈≈ ≈

[Figure 5] Random Data Output In a Page

- 32 -

datasheet FLASH MEMORY

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Address

00h Data Output

R/B

30h Address

05h E0h

5Cycles 2Cycles Data Output

Data Field Spare Field Data Field Spare Field

I/Ox

Col. Add.1,2 & Row Ad d. 1,2 ,3 Col. Add.1,2

[Figure 7] Random Data Input In a Page

[Figure 6] Program & Read Status Operation

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5.2 Page Program

The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a

single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation

must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data

loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded

data is programmed into the appropriate cell.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data

loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address

for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be

operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process.

Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically exe-

cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts,

the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by

monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while program-

ming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 6). The internal write verify detects only

errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read St atus command mode until another valid command

is written to the command register.

80h

R/B

Address & Data Input I/O0 Pass

Data

10h 70h

Fail

tPROG

I/Ox

Col. Add.1,2 & Row Add.1,2,3

"0"

"1"

80h

R/B

Address & Data Input I/O0 Pass

10h 70h

Fail

tPROG

85h Address & Data Input

I/Ox

Col. A dd. 1,2 & Row Add1,2,3 Col. Add.1,2

Data Data

"0"

"1"

[Figure 9] Page Copy-Back Program Operation with Random Data Input

[Figure 8] Page Copy-Back Program Operation

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5.3 Copy-back Program

Copy-Back program with Read for Copy-Back is configur ed to quickly and efficiently rewrite data stored in one page without data re-loading when the bit

error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The be nefit is especially obvi-

ous when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a

sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the

address of the source page moves the whole 2,112-byte data into the internal data buffer. A bit error is checked by sequential read ing the data output. In

the case where there is no bit error , the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-

Input command (85h) with destination page address. Actual programmin g operation begins after Program Confirm command (10h ) is issued. Once the

program process starts, the Read Status Register command (70h) may be ente red to read the status register. The system controller can detect the com-

pletion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the

Write Status Bit(I/O 0) may be checked(Figure 8 & Figure 9). The command register remains in Read Status command mode until another valid com-

mand is written to the command register.

During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 9.

NOTE :

Copy-Back Program operation is allowed only within the same memory plane.

"0"

"1"

00h

R/B

Add.(5Cycles) I/O0 Pass

85h 70h

Fail

tPROG

Add.(5Cycles)

Source Address Destination Address

35h 10h

I/Ox

Col. Add.1,2 & Row Add.1,2,3

00h

R/B

Add.(5Cycles) 85h 70h

tPROG

Add.(5Cycles)

Source Address Destination Address

Data

35h 10h

85h Data

Add.(2Cycles)

There is no limitation for the number of repetition.

I/Ox

Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2

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5.4 Read Status

The device contains a S tatus Register which may be read to find out whether program or erase operation is completed, and whether the program or erase

operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle outputs the content of the Status Register to

the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple

memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 2 for specific Sta-

tus Register definitions and Table 3 for specific F1h Status Register definitions. The command register remains in Status Read mode until further com-

mands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read

cycles.

[Table 2] Read Status Register Definition for 70h Command

NOTE :

I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

[Table 3] Read Status 2 Register Definition for F1h Command

NOTE :

I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

I/O Page Program Block Erase Read Definition

I/O 0 Pass/Fail Pass/Fail Not use Pass : "0" Fail : "1"

I/O 1 Not use Not use Not use Don’t -cared

I/O 2 Not use Not use Not use Don’t -cared

I/O 3 Not Use Not Use Not Use Don’t -cared

I/O 4 Not Use Not Use Not Use Don’t -cared

I/O 5 Not Use Not Use Not Use Don’t -cared

I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"

I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1" "1"otected

I/O No. Page Program Block Erase Read Definition

I/O 0 Chip Pass/Fail Chip Pass/Fail Not use Pass : "0" Fail : "1"

I/O 1 Plane0 Pass/Fail Plane0 Pass/Fail Not use Pass : "0" Fail : "1"

I/O 2 Plane1 Pass/Fail Plane1 Pass/Fail Not use Pass : "0" Fail : "1"

I/O 3 Not Use Not Use Not Use Don’t -cared

I/O 4 Not Use Not Use Not Use Don’t -cared

I/O 5 Not Use Not Use Not Use Don’t -cared

I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"

I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1" "1"otected

[Figure 10] Read ID Operation

[Figure 11] RESET Operation

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5.5 Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles

sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID

mode until further commands are issued to it. Figure 10 shows the operation sequence.

5.6 Reset

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or

erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially

programmed or erased. The command register is cleared to wait for the next command, and the St atus Register is cleared to value C0h when WP is high.

If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the

Reset command is written. Refer to Figure 11 below.

Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle

K9F2G08U0C DAh 10h 15h 44h

After Power-up After Reset

Operation mode Mode 00h Command is latched Waiting for next command

CLE

I/O

ALE

90h 00h

Address. 1cycle Maker code Device code

tCEA

tAR

tREA

tWHR

tCLR

Device 4th Cyc.

Code

ECh 3rd Cyc. 5th Cyc.

FFh

I/O

R/B

tRS

[Figure 12] Rp vs tr ,tf & Rp vs ibusy

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datasheet FLASH MEMORY

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5.7 READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/

B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address

loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs

to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the fol-

lowing reference chart(Figure 12). Its value can be determined by the following guidance.

VCC

R/B

open drain output

Device

GND

Rp ibusy

Busy

Ready Vcc

VOH

tf tr

VOL

3.3V device - VOL : 0.4V, VOH : 2.4V

tr,tf [s]

Ibusy [A]

Rp(ohm)

Ibusy

@ Vcc = 3.3V, Ta = 25°C , CL = 50pF

1K 2K 3K 4K

100n

200n 2m

100

150

200

3.6 3.6 3.6 3.6

2.4

1.2

0.8 0.6

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp value guidance

Rp(max) is determined by maximum permissible limit of tr

Rp(min, 3.3V part) = VCC(Max.) - VOL(Max.)

IOL + ΣIL = 3.2V

8mA + ΣIL

[Figure 13] AC Waveforms for Power Transition

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6.0 DATA PROTECTION & POWER UP SEQUENCE

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions

whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-

down. A recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in Figure 13. The two step

command sequence for program/erase provides additional software protection.

High

≈

≈≈

≈

Ready/Busy

5 ms max Operation

1ms

~ 2.3V ~ 2.3V

Invalid Don’t care

Don’t care

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7.0 BACKWARD COMPATIBILITY INFORMATION

The below table shows key parameters which a re different with previous product, so that the host could use make or modify its firmware without misun-

derstanding of compatibility. But the below table don’t have all the difference with previous product, but only key parameters’ changing which can be

defined to have an effect on developing NAND firmware or hardware.

Previous Generation Product Current Generation Device

Part ID K9F2G08U0B K9F2G08U0C

Features & Operations

1. tR: 25us / tPROG(200us typ, 700us Max)

tERS(1.5ms Typ, 10ms Max)

2. tRC/tWC: 25ns

3. 2 Plane Program: support

4. 2Plane Copy-back Program: Support

5. 2Plane Erase: Support

6. EDO: Support

1. tR: 40us / tPROG(250us typ, 750us Max)

tERS(2ms Typ, 10ms Max)

2. tRC/tWC: 25ns

3. 2 Plane Program: support

4. 2Plane Copy-back Program: N/A

5. 2Plane Erase: N/A

6. EDO: N/A

AC & DC Parameters 1. ICC1 : 15mA(typ)/ 30mA(max)

2. ICC2 : 15mA(typ)/ 30mA(max)

3. ICC3 : 15mA(typ)/ 30mA(max)

1. ICC1 : 20mA(typ)/ 35mA(max)

2. ICC2 : 20mA(typ)/ 35mA(max)

3. ICC3 : 20mA(typ)/ 35mA(max)

Technical Notes