Intel 450NX PClset 82454NX PCI Expander Bridge (PXB) 82453NX Data Path Multiplexor (MUX) 82452NX RAS/CAS Generator (RCG) 82451NX Memory & I/O Controller (MIOC) Revision 1.3 March 1999 Intel Corporation 1998, 1999Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatso- ever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringe- ment of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifica- tions and product descriptions at any time, without notice. The Intel 450NX PClIset may contain design defects or errors known as errata which may cause the prod- uct to deviate from the published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683 Copyright Intel Corporation 1998, 1999. Third-party brands and names are the property of their respective owners.CONTENTS Chapter 1 ITPOCGUCTION oo... eeeecee cece ee ee ee eee ee a eee eens eee eee ea nee eee eee eee eee enna eee eee ene eee eee ene eee 1-1 1.1 OVEIVIOW ee ceeeeeeenneeeeene ee cen ener tiene eeaae eee aa ae eee ae eee na gees eaaee ea geese caeeeeeaaeeesaeeeeeaaeeeeeaaeeeeneeeesaeeeneaaeesneeeesnieesseateeenaes 1-1 1.2 Intel 450NX PClset COMPONENTS oo... eee eeeeee cence ee eeeeeeeeaeeeeeneeeeaaeeeeeaaeeeeeaeeecaeeeeeaeeeseaaeeesneeeeesaeeeseaaeeeseeees 1-2 1.3 Intel 450NX PClset Feature SUMMA oo... eeeceeeneeeeenneeeceeee eee eeeeaaeeeseeeeeeaeeeeeaeeeeeneeeeseeeenaeeeeneeeeeneetees 1-3 1.4 Packaging & POWEM ooo... eect esse eee eee enter eeeae eee nee teeter eeaae erence ees ae eee eaaeeeeeeeenaeeeseaeeesneeeeseeesnaeeesneeeseneeeees 1-4 Chapter 2 Signal DeSCIiptioNS 20... ceee eee eeee eee eee e eee eee ee ea eee anne eens eee eee eae na eens cee ee esa gaaa eee aeee see seeeeeeeseeeeeeeenaeeeeens 2-1 2.1 CONVENTIONS ooo... ee ee eene eset ee eeneeeeeae ee eenae ee eaeeeeea nese aae esa aeeeeeaaeeeeeeaeeecaeeeeecaeeeseaaeecgeeeeeaeeeseaaeessneeeesneesseneeeenaes 2-1 2.2 SUMIM ALY oe eeeecee cence cece renee ee ee eae ee teenie eee ae erase nena gee eee eee ea geese nae ee ene ae ee eaeee eee ae ee eaaeeeeeeeeaaeeeneaaeesneeeeeneesneaeeeenaes 2-2 2.2.1 Signal Summary, By COMPONENE ooo... eee eee ee eeneeeeeee ee eee ater cess eee aeeeeeaaeesaeeeeeaeeeeeaeeesnneeeeeeeeeeea 2-2 2.2.1.1 MIOC Signal List ...... cece ceeeeee eee e eee eeeee eee eeeaeeeeeeesaeeeaaeeneeecaeeseeeeneesaeseeeeciaeseeseneeeaas 2-3 2.2.1.2 PXB Signal List oo... eee ceeeeeeeeeeeeeee cence eeeeeeeaeeeeeeceeseeeeceecaeseeeesneeesaeseeeeeneesiaeeneeeeees 2-4 2.2.1.3 ROG Signal List oo... cece ceeeee cece eters ences eeaeeeeeeceeseeeeeaeecaaeseeeesneeesaeseeeeenaeesaesneeeeees 2-5 2.2.1.4 MUX Signal List oo... eee ccc eeeeeee cece eeeeeeeneeeeaeeeeeeceeseee sees caeseeeesneeesaeeeeeeeseesaeeneeeeees 2-5 2.3 SySteM INSPACE oe ec ceee cece ete e teeter teeta ae ene e reece eee e tenet tena edness nee caaeeeeee cae eenae sees sages saaesneeesaeeseaeeneesiaeeeneeenaes 2-6 2.3.1 System / MIOC Interface oo. eeee eet eee eee e renee eee eeeee eee aeeeeee eee taaeeeee eae eeaae sees caaeseeeenieeeseeeeeeenaee 2-6 2.3.2 = Third-Party Agent / MIOC Interface one. eeccecceeeeeeenteeeeeeeeeeeeneeteee ener eaaeeeaeesneeesaeeeeeeeneesiaeeneeeeaees 2-8 2.4 PCT IMEC E ance eee cece eeee teeter etter tenet ea ae teat teenie ee nee eee ea aetna ee eae ee eae sees ea aeenaae sees caeegeeeseeeeaaeeseeeeeeescaesaesneeenaees 2-8 2.4.1 Primary BUS oo... eeeeceeesceeeeeneeeeeeeeeeee ee eeeee ee ceeeeeaae ee eneae esa aeeeeeaaeeesneeeee see eneaeeeseeeesesieeenaeeeeneeeeeneeeees 2-8 2.4.2 GBA-Dit ACCESS SUDPOTE ooo... eee cent teeter eee nee ee tae ee eea ae eta gees ena ae ee aaeesaaeeeesaaeeeeeaeeesaeeeesaeeeseaeersneeees 2-10 2.4.3 Internal vs. External Arbitration oo... cee eecceeeeeeesneeeeeaeeeeeeeeeeaeeeeeaaeeseeeseseeeeseneeesneeeensaeeeenaeeeseees 2-10 2.4.4 PIIXAE Interface oe. eeeeeeeeceeeeee eee e eee ceeee eee eeeaeeeeeecaaeseeeeeeeecaeeeeeeeaeesaaeseeeeceeseaeeneesiaeseeeeneeeeas 2-11 2.5 Memory Subsystem Interface oo... eececcececee cence cee eeeee entre eaae sneer cae eeeee eee taaeseeeeeeeesaeseeeesaessaeesneeesaeeeeeenaeee 2-12 2.5.1 External Interface oo... eececccceeeeeeee cent eeeee enters aeeeeee ee eeeeeeeneecaeeeaeesneeecaeegeeeeneetaeseeeesieeesiaeeeeeenaeee 2-12 2.5.2 Internal INterfaCe oon... eeeeeeceene cence cee eeeeeeeeeeee ae eeeaeeeeeeeaaeseaeeeaeeesaeeeneeeeaeesaaedeeeecaeeseaeeneeesaeseeeeeneeeeas 2-14 2.5.2.1 ROG / DRAM Interface eee ceceecceeteeeeeeeeeeecrneeeeee ene eeeaeeeneesaeeeaeesneeeceeseeeeneeseeeeneeees 2-14 2.5.2.2 DRAM / MUX Interface oo. eececcccceeeeee ene eeeeeeeeeeaeeeaeeeneeecaesseeeeneeeaeseeeesneeesaeeeeeenaeee 2-15 2.5.2.3 ROG / MUX Interface oo... ceceeceec cence eter eecteeeeeeeeeeecaeeeeeeeeaeeeaaeeeeeeseeseaeenneesaeseeeeeneeeeas 2-15 2.6 Expander Interface ooo. eee eect eee eee ee eee eee ene teeter teeta cae cae saan ge sass ge sees aesae snes sages snes sesneeseee eae 2-15 2.7 COMMON Support SiQnals oo... eeeceeeeeeeeeeeeeeeeeeeeeeeeee ae ee eeeee sages eeeaaeecaeeseseeeeeeaeeeeneeeseaeeeeneaaeessneeeeenareesags 2-17 2.7.1 STAG INGCPACE ieee cece c eee ecte eee ee ene ee ea atten eee nesta ae eee eee ae dee ee eee eae eeee ee aeeeaaeeeeeecaeeseee sees caeseeeeeneeeeas 2-17 2.7.2 Reference Signals ........eccceecccccseceeeecee cess eeeeeenneeeaee ences ceeseeeeeneeesaeseeee eee saeeeeeeseeseeeseeeesiaeseeeeneeee 2-17 2.8 Component-Specific Support SIQnals ......ceeceeecececeeeeeeeeeeceeeeeeee ce eeeaeeeeeeeaaeseaeesneeecaeeeeeeesaeeseaeeeneeeseaeeeeeeeaes 2-18 2.8.1 MIO oot eter etn ee ene nen een nee eee ae nee eee eee eee rade eee eee aes eae eae ee eaaeeeeee eee 2-18 2.8.2 PRB veecececcecsceceeeecneeeeeeeeeeeeaeeeeee es aeeeeeeeee ees aeeeeee eee eaaeseeesaeegeeeeeeecaeseaeeseeeseeseneeeesiaeseeeesiaeseeeeenaees 2-19 2.8.3 ROG oiireeeecccecccecee cere e cnet eee tenet eee ee ee ene eee ae seater rege ened eee eee ae eee ee cae edness ee eaaeseaee sees saeeeneesnaeeeeeeeneee 2-19 2.8.4 MUX eect cnet eee rene eter ener ae sneer te etree ener ee ena ae eee teed eee ee eee seeds ea ee eaaee eee essen snes sa aeeeeeeeneee 2-19 Chapter 3 Register DeSCriptions .........cceecceceeeeeeceeeeenee eee eeeneee seen ennee see eeneee ses nnee sees sees seeeegneeeseeeenneeseeeeeeeesnensaeeeenens 3-1 3.1 ACCESS RESHIICLIONS oo... ceeeeeeeeee cent centr cette eee eeneeee tana eeeeaaee ea aeeeeeaeeeeenaeeeeaeeeeeaaeeeenaaeesaeeeeeeaeesneaeeeenneeseenreeennas 3-1 3.2 1/O Mapped Registers 3-1 3.2.1 CONFIG_ADDRESS: Configuration Address Register ........ecceseeeeeseceeneeeeeeecieeeeeeeneetiaeeneeeeaees 3-1 Intel 450NX PClset -|-CONTENTS 3.3 3.4 3.2.2 CONFIG_DATA: Configuration Data Register ......ecceccceceeececsteeeeeeceeeecieeeeeeeeeeeeaeseeeesneeetaeeeeeenaes 3-2 MIOC Configuration SPaACe oe. eeeeeceeetcecnteceeeeceeeeeee eee eesaeeeeee ene eeeaaeeeeeeaaeeeaaeeneeecaaeseaeeeneesaeseeeeenneesiaseeeeesees 3-3 3.3.1 BUFSIZ: Buffer SIZES ooo. cece eeee rene eeeeeeene eee aeeeaee eae eeeaaeeeeeesaeesaaesneeecaaeseeeeeeesaeseeeeenaetaeseeeeneees 3-4 3.3.2 BUSNOJ[1:0]: Lowest PCI Bus Number, per PXB oo... eeeeeeeseeeeeeneeeeneeeeesaeeesenaeeesaeeeeesaeeesenaeeeseeees 3-5 3.3.3 CHKCON: Check Connection oo... eeecceeeceesneeeeenneeeeeeeee ease eeeaeeeeenaeeesaeeeeesaeeesnaaeessneeeeesaeeesenaeeneeees 3-5 3.3.4 CLASS: Class Code Register... eceesseceeneeeerneeeeeneeeenneeeeceeeenaaeeeseeeeeaeeeeeaaeesnneeeeenaeeeseeesneeess 3-6 3.3.5 CONFIG: Software-Defined Configuration Register .........cceecececeeseeeeeeeieeeeeeeeeesiaeseeeeneeeseeeeeeeena 3-6 3.3.6 CVCR: Configuration Values Captured On R@Set ooo... eeceeeceeteeeeeeceeeeceeeeeeeeeeeeaeeeeeeeneesaeeeneetaees 3-8 3.3.7. CVDR: Configuration Values Driven On ReSet oo... ecceeeeeteeeteeeeeeeeeeeeseeeeeeeeeetaesneeesieeseaeenneeeaas 3-9 3.3.8 DBC[15:0]: DRAM Bank Configuration ReQiSters .......eccescceseceeeeee ener eeeaeseeeecieeeeaeeeeeeeaeseeeenee 3-9 3.3.9 DEVMAP: System Bus PCI Device Map ooo... eeeeeeeeneeeerneeeeeeeeeeneeeeenaeeenneeeeesieeeeeeaeeesneeeenneeeees 3-10 3.3.10 DID: Device Identification Register 2.0... ceccceceeeeeeeceteeceeeecneeeeaaeeeeeeseesaeeeeeesaeseaeeeieesiaeeeeeeenaees 3-11 3.3.11 ECCCMD: ECC Command Register ooo... eeececeeceeesnreeenneeeeneeeeeneeeeenaeecnneeeeeeeeeneeeesneeeennneeeee 3-11 3.3.12 ECCMSK: ECC Mask Register... eeeesseceeneeeeeeeeeenreesenaeeeneeeensaeeesnaaeecneeesenaeessnneeesneeeenenrenaes 3-12 3.3.13 ERRCMD: Error Command Register 0... cceeeceeeeeeeenreeceneeeesneeeeeaeeesenaeeeneeeeenaressenseesneeeenenneeeaes 3-12 3.3.14 ERRSTS: Error Status Register ooo... eee eeseeesseeeeeeeeeeneeeeeeeeeeseeeeesaeeesenaeesnaeeesenaeesseneeesneeeesereeseaes 3-13 3.3.15 GAPEN: Gap Enables oi... eessceeeeeeesnee eee eeeeeneeeeeeeeeeneeeeeeeeenaaeeeseeaeesseeeeenaeessneaeesseesenressenes 3-14 3.3.16 HDR: Header Type Register... ceeeceesereesenneeeeeeeeeeneeeeeeeeeecneeeeeaaeeesenaeecsaeeeeeaeeennaaeetneeenseeeseaes 3-15 3.3.17 HEL[1:0] Host Bus Error Log oe eeeceesneeeeeneeeceneeeeeneeeeeeeeeeeneeeeeaaeeesenaeeseeeeeaeeennaaeeeseeenneeeseaes 3-15 3.3.18 HXGB: High Expansion Gap Base ooo... eesseeeseeeeesneeeeeneeecneeeeeeeeecenaeesseeeeeaeeeeneaeessneeeeeneeesaes 3-16 3.3.19 HXGT: High Expansion Gap TOD ou... eee eeesseeeseeeenneeeeeeeeeneeeeeeaeeeeneaeessaeeeeeaeeeennaeetnaeeseeneeseeaes 3-16 3.3.20 IOABASE: I/O APIC Base Address ou... cecccccceececeeeeeeeeeeeeneeeeaeecneeecaeeseeeeeeeeaeseaeeenaeesaseeeeeseanaes 3-16 3.3.21 IOAR: VO APIC Ranges oui... .eceecceceseeeeeeeeeeeeeeeeeeeeeeeeaaeseeeeeecsaeseeeeeaeesaaeseeeeseeseeeseeesiaeseaeeneeeeaes 3-17 3.3.22 IOR!: 1/0 RANges oo. cecceeeneeeeenneeeene cette eeeeaaee ea aeeeeeaaeeeeeeaeeeceeeeesaeeeaaeecseeeeeaeesenaaetsneeseeneessenes 3-17 3.3.23 ISA: ISA Space ieee ecceeeeceeee cence cette cae eeeeeeeeeeeaeeeeeeeeaeeeaaeeneeecaeeseeeegaeecaeseeeesneeecaeeseeeeieesiaeseneeenaees 3-18 3.3.24 LXGB: Low Expansion Gap Base uo... ceesseeeeeeeeeenneeeeeeeeeeneeeeesaeeesenaeesaeeeeeaeeesnnaeesseeseenaeeesaes 3-18 3.3.25 LXGT: Low Expansion Gap Top ou... eeeesceeesseceeeeeeenneeeeeneeeeneeeeesaeeeeneaeesseeeeeaeeeenaaeesseeseenresseaes 3-18 3.3.26 MARI[6:0]: Memory Attribute Region Registers oo... eeeeseesseeeeeneeeeneeeeeeneeeeesaeeeeenaeetseeeeenaeeesaes 3-19 3.3.27 MEA[1:0] Memory Error Effective AddreSS oo... eee ccceeeeeeeceeneeeeeeeeeeeaaeeeeeecaeeseaeeeeesaeteaeesneeeeaes 3-20 3.3.28 MEL[1:0] Memory Error Log oo......ccecccececcceceseeceeeecenaeee cece eeceeaeceeeeseaaeeeeeescaeeeseesaceeesesseeseeeeeeensanaees 3-20 3.3.29 MMBASE: Memory-Mapped PCI Base ooo... ieeeeeesneeseneeeeneeeeeeaeeesenaeeeaeeeeenaeeenenaeesneeenenreeenaas 3-21 3.3.30 MMR[8:0]: Memory-Mapped PCI] Ranges on... .ceeeeeesseeeeneeeeneeeeeenreeceeaeeesaeeeseaeeesnnaeesnneeeeenneesaes 3-21 3.3.31 PMD[1:0]: Performance Monitoring Data Register oo... .eeeeccceeeeeee este eeeeeeeeeeeaeeeeeeneeeteeeeeeenaees 3-21 3.3.32 PME[1:0]: Performance Monitoring Event Selection oo... ceccceeeeeeee eeeeeeeeeeeeeeeneeeneeeseeeeeeeneee 3-22 3.3.33 PMR[1:0]: Performance Monitoring RESPONSE ou... eee cecceececeeceeeeeeeeeeeeeeeaaeeeeesaaeseaeeeeeessaeeeeeeenaees 3-23 3.3.34 RC: Reset Control Register oo... eeceesseesenneeceeeeeeeneeeeeeeeeecneeeeeaaeeeseeaeesaeeeeeaeeesenaeesnneeeeneeeseaes 3-24 3.3.35 RCOGP: RCOGS Present 0... eesseceeneeeeennreeeeneeeenneeeeeeeeseneeeeceeeenaaeeeseaaeesaeeeeeaeeennaaeesseeeeneessenes 3-25 3.3.36 REFRESH: DRAM Refresh Control Register 0... cesceeecsesteeeeeeeeeeeecaeeeeeecneeesaeeeeeesneetaeeneeenaes 3-25 3.3.37 RID: Revision Identification Register oo... cceeeeeeceseeceeeeceeeeeeaeeeeeesaeesaeeeeesaeseaeeseeesiaeeeeeeenaees 3-26 3.3.38 ROUTE[1:0]: Route Field SCQd oie. cece cece eeneeeeeeeneeeceeteeeeneesaeseaeesneeesaesseeessaeesiaeeneeenaees 3-26 3.3.39 SMRAM: SMM RAM Control Register 0... ee eecceseeeesneeeeeneeeeneeeeesaeeeeenaeessaeeeeeaeeensnaeesneeeneaneeenaas 3-26 3.3.40 SUBA[1:0]: Bus A Subordinate Bus Number, per PXB ou... eeceesseeeeeneeeesneeeeeneeeeenaeeeeeeeneaeeeeeaas 3-28 3.3.41 SUBB[1:0]: Bus B Subordinate Bus Number, per PXB ou... eeeceesseeeeneeeesneeeeeneeeeenaeeeneeeneneeeeans 3-28 3.3.42 TCAP[0:3]: Target Capacity, per PXB/PCI Port oo... eeesceeeeeeeesneeeeenaeeeeneeeeeaeeseeeeesneeeeeeneeeeaa 3-28 3.3.43 TOM: Top Of M@Mory ........cccccccesseceseeceeseneceseeeeeceeeeessaeeceneecesneesesaeeecnsaessaeeessaaeessanaesseneesssntesseaes 3-29 3.3.44 VID: Vendor Identification Register oo... ec ceeeeeeecsneeceeeeeeecieeeeeeeeeeeaeseeeesneeesaeeeeeeesaeesiaeeneeeeaes 3-29 PXB Configuration Space oe .eeeeccccceceeeecneeeeeeeeeeeaeeeeeecneeecaeseeeeesaeeeaaeeneeecaeseeeeaeeeaeseeeesneesaeeeeessesseeeenaees 3-29 3.4.1 BUFSIZ: Buffer SIZES ooo. cece eeee rene eeeee eee eeeae sneer eae eetaaeeee ees aeesaeeeneeeeaaeseeeesaeesiaeenneesietaeseeeenaes 3-31 3.4.2 CLASS: Class Code ReQister oo... .eeiceesseesseeeernreeeeneeeeeneeeeeeeeenaaeeeseeeeeaeeeneaeeseneeeeeneesseneeesaes 3-31 3.4.3 CLS: Cache Line SiZO occ eeeeeeeene eee ee etter nee eeeeaee canes eeeaeeeeneaeeesneeeeeaaeeesnaaeeesneeeenseeesenaeessaes 3-32 3.4.4 CONFIG: Configuration Register 0... ceeeeeceeeeeeeeeeeeseceeeecneeeeaaeeeeeeaeeeaeeeeesaeseeeeieessaeseeeeenaees 3-32 3.4.5 DID: Device Identification Register oo... ce ceeeeececseeeeeeeeeeeceeeeeeecaeeeeeeeeesaeseeeesaeeseeeeeesiaeeseeeenaees 3-34 3.4.6 ERRCMD: Error Command Register .........cceessceeseeeeenneeeeeneeeeeeeeeeneeeeeaeeeeeneeeeseeeseaaeeeeneeeenneeees 3-34 3.4.7 ERRSTS: Error Status Register oo... eeeeceeeeseeeeeeeeeesneeeeeaaeeeeneeeeeaeeeeeeaeeeseeeeeseeeenaeeseneeeeneeeea 3-35 Intel 450NX PClsetCONTENTS 3.4.8 GAPEN: Gap Enables oo... cecceesneeeeenneeeeeeeee cree eeeaeeeenneeeeeeeeeeaaeeesneeeessaeeeeeaaeeesneaeesieeseneeesaas 3-36 3.4.9 HDR: Header Type Register oo... escecesseeeseeeeenneeeeenaeeeeneeeecnaeeeeeaeeesneeeecsaeeesnaeeesneaeeeseeeseateesnes 3-36 3.4.10 HXGB: High Expansion Gap Base o.oo... ei ceesseeseeeeeeeneeeeeneeeeeneeeeeeeeeeaaeecaeeeseaeeesenaeesseeeeenaeeeseas 3-36 3.4.11 HXGT: High Expansion Gap TOp ou... eeeeesseceeeeeeerneeeeeaeeeenneeeeeaeeeeeaaeeesaeeeeesaeeesenaeesseeeeenaeeeseas 3-37 3.4.12 IOABASE: I/O APIC Base Address. ou... eeccccccesceceneetieeeeeeeneeeeaeeeeeeeaeseaeeeeeeesaesseeeenieesaesneeesieaaes 3-37 3.4.13 ISA: ISA Space oo ccceecceece eect ener eecaeeeeee ce eeeaeeeeeeeaaeeeaaeeeeeecaeeseeeenaeesaaeseeeeceeseaeeenessieeseaeeeeeeeaes 3-37 3.4.14 LXGB: Low Expansion Gap BasSe ou... .ecceessreceeeeeeeeneeeeeaeeeeneeeeeaeeeeeaaeeeaeeeeeaeeeseeaeetsneeeeenaeeeseas 3-37 3.4.15 LXGT: Low Expansion Gap Top ooo... ieee esneeeeeeeeeeeeeeeeneeeeneeeeeeeeenaaeeesneeeeeaeeesenaeessneeeeeneeetees 3-38 3.4.16 MAR[6:0]: Memory Attribute Region Registers o.oo... eeesseceseeeeeneeeeeeaeeesneeeeeaeeeeenaeesneeeeeaeeeseas 3-38 3.4.17 MLT: Master Latency Timer Register... ceseeeesseeeenneeeeneeeeeeeeeesaaeeesaeeeeesaeeesenaeesneeeeenaeeeseas 3-38 3.4.18 MMBASE: Memory-Mapped PCI Base ooo... eeeeceeseeeeeereeeeneeeeerneeeeeaeeeeneeeetaeeenenreeenneeeeeneeeee 3-39 3.4.19 MMT: Memory-Mapped PCI TOD a... ecceeesneeeeeeeeerneeeeeeeeeeeeeeeaeeeeenaeeeaeeeeesaeeesenaeetseeesenaeeeseas 3-39 3.4.20 MODES: Modes Register... eee ceeeeeesneeeenneeeeeeeeeesaeeeeeaeeeeaeeeesaeeeenaaeesaeeeeeaeeesenaeesoeeeeenaeeeseas 3-39 3.4.21 MTT: Multi-Transaction Timer Register ooo... eeseeeeseeeeeenreeeeeeeeeeneeeeeaeeesneeeeenaeeeeenaeeeneeeeetneeeeees 3-39 3.4.22 PCICMD: PCI Command Register ..........ccceesseceseeeeeneeeeeeneeeeneeeensaeeeseaaeeesneeeeeaeeesnnaeecsieeeseeteeegs 3-40 3.4.23 PCISTS: PCI Status Register oo... eee esseeeesneeeeeeeeneeeeeeaeeeeneeeenaeeeseaaeecsneeeeeecaeesseeeeesnneesnaneeseas 3-41 3.4.24 PMD[1:0]: Performance Monitoring Data Register oo... .eeeeeeeeeseeeeeeceeeeeeeeeeecaeeeaeeeeeeeseeseeeenaees 3-42 3.4.25 PME[1:0]: Performance Monitoring Event Selection oo... .eeeccccceeeecneeeeeeeeeeeceaeeeeeeneeeseeeeeeenaees 3-42 3.4.26 PMR[1:0]: Performance Monitoring RESPONSE ooo... eceeececsteeeeeeeeeeecaeeeeeeceeeeaeeeeeeeaeeseaeeeeeeeaaes 3-44 3.4.27 RID: Revision Identification Register oo... ee ecceeceeeeceeeeceeeeceeeeeeeeeeeesaeeeaeeeeeesaeseeeeseeeeaeenneeeaes 3-44 3.4.28 RC: Reset Control Register oo... ceeeeeesseeeenneeeeeeeeesneeeeeeaeeesneeeeesaeeeeeaaeeesaeeeesaeeesenaeesneesenaeeeseas 3-45 3.4.29 ROUTE: Route Field SCCd oo. ec ccceeeecneeeeeeeeeeeeaeeeaeeeeeeecaeeseeeenaeessaeseeeeceeeeaaeeneessaessieseneeeaes 3-45 3.4.30 SMRAM: SMM RAM Control Register oo... eeeceeeeseeeeeeeeeenreeeeeeeeeseeeeeaeeeeneeeesaeeeeeaeeesneeeeeneeeeees 3-46 3.4.31 TCAP: Target Capacity ieee eeeeeeeesneeeeenneeeeeeeeeeaeeeeeaeeeeaeeeesaeeeenaaeeesaeeeseaeeesenaeessneeesenaeeeseas 3-46 3.4.32 TMODE: Timer Mode o.....eececcceeseeeeeccceeenee cee eeeaeeeeee eee eaeeneeeceeseeeseeeeaeseaeesneeesaeeeeeesieesiaeeneeeeias 3-47 3.4.33 TOM: Top Of M@Mory .........ccccccccssecesssseeceeeeeeceaeeceesececeeeeeesaeeeceeeesesaeeesesaeesseesessaaeeessneessasesesieeeeess 3-47 3.4.34 VID: Vendor Identification REQister 2.0... ceecceceeeeeeeceeeeeeeeecaeeeaeeeeeeesaeseaeesnaeesaeeeeeeseeseaeeeneesaes 3-48 Chapter 4 System Address Maps . ........cccseecceeeeee nn ene nei nee een nenne eee nnne ee een ncne ee eng nene ee een acne eee en seen eeenaneneeaeeeennnes 4-1 4.1 Memory Address Map oo... eeeceeeeseeeeeeeeeennee teen eee neeeeeeeeeeaaeeeeneee ees aeeeeeaaeeegeeeeeeaaeeeeeaeeesgneeeeseeesnaeeesneeeeeneeeees 4-1 4.1.1 Memory-Mapped 1/0 Spaces oe ceeecceeeneeceeeeeenneeeeenaeeeeeeeeaeeeeenaeecaeesesaeeeensneeesneeesnsaeeeenaeeesneeegs 4-4 4.1.2 SMM RAM Support oo... eee ee eee ceeeeeenneeeeenaeeeneeeeea nese eeeneeecaaeeeeeaeeeeeaaeeeseeeenaaeeeseaaeesseeeeesaeeseaeeeseees 4-4 4.2 VO SPaACe ieee eee eter teen ee ene ern een ene eee nae ane ane eee eee eee eee eee eae enna eeee seen ee 4-5 4.3 PCI Configuration Space oie. cecceeceeeeececeeeeeee cee eeeeaeeeeeeaeeeaae sees ca aeseaeeeeeeecaeeseeeeeeeeaeseeeesneeesaeseneeeneesiaeeneeesaees 4-6 Chapter 5 INTOPACES wane ee ceeeeee cee eeeeeee ee ee eee ee eee eeenee seen eenee se eennee seen eeeee seen eeee sense eeeeeseegesneesaeeseeeeseseseneeeeseeseseeeeseeeeenensees 5-1 5.1 SYSTEM BUS oo... eeeeeeeeeeee tenner eeeae ee eeeee ee eae ee eeaae ee eaeee eee ae seca neste aaaee ca aeeeeeaaeesnaeeeceeesesaeeesnaaeeseeeeeeaeeeseaeeeneees 5-1 5.2 PCI] BUS oeeeeececcceeeeeeeeceeeeeee ene ee sie eeeeee canes eaaeeneeecaeeeeee ea aeecsaeeeaee sees caeseeeeeaeesaaeseeeecaeesaaeeeeesneeesaeseeeesneesiaeeneeesaees 5-1 5.3 Expander BUS ooo... eeeeeee een reer een re ene nee ne nee ne nee ee eee ae ee ena eee eee seen 5-1 5.3.1 Expander Electrical Signal and Clock DiStriDUtion ooo... eee eeeeeeesneeeeeneeeeeeeeeeenaeeeeenaeeenaeeesenneeenaaes 5-2 5.4 Third-Party AQe@nts oo... ceeeeeeeneeeeneeeeee ener ener een ae eee aeee ees aeeeeeaaee eases ca aeeeeeaeeesnaaeeeceeeseaaeeenaaeeeseeeseaeeesenaeesnaees 5-2 5.5 COMMECHOLS ones eeeeeeenneeeeee eee enneeeeeae eee aee ee eaeeeeeaae ee ea aeae eee ae eee eaaeeeaaaeee cease eesaeeeeeaaeeeceeeeesaeeesenaeeseeeeeneesenaeesneees 5-3 Chapter 6 Memory SUDSYStCIN oo. ceceeee eee eeenee eee eee seen seen eeee see eeeeeee seen eeeeseeeeeeeeeseegeseeesaegeeeeeeseseseeeeseeseseeneeseeeeenensees 6-1 6.1 OVELVIOW noose eeecce cnn eeeeneeeenee eee aeeeeeae ee eeee ee caeeeenaae ees aeae ees aeeeeeaaee ca aaeeeeaaeeeeeaeeeenaaeeecoeeeseaaeeesenaeeesneeeenaeeeseaeeeneees 6-1 6.1.1 Physical Organization oo... eeeceesseeeenee tenner eeeee ee eeeee seein ee eeaaeeeeneee ee aeeeeeaeeeegneeeetaeeseeeeesneeeeniieeeenaa 6-1 6.1.2 Configuration Rules and Limitations 0... cc eeceecceeeeeeeeeeeceeeeeeeeene esas eeeeeceeeeeeeeeeetiaeseeeenieesiaeeeneeeaa 6-3 6.1.2.1 INCOPICAVING oo. eeeeeeeneceeenee ener eeeesaeeeeeae eee aeeeeeaeeeeenaeeecaeeeeeaaeeeseaaeecaeeeeeaaeesseneeeeseeeseateeenaas 6-3 6.1.2.2 Address Bit Permuting Rules and Limitations oo... eeeeeeseeeeeneeeeeeeeeeeneeeeenneeeneeees 6-4 6.1.2.3 Card to Card (C2C) Interleaving rules and limitations 00... ee eee eseeeeeseeeeeeneeeseeeees 6-4 Intel 450NX PClset -lii-CONTENTS 6.1.3 Address Bit PErMUuting eee eee eeseeeeeeeeeeeneeeeee eee eeeeee canes eneaeeeeaeeeesaeeeeeaaeeesneaeesseeeseaeeeseaeesneeess 6-5 6.1.4 Card to Card (C2C) Interleaving oo... eeeceesneceeenneeeeeeeeeeaeeeeeaeeeseeeeeeaaeeeeeaaeeeeeeaeesaeeeeenaeeeseaeeesneess 6-5 6.1.5 Memory Initialization oe eee ee eene eee ne eee ene ee ee eee ee tne ee eee ae ee ena ae eee ease aeeeenaaee see eeseeeeeeaeeeenneeeeeneeeea 6-6 Chapter 7 TrANSACTION SUMIMALY oo eeeccceeeeeceeeeeeeee ee eeeeeee eee eeeeeee se eeeeeeee eee eneeseeeeeneeeseeeesneesaeeeseeeeseeseseeeseeseseeeneeseenseeeees 7-1 7.1 Host To/From Memory Transactions oo... .eeeeceeeeeeeereeeeeneeeceeee eee ee eenaeeeeneeeeeaeeeeeaaeeseneeeeeieeeeeeeeesnneeeeeneeeeen 7-1 7.1.1 Reads and Writes oo... eecceeeseeeerneeeeneeeeeaeeeeeaeeeeneeeeesaeeeeeaaeecaaeeeensaeeeegaaeeceeeeeaeeeseaeeeesieeeennaeeeeenas 7-1 7.1.2 Cache Coherency Cycles oo... eeeeesseeeseceeerneeeeeaeeeeeeeeeeaeeeeeaeeeeneeeeeceeeenaaeeeseaaeeesneeeeeaeeesenaeeeneeees 7-1 7.1.3 Interrupt Acknowledge CyCleS oo... eeeceessreeeenneeeeneeteeneeeeeeaeeecaeeeeesaeeeenaaeecaeeeseaeesseneeesieeesnenreeennaes 7-1 7.1.4 LOCKEd CYCLES oe. .ecececceccecccceeeceeeeee eee cece naan eee ee cea aeeee ee caaaeee sees gaeae ease geaaeeeeseeeaeeeeesceaeeeeessecieaeeeeeeaed 7-1 7.1.5 Branch Trace CYClOS oo. eeeeeeeeeeeeene ee eeeeeeerne ee eeeaeeeeneeee ea aeeeeeeaeeeeaeeeeeeeeenaaeeesneeeeeaeeeseaaessneeeeeneeeees 7-2 7.1.6 Special CYCIOS oe eceeeecceceeeeeeeeeee esas eeeeeeeeesaeeeeeeaeeeegeeeecaaeeeeeaeeeeeeeeeecoeeesnaaeeesneaeeesneeeeeseeesenaeessneeess 7-2 7.1.7 System Management Mode ACCESSES ooo... eeeeeeeeeeeeenneeeeeeeeee tree eeeaeeeenneeeesaeeeeeaaeeeaaeeeeesaeeesenaeetsneeeees 7-3 7.1.8 = Third-Party Intervention oo... eeeceeeeeeeenne cess eee eneeeeeaaee eee eesaeeeeneaeeecneeeesaaeeesnaaeeeseeeeesaeeesenaeesneeess 7-3 7.2 OUTDOUNA TraNSactiONS eee eeeeeeeeseeeeeeee teens eee eeeeee sean eeeeaaee ea aeeeeeaaeeeneaeee eee eesaeeeenaaeeesneeaeesgeeeeenaeeeseeeesnees 7-4 7.2.1 Supported Outbound ACCESSES ou... eeeceeeeeceseeeeeenneeeeeeeeeceneeeeeaaeeeeeeeeeceeesesaeeeenaaeeesaeeeeeaeeeeenaeeeeneeegs 7-4 7.2.2 Outbound Locked Transactions 0... eeceesseeeeseeeeeeeeeceeeeeeeaeeeeeeeeeeneeeeesaeeeseaaeeeseeeeeeaeeesenaeeeseeees 7-4 7.2.3 Outbound Write COMDINING oo... eee ce eeeeeeeseeeeeeneeeeee cerca aeeeeeaaeeceeaeeecaeeeeeeaeeeeeaaeeeaeeeenesaeeeseaeeeneeegs 7-4 7.2.4 = Third-Party Intervention On OUTDOUNAS ooo... eee eennee cence ee eeeeeeeeaeeeeeeeeeesaeeeenaaeeeseeeeesaeeesenaeeennaeess 7-4 7.3 INDOUN TraNSa@ctiOnS ooo... nn nnn renee neta neni saasneeeene etna snneeied 7-5 7.3.1 INDOUNG LOCKS oon... eeecceeeeeeeenneeeeee eee e ee ee ea nee eeeae ee caeeeeeeaeeeenaaeecaaeeeensaeeeenaaeecaeeeseaaeesseaeeesieeeenenreeennaes 7-5 7.3.2 South Bridge ACCESSES oo... see eceeeeeenne test ee tener eeeeeaeeeeeeeee ea aeeeeeaeeeeeeeeeeeaeeeensaeeesenaeeegeeeeeaeeeseaeeenneeees 7-5 7.4 Configuration ACCESSES oo. ceeceeecceceeeeeeeeneeeeaeteeee cae eeeaeeeeeeeaaeesaaeeneeecaaeeeeeecaaeesaaesneeesieeseeeesieesiaeseeesneeesiaseneeenaes 7-6 Chapter 8 Arbitration, Buffers & COMCUITONCY o..ccceseceeeee eset ee enteceeeeeneneeeeeeeneeeeeeeenseseeeeeeseseeeeeeseeseeeseeneeene eneneees 8-1 8.1 PCI Arbitration SCHEME ei eeeeeesseeeenneeeeee eee eneeeeeeaee eee ee eaeeeeesaeeeeneeeeeaaeeeenaaeeesneeeesaeeeeeaeeeseneeesieeeeseateeennaes 8-1 8.2 Host Arbitration SCHEME o....eeeccseeceeeenee eect ee ene ee ee ee ee een ae eee ee eee aeeeeeeaee ea eeeeeaaeeeeeaeeeseeesesieeeenaeeesneeeenieeeeea 8-1 8.2.1 Third Party Arbitration oo... cesses ennee eee eeeeeeee teense eeeeaeeesneee ees aeeeseaaeeseneeeeeaeeeseaeeesnneeesneeeeneareeennaes 8-2 8.3 South Bridge SUPPOM oe nn nnn nine sneer ne enaesnees ne snaasneeseneeseaesnneeied 8-2 8.3.1 I/O Bridge Configuration EXAMple. oo... cee ccceeeceeeneeeeeeeeeecneeeeeeeeneeeaeseeeesieeetaeeeneesiaeseaeeeneeeseeeeneetaa 8-2 8.3.2 PHOLD#/PHLDA# Protocol oe. eec cece eeeeee ee eneeeeee enter eae eeeee eae eeeaeeeeeesaeesaaeeneeeseeseaeeeneesiaeseeeeneeeea 8-3 8.3.3 WSCH Protocol oe cece ence eee ee eee ne eee ea ae eee aeee eee aeeeeeaaeeeaaeeeecaeeeeeeaaeesaaeeeeeaaeeeseaaeeseneeeesaeeesenaeesneeess 8-3 Chapter 9 Data Integrity & Error Handling .......cccccsecceccesneeeeeeeeenee eee eesnee see eneeeeseeennneeseeeesneeeseeeesnaeseeeeseeneaeaeeeesnenaes 9-1 9.1 DRAM INteQrity oo... eeeeeeneeeeeee ener aeeeeeeaee en aeeee ca aeeereae eee aeeeesaeeeenaaeeeseeessaaeeeseaaeeeeeaeesaaeeseaaeesneeeeesieeeeseareeennaes 9-1 9.1.1 ECC GOmeration oi... eeeeeeceeesneeeeeneeceneeeeeeeeeeeaeeeceeeeesaeeeseaaeesaaeeeeeaaeeeneaaeecgeesesaeeeseeeeesneeeeneareeennaes 9-1 9.1.2 ECC Checking and Correction oo... iesceeesseeesneeeceeeeeeeeeeeenaeeeeeeeeesaeeesenaeecneeeeeaeesseneeesneeeeneareeennaes 9-1 9.1.3 ECC Error Reporting oo... eeeceeeseeeeseeeeeeeeeeeneeeeenaeeesaeeeeesaeeeeeeaeeecaeeeesaeeeeneaeeesieeesnaeeeenaaesneeeennaeeeeaas 9-1 9.1.4 Memory Scrubbing o.......cececccceccceeececeeeeeeee eect eeecea ance cerca gaeee eee cegeeaeeeeeggeaeeeeeegseaaaeeeeeseeaeeeeessenieaeeeeeeaes 9-2 9.1.5 Debug/Diagnostic SUPPOIE oo... eee eeeeceeeeneeeeeeee tenet teen ee eeeeeeecaeeeeeaaeeeaaaaeessaeeeeeaeeesnaaeeeeneeeenenteeennaes 9-2 9.2 System Bus Integrity oo. nn nn nner ene enae sees se esneeesneesaesneesoeesssaasoeeenaes 9-2 9.2.1 System Bus Control & Data INtegrity oo... eee eeeseeeeeeeeeeeee teen ee eeeeeeesaeeeeeaaeeesnaaeeesaeeeeeaeeeseaaeesneeegs 9-3 9.3 PCI ING Qrity oo. eee cece ee eeneeeeeee ee erent eee ee ater ae ee seagate eae ee ea aeeeesaeeeenaaeeeeeeeesaaeeeseaaeeseneaeecaeesnsaeeeesneeeeieeeesenteeennaes 9-3 9.4 Expander BUS ooo... eeeeeeeeeeene cece ee eenneeeeeeaeeeene eee ea gee eeeeaee ea aeeeecaeeeeesaeeeseeeeesaaeeeeeeaaeeseeeeecaeeeeaaeesseeeeesieeeesenteeenaaes 9-3 Chapter 10 System [ritialiZation 2.2... ceeeeceeeeee eee eeeeee eee eeeeee ee eeeeeee sense eeeeeseeeeeeeeseeeeeeeeeseseseneeseeeeseeeeseseeseeeneeeeesessennanes 10-1 10.1 Post Reset Initialization oo... eee eeeeeeeeeeee tener eeeeaeeeeneeee canes eeeaaeeeaeeeesaeeeeesaeeesneeeeeaeeeeesaeesseeaeeeiaeeeeeareeesaas 10-1 10.1.1 Reset Configuration using CVDR/CVCR oo .eeeeccceceeeeeeeeeeeeeeeeeeecaeseeeeeeecaeseeeeeseeseeeesaeesiaeeeeeeeaes 10-1 10.1.1.1 Configuration Protocol oo... eceececeeeeeeeeeeeeeeeeeeeeeeeecaaeseeeeeaeeeaeseeeesaeesaaeeneesiaeeseeeenaees 10-1 -iV- Intel 450NX PClsetCONTENTS 10.1.1.2 Special Considerations for Third-Party AQents oo... ceecececceeeceeeeeeeeeeeeeeeeeeeteaeeeeeeeneeeeas 10-2 Chapter 11 Clocking and Reset . ......cccceceetennne etn enn nn einen ee nnnne eee egnnne sees nne sees nee eee eg gegen eeenaneeeeeeennenaaneneeeeenaes 11-1 T1.1 CLOCKING eee eect e cece cece eee eee cee ae cette aae ee eee seas ee eee ea a aee ee ecaaaeaeeeeegeaeaeeee ee caaeeeeeeseaaeaeeeesaeeeaeseeseseeaeeeeeeeeneeeees 11-1 11.2 System ReSet oo... ee ee tees ener eee ee ee ene ee ena terete eee eee ne ater eee eae e en nae ee ea nee setae ee ene ae esa aeee sna aeeeenaaeeseneeeeeeeeeeee 11-2 11.2.1 Intel 450NX PClset Reset Structure eee eeecceceeeeeesneeeeenaeeeeeeaeeceaeeeeeaaeeeeeaeeeeeeeeeseeeenaaeeeseeees 11-2 11.2.2 Output States During RESOt oe eee ste eeeeeeeeete ee etre ee eee ae eens eesti aeeeeeeaeeseneeeeeaeeeeeeeesneeeeeeeeee 11-5 11.2.2.1 MIOC Reset State ooo. eeeceee eens eee eer neeeeeene erent eteee ences eae eeneeenieeseeeenneetaeseeeeneeee 11-6 11.2.2.2 PXB Reset State oo. cececeeececeeceeee eee eeeeeeeneeesneeseeseeeecaeseeeesneessaeeseeeesieesiaeesneesiaeeas 11-8 11.2.2.3 ROG Reset State oo. ceccceceececeeceeee cee eeeeeeneeeseesaaesneeecaeseaeeseessaeseeeeegeesaseeeeeseeees 11-9 11.2.2.4 MUX Reset State ooo ceceeececneeeeee ene eeeeeeeneeeaeesaaeeneeecaeseaeeeneessaeeseeeeneesiaseeeeeseeees 11-9 Chapter 12 Electrical Characteristics .......ccccccseecceeeeeeeceeeeeneeeeeeeeeneeseeenneeseeeeeneeeseeeennaeseeeeseeeeseeesnneeseeeeseenneeseeeennaes 12-1 12.1 Signal Specifications oo... ee eceeeeeee eee e eee eeee eee eee ee sneer eae eeeee ence eeaaeseeee eae eetaeeeeee eae enaaesneeesaeseeeesgeesaesneeeeaa 12-1 12.1.1 Unused PINS eee tenn eee renee ree nee terete eran ee ene ae era ae eee ae eee eee sa ee ee eaeeeeaeee eee eeeaeeeee 12-1 12.1.2 Signal Groups oo... ee eee eeee eee eene renee e teeter ee eae eee ee seer ee eee ae ee eeee eee neeeeeeaee sa eeeeeaeeeseaeeeenneeeeeeeeee 12-1 12.1.3. The Power Good Signal: PWRGD oo... eeceeeeeeeeeeeeeenne ee een ae eeeneeeeeaeeeeeaeeseneeeeeaeeeeeaeeeeneeeeenaeeee 12-3 12.1.4 LDSTBH USAC oie ie ecceeccce cee ceee rene ee eeeeene eee aeeeaae entree aeseeeeeeeesaeseeeeeeesaaeseeeesaeseeeeenieesaesneeeneeeeas 12-5 12.1.5 VOCA PINS o.eeeeeccccceeeee cece eee eee cette eee ae seers cane eee aeeeeeecaeegeeeeaeeeaaeseeeesaeeesaeeeeesaeesaaeseeeesaeesaeeeeeeseeeas 12-5 12.2 Maximum Ratings 200... eeceeeeeeeeeeeeeeene ee eeeae erage ee eee nese eaae eee ae eee eaaee eae eecaaeeeeeaeeesenaeeesaeeseaaeessneaeesseeeeenareeseas 12-6 12.3 DC Specifications oe eeceeccceceeeee een eece eee ee ene eeeaaeeeeeeeaeeeaae seers caaeseeeeceeesaeseeee eee saaeseeeesieeseeeseneesiaeseieeeneeeeas 12-7 12.4 AC Specifications oe eecceecceceeeeeeeneeeeeeeeee ene eeeaaeeeeeesaeeeaaeeeaeecaaeseeeeceeesaeseeeesseesaeseeeesaeeseaeseneesaeseneeeneees 12-11 12.5 Source Synchronous Data Transfers oo... ceeccecccsceeeeeeeeeeeeeeeeeeeeaeeeeeeeeeesaeseeeeeaeesaaeeeeeeseeseaeseeeesiaeseneeeees 12-22 12.6 1/0 Signal Simulations: Ensuring /O Timings oo... eeeseeeeeseeeenee eter ee eeeee teense ensue eeeeaaeeesneeeeeaeeeeeeeeesneeees 12-22 12.7 Signal Quality Specifications oo. ee eee eeeeeeeeeeeceeeee ene eeeaeeeeeeeaeeeaaeseeeecaeeseeeseeeesaeseaeesneeeseaeseeesiaeseeeeneees 12-23 12.7.1 Intel 450NX PClset Ringback Specification oo... cceceeeececee eter eeeeeeeeeeeeeecneeeeeeeseeetaeseeeeeneeee 12-23 12.7.2 Intel 450NX PClset Undershoot Specification oo... ee eecceecceeseeceeeeeeeeeeeeeeeeesaeeeeeeeeneesaeeeeeenaees 12-25 12.7.3 Skew ReEQuireMents o.oo... eeeeeeeceeesneeeeeneeeeeee teen ee eeeaeeeseeeeeesaeeeeeaaeeesneeeesaeeeseaeessneeeesieeeeneareeenaaes 12-25 12.8 Intek 450NX PClset Thermal Specifications oo... ceececccesseeeseeceeeeeeeeeeeeeeaeeeeeeseeesaeeeeeeseeseaeeeneesaeeeeeeeees 12-26 12.8.1 Thermal Solution Performance oui... ceeceeecceeteeeeeeeeeeeeceeeeeeeeeeeeaeeeeeeseeeeaaeeeeesaeseeeeeneesiaaeeeeeneees 12-26 12.9 Mechanical Specifications 2... eeceeccccceeeeeceeeeeceeeeeecneeeeaeeeeeecaeeeaaeeneeecaeeseaeeeeeeaeseaeesneeeseaeseneesiaeseeeeneees 12-27 12.9.1 Pin Lists Sorted by Pin NUMbEP: ooo... eeeeeeen ee eeeneeeeeeeeeesaeeeeeaaeeesaeeeeesaeeeneaaeessneeeeseeeeneeeeennaes 12-27 12.9.2 Pin Lists Sorted by Signal ....... eee eeeeseeeseeeeernee sees ee eeeeeeeeeeeeeaaeeeaeeeeeeaeeeesaaeessneeeesneeeeneneeenaaes 12-54 12.9.3 Package information oo... eeecccceeeeeeeeeeccceteee cee eeeeeseeeeeaaeeeaaeseeeeceeseeeeneesaeseaeesneeesaeseneetiaeseieeeneees 12-83 12.9.3.1 324 BGA Package Information oo... ..eeeeeccceeeeeeeeeeeeeeeeeeeaeeeaeeeeeesaeeseaeeeeetiaeeseeeneees 12-83 12.9.3.2 540 PBGA Package Information ........ecceeccesseeeeeeceeeeeeeeeeeeesaeeeeeesneeesaaeeeneetaeeneeeneees 12-85 Intel 450NX PClset -V-CONTENTS -Vi- Intel 450NX PClsetIntroduction | 1 1.1 Overview The Intel 450NX PCIset provides an integrated Host-to-PCI bridge and memory controller optimized for multiprocessor systems and standard high-volume (SHV) servers based on the Pentium II Xeon processor variant of the P6 family. The Intel 450NX PClIset consists of four components: 82454NX PCI Expander Bridge (PXB), 82451NX Memory and I/O Bridge Controller (MIOC), 82452NX RAS/CAS Generator (RCG), and 82453NX Data Path Multiplexor (MUX). Figure 1-1 illustrates a typical SHV server system based on the Intel 450NX PClIset. The system bus interface supports up to 4 Pentium II Xeon processors at 100 MHz. An additional bus mastering agent such as a cluster bridge can be supported at reduced frequencies. Two dedicated PCI Expander Bridges (PXBs) can be connected via the Expander L2 L2 L2 L2 Cache Cache Cache Cache E x E x Pentium II Pentium I Pentium I Pentium I] Xeon Xeon Xeon Xeon processor processor processor processor Optional Cluster ; Bridge System Bus AGTL+ 100 MHz MD[71:0] MIOC third-party Memory controls Memory MA[13:0] Subsystem and /O 1 or 2 cards Controller ontro Expander Xt XO Buses PCI PC BMIDE HDDs Expander Expander Bridge Bridge PITX4E 1B 0 South Bridge Ld] 1A 0B A ee PCl Dowco Co oo Slots Foo Eo Go oo VO Coo Ooo Ooo APIC | | XCVR ee KBC BIOS 8042 4 PCI Buses Flash 32-bit, 33 MHz, 3.3v or 5v EPROM aa a Can link pairs into 64-bit bus Figure 1-1: Simplified Intel 450NX PClset System Block Diagram Intel 450NX PClset 1-41. Introduction 1.2 Bus. Each PXB provides two independent 32-bit, 33 MHz PCI buses, with an option to link the two buses into a single 64-bit, 33 MHz bus. The Intel 450NX PCIset memory subsystem supports one or two memory cards. Each card is comprised of an RCG, a DRAM array, and two MUxXs. The MIOC issues requests to the RCG components on each card to generate RAS#, CAS#, and WE# outputs to the DRAMs. The MUX components provide the datapath for the DRAM arrays. Up to 8 GB of memory in various configurations are supported. Other capabilities of the Intel 450NX PCIset include: Full Pentium II Xeon processor bus interface (36-bit address, 64-bit data) at 100 MHz. Support for two dedicated PCI expander bridges (PXBs) attached behind the system bus so as not to add additional electrical load to the system bus. Support for both internal and external system bus and I/O bus arbitration. Supporting Devices The Intel 450NX PClIset is designed to support the PIIX4E south bridge. The PITX4E is a highly integrated multi-functional component that supports the following capabilities: PCI Rev 2.1-compliant PCI-to-ISA Bridge with support for 33-MHz PCI operations e Enhanced DMA controller 8259 Compatible Programmable Interrupt Controller System Timer functions Integrated IDE controller with Ultra DMA/33 support Intel 450NX PClset Components MIOC Memory and I/O Bridge Controller The MIOC accepts access requests from the system bus and directs those accesses to memory or one of the PCI buses. The MIOC also accepts inbound requests from the PCI buses. The MIOC provides the data port and buffering for data transferred between the system bus, PXBs and memory. In addition, the MIOC generates the appropriate controls to the RCG and MUX components to control data transfer to and from the memory. PXB PCI Expander Bridge The PXB provides the interface to two independent 32-bit, 33 MHz Rev 2.1-compliant PCI buses. The PXB is both a master and target on each PCI bus. RCG _ RAS/CAS Generator The RCG is responsible for accepting memory requests from the MIOC and converting these into the specific signals and timings required by the DRAM. Each RCG controls up to four banks of memory. MUX Data Path Multiplexor. The MUX provides the multiplexing and staging required to support memory interleaving between the DRAMs and the MIOC. Each MUX provides the data path for one-half of a Qword for each of four interleaves. Intel 450NX PClset1.3 1.3 Intek 450NX PClset Feature Summary Intel 450NX PClset Feature Summary System Bus Support Fully supports the Pentium IT Xeon processor bus protocol at bus frequencies up to 100 MHz. Functionally and electrically compatible with the original and Pentium II P6 family processor buses. Fully supports 4-way multiprocessing, with performance scaling to 3.5x that of a uni- processor system. Full 36-bit address decode and drive capability. Full 64-bit data bus (32-bit data bus mode is not supported). Parity protection on address and control signals, ECC protection on data signals. 8-deep in-order queue; 24-deep memory request queue; 2-deep outbound read-request queue per PCI bus; 6-deep outbound write-posting queue per PCI bus. AGTL+ bus driver technology. Intel 450NX PClIset adds only one load to the system bus. Intel 450GX PClset-compatible third-party request/grant and control signals, allowing cluster bridges to be placed on the system bus. DRAM Interface Support Memory technologies supported are 16- and 64-Mbit, 60nsec and 50nsec 3.3v EDO DRAM devices. Supports from 32 MB to 8 GB of memory, in 64 MB increments after the initial 32 MB. Supports 4-way interleaved operation, with 2-way interleave supported in the first bank of card 0 to permit entry-level systems with minimal memory. Supports memory address bit permuting (ABP) to obtain alternate row selection bits. Supports card-to-card interleaving to further distribute memory accesses across multiple banks of memory. Staggered CAS-before-RAS refresh. ECC with single-bit error correction and scrub-on-error in the memory. Extensive Host-to-Memory and PCI-to-Memory write data buffering. 1/0 Bridge Support Up to four independent 32-bit PCI ports (using two PXBs) - each supports up to 10 electrical loads (connectors count as loads). - each provides internal arbitration for up to 6 masters plus a south bridge on the compatibility PCI bus, or external arbitration. Synchronous operation to the system bus clock using a 3:1 system bus/PCI bus gearing ratio. - 3:1 ratio supports a 100 MHz system bus and 33.33 MHz PCI bus. - 3:1 ratio supports a 90 MHz system bus and 30 MHz PCI bus (or lower, depending on effect of 6th load). Parity protection on all PCI signals. Inbound read prefetches of up to 4 cache lines. Outbound write assembly of full/partial line writes. Data streaming support from PCI to DRAM. Intel 450NX PClset 1-31. Introduction 1.4 1-4 System Management Features Provides controlled access to the Intel Architecture System Management Mode (SMM) memory space (SM RAM). Test & Tuning Features Signal interconnectivity testing via boundary scan. Access to internal control and status registers via JTAG TAP port. I2C access is not provided in the PClset; however, error indicators are reported to pins which can be monitored and sampled using I2C capabilities if provided elsewhere in the system. System bus, memory and I/O performance counters with programmable events. Reliability/Availability/Serviceability (RAS) Features ECC coverage of system data bus and memory; parity coverage of system bus controls, PCI bus, and Expander bus. ECC bits can be corrupted via selective masking for diagnostics. Fault recording of the first two ECC errors. Each includes error type and syndrome. Memory ECC error logs include the effective address, allowing identification of the failing location. Error logs are not affected by reset, allowing recovery software to examine the logs. Packaging & Power Table 1-1 indicates the signal count, package and power for each component in the Intel 450NX PClIset. In a common high-end configuration, using two memory cards (each with one RCG and two MUX components), two PXBs and 3.3V supplies, the Intel 450NX PClIset would contribute approximately 47 watts. Table 1-1: Signals, Pins, Packaging and Power Chip | Signals | Package Footprint | Power! MIOC 348 | PLGA-5407 425mm] 13.2W PXB 7? | PLGA-5407 42.5 mm 7.8W RCG FS | BGA-324 27.0 mm 2.5W MUX 207 | BGA-324 27.0 mm 3.3 W 1. Assumes 3.3v supplies. 2. Requires heat sink. Intel 450NX PClsetSignal Descriptions | 2 2.1 This chapter provides a detailed description of all signals used in any component in the Intel 450NX PClset. Conventions The terms assertion and deassertion are used extensively when describing signals, to avoid confusion when working with a mix of active-high and active-low signals. The term assert, or assertion, indicates that the signal is active, independent of whether the active level is represented by a high or low voltage. The term deassert, or deassertion, indicates that the signal is inactive. The # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When # is not present after the signal name the signal is asserted when at the high voltage level. When discussing data values used inside the chip set, the logical value is used; ie., a data value described as "11016" would appear as "1101b on an active-high bus, and as "0010b" on an active-low bus. When discussing the assertion of a value on the actual pin, the physical value is used; i.e., asserting an active-low signal produces a "0" value on the pin. The following notations are used to describe the signal type: I Input pin oO Output pin Oo Bidirectional (input/output) pin OD Open drain output pin (other than AGTL+ signals) The signal description also includes the type of buffer used for the particular signal: AGTL+ Open drain AGTL+ interface. PCI PClI-compliant 3.3v /5v-tolerant interface LVTTL Low-voltage (3.3v) TTL-compatible signals. 2.5V 2.5v CMOS signals. Analog Typically a voltage reference or specialty power supply. Intel 450NX PClset 2-12. Signal Descriptions 2.2 2.2.1 Some signals or groups of signals have multiple versions. These signal groups may represent distinct but similar ports or interfaces, or may represent identical copies of the signal used to reduce loading effects. The following conventions are used: RR(A,B,C)XX expands to: RRAXX, RRBXX, and RRCXX RR(A,...,D)XX expands to: RRAXX, RRBXX, RRCXX, and RRDXX RRpXX, where p=A,B,C expands to: RRAXX, RRBXX, and RRCXX Typically, upper case groups (e.g., (A,B,C)) represent functionally similar but logically distinct signals; each signal provides an independent control, and may or may not be asserted at the same time as the other signals in the grouping. In contrast, lower case groups (e.g., (a,b,c)) typically represent identical duplicates of a common signal provided to reduce loading. Summary Figure 2-1 illustrates the partitioning of interfaces across the components in the Intel 450NX PClIset. The remainder of this section lists the signals and signal counts in each interface by component. The signal functions are described in subsequent sections. ! System Interface Memory MIOC Interface k (External) oO Expander O|~ Interface (2) 1 0 x \> Memory Interface (Internal) memory cards PXB #1 PXB #0 etn Tel 1A PCI Interfaces (2) PCI Interfaces (2) PCI Bus #0A is the Compatibility Bus Figure 2-1: Interface Summary: Partitioning Signal Summary, By Component The following tables provide summary lists of all signals in each component, sorted alphabetically within interface type. The signals are described in a later section. Intel 450NX PClset2.2.1.1 MIOC Signal List 2.2 Summary System Interface TSs A[35:3]# AGTL+ I/O | DEP[7:0]# AGTL+ I/O ADS# AGTL+ I/O | DRDY# AGTL+ I/O AERR# AGTL+ I/O | HIT# AGTL+ I AP[1 :0]# AGTL+ I/O | HITM# AGTL+ I BERR# AGTL+ I/O | INIT# 2.5V OD BINIT# AGTL+ I/O |LOCK# AGTL+ I BNR# AGTL+ I/O | REQ([4:0]# AGTL+ I/O BP[1 :0]# LVTTL I/OD | RP# AGTL+ I/O BPRI# AGTL+ I/O | RS[2:0]# AGTL+ I/O BREQ[O}# AGTL+ O RSP# AGTL+ I/O D[63:0]# AGTL+ I/O | TRDY# AGTL+ I/O DBSY# AGTL+ I/O DEFER# AGTL+ I/O Third-Party Agent Interface 4 lIOGNT# LVTTL I TPCTL[1:0] LVTTL I IOREQ# LVTTL O Memory Subsystem / External Interface 119 BANK[2:0]# AGTL+ O DVALID(a,b)# AGTL+ O CARD[1:0]# AGTL+ O MA[13:0]# AGTL+ O CMND[1:0]# AGTL+ O MD[71:0]# AGTL+ I/O CSTB# AGTL+ O MRESET# AGTL+ O DCMPLT(a,b)# AGTL+ I/O | PHIT(a,b)# AGTL+ I DOFF[1 :0]# AGTL+ O ROW# AGTL+ O DSEL[1 :0]# AGTL+ O RCMPLT(a,b)# AGTL+ I DSTBN[3:0]# AGTL+ I/O | RHIT(a,b)# AGTL+ I DSTBP[8:0]# AGTL+ I/O | WDEVT# AGTL+ O Expander Interface (two per MIOC: 0,1) 2x 33 X(0,1)ADS# AGTL+ I/O | X(0,1)HSTBP# AGTL+ O X(0,1)BE[1 :0]# AGTL+ I/O _ | X(0,1)PAR# AGTL+ I/O X(0,1)BLK# AGTL+ O X(0,1)RST# AGTL+ O X(0,1)CLK CMOS O X(0,1)RSTB# AGTL+ O X(0,1)CLKB CMOS O X(0,1)RSTFB# AGTL+ I X(0,1)CLKFB CMOS I X(0,1)XRTS# AGTL+ I X(0,1)D[15:0]# AGTL+ I/O | X(0,1)XSTBN# AGTL+ I X(0,1)HRTS# AGTL+ O X(0,1)XSTBP# AGTL+ I X(0,1)HSTBN# AGTL+ O Common Support Signals 16 CRES[1:0] Analog I TMS 2.5V I TCK 2.5V I TRST# 2.5V I TDI 2.5V I VCCA (3) Analog I TDO 2.5V OD ___|VREF (6) Analog I Intel 450NX PClset 2-32. Signal Descriptions 2.2.1.2 Component-Specific Support Signals S CRESET# LVTTL O PWRGD LVTTL I ERR[1 :0]# LVTTL I/OD |PWRGDB LVTTL O HCLKIN 2.5V I RESET# AGTL+ I/O INTREQ# LVTTL O SMIACT# LVTTL O TOTAL SIGNALS S48 PXB Signal List PCI Bus Interface (2 per PXB: A,B) 2x 61 P(A,B)AD[31 :0] PCI Y/O P(A,B)PAR PCI Y/O P(A,B)C/BE[3:0]# PCI Y/O P(A,B)PERR# PCI Y/O P(A,B)CLKFB LVTTL I P(A,B)REQ[5:0]# PCI I P(A,B)CLK LVTTL O P(A,B)RST# PCI O P(A,B)DEVSEL# PCI Y/O P(A,B)SERR# PCI OD P(A,B)FRAME# PCI Y/O P(A,B)STOP# PCI Y/O P(A,B)GNT[5:0]# PCI O P(A,B)TRDY# PCI Y/O P(A, B)IRDY# PCI Y/O P(A,B)XARB# PCI I P(A,B)LOCK# PCI Y/O PCI Bus Interface / Non-Duplicated (one set per PXB) 6 ACK64# PCI Y/O PHLDA# PCI O MODE64# PCI I REQ64# PCI Vo PHOLD# PCI I WSC# PCI O Expander Interface (one per PXB) 30 XADS# AGTL+ I/O | XHSTBP# AGTL+ I XBE[1 :0]# AGTL+ I/O | XIB AGTL+ O XBLK# AGTL+ I XPAR# AGTL+ I/O XCLK CMOS I XRST# AGTL+ I XD[15:0]# AGTL+ I/O | XXRTS# AGTL+ O XHRTS# AGTL+ I XXSTBN# AGTL+ O XHSTBN# AGTL+ I XXSTBP# AGTL+ O Common Support Signals 12 CRES[1:0] Analog I TMS 2.5V I TCK 2.5V I TRST# 2.5V I TDI 2.5V I VCCA (3) Analog I TDO 2.5V OD | VREF (2) Analog I Component-Specific Support Signals INTRQ(A,B)# PCI OD_ | PIIXOK# LVTTL I P(A,B)MON[1 :0]# LVTTL I/OD |PWRGD LVTTL I TOTAL SIGNALS vy? Intel 450NX PClset2.2.1.3 2.2.1.4 RCG Signal List 2.2 Summary Memory Subsystem / External Interface 27 BANK[2:0]# AGTL+ I MRESET# AGTL+ I CARD# AGTL+ I PHIT# AGTL+ O CMND[1:0]# AGTL+ I RCMPLT# AGTL+ O CSTB# AGTL+ I RHIT# AGTL+ O GRCMPLT# AGTL+ I/O ROW# AGTL+ I MA[13:0]# AGTL+ I Memory Subsystem / Internal Interface 123 ADDR(A,B,C,D)[13:0] LVTTL O LRD# AGTL+ O AVWP# AGTL+ O RAS(A,B,C,D)(a,b,c,d)[1:0]# LVTTL O CAS(A,B,C,D)(a,b,c,d)[1:0]# LVTTL O WDME# AGTL+ O LDSTB# AGTL+ O WE(A,B,C,D)(a,b)# LVTTL O Common Support Signals 10 CRES[1:0] Analog I TMS 2.5V I TCK 2.5V I TRST# 2.5V I TDI 2.5V I VCCA Analog I TDO 2.5V OD | VREF (2) Analog I Component-Specific Support Signals & BANKID# LVTTL I DR50T# LVTTL I DR5OH# LVTTL I HCLKIN 2.5V I TOTAL SIGNALS VFS MUX Signal List Memory Subsystem / External Interface 48 DCMPLT# AGTL+ I/O DVALID# AGTL+ I DOFF[1 :0]# AGTL+ I GDCMPLT# AGTL+ I/O DSEL# AGTL+ I MD[85:0]# AGTL+ I/O DSTBP[1 :0]# AGTL+ I/O MRESET# AGTL+ I DSTBN[1 :0]# AGTL+ I/O |WDEVT# AGTL+ I Memory Subsystem / Internal Interface 148 AVWP# AGTL+ I Q1D[35:0] LVTTL I/O LDSTB# AGTL+ I Q2D[35:0] LVTTL I/O LRD# AGTL+ I Q3D[35:0] LVTTL Io QOD[35:0] LVTTL 1/0 | WDME# AGTL+ I Common Support Signals 10 CRES[1:0] Analog I TMS 2.5V I TCK 2.5V I TRST# 2.5V I TDI 2.5V I VCCA Analog I TDO 2.5V OD | VREF (2) Analog I Component-Specific Support Signals 4 HCLKIN 2.5V I TOTAL SIGNALS soy Intel 450NX PClset 2-52. Signal Descriptions 2.3 System Interface The MIOC provides the Intel 450NX PClsets sole connection to the system bus. This section describes the Intel 450NX PClset-specific uses of these signals. 2.3.1. System / MIOC Interface A[85:3]# ADS# AERR# AP[1 :O}# BERR# BINIT# BNR# BP[1 :O}# BPRI# BREQ(O}# 2-6 Address Bus AGTL+ I/O A[35:3]# connect to the system address bus. During processor cycles the A[35:3]# are inputs. The MIOC drives A[35:3]# during snoop cycles on behalf of PCI initiators. The address bus is inverted on the system bus. Address Strobe AGTL+ I/O The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. Address Parity Error AGTL+ I/O AERR# is asserted by any agent that detects an address parity error. Address Parity AGTL+ I/O Parity protection on the address bus. AP#[1] covers A#[35:24], and AP#[0] covers A#[23:3]. They are valid on both cycles of the request. Bus Error AGTL+ I/O This signal is asserted by any agent that observes an unrecoverable bus protocol violation. Bus Initialization AGTL+ I/O BINIT# is asserted to re-initialize the bus state machines. The MIOC will terminate any ongoing PCI transaction and reset its inbound and outbound queues. No configuration registers or error logging registers are affected. Block Next Request AGTL+ I/O Used to block the current request bus owner from issuing a new request. Performance Monitoring LVTTL I/OD In normal operation, the MIOC can be configured to drive performance monitoring data out of either of these pins, similar in function to the BP pins provided on the processors. Priority Agent Bus Request AGTL+ O The MIOC is the only Priority Agent on the system bus. It asserts this signal to obtain ownership of the address bus. BPRI# has priority over symmetric bus requests. Symmetric Agent Bus Request AGTL+ O This signal is asserted by the MIOC when RESET# is asserted, to select the boot processor. It is deasserted 2 host clocks after RESET# is deasserted. Intel 450NX PClsetD[63:0]# DBSY# DEP[7:0}# DEFER# DRDY# HIT# HITM# INIT# LOCK# REQ(4:0]# RP# RS[2:0]# 2.3 System Interface Data AGTL+ I/O These signals are connected to the system data bus. The data signals are inverted on the system bus. Data Bus Busy AGTL+ I/O Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Data Bus ECC/Parity AGTL+4 I/O These signals provide parity or ECC for the D#[63:0] signals. The MIOC only provides ECC. Defer AGTL+ I/O DEFER# is driven by the addressed agent to indicate that the transaction cannot be guaranteed to be globally observed. Data Ready AGTL+ I/O Asserted for each cycle that valid data is transferred. Hit AGTL+ I The MIOC never asserts HIT#; it has no cache, and never snoop stalls. Hit Modified AGTL+ I The MIOC never asserts HITM#; it has no cache, and never snoop stalls. Soft Reset 2.5V OD INIT# may be asserted to request a soft reset of the processors. During a system hard reset, the INIT# signal may be optionally asserted to cause the processors to initiate their BIST. The INIT# signal is not asserted during power-good reset. Lock AGTL+ I All system bus cycles sampled with the assertion of LOCK# and ADS#, until the negation of LOCK#, must be atomic; ie., no PCI activity to DRAM is allowed and the locked cycle must be translated to PCI if targeted for the PCI bus. Request Command AGTL+ I/O Asserted during both clocks of a request phase. In the first clock, the signals define the transaction type to a level which is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type. Request Parity AGTL+ I/O Even parity protection on ADS# and REQ[4:0]#. It is valid on both cycles of the request. Response Signals AGTL+ I/O Indicate response type as shown below: 000 Idle state 100 Hard failure 001 Retry 101. No Data 010 Deferred 110 Implicit writeback 011 reserved 111 Normal Data Intel 450NX PClset 2-72. Signal Descriptions 2.3.2 2.4 2.4.1 RSP# TRDY# Response Parity Signal AGTL+ I/O Parity protection on RS[2:0]#. Target Ready AGTL+ I/O Indicates that the target of the system transaction is able to enter the data transfer phase. Third-Party Agent / MIOC Interface The following signals provide support for an additional non-processor, third-party agent (TPA) on the system bus. Such agents may need priority access to the system bus itself, or may need to intervene in transactions between the processors and the Intel 450NX PClset. lIOGNT# IOREQ# TPCTL[1:0] I/O Grant LVTTLI The IOGNT# signal has two modes: Internal Arbitration Mode and External Arbitration Mode, selected by a bit in the MIOCs CONFIG register. In Internal Arbitration Mode IOGNT# is an input from another bridge device which is requesting ownership of the BPRI# signal. In external arbitration mode, this bridge requests BPRI# ownership from an external bridge arbiter. |IOGNT# should be asserted by the external arbiter when this MIOC has been granted ownership of the BPRI# signal. I/O Request LVTTL O The IOREQ# signal has two modes: Internal Arbitration Mode and External Arbitration Mode, selected by a bit in the MIOCs CONFIG register. In Internal Arbitration Mode IOREQ# is the grant to another bridge device that is making a request for ownership of the BPRI# signal. In external arbitration mode this signal is asserted to request ownership of the BPRI# signal. Third Party Control LVTTL I These signals allow an agent participating in transactions between the Intel 450NX PClIset and another bus agent as a third-party to control the responses generated by the Intel 450NX PClIset. 00 Accept The MIOC will accept the request and provide the normal response. O01 reserved 10 Retry The MIOC will generate a RETRY response. 11 Defer The MIOC will generate a DEFERRED response. PCI Interface Primary Bus There are two primary PCI buses per PXB, identified as the a bus and the b bus groups. Each signal name includes a p, indicating the PCI bus port; p= Aor B. Intel 450NX PClsetPpAD[31 :0] PpC/BE[3:0]# PpCLK PpCLKFB PpDEVSEL# PpFRAME# PpIRDY# PpPAR PpRST# PpPERR# PpLOCK# 2.4 PCI Interface PCI Address/Data PCI I/O PCI Address and Data signals are multiplexed on this bus. The physical byte address is output during the address phase and the data follows in the subsequent data phase(s). Command/Byte Enable PCI I/O PCI Bus Command and Byte Enable signals are multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/ BE[3:0]# are used as byte enables. PCI Clock LVTTL O This signal is an output with a derived frequency equal to 1/3 of the system bus frequency. PCI Clock Feedback LVTTL I This signal is connected to the output of a low skew PCI clock buffer tree. It is used to synchronize the PCI clock driven from PpCLK to the clock used for the internal PCI logic. Device Select PCI I/O DEVSEL+# is driven by the device that has decoded its address as the target of the current access. Frame PCI I/O The PXB asserts FRAME# to indicate the start of a bus transaction. While FRAME# is asserted, data transfers continue. When FRAME# is negated, the transaction is in the final data phase. FRAME# is an input when the PXB acts as a PCI target. Initiator Ready PCI I/O This signal is asserted by a master to indicate its ability to complete the current data transfer. IRDY# is an output when the PXB acts as a PCI initiator and an input when the PXB acts as a PCI target. Parity PCI I/O PAR is driven by the PXB when it acts as a PCI initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the PXB when it acts as a PCI target during each data phase of a PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#. PCI Reset PCI O PCI Bus Reset forces the PCI interfaces of each device to a known state. The PXB generates a minimum 1 ms pulse on RST#. PCI Parity Error PCI I/O Pulsed by an agent receiving data with bad parity one clock after PAR is asserted. The PXB will generate PERR# active if it detects a parity error on the PCI bus and the PERR# Enable bit in the PCICMD register is set. Lock PCI I/O LOCK# indicates an exclusive bus operation and may require multiple transactions to complete. It is possible for different agents to use the PCI Bus while a single initiator retains ownership of the LOCK# signal. Intel 450NX PClset 2-92. Signal Descriptions 2.4.2 2.4.3 2-10 PpTRDY# Target Ready PCI I/O The assertion of TRDY# indicates the target agents ability to complete the current data phase of the transaction. TRDY# is an input when the PXB acts as a PCI master and an output when the PXB acts as a PCI target. PpSERR# System Error PCI OD The PXB asserts this signal to indicate an error condition. PpSTOP# Stop PCI I/O STOP# is used for disconnect, retry, and abort sequences on the PCI Bus. It is an input when the PXB acts as a PCI initiator and an output when the PXB acts as a PCI target. 64-bit Access Support These signals are used only in 64-bit bus mode. There is one set per PXB. ACK64# 64-bit Access Acknowledge PCI I/O This signal is driven by the accessed target to indicate its willingness to transfer 64-bit data. When the PXB is the bus target, this signal is an output. If asserted, the PXB will transfer 64-bit data; otherwise, the PXB will transfer 32-bit data. When the PXB is the bus master, this signal is an input. MODE64# 64-bit Bus Mode PCII A strapping pin that selects whether the pair of 32-bit PCI buses are used as two independent 32-bit buses, or linked together as a single 64-bit bus. If asserted, the buses are used as a single 64-bit bus: the 32-bit data bus of the PCI B port becomes the high Dword of the 64-bit bus. An internal pull-up insures that the pin appears deasserted if left unconnected. REQ64# 64-bit Access Request PCI I/O This signal is driven by the bus master to indicate its desire to transfer 64-bit data. When the PXB is the bus master, this signal is an output. The PXB will assert this signal if it can transfer 64-bit data. When the PXB is the bus target, this signal is an input. The following 64-bit extension signals are mapped from the existing B port signals: AD[63:32] from PBAD[31:0] C/BE[7:4] from PBC/BE[3:0] PAR64 from PBPAR All other controls and status signals in 64-bit operation are taken from the Bus A signal set. Unused pins on the B side should be tied inactive. Internal vs. External Arbitration Each PXB supports both internal arbitration and external arbitration, independently for each PCI bus. While in internal arbitration mode, six pairs of request/grant signals are used to support up to six PCI masters on the bus (plus the PXB itself, and the PIIX4E south bridge on Intel 450NX PClset2.4.4 2.4 PCI Interface the compatibility PCI bus). While in external arbitration mode, only one pair (#0) are used, and have different meanings. Each signal name includes a p, indicating the PCI bus port; p= Aor B. PpXARB# External Arbitration Mode PCII A strapping pin, sampled at the trailing edge of reset. If asserted, the PCI bus is controlled using an external arbiter. If deasserted, the PCI bus is controlled using the PXBs internal arbiter. An internal pull-up insures that the pin appears deasserted if left unconnected. Internal Arbitration Mode (per PCI bus, p=A,B) PpREQ[5:0]# PCI Bus Request PCI I Six independent PCI bus request signals used by the internal PCI arbiter for PCI initiator arbitration. Unused signals should be strapped inactive. PpGNT[5:0]# PCI Grant PCI O Six independent PCI bus grant signals used by the internal PCI arbiter for PCI initiator arbitration. External Arbitration Mode (per PCI bus, p=A,B) When operating in external arbitration mode, REQ[5:1]# and GNT[5:1]# signals are not used. The REQ[0]# signal is redefined as HGNT#, and the GNT[0]# signal is redefined as HREQ#. PpHREQ# Host Request PCI O Generated by the PXB to the external PCI arbiter to request control of the PCI bus to perform a Host-PCI access. PpHGNT# Host Grant PCI I Generated by the external PCI arbiter to grant the PCI bus to the PXB to perform a Host-PCI transfer. PIIX4E Interface The compatibility PCI bus (PCI Bus 0A) supports a PIIX4E south bridge, and requires several additional handshake signals, provided by the PXB. They are active only for Bus 0A. NOTE These signals, and the associated PHOLDA# and WSC# protocols, cannot be used with the PXB in external arbiter mode. PHOLD# PCI Hold PCI I This signal is the PILX4Es request for the PCI bus. PHLDA# PCI Hold Acknowledge PCI O This signal is driven by the PXB to grant PCI bus ownership to the PIDX4E. Intel 450NX PClset 2-142. Signal Descriptions WSC# Write Snoop Complete PCI O This signal is asserted active to indicate completion of snoop activity on the system bus on the behalf of the last PCI-DRAM write transaction, and that it is safe to send the APIC interrupt message. 2.5 Memory Subsystem Interface The memory subsystem is comprised of the DRAM arrays and the associated RCGs and MUxs. There is the external interface (between the MIOC and the memory subsystem), and the internal interface (between the various parts of the memory subsystem.) 2.5.1 External Interface BANK[2:0]# CARD[1:0]# CMND[1:0]# CSTB# MA[13:0}# ROW# GRCMPLT# 2-12 Bank Selects AGTL+ MIOC > RCG These signals indicate which memory bank will service this access. BANK[2:0]# are connected to all RCGs on both memory cards. Card Selects AGTL+ MIOC-> RCG These signals indicate which memory card will service this access. Valid patterns in the Intel 450NX PClset are 01b=cardO and 10b=card1, allowing CARD[0]# to be connected only to card 0 and CARD[1]# to be connected only to card 1. Each CARD signal is connected to all RCGs on the given memory card. Access Command AGTL+ MIOC > RCG These signals encode the command of the current operation. CMND[1:0]# are connected to all RCGs on both memory cards. Command Strobe AGTL+ MIOC-> RCG This strobe, when activated, indicates the initiation of an access. This signal is connected to all RCGs on both memory cards. Memory Address bus AGTL+ MIOC-> RCG These signals define the address of the location to be accessed in the DRAM., and are driven on two successive clock cycles to provide up to 28 bits of effective memory address. The signals are connected to all RCGs on both memory cards. Row Selects AGTL+ MIOC > RCG These signals indicate which row in the selected memory bank will service this access. These signals are connected to all RCGs on both memory cards. Global RCMPLT# AGTL+4, I/O, all RCGs A global version of the RCMPLT(a,b)# signals, asserted coincident with RCMPLT#, and by the same agent. Whereas each RCMPLT# signal connects the RCGs on one card with the MIOC, the GRCMPLT# signal connects the Intel 450NX PClsetMRESET# RCMPLTa# RCMPLTb# PHIT(a,b)# RHIT(a,b)# DSTBP[3:0]# DSTBNI3:0]# MD[71:36]# MD[35:00]# DCMPLTa# DCMPLTb# DOFFI1 :O]# 2.5 Memory Subsystem Interface RCGs across both cards while excluding the MIOC. This allows all RCGs to monitor each request completion without placing undue loading on the RCMPLT# signals. Memory Subsystem Reset AGTL+ MIOC-> RCG/MUX This signal represents a hard reset of the memory subsystem. It is asserted following PWRGD or upon the MIOC issuing a processor RESET due to software invocation. Request Complete AGTL+ RCG> MIOC This signal, which is driven by the currently active RCG, indicates the completion of a request into the memory array. Typically the a signal connects the MIOC and all RCGs on Card #0, while the b signal connects the MIOC and all RCGs on Card #1. Page and Row Hit Status AGTL+ RCG-~ MIOC These signals indicate what resource, if any, delayed the initiation of a read. Typically the a signal connects the MIOC and all RCGs on Card #0, while the b signal connects the MIOC and all RCGs on Card #1. Data Strobes AGTL+ MUX MIOC This set of four signal-pairs are strobes which qualify the data transferred between the MUX and MIOC. Each strobe pair qualifies 18 bits (two bytes and two check bits), as follows: DSTB[0]# qualifies MD[17:00]#. DSTB[2]# qualifies MD[53:36]#. DSTB[1]# qualifies MD[35:1 8]#. DSTB[3]# qualifies MD[71:54]#. In a 4:1 interleaved system, with 2 MUXs per card, DSTB[1:0]# strobes the low MUX and DSTB[3:2]# strobes the high MUX. Ina 2:1 interleaved system, with only a single MUX per card, DSTB[1:0]# strobes the MUX, and DSTB[3:2]# is not used. Memory Data AGTL+ MUX MIOC These signals are connected to the external datapath of the MUXs. Each MUX provides 36 bits of the 72-bit datapath to the MIOC. AGTL+ MUX MIOC/MUX Data Transfer Complete MIOC+>MUXs This signal is driven by the source of the data transfer: the MIOC for writes, and the MUX for reads. DCMPLT# active indicates that the data transfer is complete. Typically the a signal connects the MIOC and all MUXs on Card #0, while the b signal connects the MIOC and all MUXs on Card #1. Data Offset AGTL+ MIOC-> MUX These two bits, when qualified by the DVALID# signal, define the initial Qword access order for the data transfer. The result is that the critical chunk is accessed first and the remaining chunks are accessed in Intel Toggle order. Intel 450NX PClset 2-132. Signal Descriptions 2.5.2 2.5.2.1 2-14 DSEL# DVALIDa# DVALIDb# GDCMPLT# WDEVT# Data Card Select AGTL+ MIOC> MUX This signal, when qualified by the DVALID# signal, selects which card the memory transfer is coming from or destined towards. Each memory card uses a single DSEL# input, sent to each MUX on the card. The MIOC provides two DSEL# outputs (DSEL[1 :0]#), one sent to each card. Data Transfer Complete AGTL+ MIOC-> MUX This signal indicates that the DSEL[1:0]#, DOFF[1:0]#, and WDEVT# signals are valid. Typically the a signal connects the MIOC and all MUXs on Card #0, while the b signal connects the MIOC and all MUXs on Card #1. Global DCMPLT# AGTL+, I/O, all MUXs A global version of the DCMPLT(a,b)# signals, asserted coincident with DCMPLT#, and by the same agent. Whereas each DCOMPLT# signal connects the MUXs on one card with the MIOC, the GDCMPLT# signal connects the MUxs across both cards while excluding the MIOC. This allows all MUXs to monitor each data completion without placing undue loading on the DCMPLT# signals. Write Data Event AGTL+ MIOC> MUX This signal, when qualified by the DVALID# signal, indicates the type of data transfer command. If asserted, the command represents a write data transfer. If deasserted, the command represents a read data transfer. Internal Interface RCG / DRAM Interface Each RCG provides four sets of signals to drive four banks in the DRAM array. In each of the following signal names, the "B" indicates a set of signals per bank. Each RCG controls four banks; therefore B =A, B,C or D. CASB(a,b,c,d)[1 :0]# ADDRB[13:0] Column Address Strobes LVTTL RCG~+ DRAM These signals are used to latch the column address into the DRAMs. The a, bo, c and d versions are duplicates for load reduction. DRAM Address LVTTL RCG> DRAM ADDR is used to provide the multiplexed row and column address to DRAM. RASB(a,b,c,d)[1 :O]# WEB(a,b)# Row Address Strobe LVTTL RCG~+ DRAM The RAS signals are used to latch the row address into the DRAMs. Each signal is used to select one DRAM row. The 1:0 signals indicate which row within the bank. The a, b, c and d versions are duplicates for load reduction. Write Enable Signal LVTTL RCG> DRAM WE# is asserted during writes to main memory. The a and b versions are duplicates for load reduction. Intel 450NX PClset2.5.2.2 2.5.2.3 2.6 2.6 Expander Interface DRAM / MUX Interface QOD[35:0] Q1D[35:0] Q2D[35:0] Q3D[35:0] Memory Data, Interleave 0 LVTTL DRAMs MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave zero. Memory Data, Interleave 1 LVTTL DRAMs MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave one. Memory Data, Interleave 2 LVTTL DRAMs MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave two. Memory Data, Interleave 3 LVTTL DRAMs MUX These signals are connected to the output of the DRAMs. This is one-half of a Quad-word and is connected to interleave three. RCG / MUX Interface AVWP# LDSTB# LRD# WDME# Advance MUX Write Path Pointers AGTL+ RCG- MUX This signal is activated by an RCG after performing a memory write. Load Data Strobe AGTL+ RCG> MUX This signal controls when read data is latched from the DRAM data bus. Load Read Data AGTL+ RCG> MUX This signal indicates when read data is ready to load from the DRAMs. Write Data to Memory Enable AGTL+ RCG- MUX This signal enables the MUXes to drive write data to the DRAMs. Expander Interface The MIOC component has two Expander interfaces, one for each of the two PXBs supported by Intel 450NX PClIset. These two high speed, low latency interfaces are identified as the XO bus and the X1 bus groups. Each signal name includes a p, indicating the Expander port. On the MIOC, p = 0 or 1, designating one of the two interfaces. On the PXB, p is not used. XpADS# XpBE[1 :O}# Address / Data Strobe. AGTL+ MIOC<e PXB Bidirectional signal asserted by the sending agent during data transmission. Byte Enables. AGTL+ MIOCs PXB Bidirectional signals indicating valid bytes during the data phases of a transmission. Intel 450NX PClset 2-152. Signal Descriptions 2-16 XpD[15:0]# XpHATS# XpHSTBP# XpHSTBN# XpPAR# XpXRTS# XpXSTBP# XpXSTBN# Support Signals XpBLK XpCLK XpCLKB XpCLKFB XpIB XpRST# Datapath AGTL+ MIOC<s PXB This bidirectional datapath is used to transfer addresses and data between the MIOC and the PCI Expander. Host Request to Send. AGTL+ MIOC-> PXB Request to use the bidirectional Expander bus sent from MIOC to PXB, synchronous to HCLKIN. Host Strobes AGTL+ MIOC-> PXB This pair of opposite-phase strobes are used by the PXB to latch and synchronize incoming data. Bus Parity. AGTL+ MIOCs PXB Bidirectional signal indicating even parity across XD[15:0] and XBE[1:0]. Expander Request to Send. AGTL+ PXB> MIOC Request to use the bidirectional Expander bus sent from PXB to MIOC, synchronous to HCLKIN. Expander Strobes AGTL+ PXB> MIOC This pair of opposite-phase strobes are used by the MIOC to latch and synchronize incoming data. Block Counters. AGTL+ MIOC-> PXB This signal is asserted when the Performance Counter Master Enable bit in the MIOCs CONFIG register is set, and is used to affect a nearly simultaneous stop/start of the performance counters across both the MIOC and all PXBs. Host Clock. CMOS MIOC-> PXB This is the primary clock source provided to the PXB, analogous to HCLKIN for the MIOC, RCG and MUX. Inside the PXB, it is divided by 3 to produce a PCI clock output at 33.33 MHz from an HCLKIN of 100 MHz. Host Clock, 2nd Version. CMOS MIOC- ext This is a duplicate of the XpCLK signal, to be used in maintaining PLL synchronization in the MIOC. See XpCLKFB below. Host Clock, Feedback. CMOS ext> MIOC This signal is a length-matched copy of the XpCLK signal sent to the PXB, used to maintain PLL synchronization in the MIOC. The XpCLKB signal is length-matched to the XpCLKs path to the PXB, then returned to the MIOC as the XpCLKFB input. Driving Inbound. AGTL+ PXB- ext This active-high signal is asserted when the PXB is driving data over the Expander bus. This pin is not connected to the MIOC. PXB Reset. AGTL+ MIOC PXB This signal issues a hard reset of the PXB, including the dependent PCI buses. Intel 450NX PClset2.7 2.7.1 2.7.2 XpRSTB# XpRSTFB# 2.7 Common Support Signals PXB Reset, 2nd Version. AGTL+ MIOC-> ext This is a duplicate of the XpRST# signal, to be used in maintaining PLL synchronization in the MIOC. See XpRSTFB# below. PXB Reset, Feedback. AGTL+ ext> MIOC The XpRSTB# signal is length-matched to the XpRST#s path to the PXB, then returned to the MIOC as the XpRSTFB# input. Common Support Signals JTAG Interface All four components in the Intel 450NX PCIset have a JTAG Test Access Port (TAP) to allow access to internal registers and perform boundary scan. Each interface is identical. TCK TDI TDO TMS TRST# Test Clock 2.5V I Test Clock is used to clock state information and data into and out of the device during boundary scan. Test Data Input 2.5V I Test Input is used to serially shift data and instructions into the TAP. Test Output 2.5V OD Test Output is used to shift data out of the device. Test Mode Select 2.5V I Test Mode Select is used to control the state of the TAP controller. Test Reset 2.5V I Test Reset is used to reset the TAP controller logic. Reference Signals All four components have the following support signals to provide voltage references or compensation for the AGTL+ interfaces or the PLL circuitry. CRES[1:0] VCCA (n) I/O Buffer Compensation Resistor Terminals Analog I For correct component operation an external 768 ohm resistor must be connected between CRES1 and CRESO. This resistor should have a minimum precision of 1%. PLL Analog Voltage Analog | This pin is an independent power supply for a PLL. In normal operation, this pin provides power to the PLL, and requires special decoupling (refer to Electrical Characteristics). Intel 450NX PClset 2-172. Signal Descriptions VREF (n) AGTL+ Reference Voltage Analog | This is the reference voltage derived from the termination voltage to the pull- up resistors. The MIOC has 6 VREF pins, while the PXB, RCG and MUX each have 2 VREF pins. 2.8 Component-Specific Support Signals 2.8.1 MIOC CRESET# ERR[1:0]# HCLKIN INTREQ# PWRGD PWRGDB RESET# 2-18 Clock Selection Reset. LVTTLO This is a delayed version of the RESET# signal provided to the processors. This signal is asserted asynchronously along with RESET#, but is deasserted two system bus clocks following the deassertion of RESET#. Error Code LVTTLI/OD These pins reflect irrecoverable errors detectable by the Intel 450NX PClIset. 00 | No error 01 | PClIset Internal Error Expander Bus Parity 10 | Multi-Bit Memory Error | Multi-Bit Memory ECC error 11 | System Bus Error Address Parity, Request Parity, Protocol Violation, BERR, Multi-Bit Host ECC error Host Clock In 2.5V I This pin receives a buffered system clock. This is a single trace from the clock synthesizer to minimize clock skew. Interrupt Request LVTTL O This pin is asserted by the MIOC when an internal event occurs and sets a status flag, and that flag has been configured to request an interrupt. Power Good LVTTL I This pin should be connected to a 3.3v version of the systems power good indicator, and should be asserted only after all power supplies and clocks have reached their stable references and been stable for at least 1 msec. Buffered Power Good LVTTLO A buffered (but not synchronized) version of the PWRGD input, which is used to drive the PWRGD input on each PXB in the system. Reset AGTL+ I/O In normal operation, this signal is an output. The MIOC will reset the system bus either on power-up or when programmed through the Reset Control register. Intel 450NX PClset2.8.2 2.8.3 2.8.4 SMIACT# PXB INTRQ(A,B)# PAMON[1 :O}# PBMONT1 :O}# PIIXOK# PWRGD RCG BANKID# DR50H# DR50T# HCLKIN MUX HCLKIN 2.8 Component-Specific Support Signals SMI Active. LVTTLO This signal provides a visible indicator that the system has entered System Management Mode. Interrupt Requests PCI OD These pins are asserted by the PXB when an internal event occurs and sets a status flag, and that flag has been configured to request an interrupt. There is one pin for each side (A,B) of the PXB. The signals may be connected to the standard PCI bus interrupt request lines. Performance Monitors LVTTL I/OD These pins track the two performance monitoring counters associated with each PCI bus (a,b) in the PXB. PMON[O] tracks the PMD[0] counter while PMON|1] tracks the PMD[1] counter. PIIX Reset Complete. LVTTLI This signal is tied to the PIIXs CPURST output, and is used to detect when the PIIX completes its reset functions. Power Good LVTTL I This input should be driven from the MIOCs PWRGDB output. Bank Identifier LVTTLI This strapping pin should be tied high (deasserted), or have an external pullup. 50ns DRAM Here. LVTTLI This strapping pin selects between 60ns and 50ns DRAM timings for this RCG, Deasserted: 60ns timings will be used. Asserted: 50ns timings will be used. 50ns DRAM There. LVTTLI This strapping pin should match the DR50H# strapping pin described above. Host Clock In 2.5V I This pin receives a buffered system clock. Host Clock In 2.5V I This pin receives a buffered system clock. Intel 450NX PClset 2-192. Signal Descriptions 2-20 Intel 450NX PClsetRegister Descriptions | 3 3.1 3.2 3.2.1 The Intel 450NX PClIset internal registers (both I/O Mapped and Configuration registers) are accessible by the processor. Each MIOC, and each PCI bus in each PXB has an independent configuration space. This chapter provides detailed descriptions of each register. Access Restrictions Register Attributes Read Only Writes to this register have no effect. Read/Write | Data may be read from and written to this register. Selected bits in the register may be designated as "read-only"; such bits are not affected by data writes to the register. Read/Clear Data may be read from the register. A data write operates strictly as a clear: Sticky Data in this register remains valid and unchanged, during and following any reset except the power-good reset. I/O Mapped Registers The Intel 450NX PClIset contains two registers that reside in the processor I/O address space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. CONFIG_ADDRESS: Configuration Address Register I/O Address: CF8h [Dword] Size: 32 bits Default Value: | 00000000h Attribute: Read/Write The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended. Intel 450NX PClset 3-13. Register Descriptions 3.2.2 Bits Description 31 Configuration Enable (CFGE). When this bit is set to 1 accesses to PCI configuration space are enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled. 30:24 reserved (0) 23:16 Bus Number. The Bus Number field selects which PCI bus should receive the configuration cycle. The system bus and the compatibility PCI bus (PCI Bus 0A) are both accessed using Bus Number 0; which bus is accessed depends on the Device Number. 15:11 Device Number. This field selects one agent on the PCI bus selected by the Bus Number. On Bus Number 0, Device Numbers 0-15 are on the compatibility PCI bus (PCI Bus 0A), while Device Numbers 16-31 refer to devices on the system bus, including the Intel 450NX PClset itself and any Third Party Agents which use this configuration mechanism. No. Device No. Device No. Device No. Device 10h | MIOC 14h | PXB 1, Bus a}] 18h 1Ch | Third Party Agent 11h 15h | PXB 1, Bus b}] 19h 1Dh | Third Party Agent 12h | PXB 0, Bus a}] 16h 1Ah 1Eh | Third Party Agent 13h | PXB 0, Bus b]} 17h 1Bh 1Fh | n/a 10:8 Function Number. The 450NX PClIset devices are not multi-function devices, and therefore this field should always be "0" when accessing them. 7:2 Register Number. This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. 1:0 reserved (0) CONFIG_DATA: Configuration Data Register I/O Address: CFCh Size: 32 bits Default Value: | 00000000h Attribute: Read/Write The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Bits Description 31:0 Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1 any I/O reference that falls in the CONFIG_DATA I/O space will be mapped to configuration space using the contents of CONFIG_ADDRESS. Intel 450NX PClset3.3 MIOC Configuration Space Table 3-1: MIOC Configuration Space 1 CHKCON RC CONFIG ERRCMD ERRSTS BUFSIZ CVCR CVDR TOM LXGT LXGB HXGB HXGT MAR2 MAR1 MARO GAPEN MAR6 MARS MAR4 MARS IOAR IOABASE SMRAM MMBASE MMR1 MMRO MMR3 MMR2 IOR ISA 3.3 MIOC Configuration Space DBC 01 DBC 00 DBC 03 DBC 02 DBC 05 DBC 04 DBC 07 DBC 06 DBC 09 DBC 08 DBC 11 DBC 10 DBC 13 DBC 12 DBC 15 DBC 14 RCGP Reserved REFRESH MEA1 MEAO MEL1 MELO HEL1 HELO ECCMSK | ECCCMD ROUTEO TCAPO TCAP1 ROUTE1 TCAP2 TCAP3 BUSNO1 | SUBBO SUBAO | BUSNOO DEVMAP SUBB1 SUBA1 PMDO PMRO PMDO PMD1 PMR1 PMD1 PME1 PMEO Intel 450NX PClset 80h 84h 88h 8Ch 90h 94h 98h 9Ch AOh A4h A8h ACh Boh B4h B8h BCh Coh C4h C8h CCh DOh D4h D8h DCh E0h E4h E8h ECh FOh F4h F8h FCh 3-33. Register Descriptions 1. The first 64 bytes are predefined in the PCI Specification. All other locations are defined specifically for the component of interest. 3.3.1 3-4 Table 3-1 illustrates the MIOCs Configuration Space Map. Many of these registers affect both host-initiated transactions and PCI-initiated transactions, and are therefore duplicated in both the MIOC and PXB Configuration Spaces. It is softwares responsibility to ensure that both sets of registers are programmed consistently to achieve correct operation. BUFSIZ: Buffer Sizes Address Offset: 48-4Ah Size: 24 bits Default Value: 304310h Attribute: Read Only Bits Description 23:18 Inbound Write Transaction Capacity. Total number of inbound write transactions, per Expander Port, that can be accepted by the MIOC. Value=12. 17:12 Inbound Read Transaction Capacity. Total number of inbound read transactions, per Expander Port, that can be accepted by the MIOC. Value=4. 11:6 Inbound Write Data Buffer Capacity. Total number of data buffers, per Expander Port, available in the MIOC for use by inbound write transactions, in increments of 32 bytes. Value=12. 5:0 Inbound Read Data Buffer Capacity. Total number of data buffers, per Expander Port, available in the MIOC for use by inbound read transactions, in increments of 32 bytes. Value=16. Intel 450NX PClset3.3.2 3.3.3 3.3 MIOC Configuration Space BUSNO[1:0]: Lowest PCI Bus Number, per PXB Address Offset: DOh, D3h Size: 8 bits each Default Value: 00h each Attribute: Read/Write The MIOC supports two Expander Ports; each can support one PXB. PXB #0 is connected to Expander Port #0, and PXB #1 is connected to Expander Port #1. Each PXB supports one or two PCI buses, connected to PCI Ports A and B. The PCI bus connected to Port #0A must be the compatibility PCI bus from which a system boots. Three registers (BUSNO, SUBA and SUBB) define the bus hierarchy for each PXB. BUSNOJ[O] Holds the PCI-bus-number of the bus connected to PXB #0 Bus #A. This must be set to 0. SUBA[0] Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus #A. The PCI bus number for PXB #0 Bus #B is SUBA[0]+1. SUBB[0] Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus #B. This also represents the highest PCI-bus-number accessible from PXB #0. BUSNO[1] Holds the PCI-bus-number of the bus connected to PXB #1 Bus #A. SUBA[1] Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus #A. The PCI bus number for PXB #1 Bus #b is SUBA[1]+1. SUBB[1] Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus #B. This also represents the highest PCI-bus-number accessible from PXB #1 (and therefore the Intel 450NX PClIset). If PXB#1 is not in use, program this register to 0. If PXBi is operating in 64-bit bus mode, SUBB[i] must equal SUBA|I]. Bits Description 7:0 PCI Bus Number. NOTE Inactive PXBs should be disabled by writing the corresponding Reset Expander Port bit in the RC register and resetting the corresponding "Device present" bit in the DEVMAP register. CHKCON: Check Connection Address Offset: 43h Size: 8 bits Default Value: 10h Attribute: Read/Write Bits Description 7:6 reserved Intel 450NX PClset 3-53. Register Descriptions 3.3.4 3.3.5 3-6 5 Live Port #1 Flag. If set, the port is "live". Default=0. 4 Live Port #0 Flag. If set, the port is "live." Default=1. 3:2 reserved 1 Test Port #1 Enable. Setting this enable triggers the check connection protocol for port 1. Default=0. 0 Test Port #0 Enable. Setting this enable triggers the check connection protocol for port 0. Default=0. NOTE Setting both Test Port #1 Enable and Test Port #0 Enable simultaneously is prohibited, and will have unpredictable results, up to and including system hangs requiring a full system reset. Inactive PXBs should be disabled by writing the corresponding Reset Expander Port bit in the RC register. Transactions sent to inactive PXBs can result in system hangs. CLASS: Class Code Register Address Offset: 09 - OBh Size: 24 bits Default Value: 060000h Attribute: Read Only Bits Description 23:16 Base Class For the MIOC, this field is hardwired to 06h. 15:8 Sub-Class For the MIOC, this field is hardwired to 00h. 7:0 Register-Level Programming Interface For the MIOC this field is hardwired to 00h. CONFIG: Software-Defined Configuration Register Address Offset: 40-41h Size: 16 bits Default Value: 1000h Attribute: Read/Write Bits Description 15:13 reserved (0) Intel 450NX PClset12 11 10 3.3 MIOC Configuration Space Outbound Fairness Disable. When this bit is clear, Host-PCI writes and reads that receive a retry by the MIOC follow a fairness algorithm to guarantee that retried transactions receive first priority before new transactions. If set, Host-PCI writes and reads are serviced in the order first observed without regard to retry history. Default=1. Performance Counter Master Enable (PCME). This bit provides a mechanism to (nearly) simultaneously freeze or start the performance counters across both the MIOC and PXBs. If this bit is cleared the MIOCs and PXBs performance counters will not increment If set the MIOCs and PXBs performance counters resume normal operation. Default = 0. reserved (0) Third Party Support Disable If set, performance optimizations are enabled that may result in coherency violations in the presence of a third party agent. This bit should be clear for systems with TPAs. Default = 0. External Arbiter Enable. If set, access to the system bus is controlled by an external arbiter. If cleared, the MIOCs internal arbiter is used. Default=0. WC Write Post During I/O Bridge Access Enable (UWPE). This bit should be cleared for normal operation. Default=0. Outbound I/O Write Posting Enable. If set, Host-PCI I/O writes will be posted. If cleared, Host-PCI1/O writes will not be posted. In normal operation, this enable should be set. Default=0. Read-Around-Write Enable (RAWE). If RAWE is set, it enables the read-around-write capability for the MIOC and memory subsystem. If cleared, read accesses will not advance past any previously posted writes. In normal operation, this enable should be set. Default=0. ISA Expansion Aliasing Enable. If set, every I/O access with an address in the range x100-x3FFh, x500-x7FFh, x900- XBFF and xDOO-xFFFh is internally aliased to the range 0100-03FFh before any other address range checking is performed. This bit only affects routing, the unmasked address is passed to the PCI bus. Default=0. reserved (0) Card to Card Interleave Enable. If set, Host or PCI accesses to memory are distributed to both memory cards on a cache line granularity. This provides a performance enhancement for systems which utilize two memory cards. When this bit is clear, C2C interleaving is disabled. Default =0. Intel 450NX PClset 3-73. Register Descriptions 3.3.6 1:0 Memory Address Bit Permuting. The MIOC supports cache-line permuting across banks. This field controls the type of permuting used, as follows: 00b No permuting. 01b 2-way Permuting. 10b 4-way Permuting. 11b reserved Default=0. CVCR: Configuration Values Captured on Reset Address Offset: 4E-4Fh Size: 16 bits Default Value: 0000h Attribute: Read-Only This register captures the configuration values driven on A#[15:0] at the trailing edge of RESET#. This allows an external device to override the default values provided by the MIOC via its CVDR register. Bits Description 15:13 reserved (0) 12:11 APIC Cluster ID. Captured from A#[12:11]. Represents the APIC Cluster identifier. 10 reserved (0) 9 Enable BERR# Input. Captured from A#[9]. If set, the MIOC will observe the assertion of the BERR# input. Further details on BERR# processing may be found in the ERRCMD register. 8 Enable AERR# Input. Captured from A#[8]. If set, the MIOC will observe the assertion of the AERR# input. Further details on AERR# processing may be found in the ERRCMD register. If this enable is asserted, then the BINIT# Driver Enable in the ERRCMD register must also be asserted. 7 In-Order Queue Depth 1. Captured from A#[7]. If set, the MIOC will limit its In-Order Queue Depth to 1 (no pipelining support), instead of the usual 8. 6 1M Power-on Reset Vector. Captured from A#[6]. This bit has no meaning for the MIOC. If set, all Pentium II Xeon processors on the system bus will use the 1MB-1 (OOOFFFFFh) reset vector, instead of their usual 4 GB-1 (FFFFFFFFh) vector. 5 Enable FRC Mode. Captured from A#[5]. This bit has no meaning for the MIOC. If set, all Pentium II Xeon processors on the system bus will enter FRC-enabled mode. 4:0 reserved (0) Intel 450NX PClset3.3.7 3.3.8 3.3 MIOC Configuration Space CVDR: Configuration Values Driven On Reset Address Offset: 4C-4Dh Size: 16 bits Default Value: 0000h Attribute: Read/Write, Sticky During RESET# assertion, and for one host clock past the trailing edge of RESET#, the MIOC drives the contents of this register onto the A[15:0]# pins. Bits Description 15:13 reserved (0) 12:11 APIC Cluster ID. This two-bit field representing the APIC Cluster identifier is driven to A#[12:11] during RESET#. Note that there are no pins to input the cluster ID; software must explicitly load the value into this register. Default=0. 10 Enable BINIT# Input. If set, A#[10] will be asserted during RESET#, and all system bus agents will enable BINIT# observation. This bit should be set under normal operation. Default=0. 9 Enable BERR# Input. If set, A#[9] will be asserted during RESET#, and all system bus agents will enable BERR# observation. Default=0. 8 Enable AERR# Input. If set, A#[8] will be asserted during RESET#, and all system bus agents will enable AERR# observation. Default=0. 7 In-Order Queue Depth 1. If set, A#[7] will be asserted during RESET#, and all Pentium II Xeon processors on the system bus will limit their In-Order Queue Depth to 1 (no pipelining support), instead of their usual 8. Default=0. 6 1M Power-on Reset Vector. If set, A#[6] will be asserted during RESET#, and all Pentium II Xeon processors on the system bus will use the 1MB-1 (OQOOFFFFFh) reset vector, instead of their usual 4 GB-1 (FFFFFFFFh) vector. Default=0. 5 Enable FRC Mode. If set, A#[5] will be asserted during RESET#, and all Pentium II Xeon processors on the system bus will enter FRC enabled mode. Default=0. 4:0 reserved (0) DBC[15:0]: DRAM Bank Configuration Registers Address Offset: 80-9Fh Size: 16 bits each Default Value: | A200h each Attribute: Read/Write Intel 450NX PClset 3-93. Register Descriptions 3.3.9 3-10 The Intel 450NX PClIset memory subsystem supports at most two RCGs (one RCG and four banks per card) for a maximum of 8 GB of memory. This corresponds to DBC[0:3] on the first card and DBC[8:1 1] on the second card. Unused DBC registers should be configured as inactive, with the Bank Present bit cleared and the TOB field set to that of the previous bank, indicating that the amount of memory in that bank is zero. Bits Description 15 4:1 Interleave. If set, bank is a 4:1 interleave. If cleared, bank is a 2:1 interleave. Default=1. 14 Single Row. This bit is set if the bank contains only a single row. If cleared, the bank contains two rows; both rows must be configured identically. Default=0. 13 Bank Present. This bit is set to indicate that this memory bank is present, and refresh cycles should be issued to the bank. This bit must be cleared if this bank is not physically present. Default=1. 12:10 reserved (0) 9:0 Top of Bank (TOB). This field contains the effective address of the top of memory in this bank and all lower banks, and is used to determine which bank is selected. Each TOB field specifies the amount of memory, in 32 MB chunks, contained in this bank and all lower banks. Unpopulated banks must have their TOB set equal to that of the previous bank indicating that the amount of memory in that bank is zero. Default = 200h, each. DEVMAP: System Bus PCI Device Map Address Offset: D6-D7h Size: 16 bits Default Value: 0005h Attribute: Read/Write, Read Only This register indicates which PCI devices on the system bus have active configuration spaces. At reset, DEVMAP is initialized with all devices not present except the MIOC and the compatibility PCI bus. Bits Description 15 reserved (0) 14:0 PCI Bus #0, Device [30:16] Present. Each bit corresponds to a device on PCI Bus #0 (numbers 16-30). If set, the device is present in the system and is expected to respond to configuration cycles directed to it. Bit Ois hardwired "on", and is read-only. Default=0005h (MIOC, PCI #0A present) Intel 450NX PClset3.3.10 3.3.11 3.3 MIOC Configuration Space DID: Device Identification Register Address Offset: 02 -03h Size: 16 bits Default Value: 84CAh Attributes: Read Only Bits Description 15:0 Device Identification Number. The value 84CAh indicates the Intel 450NX PCIset MIOC. ECCCMD: ECC Command Register Address Offset: B8h Size: 8 bits Default Value: OOh Attribute: Read/Write This register controls the Intel 450NX PClIset responses to ECC errors on data retrieved from the memory subsystem or received from the system bus. Bits NI Description reserved (0) System Bus, Report Multi-Bit Errors (HRM). If set, the Intel 450NX PClset will log multiple-bit ECC errors on data received from the system bus in the appropriate HEL register. If the BERR# driver is enabled, BERR# will also be asserted. Default=0. System Bus, Report Single-Bit Errors (HRS). If set, on detection of a single-bit ECC error on data received from the system bus the Intel 450NX PClset will log the error in the appropriate HEL register, and assert the INTREQ# signal. Default=0. System Bus, Correct Single-Bit Errors (HCS). If set, on detection of a single-bit ECC error on data received from the system bus the Intel 450NX PClset will correct the data and generate a new ECC code before writing the data into memory. Default=0. Memory, Scrub Single-Bit Errors (MSS). If set, on detection of a single-bit ECC error on data read from the memory array the Intel 450NX PClIset will perform a scrub operation to correct the location in the memory. The MCS bit in this register must be set for this feature to be effective. Default=0. Memory, Report Multi-Bit Errors (MRM). If set, on detection of a multiple-bit ECC error on data read from the memory array the Intel 450NX PClIset will log the error in the appropriate MEL and MEA registers. If the BERR# driver is enabled, BERR# will also be asserted. Default=0. Intel 450NX PClset 3-113. Register Descriptions 3.3.12 3.3.13 3-12 1 Memory, Report Single-Bit Errors (MRS). If set, on detection of a single-bit ECC error on data read from the memory array the Intel 450NX PClIset will log the error in the appropriate MEL and MEA registers, and assert the INTREQ# signal. Default=0. 0 Memory, Correct Single-Bit Errors (MCS). If set, on detection of a single-bit ECC error on data read from the memory array the Intel 450NX PClIset will correct the data and generate a new ECC code before returning the data to the requestor. Default=0. ECCMSK: ECC Mask Register Address Offset: B9h Size: 8 bits Default Value: OOh Attribute: Read/Write This register is used to test the ECC error detection logic in the memory subsystem. The register is written with a masking function which is applied on subsequent writes to memory. All subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of the memory locations written while masked will return an invalid ECC code. To disable testing, the mask value is left at Oh (default). Bits Description 7:0 ECC Generation Mask. Each bit of the computed ECC is XORed with the corresponding bit in this mask field before it is stored in the memory array. ERRCMD: Error Command Register Address Offset: 46h Size: 8 bits Default Value: OOh Attribute: Read/Write This register controls the MIOC responses to various system and data errors. Bits Description 7:6 reserved (0) 5 BERR#-to-BINIT# Enable. If set, on observation or assertion of BERR#, (and Enable BERR# Input is set) the MIOC will also assert BINIT#. Default=0. 4 Fast System Bus Time-out. This bit controls the duration of a watchdog timer which is started at the end of the system bus response phase. If this bit is set, the timer expires in 256 host cycles. If cleared, the timer expires in 2! cycles. Default=0. Intel 450NX PClset3.3.14 3.3 MIOC Configuration Space 3 BINIT# on System Bus Time-outs. If this bit is set, and the BINIT# Driver Enable is set, the MIOC will assert BINIT# ona system bus access time-out. Default=0. 2 AERR# Driver Enable. If set, parity errors on the system bus address and request signals are reported by asserting AERR#. Default=0. 1 BERR# Driver Enable. If set, BERR# will be asserted for uncorrectable ECC errors on memory reads or data arriving from the system data bus. Default=0. 0 BINIT# Driver Enable. If set, BINIT# will be asserted upon detecting protocol violations on the system bus. This enable should only be cleared for system boot. In normal operation, this enable must be set. Default=0. ERRSTS: Error Status Register Address Offset: 44-45h Size: 16 bits Default Value: 0000h Attribute: Read/Write Clear, Sticky This register records error conditions detected in the address or controls of the system bus, or in the MIOC itself. Recording of these error conditions is controlled via the ERRCMD register. ERRSTS is sticky through reset, and bits will remain set until explicitly cleared by software writing a 1 to the bit. Bits Description 15:13 reserved (0) 12 Received Hard Fail Response on System Bus. This flag is set when the MIOC detects a Hard Fail response on the system bus. If the BINIT# Driver Enable in the ERRCMD register is set, BINIT# is also asserted. 11 Expander Bus #1 Protocol Violation Flag. This flag is set when the Expander Bus #1 interface receives unexpected data that the MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is also asserted. 10 Expander Bus #0 Protocol Violation Flag. This flag is set when the Expander Bus #0 interface receives unexpected data that the MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is also asserted. 9 Performance Monitor #1 Event Flag. This flag is set when the Performance Monitor #1 requests that an interrupt request be asserted. While this bit is set, the INTREQ# line will be asserted. 8 Performance Monitor #0 Event Flag. This flag is set when the Performance Monitor #0 requests that an interrupt request be asserted. While this bit is set, the INTREQ# line will be asserted. Intel 450NX PClset 3-133. Register Descriptions 3.3.15 3-14 yeserved () System Bus Time-out Flag. This flag is set when the watchdog timer monitoring accesses on the system bus times out. See the BINIT#on-System-Bus-Time-outs Enable and the BINIT# Driver Enable in the ERRCMD register. Expander Bus 1 Parity Error Flag. This flag is set when Expander Bus #1 reports a parity error on data inbound from the PXB. This condition is a catastrophic fail and will also assert BINIT#. Expander Bus 0 Parity Error Flag. This flag is set when Expander Bus #0 reports a parity error on data inbound from the PXB. This condition is a catastrophic fail and will also assert BINIT#. BERR# Error Flag. This flag is set when BERR# is detected asserted on the system bus. Address Parity Error. This flag is set upon detecting the assertion of AP#, indicating a parity error on the system address signals. If the AERR# Driver Enable is set in the ERRCMD register, AERR# is asserted. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is asserted. Response Parity Error Flag. This flag is set upon detecting the assertion of RP#, indicating a parity error on the system bus response signals. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is also asserted. Request Parity Error. This flag is set upon detecting the assertion of RP#, indicating an error on ADS or request signals. If the AERR# Driver Enable is set in the ERRCMD register, AERR# is asserted. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is asserted. GAPEN: Gap Enables Address Offset: 60h Size: 8 bits Default Value: OEh Attribute: Read/Write Bits Description 7 reserved (0) 6 ISA Space Enable. When set, the ISA Space address range is enabled. Memory-mapped accesses that fall within this address range are forwarded to the compatibility PCI bus. If this bit is cleared, accesses to this address range are handled normally. Default=0. 5 High Expansion Gap Enable. When set, the High Expansion Gap (HXG) is enabled. Default=0. Intel 450NX PClset3.3.16 3.3.17 3.3 MIOC Configuration Space Low Expansion Gap Enable. When set, the Low Expansion Gap (LXG) is enabled. Default=0. High BIOS Space Enable. If set, a 2 MByte space is opened at location (4GB - 2MB), and accesses into this address range will be directed to the compatibility PCI bus instead of memory. Default=1. High Graphics Adapter Space Enable. If set, a 64KB space is opened in the upper half of the Graphics Adapter portion of the Low Compatibility Region (address range B_OO00h-BFFFFh), and accesses into this address range will be directed to the compatibility PCI bus instead of memory. Default=1. Low Graphics Adapter Space Enable. If set, a 64KB space is opened in the lower half of the Graphics Adapter portion of the Low Compatibility Region (address range A_OOOOh-AFFFFh), and accesses into this address will be directed to the compatibility PCI bus instead of memory. Default=1. reserved (0) HDR: Header Type Register Address Offset: OEh Size: 8 bits Default Value: OOh Attribute: Read Only This register identifies the header layout of the configuration space. Writes to this register have no effect. Bits NI Description Multi-function Device. The MIOC is not a multi-function device, and this bit is hardwired to 0. Configuration Layout. This field is hardwired to 00h, which represents the default PCI configuration layout. HEL[1:0] Host Bus Error Log Address Offset: B4-B7h Size: 16 bits each Default Value: | 0000h each Attribute: Read/Write, Sticky These registers are loaded on the first and second ECC errors detected on data received from the system bus. HEL[0] logs the first error, and HEL[1] logs the second. The registers hold their data until reloaded due to a new error condition, or until they are explicitly cleared by software or a power-good reset. Intel 450NX PClset 3-153. Register Descriptions 3.3.18 3.3.19 3.3.20 3-16 Bits Description 15:8 Syndrome. Holds the calculated syndrome that identifies the specific bit in error. 7:2 reserved (0) 1 Multiple-Bit Error Logged (MBE). This flag is set if the logged error was a multiple-bit (uncorrectable) error. 0 Single-Bit Error Logged (SBE). This flag is set if the logged error was a single-bit (correctable) error. HXGB: High Expansion Gap Base Address Offset: 58-5Ah Size: 24 bits Default Value: |000000h Attribute: Read/Write Bits Description 23:0 Gap Base Address. This field specifies the A[43:20] portion of the gaps base address, in 1MB increments. The A[19:0] portions of the gaps base address are zero. HXGT: High Expansion Gap Top Address Offset: 5C-5Eh Size: 24 bits Default Value: |000000h Attribute: Read/Write Bits Description 23:0 Gap Top Address. This field specifies the A[43:20] portion of the gaps highest address, in 1MB increments. The A[19:0] portion of the gaps top address is FFFFFh. IOABASE: I/O APIC Base Address Address Offset: 68-69h Size: 16 bits Default Value: OFECh Attribute: Read/Write Bits Description 15:12 reserved (0) 11:0 V/O APIC Base Address. This field specifies the A[31:20] portion of the 1/O APIC Spaces base address, in 1MB increments. The A[43:32] and A[19:0] portions of the address are zero. Intel 450NX PClset3.3.21 3.3.22 3.3 MIOC Configuration Space IOAR: I/O APIC Ranges Address Offset: 6A-6Bh Size: 16 bits Default Value: 0000h Attribute: Read/Write Each of the three fields in the IOAR register specifies the highest APIC number (0-15) that should be directed to that PCI bus, for buses 0A, 0B and 1A. All higher APIC ID are directed to PCI Bus 1B. Bits Description 15:12 reserved (0) 11:8 PCI Bus #1A Highest APIC ID (BUSTA). This field represents the highest APIC ID that should be directed to PCI Bus #1A. 7:4 PCI Bus #0B Highest APIC ID (BUSOB). This field represents the highest APIC ID that should be directed to PCI Bus #0B. 3:0 PCI Bus #0A Highest APIC ID (BUSOA). This field represents the highest APIC ID that should be directed to PCI Bus #0A. IOR: I/O Ranges Address Offset: 7E-7Fh Size: 16 bits Default Value: OFFFh Attribute: Read/Write The IOR register defines the I/O range addresses for each PCI bus. These are specified in sixteen 4KB segments. The starting (base) address for PCI Bus #0A is Oh. Bits Description 15:12 reserved (0) 11:8 PCI Bus #1A Upper Address (BUS1A). This field represents the A[15:12] portion of the highest I/O address that should be directed to PCI Bus #1A. The A[11:0] portion of this address is FFFh. 7A PCI Bus #0B Upper Address (BUSOB). This field represents the A[15:12] portion of the highest I/O address that should be directed to PCI Bus #0B. The A[11:0] portion of this address is FFFh. 3:0 PCI Bus #0A Upper Address (BUSOA). This field represents the A[15:12] portion of the highest I/O address that should be directed to PCI Bus #0A. The A[11:0] portion of this address is FFFh. If PXB x is operating in 64-bit bus mode, BUSxB must equal BUSXA. Intel 450NX PClset 3-173. Register Descriptions 3.3.23 3.3.24 3.3.25 3-18 ISA: ISA Space Address Offset: 7Ch Size: 8 bits Default Value: OOh Attribute: Read/Write This register defines the ISA Space address range. If enabled, memory-mapped accesses into this address range will be forwarded to the compatibility PCI bus. This space is defined to support ISA cards incapable of using the full 32-bit PCI address. Bits Description 7:6 reserved (0) 5:4 ISA Space Size. This field specifies the size of the gap. Legal sizes are: 0Ob: 1 MB 10b: 4 MB O1b: 2 MB 11b: 8 MB 3:0 ISA Space Base Address. This 4-bit field specifies the A[23:20] portion of the gaps base address. The A[43:24] and A[19:0] portions of the gaps base address are zero. LXGB: Low Expansion Gap Base Address Offset: 54-55h Size: 16 bits Default Value: 0000h Attribute: Read/Write Bits Description 15:12 reserved (0) 11:0 Gap Base Address. This field specifies the A[31:20] portion of the gaps base address, in 1MB increments. The A[43:32] and A[19:0] portions of the gaps base address are zero. LXGT: Low Expansion Gap Top Address Offset: 56-57h Size: 16 bits Default Value: 0000h Attribute: Read/Write Bits Description 15:12 reserved (0) 11:0 Gap Top Address. This field specifies the A[81:20] portion of the gaps highest address, in 1MB increments. The A[43:32] portion of the gaps top address is zero, while the A[19:0] portion of the gaps top address is FFFFFh. Intel 450NX PClset3.3.26 3.3 MIOC Configuration Space MAR[6:0]: Memory Attribute Region Registers Address Offset: Default Value: 61-67h 03h for MAR[O] OOh for all others 8 bits each Read/Write Size: Attribute: Seven Memory Attribute Region (MAR) registers are used to program memory attributes of various sizes in the 640 Kbyte-IMByte address range. Each MAR register controls two segments, typically 16 Kbyte in size. Each of these segments has an identical 4-bit field which specifies the memory attributes for the segment, and apply to both host-initiated accesses and PClL-initiated accesses to the segment. Bits Description 7:6 reserved (0) 5 Segment 1, Write Enable (WE). When cleared, host-initiated write accesses are directed to the compatibility PCI bus. When set, write accesses are handled normally according to the outbound access disposition. 4 Segment 1, Read Enable (RE). When cleared, host-initiated read accesses are directed to the compatibility PCI bus. When set, read accesses are handled normally according to the outbound access disposition. 3:2 reserved (0) 1 Segment 0, Write Enable (WE). Identical to segment 1 WE, above. 0 Segment 0, Read Enable (RE). Identical to segment 1 RE, above. Table 3-2 summarizes the possible outcomes of the various Read Enable (RE) and Write Enable (WE) combinations: Table 3-2: MAR-controlled Access Disposition WE, Outbound Outbound locked Inbound RE Write Read Write Read Write Read 00 PCI 0a PCI 0a PCI 0a PCI 0a unclaimed | unclaimed 01 PCI 0a Memory! PCI 0a PCI 0a unclaimed | Memory 10 Memory! PCI 0a PCI 0a PCI 0a Memory unclaimed 11 Memory! Memory! Memory! Memory! Memory Memory 1. Normally, the access will be directed to the DRAM. However, if this MAR region is overlapped by an enabled expansion gap, the access will instead be left unclaimed on the system bus. A third-party agent may then claim the access. 2. Normally, the access will be directed to the DRAM. However, if this MAR region is overlapped by an enabled expansion gap, the access will instead be directed up to the system bus. A third-party agent may then claim the access. Intel 450NX PClset3. Register Descriptions 3.3.27 3.3.28 3-20 MEA[1:0] Memory Error Effective Address Address Offset: A8-A9h Size: 8 bits each Default Value: 00h each Attribute: Read/Write, Sticky These registers contain the effective address information needed to identify the specific DIMM that produced the error. Bits Description 7 Card. Holds the card number (0,1) where the suspect DIMM resides. 6:4 Bank. Identifies the bank within the card (0..7) where the suspect DIMM resides. 3 Row. Identifies the row within the bank (for double row DIMMs). 2 reserved (0) 1:0 Effective Address [4:3]. These two bits of the effective address indicate the "starting" Qword in the critical order access. When combined with the chunk number of the error, as logged in the MEL registers, this identifies the specific DIMM where the error occurred. MEL[1:0] Memory Error Log Address Offset: BO-B3h Size: 16 bits each Default Value: | 0000h each Attribute: Read/Write, Sticky These registers are loaded on the first and second ECC errors detected on data retrieved from the memory. MEL[0] logs the first error, and MEL[1] logs the second. Bits Description 15:8 Syndrome. Holds the calculated syndrome that identifies the specific bit in error. 7:4 reserved (0) 3:2 Chunk Number. Specifies which of the four possible chunks in the critical chunk ordered transfer the error occurred in, from zero to three. 1 Multiple-Bit Error Logged (MBE). This flag is set if the logged error was a multiple-bit (uncorrectable) error. 0 Single-Bit Error Logged (SBE). This flag is set if the logged error was a single-bit (correctable) error. Intel 450NX PClset3.3.29 3.3.30 3.3.31 3.3 MIOC Configuration Space MMBASE: Memory-Mapped PCI Base Address Offset: 70-71h Size: 16 bits Default Value: 0002h Attribute: Read/Write The MMBASE register defines the starting address of the Memory-Mapped PCI Space, and each MMR register defines the highest address to be directed to a PCI bus. If PXB 0 is operating in 64-bit bus mode, MMR[1] must equal MMR[O]. If PXB 1 is operating in 64-bit bus mode, MMR[3] must equal MMR[2]. Bits Description 15:12 reserved (0) 11:0 PCI Space Base Address. This field specifies the A[31:20] portion of the PCI spaces base address, in 1MB increments. The A[43:32] and A[19:0] portions of the address are zero. MMR[3:0]: Memory-Mapped PCI Ranges Address Offset: 74-7Bh Size: 16 bits each Default Value: 0001h each Attribute: Read/Write These registers define the high addresses for addresses to be directed to the PCI space. Bits Description 15:12 reserved (0) 11:0 PCI Space Top Address. This field specifies the A[31:20] portion of the PCI spaces highest address, in 1MB increments. The A[43:32] portion of this address is zero, while the A[19:0] portion of this address is FFFFFh. PMD/[1:0]: Performance Monitoring Data Register Address Offset: D8-DCh, E0-E4h Size: 40 bits each Default Value: | 0000000000h each Attribute: Read/Write Two performance monitoring counters are provided in the MIOC. The PMD registers hold the performance monitoring count values. Each counter can be configured to reload the data when it, or the other counter overflows. Event selection is controlled by the PME registers, and the action performed on event detection is controlled by the PMR registers. An additional Performance Counter Master Enable Intel 450NX PClset 3-213. Register Descriptions 3.3.32 3-22 (PCME) in the MIOCs CONFIG register allows (nearly) simultaneous stopping /starting of all counters in the MIOC and each PXB. The counters cannot be read or written coherently while the counters are running. Bits Description 39:0 Count Value. PME[1:0]: Performance Monitoring Event Selection Address Offset: E8-E9h, EA-EBh Size: 16 bits each Default Value: | 0000h each Attribute: Read/Write Bits Description 15 reserved (0) 14 Count Data Cycles 1: Count the request length of the selected transaction. 0: Count the selected event 13 reserved (0) 12:10 Initiating Agent Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions issued by specific agents. 000 Symmetric Agent 0 (DID=0/000) 100 Any symmetric agent (DID=0/xxx) 001 Symmetric Agent 1 (DID=0/001) 101 Third party agent (DID=1/other) 010 Symmetric Agent 2 (DID=0/010) 110 Intel 450NX PCIset agent (DID=1/001) 011 Symmetric Agent 3 (DID=0/011) 111 Any agent 9:8 Transaction Destination Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions directed to a specific resource. 00 Any 10 Not Third Party or Memory! 01 Main Memory 11 Third party 1. The usual destination in this category is a PCI Target. Also included are Internal CFC /CF8 accesses, Branch trace messages, Interrupt acknowledge, and some special transactions. 7:6 Data Length Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions of a specific length. 00 Any 10. Part-lines or partials O01 Lines 11 reserved 5:0 Event Selection. This field specifies the basic system bus transaction, system bus signal assertion, or memory event to be monitored. Individual Bus Transactions 00 0000 Deferred Reply 00 1000 reserved 00 0001 = reserved 00 1001 reserved 000010 reserved 00 1010 Memory Read Invalidate Intel 450NX PClset3.3.33 3.3 MIOC Configuration Space 000011 reserved 001011 reserved 000100 I/O Read 00 1100 Memory Read Code 00 0101 I/O Write 001101 Memory Writeback 000110 reserved 001110 Memory Read 000111 reserved 001111 Memory Write Generic (Grouped) Bus Transactions 010000 Any bus transaction 010100 Any I/O transaction 010001 Any memory transaction 010101 Any I/O or memory transactions 010010 Any memory read 010110 Any I/O or memory read 010011 Any memory write 010111 Any I/O or memory write Bus Signal Assertions 011000 HIT! 011100 BNRI? 011001 HITM! 011101 BPRI@ 011010 RETRY! 011110 LOCK? 011011 DEFER! 011111 reserved Memory Hits/Misses 100 000 Bank was idle? 100010 Waited for address lines! 100001 Waited for Row precharge! ? 100011 Hit open page! All other encodings are reserved. Notes: 1. Counting data cycles is undefined for this selection. 2. The Agent, Destination and Length fields cannot be applied to this selection, and should be programmed to "any". PMR[1:0]: Performance Monitoring Response Address Offset: DDh, E5h Size: 8 bits each Default Value: 00h each Attribute: Read/Write The PMR register specifies how the event selected by the corresponding PME register affects the associated PMD register, the BP[1:0] pins, and the INTREQ# pin. Events defined by PME[O] can be driven out BPO and events defined by PME[1] can be driven out BP1. Bits Description 7:6 Interrupt Assertion Defines how selected event affects INTREQ# assertion. Whenever INTREQ# is asserted, a flag for this counter is set in the Error Status (ERRSTS) register, so that software can determine the cause of the interrupt. This flag is reset by writing the ERRSTS register. 0 Selected event does not assert INTREQ# 1 reserved 2 Assert INTREQ# pin when event occurs 3 Assert INTREQ# pin when counter overflows 5:4 Performance Monitoring pin assertion Defines how the selected event affects the Performance Monitoring pin for this counter. 0 Selected event does not assert this counters PM pin 1 reserved Intel 450NX PClset 3-233. Register Descriptions 3.3.34 3-24 2 Assert this counters PM pin when event occurs 3 Assert this counters PM pin when counter overflows 3:2 Count Mode Selects when the counter is updated for the detected event. 0 Stop counting. 1 Count each cycle selected event occurs. 2 Count on each rising edge of the selected event. 3 Trigger. Start counting on the first rising edge of the selected event, and continue counting each clock cycle. 1:0 Reload Mode Reload has priority over increment. If a reload event and a count event happen simultaneously, the count event has no effect. 0 Never Reload 1 Reload when this counter overflows. 2 Reload when the other counter overflows. 3 Reload unless the other counter increments. RC: Reset Control Register Address Offset: 42h Size: 8 bits Default Value: OOh Attribute: Read/Write The RC initiates processor reset cycles and initiates Built-in Self Test (BIST) for the processors. Bits Description 7:6 reserved (0) 5 Reset Expander Port #1. While this bit is set, the X1RST# signal is asserted. When this bit is cleared, the X1RST# pin will be deasserted, unless other assertion criteria are still in effect (e.g., system hard reset). Default=0. 4 Reset Expander Port #0. While this bit is set, the XORST# signal is asserted. When this bit is cleared, the XORST# will be deasserted, unless other assertion criteria are still in effect (e.g., system hard reset). Default=0. 3 Processor BIST Enable (BISTE). This bit modifies the action of the RCPU and SHRE bits, below. If this bit is set, a subsequent invocation of system hard reset causes the INIT# signal to be asserted coincident with the deassertion of RESET#; this combination will invoke the Built-In Self Test (BIST) feature of the processors. Default=0. Intel 450NX PClset3.3.35 3.3.36 3.3 MIOC Configuration Space 2 Reset Processor (RCPU). The transition of this bit from 0 to 1 causes the MIOC to initiate a hard or soft reset. Selection of hard or soft reset, and processor BIST, are controlled by the BISTE and SHRE enables, which must be set up prior to the 0-to-1 transition on the RCPU bit. Default=0. 1 System Hard Reset Enable (SHRE). This bit modifies the action of the RCPU bit, above. If set, the Intel 450NX PClIset will initiate a system hard reset upon a subsequent 0-to-1 transition of the RCPU bit. If this bit is cleared, the Intel 450NX PClset will initiate a soft reset upon a subsequent 0-to-1 transition of the RCPU bit. Default=0. 0 reserved (0) RCGP: RCGs Present Address Offset: A3h Size: 8 bits Default Value: 00h Attribute: Read/Write The Intel 450NX PCIset memory subsystem supports at most two RCGs (one per card). This corresponds to RCG #0 and RCG #2, bits 0 and 2 in the RCGP register. Bits Description 7:4 reserved (0) 3:0 RCGs Present [3:0]. If bit i is set, then RCGIi] was detected as present in the system following power-on reset. If cleared, then RCG[i] is not present. Default= <hardware generated>. REFRESH: DRAM Refresh Control Register Address Offset: A4-A5h Size: 16 bits Default Value: 0411h Attribute: Read/Write Bits Description 15:11 reserved (0) 10:0 Refresh Count. Specifies the number of system bus cycles between refresh cycles. Typically, the value is chosen to provide a refresh at least every 15.625 usec. @ 100.0 MHz: 61Ah = 15.620 usec @ 90.0MHz: 57Eh = 15.622 usec Maximum value is 20.48 usec at 100 MHz. Default=411h Intel 450NX PClset 3-253. Register Descriptions 3.3.37 3.3.38 3.3.39 3-26 RID: Revision Identification Register Address Offset: 08h Size: 8 bits Default Value: OOh Attribute: Read Only Bits Description 7:0 Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the MIOC ROUTE[1:0]: Route Field Seed Address Offset: C3h, CBh Size: 8 bits Default Value: 40h Attribute: Read/Write Bits Description 7:4 Outbound-to-B Route Seed. This field represents the seed value used to create the routing field for outbound packets to the PXBs B-port. Default: 0100b 3:0 Outbound-to-A Route Seed. This field represents the seed value used to create the routing field for outbound packets to the PXBs A-port. Default: 0000b SMRAM: SMM RAM Control Register Address Offset: 6C-6Fh Size: 32 bits Default Value: | O00000Ah Attribute: Read/Write Bits Description 31 SMRAM Enable (SMRAME). If set, the SMRAM functions are enabled. Host-initiated accesses to the SMM space can be selectively directed to memory or PCI, as defined below and in Table 3-3. If SMRAME is cleared, SMRAM functions are disabled. Default=0. 30:27 reserved (0) 26 SMM Space Open (D_OPEN). If set, all accesses (code fetches or data references) to SMM space are passed to memory, regardless of whether the SMMEM# signal is asserted. D_LOPEN may be set or cleared by software. D_OPEN will also be automatically cleared, and will become read-only, when the D_LCK enable is set. Default=0. Intel 450NX PClset25 24 23:20 19:16 15:0 3.3 MIOC Configuration Space SMM Space Closed (D_CODE). This bit should not be set unless D_LOPEN=0. If D_CODE is set, only code fetches to SMM space may be passed to the DRAM, depending on the SMMEM# signal. Data accesses to SMM space will not be passed to the DRAM, regardless of the SMMEM# signal. Default=0. SMM Space Locked (D_LCK). When software writes a 1 to this bit, the hardware will clear the D_OPEN bit, and both D_LCK and D_OPEN then become read only. No application software, except the SMI handler, should violate or change the contents of SMM memory. Default=0. SMM Space Size. This field specifies the size of the SMM RAM space, in 64 KB increments. Oh 64KB 4h 320KB 8h 576 KB Ch 832 KB th 128 KB 5h 384 KB 9h 640 KB Dh 896 KB 2h 192 KB 6h 448 KB Ah 704 KB Eh 960 KB 3h 256 KB 7h 512 KB Bh 768 KB Fh 1MB Default: Oh (64 KB). reserved (0) SMM Space Base Address. This field specifies the A[31:16] portion of the SMM RAM space base address (A[15:0]=0000h). The space may be relocated anywhere below the 4GB boundary and the Top of Memory (TOM); however, the base address must be aligned on the next highest power-of-2 natural boundary given the chosen size. Incorrect alignment results in indeterminate operation. Default: OOOAh. Table 3-3: SMRAM Space Cycles Code Data Fetch Reference Usage Normal! | Normal! | SMM RAM space is not supported. =| o| SMRAME o| <x} D_OPEN o| x| D_CODE |x| D_LCK o| | SMMEM PCI 0a PCI 0A Normal SMM usage. Accesses to the SMM RAM space from processors in SMM will oO DRAM DRAM access the DRAM. Accesses by processors not in SMM will be diverted to the compatibility PCI bus. oO x 1 | Xj] 0 |} PCI OA PCI 0A A modification of the normal SMM usage, in 11x 141 lDRAM PCI 0A which only code fetches are accepted from processors in SMM mode. X || X Illegal Combination 0 | O]| X || DRAM DRAM Full access by any agent to SMM RAM space. 1. SMRAM functions are disabled. Intel 450NX PClset 3-273. Register Descriptions 3.3.40 3.3.41 3.3.42 3-28 SUBA[1:0]: Bus A Subordinate Bus Number, per PXB Address Offset: Dih, D4h Size: 8 bits each Default Value: 00h each Attribute: Read/Write See the description of BUSNO. SUBB[1:0]: Bus B Subordinate Bus Number, per PXB Address Offset: D2h, D5h Size: 8 bits each Default Value: 00h each Attribute: Read/Write See the description of BUSNO. TCAP[0:3]: Target Capacity, per PXB/PCI Port Address Offset: C0O-C2h, C4-C6h Size: 24 bits each C8-CAh, CC-CEh Default Value: 041082 each Attribute: Read/Write Each of these registers is programmed by software with the maximum number of transactions and data bytes that the receiving PXB/PCI port can accept for outbound transactions. Register | Controls outbound transactions to ... if in ... dual 32-bit Bus Mode __| 64-bit Bus Mode TCAP[O] | PXB #0 / PCI Bus A PXB #0 TCAP[1] | PXB #0 / PCI Bus B N/A TCAP[2] | PXB #1 / PCI Bus A PXB #0 TCAP[3] | PXB #1/ PCI Bus B N/A NOTE Setting a value below the listed minimum-allowed value will have unpredictable results, up to and including potential deadlocks requiring a hard reset of the PCiset. Bits Description 23:18 Outbound Write Transaction Capacity. This field specifies the total number of outbound write transactions, per PXB/PCI port, that can be forwarded and queued by the PXB. MIOC maximum: 12 Minimum allowed: 1, 2 or 3 Default= 1 - If no outbound locks are supported, then the minimum is 1. - If ordinary outbound locks are supported, then the minimum is 2. - If outbound split locks are supported, then the minimum is 3. Intel 450NX PClset3.3.43 3.3.44 3.4 3.4 PXB Configuration Space 17:12. Outbound Read Transaction Capacity. This field specifies the total number of outbound read transactions, per PXB/PCI port, that can be forwarded and queued in the PXB. MIOC maximum: 2 Minimum allowed: 1 Default= 1 11:6 Outbound Write Data Buffer Capacity. This field specifies the total number of data buffers, per PXB/PCI port, available in the PXB for use by outbound write transactions, in increments of 32 bytes. MIOC maximum: 12 Minimum allowed: 2 Default= 2 5:0 Outbound Read Data Buffer Capacity. This field specifies the total number of data buffers, per PXB/PCI port, available in the PXB for use by outbound read transactions, in increments of 32 bytes. MIOC maximum: 16 Minimum allowed: 2 Default= 2 TOM: Top of Memory Address Offset: 50-52h Size: 24 bits Default Value: | OOOFFFh Attribute: Read/Write Bits Description 23:0 Memory Address Ceiling. Represents bits A[43:20] of the highest physical address to be directed toward this nodes DRAM. The lower A[19:0] bits of this address are FFFFFh. Default=O00FFFh (4GB-1). VID: Vendor Identification Register Address Offset: 00-O1h Size: 16 bits Default Value: 8086h Attributes: Read Only Bits Description 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086n. PXB Configuration Space Each PXB supports two independent PCI buses (Bus A and Bus B), which can be configured independently. Each PCI bus therefore has its own configuration space. Both configuration spaces are identical. When operating the PXB in 64-bit Bus Mode, only the A- Intel 450NX PClset 3-293. Register Descriptions side configuration space is used. The B-side configuration space is not accessible while in 64- bit mode. Table 3-4 illustrates the PXB/PCI Bus Configuration Space Map. Table 3-4: PXB Configuration Space 1 DID VID 00h PCISTS PCICMD 04h CLASS RID HDR MTT CLS CONFIG MODES 24h 28h 2Ch 30h 34h 38h 3Ch 40h ROUTE RC ERRCMD ERRSTS TCAP 44h BUFSIZ TMODE 48h 4Ch TOM 50h LXGT LXGB 54h HXGB 58h HXGT PMDO 5Ch MAR2 MAR1 MARO GAPEN PMRO PMDO 60h MAR6 MARS5 MAR4 MARS PMD1 64h IOABASE PMR1 PMD1 SMRAM 68h PME1 PMEO 6Ch MMBASE 70h 74h 78h ISA 7Ch 3-30 Intel 450NX PClset 80h 84h 88h 8Ch 90h 94h 98h 9Ch AOh A4h A8h ACh Boh B4h B8h BCh Coh C4h C8h CCh DOh D4h D8h DCh E0h E4h E8h ECh FOh F4h F8h FCh3.4 PXB Configuration Space 1. The first 64 bytes are predefined in the PCI Specification. All other locations are defined specifically for the component of interest. 3.4.1 3.4.2 BUFSIZ: Buffer Sizes NOTE The default values shown below correspond to those programmed into the C0-stepping of the PXB. For information regarding earlier steppings, please refer to latest release of the Intel 450NX PCiset Specification Update. Address Offset: 48-4Ah Size: 24 bits Default Value: 302308h (64-bit bus mode)Attribute: Read Only 182184h (32-bit bus mode) This register contains the hardwired information defining the maximum number of outbound transactions and data bytes that this PXB/PCI port can accept. Bits Description 23:18 Outbound Write Transaction Capacity. This field specifies the total number of outbound write transactions that can be accepted and queued in this PXB/PCI port. Value= 6 (32-bit bus mode) 12 (64-bit bus mode) 17:12. Outbound Read Transaction Capacity. This field specifies the total number of outbound read transactions that can be accepted and queued in this PXB/PCI port. Value= 2 (32-bit bus mode) 2 (64-bit bus mode) 11:6 Outbound Write Data Buffer Capacity. This field specifies the total number of data buffers available in this PXB/PCI port for use by outbound write transactions, in increments of 32 bytes. Value= 6(x32 bytes) (32-bit bus mode) 12 (x 32 bytes) (64-bit bus mode) 5:0 Outbound Read Data Buffer Capacity. This field specifies the total number of data buffers available in this PXB/PCI port for use by outbound read transactions, in increments of 32 bytes. Value= 4 (x32 bytes) (32-bit bus mode) 8 (x32 bytes) (64-bit bus mode) CLASS: Class Code Register Address Offset: 09 - OBh Size: 24 bits Default Value: 060000h Attribute: Read Only Intel 450NX PClset 3-313. Register Descriptions 3.4.3 3.4.4 3-32 Bits 23:16 Description Base Class For the PXB, this field is hardwired to 06h. Sub-Class For the PXB, this field is hardwired to O0Oh. Register-Level Programming Interface For the PXB, this field is hardwired to 00h. CLS: Cache Line Size Address Offset: OCh Size: 8 bits Default Value: 08h Attribute: Read/Write Bits Description 7:0 Cache Line Size This field specifies the cache line size, in 32-bit Dword units. The Intel 450NX PClset supports only one value: 8 Dwords (32 bytes). Default=08h. CONFIG: Configuration Register Address Offset: 40-41h Size: 16 bits Default Value: 2310h Attribute: Read/Write, Read-Only Bits Description 15 reserved (0) 14 PCI Bus Lock Enable. This mode works only if internal bus arbitration is selected. When set, the internal arbiter detects when the lock is established and inhibits a PCI bus grant to all agents except the agent that established the lock. Default=0. 13 WSC# Assertion Enable. If cleared, the WSC# signal will always remain asserted. While asserted, writes continue to be accepted from the PIIX even with writes outstanding. This option is provided to allow improved performance in systems with ISA masters that desire to write to main memory. Default=1. 12 PCI-TPA Prefetch Line Enable (PLE). If set, inbound line accesses (e.g., MRM and MRL accesses) to third-party space are treated as prefetchable. Default=0. Intel 450NX PClset11 10 5:4 3.4 PXB Configuration Space PCI-TPA Prefetch Word Enable (PWE). If set, inbound sub-line accesses (e.g., MR accesses) to third-party space are treated as prefetchable. Default=0. Block Requests. This enable is provided for debug, diagnostic and error recovery purposes. If set, the internal arbiter ignores all further REQ[0:5]# assertions by any of the six PCI agents, and will deassert any current PCI agents GNT# in order to prevent further inbound transactions from a parking agent. This enable has no effect if the PXB is configured to use external arbitration. Default=0. V/O Address Mask Enable. If set, on outbound I/O accesses the PXB will force A[31:16] to zero before placing the address on the PCI bus. Default=1. Outbound Write Around Retried/Partial Read Enable. If set, the PXB allows outbound writes to pass retried or partially completed (ie., disconnected) outbound reads. This enable must be set for Pentium IJ Xeon processor / Intel 450NX PClIset systems. Default=1. Burst Write Combining Enable (BWCE). If set, back-to-back sequentially addressed outbound writes may be combined in the outbound write buffers before placement on the PCI bus. When the BWCE is cleared, all outbound write combining is disabled, and each host transaction results in a corresponding transaction on the PCI bus. Default=0. Re-streaming Buffer Enable. If set, the data returned and buffered for a Delayed Inbound Read may be re-accessed following a disconnect. If cleared, following a disconnect, the buffer is invalidated, and a subsequent read to the next location will initiate a new read. Default=0 (Disabled). Read Prefetch Size. This field configures the number of Dwords that will be prefetched on Memory Read Multiple commands for systems based on B1 or earlier steppings of the PXB!. Legal values are: 00 16 Dwords (2 x 32 bytes) 10 64 Dwords @& x 32 bytes) 01 32 Dwords (4 x 32 bytes) 11_sreserved The normal selection is 32 Dwords The 64 Dword selection provides highest performance when the PXB is in 64-bit bus mode. Default=01 ($2 Dwords). External Arbiter Enable. This is a read-only bit that selects internal or external arbitration for the PCI bus. The bit reflects the state of the P(A,B)XARB# strapping pin for this bus (A or B). Default=[P(A,B)XARB pin]. 64-bit Bus Enable. This is a read-only bit that selects whether the PXB operates as two 32-bit PCI buses or a single 64-bit PCI bus. The bit reflects the state of the MODE64# strapping pin. Default=[MODE64# pin]. 1. For systems based on CO or later steppings of the PXB, the read prefetch size is fixed at 32 Dwords (4 x 32 bytes). Intel 450NX PClset 3-333. Register Descriptions 3.4.5 3.4.6 3-34 reserved reserved DID: Device Identification Register Address Offset: 02 -03h Size: 16 bits Default Value: 84CBh Attributes: Read Only Bits Description 15:0 Device Identification Number. The value 84CBh indicates the Intel 450NX PCIset PXB. ERRCMD: Error Command Register Address Offset: 46h Size: 8 bits Default Value: OOh Attribute: Read/Write This register provides extended control over the assertion of SERR# beyond the basic controls specified in the PCI-standard PCICMD register. Bits 7 6 Description reserved Assert SERR# on Observed Parity Error. If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the asserting agent. Assert SERR# on Received Data with Parity Error. If set, the PXB asserts SERR# upon receiving PCI data with a parity error. This occurs regardless of whether PXB asserts its PERR# pin. Assert SERR# on Address Parity Error. If set, the PXB asserts SERR# on detecting a PCI address parity error. Assert PERR# on Data Parity Error. If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon receiving PCI data with parity errors. Assert SERR# On Inbound Delayed Read Time-out. Each inbound read request that is accepted and serviced as a delayed read will start a watchdog timer 2) cycles). If this enable is set, the PXB will assert SERR# if the data has been returned and the timer expires before the requesting master initiates its repeat request. Default=0. Intel 450NX PClset3.4.7 3.4 PXB Configuration Space Assert SERR# on Expander Bus Parity Error. If set, the PXB asserts SERR# upon detecting a parity error on packets arriving from the Expander bus. (Note that SERR# will be asserted on both PCI buses). Return Hard Fail Upon Generating Master Abort. If set, the PXB will return a Hard Fail response through the MIOC to the system bus after generating a master abort time-out for an outbound transaction placed on the PCI bus. If cleared, the PXB will return a normal response (with data of all 1s for a read). In either case, an error flag is set in the PCISTS register. Default=0. ERRSTS: Error Status Register Address Offset: 44h Size: 8 bits Default Value: OOh Attribute: Read/Write Clear, Sticky This register records error conditions detected from the PCI bus (not already covered in PCISTS), from the Expander bus, and performance monitoring events. Bits remain set until explicitly cleared by software writing a 1 to the bit. Bits > Description reseroed{(O} Parity Error observed on PCI Data. This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the asserting agent. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Parity Error on Received PCI Data. This flag is set if the PXB detects a parity error on data being read from the PCI bus. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Parity Error on PCI Address. This flag is set if the PXB detects a parity error on the PCI address. This flag may be configured to assert SERR# in the ERRCMD register. Inbound Delayed Read Time-out Flag. Each inbound read request that is accepted and serviced as a delayed read will initiate a watchdog timer (2! cycles). If the data has been returned and the timer expires before the requesting master initiates its repeat request, this flag will be set. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Expander Bus Parity Error Flag. This flag is set when Expander bus reports a parity error on packets received from the MIOC. This flag is set in both PCI configuration spaces. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. Intel 450NX PClset 3-353. Register Descriptions 3.4.8 3.4.9 3.4.10 3-36 1 Performance Monitor #1 Event Flag. This flag is set when the Performance Monitor #1 requests that an interrupt request be asserted. The PME and PMR registers describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted. 0 Performance Monitor #0 Event Flag. This flag is set when the Performance Monitor #0 requests that an interrupt request be asserted. The PME and PMR registers describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted. GAPEN: Gap Enables Address Offset: 60h Size: 8 bits Default Value: OEh Attribute: Read/Write This register controls the enabling of the two programmable memory gaps, and several fixed- size/fixed-location spaces. This register applies to both host-initiated transactions and PCI- initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. HDR: Header Type Register Address Offset: OEh Size: 8 bits Default Value: OOh Attribute: Read Only Bits Description NI Multi-function Device. Selects whether this is a multi-function device, that may have alternative configuration layouts. This bit is hardwired to 0. 6:0 Configuration Layout. This field identifies the format of the 10h through 3Fh space. This field is hardwired to 00h, which represents the default PCI configuration layout. HXGB: High Expansion Gap Base Address Offset: 58-5Ah Size: 24 bits Default Value: |000000h Attribute: Read/Write This register defines the starting address of the High Expansion Gap (HXG). This register applies to both host-initiated transactions and PClI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. Intel 450NX PClset3.4.11 3.4.12 3.4.13 3.4.14 3.4 PXB Configuration Space HXGT: High Expansion Gap Top Address Offset: 5C-5Eh Size: 24 bits Default Value: |000000h Attribute: Read/Write This register defines the highest address of the High Expansion Gap (HXG), above. HXGT applies to both host-initiated transactions and PClI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. IOABASE: I/O APIC Base Address Address Offset: 68-69h Size: 16 bits Default Value: OFECh Attribute: Read/Write This register defines the base address of the 1MB I/O APIC Space address range. IOABASE applies to both host-initiated transactions and PClI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. ISA: ISA Space Address Offset: 7Ch Size: 8 bits Default Value: OOh Attribute: Read/Write This register defines the ISA Space address range. The register applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. LXGB: Low Expansion Gap Base Address Offset: 54-55h Size: 16 bits Default Value: 0000h Attribute: Read/Write This register defines the starting address of the Low Expansion Gap (LXG). LXGB register applies to both host-initiated transactions and PClI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. Intel 450NX PClset 3-373. Register Descriptions 3.4.15 3.4.16 3.4.17 3-38 LXGT: Low Expansion Gap Top Address Offset: 56-57h Size: 16 bits Default Value: 0000h Attribute: Read/Write LXGT defines the highest address of the Low Expansion Gap (LXG), above. This register applies to both host-initiated transactions and PClI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. MAR[6:0]: Memory Attribute Region Registers Address Offset: 61-67h Size: 8 bits each Default Value: 03h for MAR[0O] Attribute: Read/Write 00h for all others The Intel 450NX PClIset allows programmable memory attributes on 14 memory segments of various sizes in the 640 Kbyte to 1 MByte address range. Seven Memory Attribute Region (MAR) registers are used to support these features. These registers apply to both host-initiated transactions and PC]-initiated transactions, and are therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. MLT: Master Latency Timer Register Address Offset: ODh Size: 8 bits Default Value: OOh Attribute: Read/Write MLT is an 8-bit register that controls the amount of time (measured in PCI clocks) the Intel 450NX PClIset, as a bus master, can burst data on the PCI Bus. The Count Value is an 8 bit quantity; however, MLT[2:0] are reserved and assumed to be 0 when determining the Count Value. The number of clocks programmed in the MLT represents the guaranteed time slice allotted to the Intel 450NX PClset, after which it must complete the current data transfer phase and then surrender the bus as soon as its bus grant is removed. Bits Description 7:3 Master Latency Timer Count Value. Counter value in 8 PCI clock units. 2:0 reserved (0) Intel 450NX PClset3.4.18 3.4.19 3.4.20 3.4.21 3.4 PXB Configuration Space MMBASE: Memory-Mapped PCI Base Address Offset: 70-71h Size: 16 bits Default Value: 0002h Attribute: Read/Write The MMBASE register specifies the starting address of this memory-mapped PCI range, and is identical to the MMBASE register in the MIOC. The MMT register specifies the highest address that will be directed to PCI Bus #1B, and corresponds identically to the MMR{[3] register in the MIOC. The MMBASE register must be programmed identically to the MMBASE register in the MIOC to achieve correct functioning. See the MIOC Configuration Space for a detailed description. MMT: Memory-Mapped PCI Top Address Offset: 7A-7Bh Size: 16 bits Default Value: 0001h Attribute: Read/Write This register defines the highest address of the memory-mapped PCI space. See the MMBASE register above for a detailed description. The MMT register must be programmed identically to MMR{[3] in the MIOC to achieve correct functioning. MODES: Modes Register Address Offset: AQh Size: 8 bits Default Value: OOh Attribute: Read/Write Bits Description 7:0 reserved (0) 0 Continuous Prefetch Enable When this bit is set the PXB continuously issues a new read to prefetch more data for that master as the previous read data is consumed. This results in improved PCI inbound read performance. When cleared, continuous prefetching is disabled. Default=0. MTT: Multi-Transaction Timer Register Address Offset: 43h Size: 8 bits Default Value: OOh Attribute: Read/Write This register controls the amount of time that the PCI bus arbiter allows a PCI initiator to perform multiple back-to-back transactions on the PCI bus. Intel 450NX PClset 3-393. Register Descriptions 3.4.22 3-40 Bits 7:3 Description MITT Count Value. Specifies the guaranteed time slice (in 8-PCI-clock increments) allotted to the current agent, after which the PXB will grant the bus as soon as other PCI masters request the bus. A value of 0 disables this function. Default=0. reserved (0) PCICMD: PCI Command Register Address Offset: 04 -05h Size: 16 bits Default Value: 0016h Attribute: Read/Write, Read-Only This is a PCI specification required register with a fixed format. Bits 15:10 9 Description reserved (0) Fast Back-to-Back. Fast back-to-back cycles are not implemented by the PXB, and this bit is hardwired to 0. SERR# Enable (SERRE). If this bit is set, the PXBs SERR# signal driver is enabled and SERR# is asserted for all relevant bits set in the ERRSTS and PCISTS as controlled by the corresponding bits of the ERRCMD register. If SERRE is set and the PXBs PCI parity error reporting is enabled by the PERRE bit, then the PXB will assert SERR# on address parity errors. Default=0. Address/Data Stepping. The PXB does not support address/data stepping, and this bit is hardwired to 0. Parity Error Response (PERRE). If PERRE is set, the PXB will report parity errors on data received by asserting the PERR# signal. Address parity errors are not reported using PERR#, but instead through the SERR# signal, and only if both PERRE and SERRE are set. If PERRE is cleared, then PCI parity errors are not reported by the PXB. Default=0. reserved (0) Memory Write and Invalidate Enable. Selects whether the PXB, as a PCI master, can generate Memory Write and Invalidate cycles. Default=1. Special Cycle Enable. The PXB will ignore all special cycles generated on the PCI bus, and this bit is hardwired to 0. Intel 450NX PClset3.4.23 3.4 PXB Configuration Space Bus Master Enable. The PXB does not permit disabling of its bus master capability, and this bit is hardwired to 1. Memory Access Enable. The PXB does not permit disabling access to main memory, and this bit is hardwired to 1. I/O Access Enable. The PXB does not respond to PCI I/O cycles, and this bit is hardwired to 0. PCISTS: PCI Status Register Address Offset: 06 -07h Size: 16 bits Default Value: 0280h Attribute: Read/Write Clear, Sticky This is a PCI specification required register, with a fixed format. Bits 15 12 11 10:9 Description Parity Error (PE). This bit is set when the PXB detects a parity error in data or address on the PCI bus. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Signaled System Error (SSE). This bit is set when the PXB asserts the SERR# signal. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Received Master Abort (RMA). This bit is set when the PXB, as bus master, terminates its transaction (except for Special Cycles) with a master abort. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Received Target Abort (RTA). This bit is set when the PXB, as bus master, receives a target abort for its transaction. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. Signaled Target Abort (STA). This bit is set when the PXB, as bus target, terminates a transaction with target abort. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. DEVSEL# Timing (DEVT). This 2-bit field encodes the timing of the DEVSEL# signal when the PXB responds as a target, and represents the slowest time that the PXB asserts DEVSEL# for any bus command except Configuration Reads or Writes. This field is hardwired to the value 01b (medium). Intel 450NX PClset 3-413. Register Descriptions 3.4.24 3.4.25 3-42 8 Data Parity Error (DPE). This bit is set when all of the following conditions are met: 1. The PXB asserted PERR# or sampled PERR# asserted. 2. The PXB was the initiator for the operation in which the error occurred. 3. The PERRE bit in the PCICMD register is set. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default=0. 7 Fast Back-to-Back (FB2B). The PXB supports fast back-to-back transactions, and this bit is hardwired to 1. 6 UDF Supported. The PXB does not support User Definable Features (UDF), and this bit is hardwired to 0. 5 66 MHz Capable. The PXB is not capable of running at 66 MHz, and this bit is hardwired to 0. 4:0 reserved (0) PMD/[1:0]: Performance Monitoring Data Register Address Offset: D8-DCh, E0-E4h Size: 40 bits each Default Value: | 000000000000h each Attribute: Read/Write Two performance monitoring counters, with associated event selection and control registers, are provided for each PCI bus in the PXB. The PMD registers hold the performance monitoring count values. Event selection is controlled by the PME registers, and the action performed on event detection is controlled by the PMR registers. Bits Description 39:0 Count Value. PME[1:0]: Performance Monitoring Event Selection Address Offset: E8- EBh Size: 16 bits each Default Value: | 0000h each Attribute: Read/Write Bits Description 15 reserved (0) 14 Count Data Cycles 1: Count the data cycles associated with the selected transactions. 0: Count the selected event Intel 450NX PClset13:10 9:8 7:6 5:0 3.4 PXB Configuration Space Initiating Agent Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions issued by specific agents. 0000 AgentO 1000 reserved 0001 Agent1 1001 reserved 0010 Agent2 1010 reserved 0011 Agent3 1011 reserved 0100 Agent4 1100 reserved 0101 Agent5 1101 south bridge 0110 reserved 1110 Intel 450NX PCIset agent (i.e., outbound) 0111 reserved 1111 Any agent Note: This field is applicable only if the PCI bus is operated in internal arbiter mode. If the bus is operated using an external arbiter, this field must be set to Any Agent to trigger any events. Transaction Destination Selection. This field qualifies the tracking of bus transactions by limiting event detection to those transactions directed to a specific resource. 00 Any 10 PCI Target 01 Main Memory 11 Third party reserved Event Selection. This field specifies the basic PCI bus transaction or PCI bus signal to be monitored. Individual Bus Transactions 00 0000 reserved 00 1000 reserved 00 0001 = reserved 00 1001 reserved 000010 I/O Read 001010 reserved 000011 I/O Write 001011 reserved 000100 reserved 001100 Memory Read Multiple 00 0101 reserved 001101 Dual Address Cycle 000110 Memory Read 001110 Memory Read Line 000111 Memory Write 001111 Memory Write & Invalidate Generic (Grouped) Bus Transactions 010000 Any bus transaction 010100 Any I/O transaction 010001 Any memory transaction 010101 Any I/O or memory transactions 010010 Any memory read 010110 Any I/O read or memory read 010011 Any memory write 010111 Any I/O read or memory write Bus Signal Assertions 011000 reserved 011100 reserved 011001 reserved 011101 reserved 011010 RETRY! 011110 LOCK 011011 reserved 011111 ACK64 All other encodings are reserved. Notes: 1. Counting data cycles is undefined for this selection. Intel 450NX PClset 3-433. Register Descriptions 3.4.26 3.4.27 3-44 PMR[1:0]: Performance Monitoring Response Address Offset: DDh, E5h Size: 8 bits each Default Value: | 0000h each Attribute: Read/Write There are two PMR registers for each PCI bus, one for each PMD counter. Each PMR register specifies how the event selected by the corresponding PME register affects the associated PMD register, P(A,B)MON# pins, and the INT(A,B)RQ# pins. Bits Description 7:6 Interrupt Assertion Defines how selected event affects INTRQ# assertion. Whenever INTRQ# is asserted, a flag for this counter is set in the Error Status Register, so that software can determine the cause of the interrupt. This flag is reset by writing the Error Status Register. 0 Selected event does not assert INTRQ # 1 reserved 2 Assert INTRQ# pin when event occurs 3 Assert INTRQ# pin when counter overflows 5:4 Performance Monitoring pin assertion Defines how the selected event affects the PMON# pin for this counter. 0 PMON# pin is tristated. Selected event has no effect. 1 reserved 2 Assert this counters PMON# pin when event occurs 3 Assert this counters PMON# pin when counter overflows 3:2 Count Mode Selects when the counter is updated for the detected event. 0 Stop counting. 1 Count each cycle selected event is active. 2 Count on each rising edge of the selected event. 3 Trigger. Start counting on the first rising edge of the selected event, and continue counting each clock cycle. 1:0 Reload Mode Reload has priority over increment. That is, if a reload event and a count event happen simultaneously, the count event has no effect. 0 Never reload 1 Reload when this counter overflows. 2 Reload when the other counter overflows. 3 Reload unless the other counter increments. RID: Revision Identification Register Address Offset: 08h Size: 8 bits Default Value: OOh Attribute: Read Only Intel 450NX PClset3.4.28 3.4.29 3.4 PXB Configuration Space Bits Description 7:0 Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the PXB. These bits are read only and writes to this register have no effect. RC: Reset Control Register Address Offset: 47h Size: 8 bits Default Value: Oth Attribute: Read/Write/Sticky The RC register controls the response of the PXB to XRST#. Bits Description 7:1 reserved (0) 0 Reset PCI clocks on XRST# Clearing this bit enables PCICLKA and PCICLKB to run undisturbed through reset. When set, PCI clock phase will be reset whenever XRST# is asserted. When clear, System Hard Resets, PXB Resets, Soft Resets, BINIT Resets will not disturb PCICLKA and PCICLKB. This bit is defined to be sticky so that it can only be modified by PWRGD or configuration write. Default=1. ROUTE: Route Field Seed Address Offset: C3h Size: 8 bits Default Value: 73h (A-side space) Attribute: Read/Write 62h (B-side space) Bits Description 7:4 Inbound-to-Host-Bus Route Seed. This field represents the "seed" value used to create the routing field for packets inbound to the system bus (i.e., third-party). Default: 0111b (A-side configuration space) 0110b (B-side configuration space) 3:0 Inbound-to-Memory Route Seed. This field represents the "seed" value used to create the routing field for packets inbound to memory. Default: 0011b (A-side configuration space) 0010b (B-side configuration space) Intel 450NX PClset 3-453. Register Descriptions 3.4.30 3.4.31 3-46 SMRAM: SMM RAM Control Register Address Offset: 6C-6Fh Size: 32 bits Default Value: | O00000Ah Attribute: Read/Write This register defines the System Management Mode RAM address range, and enables the control access into that range. Fields of this register which exist in the MIOC SMRAM register must be programmed to the same values. Bits Description 31 SMRAM Enable (SMRAME). If set, the SMRAM space is protected from inbound PCI bus access. If clear, this register has no effect on inbound memory accesses. Default=0. 30:24 reserved (0) 23:20 SMM Space Size. This field specifies the size of the SMM RAM space, in 64 KB increments. Oh 64KB 4h 320 KB 8h 576 KB Ch 832 KB th 128KB 5h 384 KB 9h 640 KB Dh 896KB 2h 192 KB 6h 448 KB Ah 704 KB Eh 960 KB 3h 256 KB 7h 512 KB Bh 768 KB Fh 1MB Default: Oh (64 KB). 19:16 reserved (0) 15:0 SMM Space Base Address. This field specifies the A[31:16] portion of the SMM RAM space base address (A[15:0]=0000h). The space may be relocated anywhere below the 4GB boundary and the Top of Memory (TOM); however, the base address must be aligned on the next highest power-of-2 natural boundary given the chosen size. Incorrect alignment results in indeterminate operation. Default: OO0OAh (representing a base address of AQ000h) TCAP: Target Capacity Address Offset: CO-C2h Size: 24 bits Default Value: 041082h Attribute: Read/Write This register is programmed with the maximum number of transactions and data bytes that the receiving MIOC can accept from this PXB/PCI port for inbound transactions. The MIOC space has a set of four similar TCAP registers, one per PXB/PCI bus, that is programmed with the transaction and data limits for outbound transactions. If the PXB is in 32-bit bus mode, divide the MIOC BUFSIZ limits in half. If the PXB is in 64-bit bus mode, the full MIOC BUFSIZ limits can be used, except in either case, the PXBs maximum values (shown below) cannot be exceeded. Intel 450NX PClset3.4.32 3.4.33 3.4 PXB Configuration Space Bits Description 23:18 Inbound Write Transaction Capacity. This field specifies the total number of inbound write transactions that can be forwarded and enqueued in the MIOC from this PXB/PCI port. 32-bit Bus =PXB maximum: 6 Minimum allowed: 1 Default= 1 64-bit Bus PXB maximum: 12 Minimum allowed: 1 Default= 1 17:12 Inbound Read Transaction Capacity. This field specifies the total number of inbound read transactions that can be forwarded and enqueued in the MIOC from this PXB/PCI port. 32-bit Bus = PXB maximum: 2 Minimum allowed: 1 Default= 1 64-bit Bus =PXB maximum: 2 Minimum allowed: 1 Default= 1 11:6 Inbound Write Data Buffer Capacity. This field specifies the total number of data buffers available in the MIOC for use by inbound write transactions from this PXB/PCI port, in increments of 32 bytes. 32-bit Bus PXB maximum: 6 Minimum allowed: 2 Default= 2 64-bit Bus PXB maximum: 12 Minimum allowed: 2 Default= 2 5:0 Inbound Read Data Buffer Capacity. This field specifies the total number of data buffers available in the MIOC for use by inbound read transactions from this PXB/PCI port, in increments of 32 bytes. 32-bit Bus PXB maximum: 8 Minimum allowed: 2 Default= 2 64-bit Bus PXB maximum: 16 Minimum allowed: 2 Default= 2 TMODE: Timer Mode Address Offset: C4h Size: 8 bits Default Value: OOh Attribute: Read/Write This register allows nominally fixed-duration timers to be adjusted to shorter values for test purposes. Bits Description 7:2 reserved (0) 1:0 Delayed Read Request Expiration Counter. This counter is strictly for test purposes. Changing it from the default value is a violation of the PCI specification. 00 normal mode is clocks) 01 128 clocks 10 64 clocks 11 16 clocks TOM: Top of Memory Address Offset: 50-52h Size: 24 bits Default Value: | OOOFFFh Attribute: Read/Write Intel 450NX PClset 3-473. Register Descriptions This register specifies the highest physical address that could be directed to the memory. This register applies to both host-initiated transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed identically to achieve correct functioning. See the MIOC Configuration Space for a detailed description. 3.4.34 VID: Vendor Identification Register Address Offset: 00-O1h Size: 16 bits Default Value: 8086h Attributes: Read Only Bits Description 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086n. 3-48 Intel 450NX PClsetSystem Address Maps | 4 4.1 Memory Address Map A Pentium II Xeon processor system based on the Intel 450NX PClIset supports up to 64 GBytes of addressable memory space. Within this memory address range the Intel 450NX PClIset has two structured compatibility regions, two expansion gaps, and two general purpose memory-mapped I/O spaces, as illustrated in Figure 4-1. The two compatibility regions are the 1 MB Low Compatibility Region at the bottom of the address space, and the 20 MB High Compatibility Region just below the 4 GB boundary. The two expansion gaps allow holes to be opened in the address space, where accesses can be directed to the PCI buses or to a third-party agent, instead of to memory. The two I/O spaces allow control over which addresses are forwarded to each of the four PCI buses supported by the Intel 450NX PClset. Spaces and Gaps The Intel 450NX PCIset memory address map is based on spaces and gaps. A space is an address range where the access is directed to a specific destination, usually (but not always) a PCI bus. Any DRAM behind the space is not reclaimed, unless it is also covered by a gap (described below). The Intel 450NX PClset supports a variety of spaces with fixed or configurable address ranges and individual enables. A gap is a memory-mapped address range where the access is specifically not directed to DRAM. The DRAM behind the gap is reclaimed; that is, the effective address presented to the memory has the gaps subtracted from it, presenting a contiguous address space to the memory. The gap does not control where the access is directed. Accesses may be directed through an overlapping space, or left unclaimed on the system bus for a third-party agent to claim. In typical maps, large spaces will be contained within gaps, to reclaim the DRAM that would otherwise be wasted. The Intel 450NX PClIset supports two configurable gaps. Low Compatibility Region The Low Compatibility Region spans the first IMB address range (Oh to F_FFFFh). This region is divided into five subregions, some of which are further subdivided. The 640KB DOS Region is split into a 512KB DOS area (memory only) and a 128KB ISA Window, which can be mapped to either main memory or the PCI memory. The 128KB Graphics Adapter Memory is normally mapped to a video device on the PCI bus, typically a VGA controller. This region is also the default location of the configuration SMM RAM space. Intel 450NX PClset 4-44-2 4. System Address Maps F_FFFF_FFFP 64 GB i 20 MB Total / High BIOS 2MB i mo ooo | i i 14 MB i i j Top of i Memory 1_0000_0000 i FEF0_0000 Local APIC 1MB High 4 GB FEE0_0000 1 MB Compatibility 1 MB Region FECO 0000 /O APIC 1 MB 7 A Local PC|Bus 1! High Local PC! Bus 1 Expansion Local PCI Bus 0 Gap Local PC! Bus 0 100_0000 16 MB A ; Low Low ISA Space Expansion Gap 10_0000 =a Low F 0000 System BIOS | 64K C ibili a oAecion ity 2 0000 |_EXt System BIOS} 64K |. SAT coke Channel /O 4 ISA Expansion | 428K | -8000} i C_0000 Video BIOS | 32KB \ Graphics Adapter Memory 128K 4 A_0000 Areas are not \ 80000 ISA Window | 128kB drawn to scale. \ DOS Region |640K 4 DOS Area |512KB WW 6 Figure 4-1: e System Memory Address Space The 128KB ISA Expansion Region is divided into eight 16KB blocks that can be independently configured for read/write accessibility. Typically, these blocks are mapped through the PCI bridge to ISA space. Memory that is disabled is not remapped. Traditionally, the lower 32KB contains the video BIOS located on a video card, and the upper 96KB is made available to expand memory windows in 16 KB blocks depending on the requirements of other channel devices in the corresponding ISA space. The 64KB Extended System BIOS Region is divided into four 16KB blocks and may be mapped either to memory or the compatibility PCI bus. Typically, this area is used for to be shadowed into RAM. RAM or ROM. Selecting appropriate read/write attributes for this region allows the BIOS Intel 450NX PClset4.1 Memory Address Map Top Of 1 f Memory High Gap 8 wasted Low Gap @ oO Host Bus Address Physical Memory Figure 4-2: Gaps, Spaces and Reclaiming Physical Memory The 64KB System BIOS Region is treated as a single block and is normally mapped to the compatibility PCI bus. Selecting appropriate read/write attributes for this region allows the BIOS to be shadowed into RAM. After power-on reset, the Intel 450NX PClIset has this area configured to direct accesses to PCI memory, allowing fetches from the boot ROM during system initialization. High Compatibility Region The High Compatibility Region spans 20 MB immediately below the 4 GB address boundary (address range FECO_0000h to FFFF_FFFFh). This region supports four fixed spaces with predefined functions for compatibility with PC-based systems. The 2MB High BIOS Space is where the processor begins execution after reset. Following power-on, the Intel 450NX PClIset has this space enabled; accesses will be directed to the compatibility PCI bus. If an ISA bridge is also used, this area is then aliased by the ISA bridge to the top of the ISA address range (14-16MB). If this space is disabled, accesses will be directed to memory (unless superceded by an expansion gap.) The 1MB Local APIC Space is reserved for use by the processor. In Pentium II Xeon processors, this contains the default local APIC space (which can be remapped to the I/O APIC space, below). Accesses to this region will not be claimed by the Intel 450NX PClIset. No resources should be mapped to this region. The 1MB Reserved Space is defined for future use. No resources should be mapped to this region. The 1MB I/O APIC Configuration Space provides an area where I/O APIC units in the system can be mapped, and the I/O APICs within the processors can be remapped for consistency of access. At least one 1/O APIC must be included in an Intel 450NX PClset- based system. The I/O APIC space may be relocated anywhere in the 4 GB boundary. Intel 450NX PClset 4-34. System Address Maps 4.1.1 4.1.2 Top of Memory and Expansion Gaps A Top of Memory pointer identifies the highest memory-mapped address that can be serviced by this node. Accesses to addresses above this pointer will not be directed to local memory or the PCI buses, but will be allowed to sit unclaimed on the system bus. A third- party agent on the system bus may claim such accesses, either servicing them with its own local resources or forwarding them to other nodes for service (i.e., a cluster bridge). Any access that remains unclaimed will eventually timeout in the Intel 450NX PClset; on timeout the access is claimed by the Intel 450NX PClIset and terminated. Below the Top of Memory, there are two programmable expansion gaps: the Low Expansion Gap and the High Expansion Gap. Each gap, if enabled, opens a hole in the physical address space, where accesses will not be directed to memory. Instead, these accesses may be directed to one of the PCI buses, or will be allowed to sit unclaimed on the system bus where they may be claimed by a third-party agent, as above. Both expansion gaps are defined using base and top addresses, on IMB boundaries. The Low Expansion Gap must be located above the Low Compatibility Region, and below the High Expansion Gap, the 4GB boundary, and the Top of Memory. The High Expansion Gap must be located above the enabled Low Expansion Gap, above 1MB, and below the Top of Memory. At power-on, both gaps are disabled. Memory-Mapped I/O Spaces The Intel 450NX PCIset provides two programmable I/O spaces: the Low ISA Space and the PCI Space. Both spaces allow accesses to be directed to a PCI bus. Any region defined as memory-mapped I/O must have a UC (UnCacheable) memory type, set in the Pentium II Xeon processors MTTR registers. Low ISA Space The Low ISA Space is provided to support older ISA devices which cannot be relocated above the 16 MB address limit of older systems. Accesses to this space will be directed down to the compatibility PCI bus (OA). The Low ISA Space can start on any 1 MB boundary below 16 MB, and can be of size 1, 2, 4 or 8 MB. PCI Space The PCI Space consists of four contiguous address ranges, allowing accesses to be directed to each of the four PCI buses supported by the Intel 450NX PClIset. Each address range corresponds to a PCI bus, and is configurable on 1 MB boundaries. SMM RAM Support Intel Architecture processors include a System Management Mode (SMM) that defines a protected region of memory called SM RAM. The Intel 450NX PClIset allows an SM RAM region to be defined and enabled. When enabled, memory reads and writes to addresses that fall within the SM RAM address range are protected accesses. If the configuration enables permit access, and the requesting agent asserts SMMEM+# (priveleged access), the MIOC will Intel 450NX PClset4.2 4.2 |/O Space direct the access to DRAM. Otherwise, the access will be forwarded to the compatibility PCI bus. If SMM is not enabled in the Intel 450NX PClIset, accesses are treated normally. I/O Space The Intel 450NX PClIset allows I/O accesses to be mapped to resources supported on any of the four PCI buses. The 64KB I/O address range is partitioned into sixteen 4KB segments which may be partitioned amongst the four PCI buses, as shown in Figure 4-3. Host-initiated accesses that fall within a bus I/O range are directed to that bus. Segment 0 always defaults to the compatibility PCI bus. The Intel 450NX PClsets I/O Range Register defines the mapping of I/O segments to each PCI bus. This is illustrated in Figure 4-3. Accesses that fall within an I/O address range and forwarded to the selected PCI bus, but not claimed by a device on that bus, will time-out and be terminated by the Intel 450NX PClset. lO Space Mapping to PCI Buses Seqment Confiquration ISA Alias Mode ISA Alias Mode BREE Seament + FFFF Disabled Enabled a VO xFFF XxFFF F000 Space Bus 1B xD00 xDOOF | xC00 xCO00 | VO + |OR.BUSIA | Space (top) x900 x900 Bus 1A x800 x800 | I + |OR.BUSOB 4000 (top) x500 x500 vO x400 x400 Segment 3 Space 3000 Bus 0B x100 x100 Segment x000 x000 2 ' 2000 A + |OR.BUSOA Segment /O (top) Segment 0 1000 1 Space O3FF Bus 0A Segment 0100 0000 0 + 0000 0000 Figure 4-3: |1/O Space Address Mapping The Intel 450NX PClset optionally supports ISA expansion aliasing, as shown in Figure 4-3. When ISA expansion aliasing is supported, the ranges designated as I/O Expansion are internally aliased to the 0100h-O3FFh range in Segment 0 before the normal I/O address range checking is performed. This aliasing is only for purposes of routing to the correct PCI bus. The address that appears on the PCI bus is unaltered. ISA expansion aliasing is enabled or disabled through the ISA Aliasing Enable bit in the MIOCs CONFIG register. Intel 450NX PClset 4-54. System Address Maps 4.3 Restricted-Access Addresses By default, all Host-PCI I/O writes will be posted. However, in traditional Intel-architecture systems, there are certain I/O addresses to which posting is not desirable, due to ordering side effects. Table 4-1 lists the I/O addresses for which I/O write posting will not be supported, regardless of the posting enable in the MIOCs CONFIG register. These accesses will be deferred instead. Table 4-1: Non-Postable I/O Addresses Address Function 0020h-0021h | 8259A Interrupt Controller, Master, Interrupt Masks 0060h-0064h Keyboard controller: com/status and data 0070h NMI# Mask 0092h A20 Gate O0A0h-00A1h_ | 8259A Interrupt Controller, Slave, Interrupt Masks OOFOh IGNNE#, IRQ13 OCF8h, OCFCh | PCI configuration space access PCI Configuration Space The Intel 450NX PClset provides a PCI-compatible configuration space for the MIOC, and two in the PXB -- one for each PCI bus. I/O reads and writes issued on the system bus are normally claimed by the MIOC and forwarded through the PXBs as I/O reads and writes on the PCI bus. However, I/O accesses to the OCF8h and OCFCh addresses are defined as special configuration accesses for I/O devices. Each configuration space is selected using a Bus Number and a Device Number within that bus. PCI buses are numbered in ascending order within hierarchical buses. PCI Bus #0 represents both the compatibility PCI bus as well as the devices in the Intel 450NX PClset and any third party agents attached to the system bus. The MIOC and each PCI bus within each PXB in the system is assigned a unique Device Number on Bus #0, as shown in Table 4-2. The PXBs are numbered based on the Expander bus port used. Table 4-2: Device Numbers for Bus Number 0! 2 Device Device Device Device Number Number 10h MIOC 18h 11h reserved 19h 12h | PXB 0, Bus a? 1Ah 13h PXB 0, Bus b 1Bh Intel 450NX PClset4.3 PCI Configuration Space Table 4-2: Device Numbers for Bus Number 0! 2 Device Device Device Device Number Number 14h PXB 1, Bus a 1Ch Third Party Agent 15h PXB 1, Bus b 1Dh Third Party Agent 1Eh Third Party Agent 1Fh_ | n/a* 1. Device numbers 0-15 represent devices actually on the compatibility PCI bus. 2. Shaded columns are defined for future PCIset compatibility. 3. This is the compatibility PCI bus. 4. Bus #0/Device #31 is used (along with a Function Number of all 1s and a Register Number of all 0s) to generate a PCI Special Cycle. Therefore Bus #0/Device #31 is never mapped to a device. Intel 450NX PClset 4-74. System Address Maps 4-8 Intel 450NX PClsetInterfaces | 5 3.1 5.2 5.3 System Bus The host interface of the Intel 450NX PClset is targeted toward Pentium II Xeon processor-based multiprocessor systems, and is specifically optimized for four processors sharing a common bus with bus clock frequencies of 100 MHz. The MIOC provides the system bus address, control and data interfaces for the Intel 450NX PClIset, and represents a single electrical load on the system bus. The Intel 450NX PClIset recognizes and supports a large subset of the transaction types that are defined for the P6 family processors bus interface. However, each of these transaction types have a multitude of response types, some of which are not supported by this controller. The responses that are supported by the MIOC are: Normal without Data, Normal with Data, Retry, Implicit Write Back, Deferred Response. Refer to the chapter on Transactions for more details on the transaction types supported by the Intel 450NX PClset. PCI Bus Each PXB provides two independent 32-bit, 33 MHz Rev. 2.1-compliant PCI interfaces which support 5 volt or 3 volt PCI devices. Each bus will support up to 10 electrical loads, where the PXB and the PIIX4E south bridge each represent one load, and each connector/device pair represents two loads. The internal bus arbiter supports six PCI bus masters in addition to the PXB itself and the south bridge on the compatibility bus. The compatibility bus is always bus #OA (PXB #0, Bus A). The PCI buses are operated synchronously with the system bus, using the system bus clock as the master clock. A system bus/PCI bus clock ratio of 3:1 supports the Pentium II Xeon processor at 100 MHz with 33.3 MHz PCI bus, or a degraded 90 MHz system bus with a 30 MHz PCI bus (or lower, depending on the effect of the 6th load on the system bus). A configuration option allows the two 32-bit PCI buses (A and B) on a single PXB to be operated in combination as a single 64-bit PCI bus. Bus A data represents the low Dword, while bus B data represents the high Dword. Expander Bus The Expander Interface provides a bidirectional path for data and control between the PXB and MIOC components. The Expander bus consists of a 16 bit wide data bus which carries command, address, data, and transaction information. There are two additional bits that carry Intel 450NX PClset 5-1| 5. Interfaces 5.3.1 3.4 Byte enable information for data fields. All 18 of these bits are protected by an even parity signal. Two synchronous arbitration signals (one in each direction) are used for each Expander bus. Expander Electrical Signal and Clock Distribution The Expander bus is designed to allow multiple high bandwidth I/O ports to be added to the Intel 450NX PCIset with minimal impact on signal pin count. The Expander bus also provides flexibility in server system topology by allowing the I/O subsystem to be located away from the main PCIset. This flexibility is achieved with a signaling scheme that uses a combination of synchronous and source synchronous clocking. This is illustrated in Figure 5-1. Expander Bus rT TTT TT 4 | HRTS# MIOC > XRTS. ___| PXxB | XADS# . | =e_____XPAR__ #8) 4 _ | p> | HSTBP# ~ ~ Strobe |p | HSTBN# | Synch ASIBP <_} qj] XSTBN# <H] Strobe Synch | XB XRSTBA ) (1) | RST He | xaste aa) | | | ee R ng PLL HCLKIN 4 xo on ) (L4) be 4 8 PLL FB Required length matching: L1=L2=L3=L4 Core CLK Figure 5-1: Expander Bus Clock Distribution Third-Party Agents In addition to the processors and the Intel 450NX PClset, the Pentium II Xeon processor bus allows for additional bus masters, generically referred to as third-party agents (TPA). These agents may be symmetric agents, in which case they must participate in the bus arbitration algorithm used by the processors. They may also be priority agents, in which case they must negotiate with the Intel 450NX PClIset for control of the system bus. Intel 450NX PClset3.9 5.5 Connectors The Intel 450NX PCIset supports the same request/grant and third-party control signals originally provided by the Intel 450GX PClset. Theses signals are used to exchange priority ownership of the bus between the TPA and the Intel 450NX PCIset. The Intel 450NX PClset makes no assumptions about the relative priorities between the Intel 450NX PClIset and the TPA, and will grant priority ownership at the next natural transaction boundary. The Intel 450NX PCIset also makes no assumptions about the frequency of TPA requests or the duration of TPA bus ownership; it is the responsibility of the TPA to ensure that its use of the system bus is commensurate with its intended purpose and expected system performance. Connectors Connectors are permitted only for the memory cards and between the MIOC and PXBs. Between MIOC and PXB, some degree of stretch distance is possible, with specific distance dependent on the design and medium chosen. Connectors are specifically not permitted between the MIOC and the system bus. Intel 450NX PClset 5-3| 5. Interfaces | 5-4 Intel 450NX PClsetMemory Subsystem | 6 6.1 6.1.1 Overview The Intel 450NX PClsets memory subsystem consists of one or two memory cards. Each card is comprised of one RCG component, a DRAM array, and two MUX components. Table 6-1 summarizes the Intel 450NX PClsets general memory characteristics. Table 6-1: General Memory Characteristics DRAM type Extended Data Out (EDO) Memory modules 72-bit, single and double high DIMMs DRAM technologies | 16 Mbit and 64 Mbit 50 and 60 nsec 3.3V Interleaves 4:1, 2:1 (in bank 0, of card 0) Memory size 2:1 interleave: 32 MB 4:1 interleave: 64 MB to 8 GB, in 64 MB increments Physical Organization The Intel 450NX PClIset supports up to 8 banks of memory, configured across one or two memory cards. Each bank can support up to 1GB using 64 Mbit double-high DIMMs to provide a total of 8 GB of memory in 8 banks. Each bank can support one or two rows of 2 or 4 interleaves. Each row represents a set of memory devices simultaneously selected by a RAS# signal. Each interleave generates 72 bits (64 data, 8 ECC) of data per row using one DIMM. Four interleaves provide a total of 256 bits of data (32 bytes) which is one cache line for the Pentium II Xeon processor. Data from multiple interleaves are combined by the MUXs to exchange 72 bits of data with the MIOC at an effective rate of one cache line every 30ns (effective rate: 1.067GB/s) for a 4-way interleaved memory. Figure 6-1 illustrates this configuration. The RCG and MUX Components The RCGs generate the signals to control accesses to the main memory DRAMs. The RCG initiates no activity until it receives a command from the MIOC. The maximum number of RCGs per Intel 450NX PClset system is two. Each RCG controls up to four banks of DRAM. Each bank of memory may consist of one (for single-sided DIMMs) or two (for double-sided or double-high DIMMs) rows. Internally, each RCG component contains four RAS/CAS control units (RCCUs), each dedicated to one bank of DRAM. This is illustrated in Figure 6-2. Each MUX component has four 36-bit data 1/O connections to DRAM (one 18-bit path for each of four possible interleaved quad-words) and one 36-bit data I/O connection to the MD Intel 450NX PClset 6-16. Memory Subsystem Pentium Il Xeon processor system bus { addr[35:0], data[7 1:0] & ctris MIOoc MD[71:0] Memory Control Interface _ _ _ | | to PCl via Expander bridge Figure 6-1: Memory Configuration using 2 Cards To/From MIOCG tt a Memory Array o Oe reo 5 / oF =. s RASAla-d][1 -0]#, CASAla-d][1-0]#, WEA[aib]# S8m<z oO | | Oo-r2ca ADDRA[13:0] A Bank A > RASB[a:d][1-0]#, CASB[a:d][1-0]#, WEBlaib]# _ T T a ADDRB[13:0] Bank B RCG vy #0 RASCIa:d][1:0}#, CASC[a:d][1:0]#, WEC[4:-b]# I I I ADDRC[13:0] Bank C RASDIa:d][1:0}#, CAS D[a-d][1 -0]#, WEDIebI# I | | 2 # ADDRD[13:0] x Bank D a AVWP# LDSTB#| : LRD# MUXs (2) | To/From Other RCGs WDME# DOEFI ow RSELE 0] DCMPLT[a:b]# GDCMPLT# DVALID[a:b]}# DSTBP[3:0]# WDEVT# DSTBN[3:0]# To/From Other MUXs From MIOG To/From MIOC Figure 6-2: Example Showing RCG/MUX Control Signals 6-2 Intel 450NX PClset6.1.2 6.1.2.1 6.1 Overview bus. There are two MUX components per board to provide a 72-bit data path from each of four possible interleaved quad-words to the MD bus. This is illustrated in Figure 6-3. aooong mmm 90099 Memory LEER gees Card AaAa AaAa COOoC09d COOoC09d MUX MUX A ache A see a NIN ele 9} gale, o] OS ) ote io] BS ny oO See al Bh, QO] nln s| Ala =) ajo MD[71:0] > DSTBP[3:0#, - DSTBN[3:0]# To MIOC To other memory card Figure 6-3: Memory Card Datapath Configuration Rules and Limitations Memory array configurations are governed by the following rules: Either one or two cards can be populated in a working system. Any number of memory rows, on either card, can be populated in a working system. Memory banks can be populated in any order on either card. Cards designed to support 4:1 interleaving will also support 2:1 interleaves (in the first bank only). Within any given row, the populated interleaves must have DIMMs of uniform size. Memory sizes (16 Mb vs. 64 Mb) may be mixed within a memory card, but must be the same within a bank. Memory speeds (60ns or faster) may be mixed, but all four banks within an RCG operate at the same speed, and must therefore be configured to the slowest DIMM in the set. Interleaving The Intel 450NX PClIset supports 4:1 interleaving across all banks, and 2:1 interleaving in the first bank of card #0 only. The Intel 450NX PClIset does not support non-interleaved configurations. Interleave configuration register programming must be consistent across the entire memory system. For example, if one bank is configured as 4:1 then the entire memory sub-system must be 4:1 and the associated memory bank configuration registers must be programmed as 4:1. To support a 4:1 interleave requires two MUXs. Supporting a 2:1 interleave requires only one MUX. A two-MUX design will also support 2:1 interleaves. An entry-level card (Le., 2:1 Intel 450NX PClset 6-36. Memory Subsystem 6.1.2.2 6.1.2.3 interleave) that may be expanded beyond the first bank must therefore be designed using two MUxs. Table 6-2 gives a summary of the characteristics of memory configurations supported by the Intel 450NX PClIset for 4-way interleaved memory cards. Table 6-2: Minimum and Maximum Memory Size per Card Addressing Memory size for 4-way interleave Technology & . ; . (Double- Contig. Size Mode Size Min Max high row/col | (DIMMs) | (DIMMs) DIMMs) 16M| 2Mx8) 2Mx72| Asymmetric | 11] 10 64MB;} 256MB; 512 MB 4M x4 4M x72 | Symmetric 11} 11) 128MB| 512 MB 1 GB Asymmetric | 12] 10 64M| 8Mx8| 8Mx72]| Asymmetric | 12] 11) 256 MB 1 GB 2 GB 16Mx4/} 16M x 72 | Symmetric 12} 12) 512MB 2 GB 4 GB Asymmetric | 13] 11 Address Bit Permuting Rules and Limitations The Intel 450NX PClIset supports permuting of cache lines across two or four populated banks. For a complete description of the operation of Address Bit Permuting (ABP) see 6.1.3. The following rules and limitations are required for ABP to operate properly. e All banks must be in 4:1 interleave mode. There must be a power of two number of banks populated. e All banks within an ABP group (2 banks in 2 bank permuting and 4 banks in 4 bank permuting) must be the same size. All populated rows must be adjacent and start at bank 0. Both cards in a system must be configured to allow equivilent ABP settings (i.e., Card 0 and Card 1 must both be configured according to the above rules for the current setting of the ABP enable.) Card to Card (C2C) Interleaving rules and limitations Card to Card Interleaving is described in detail in 6.1.4. All of the ABP rules defined above apply to C2C interleaving, plus the following rules: The memory cards must be identically populated with memory DIMMs of the same size and type. e The DBC registers must be programmed in the alternate C2C order as defined in the C2C functional description in 6.1.4. Intel 450NX PClset6.1.3 6.1.4 6.1 Overview Address Bit Permuting Address Bit Permuting works by increasing the likelihood that requests spaced closely together in time access different banks of memory which will already be closed and precharged. This is achieved by distributing the addresses, on a cache line size granularity, across either two or four banks of memory. The lowest order address bits which define a cache line are used as the bank selects into the memory array so that all requests to a zero based cache line are directed at bank 0. This is illustrated in Figure 6-4. Request address accesses bank: 4 Bank Permuting Oh, 80h, 100h, .... 20h, AOh, 120h, ... 40h, COh, 140h,... 60h, EOh, 160h, ... Request address accesses bank: Oh, 40h, 80h, .... 20h, 60h, AOh, ... 2 Bank Permuting Figure 6-4: Effect of Address Bit Permuting on Bank Access Order Card to Card (C2C) Interleaving The purpose of the C2C feature is to further distribute memory accesses across multiple banks of memory as done with the ABP modes. This mode is supported in addition to the standard ABP modes so that maximum distribution of memory accesses and hence, maximum sustained bandwidth can be acheived. The distribution of accesses to each memory card with C2C enabled is by cache line with all even cache lines sent to Card 0 and all odd cache lines sent to Card 1. The feature can be enabled, if all of the restricions are met, by setting bit 2 of the MIOC CONFIG register. With C2C enabled the DRAM Bank Configuration Registers become mapped to the physical memory differently than with C2C disabled (default mode). Figure 6-5 shows both the C2C disabled and enabled modes mapping of DRAM Bank Configuration Registers to physical bank location. With C2C enabled and 2 bank ABP enabled Banks 0, 1, 2 and 3 must all be the same size and type and Banks 4, 5, 6 and 7 (if present) must be the same size and type. With C2C enabled and 4 bank ABP enabled Banks 0 through 7 must all be the same size and type. Intel 450NX PClset 6-56. Memory Subsystem With C2C enabled and no ABP enabled each pair of consecutive banks must be of the same size and type. For example Banks 0 and 1 must be the same size and type and Banks 2 and 3 must be the same size and type but need not match Banks 0 and 1. C2C Disabled Bank Register Ordering Memory Card 0 Memory Card 1 C2C Enabled Bank Register Ordering Memory Card 0 Memory Card 1 Figure 6-5: DRAM Bank Configuration register programming with C2C Disabled and Enabled 6.1.5 Memory Initialization The MIOC provides an MRESET# output, which is asserted on power-good reset, system hard reset, and a BINIT reset. The MRESET# signal is sent to all RCGs and MUXs in the memory subsystem. When asserted, each RCG and MUxX clears their transaction queues, data buffers and transaction state. Any transactions that may have been in-progress or pending in the memory subsystem are lost. Note that this may corrupt the contents of the DRAMs, and could leave the DRAMs themselves in an intermediate state, unable to accept a new transaction. Following MRESET# deassertion, the MIOC will re-initialize the memory subsystem by issuing eight CAS#-before-RAS# refreshes per bank (this does not affect the data held in the memory). 6-6 Intel 450NX PClsetTransaction Summary | 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 This chapter describes the transactions supported by the Intel 450NX PClset. Host To/From Memory Transactions Reads and Writes The Read transactions supported by the Intel 450NX PClset are: Partial Reads, Part-line Reads, Cache Line Reads, Memory Read and Invalidate (length > 0), Memory Read and Invalidate (length = 0), Memory Read (length = 0). The Write transactions supported by the Intel 450NX PClIset are: Partial Writes, Part-line Writes, Cache Line Writes. Cache Coherency Cycles The MIOC implements an implicit writeback response during system bus read and write transactions when a system bus agent asserts HITM# during the snoop phase. In the read case the MIOC snarfs the writeback data and updates the DRAM. The write case has two data transfers: the requesting agents data followed by the snooping agents writeback data. Interrupt Acknowledge Cycles A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an 8259-compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial read transaction, except that the address bus does not contain a valid address. The interrupt acknowledge request issued by the processor is deferred by the MIOC and forwarded to PXB #0, which performs a PCI Interrupt Acknowledge cycle on PCI bus #0A (the compatibility PCI bus). Locked Cycles The system bus specification provides a means of performing a bus lock. Any Host-PCI locked transaction will initiate a PCI locked sequence. The processor implements the bus lock Intel 450NX PClset 7-17. Transaction Summary 7.1.5 7.1.6 mechanism which means that no change of bus ownership can occur from the time the agent has established the locked sequence (i.e., asserts LOCK# signal on the first transaction and data is returned) until it is completed. The DRAM is locked from the PCI perspective until the host locked transaction is completed. Branch Trace Cycles An agent issues a Branch Trace Cycle for taken branches if execution tracing is enabled. The address Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carries the linear address of the instruction causing the branch and D[31:0]# carries the target linear address. The MIOC will respond and retire this transaction but will not latch the value on the data lines or provide any additional support for this type of cycle. Special Cycles Special cycles are used to indicate to the system some internal processor conditions. The first address phase Aa[35:3]# is undefined and can be driven to any value. The second address phase, Ab[15:8]# defines the type of Special Cycle issued by the processor. Table 7-1 below specifies the cycle type and definition as well as the action taken by the MIOC when the corresponding cycles are identified. Table 7-1: MIOC Actions on Special Cycles Ab[15:8] | Cycle Type Action Taken 0000 0000 | NOP This transaction has no side-effects. 0000 0001 | Shutdown This cycle is claimed by the MIOC. No corresponding cycle is delivered to the PCI bus. The MIOC asserts INIT# back to the agent for a minimum of 4 clocks. 0000 0010 | Flush The MIOC claims this cycle and retires it. 0000 0011 | Halt This cycle is claimed by the MIOC, forwarded to the compatability PCI bus as a Special Halt Cycle, and retired on the system bus after it is terminated on the PCI bus viaa master abort mechanism. 0000 0100 | Sync The MIOC claims this cycle and retires it. 0000 0101 | Flush The MIOC claims this cycle and retires it. Acknowledge 0000 0110 | Stop Clock This cycle is claimed by the MIOC and propagated to the Acknowledge | PCI bus asa Special Stop Grant Cycle. It is completed on the system bus after it is terminated on the PCI bus via a master abort mechanism. 0000 0111 | SMI The MIOCs SMIACT# signal will be asserted upon Acknowledge | detecting an SMI Acknowledge cycle with SMMEM# asserted, and will remain asserted until detecting a subsequent SMI Acknowledge cycle with SMMEM# deasserted. all others | Reserved Intel 450NX PClset7.1.7 7.1.8 7.1 Host To/From Memory Transactions System Management Mode Accesses The Intel 450NX PCIset uses an SMRAM configuration register to enable, define and control access to the SMM RAM space. The SMM RAM space defaults to location AOOOh, with a size of 64 KB, but may be relocated and grown in increments of 64 KB. A master enable (SMRAME) and three access-control enables (Open, Closed, Locked) determine how accesses to the space are to be serviced. Table 7-2 summarizes how accesses to the SMM RAM space are serviced. Table 7-2: SMRAM Space Cycles Code Data Fetch Reference Usage Normal! | Normal! | SMM RAM space is not supported. PCI 0a PCI 0a Normal SMM usage. Accesses to the SMM RAM space from processors in SMM will DRAM DRAM access the DRAM. Accesses by processors not in SMM will be diverted to the compatibility PCI bus. 1), 0/1) X]} 0 |) PCI 0a PCI 0a A modification of the normal SMM usage, in 4/0114/x/I4 lpRAM PCI Oa which only code fetches are accepted from processors in SMM mode. 1) 1)X {04} X |}DRAM DRAM Full access by any agent to SMM RAM space. Typically used by the BIOS to initialize SMM RAM space. 1. SMRAM functions are disabled. The access is serviced like any other. The address is checked against the other space and gap definitions to determine its disposition -- to PCI, to memory, or to the system bus for a third party agent to claim. | oO] SMRAME o| x| D_OPEN o| x| C_CODE |x| C_LCK o| x| SMMEM oO oO x a Third-Party Intervention The Intel 450NX PClIset supports the same third-party control sideband controls that were defined in Intel 450GX PClIset. These controls allow an external agent on the system bus to affect the way in which the MIOC responds to a system bus request to memory. This external agent is referred to as a third-party to the transaction. When a third-party agent intervenes in the normal transaction flow, both the MIOC and the third-party share responsibility for generating the appropriate response; however, the MIOC is always the owner of the transaction, and hence must be the responding bus agent. The third-party controls how the MIOC responds by asserting a code on the sideband TPCTL[1:0] signals during the snoop phase. The MIOC samples these signals in the last cycle of the snoop phase. Table 7-3 indicates the actions possible using the TPCTL[1:0] signals. Intel 450NX PClset 7-37. Transaction Summary 7.2 7.2.1 7.2.2 7.2.3 7.2.4 Table 7-3: TPCTL[1:0] Operations TPCTL [1:0] Action 00 Accept. The MIOC accepts the request, and provides the normal response. The third-party agent is not involved in the transaction. 01 Hard Fail. Not supported by the Intel 450NX PClset. 10 Retry. The MIOC will generate a retry response. The access will be retried by the requesting agent. 11 Defer. The MIOC will issue a defer response, and the third-party agent will complete the transaction at a later time using a deferred reply. Outbound Transactions Supported Outbound Accesses The PXB translates valid system bus commands into PCI bus requests. For all Host-PCI transactions the PXB is a non-caching agent since the Intel 450NX PClIset does not support cacheability on PCI. However, the PXB must respond appropriately to the system bus commands that are cache oriented. Outbound Locked Transactions The Intel 450NX PCIset supports memory-mapped outbound locked operations. I/O- mapped outbound locked transactions are not supported. Further, a locked transaction cannot be initiated with a zero-length read. These restrictions are consistent with the transactions supported by the processor. Outbound Write Combining The Intel 450NX PClIset provides its own write combining for Host-PCI write transactions. If enabled, and multiple Host-PCI writes target sequential locations in the PCI space, the data is combined and sent to the PCI bus as a single write burst. This holds true for all memory attributes, not just WC. There is no corresponding write-combining for the Host-DRAM path. Third-Party Intervention on Outbounds The use of the third-party control signals (TPCTL) is not supported for outbound transactions (Host-PCD. Assertion of the TPCTL signals during an outbound transaction will have Intel 450NX PClset7.3 7.3.1 7.3.2 7.3 Inbound Transactions indeterminate results. Assertion of DEFER# during an outbound transaction will also have indeterminate results. Inbound Transactions For all inbound transactions, the Intel 450NX MIOC will use an Agent ID of 1001b (9). This is the same agent ID used by the Intel 450GX PClset, which the Intel 450NX PClIset replaces. Note that memory-mapped accesses across PCI buses (i.e., peer-to-peer transfers) are not supported. Also, inbound I/O transactions are not supported, either to other PCI buses or to the system bus. Inbound LOCKs Inbound (PCI-to-system bus) LOCKs are not supported in the Intel 450NX PClset. Use of inbound locks on the Intel 450NX PClIset may result in unanticipated behavior. The Intel 450NX PCISet is NOT compatible with devices on the compatibility PCI bus which are capable of initiating inbound bus- or resource-locks. Deadlock may occur between outbound locked transactions, south bridge-initiated Secure Sideband Requests (PHOLD#), and LOCK# assertion by the offending device. Devices capable of asserting LOCK# to access memory should not be used on the compatibility PCI bus. South Bridge Accesses The PXBs Bus a has sideband signals to support the PIIX4E south bridge for ISA expansion. The PXB does not support an EISA bridge. WSC# Handshake When the PIEX4E south bridge issues an interrupt for an ISA master, it must first check that any writes posted from ISA to memory have been observed before the interrupt is issued. This action is necessary to guarantee that an ISA write followed by an ISA interrupt is observed in that same order by a processor on the system bus. Whenever the compatibility bus PXB receives a write from the south bridge, it will deassert the WSC# (Write Snoop complete) signal. WSC# will remain de-asserted until the write Completion for that write has returned. When the Completion returns, WSC# is again asserted. While WSC# is de-asserted the PXB must retry any additional writes from the south bridge. The PXB will only support the WSC# Handshake when the internal arbiter is used. When operating in external arbiter mode, the PXB will always hold WSC# asserted. The WSC# mode may be disabled by a bit in the PXBs CONFIG register. If disabled, WSC# stays asserted and inbound writes from the south bridge are accepted. Intel 450NX PClset 7-57. Transaction Summary 7.4 Distributed DMA Distributed DMA across the PCI bus is not supported by the Intel 450NX PClIset. This function is incompatible with the passive release mechanism portion of the PHOLD#/PHLDA# protocol used to grant PCI bus access to south bridges. Accesses Prohibited to Third-Party Agent The Intel 450NX PClIset only supports inbound south bridge accesses to memory. Inbound accesses from a south bridge using the PHOLD#/PHLDA# protocol, directed to a third-party agent on the system bus, are not supported. Such accesses, involving interactions with unknown and unpredictable agents, could violate the rules governing the PHOLD#/PHLDA# protocol, potentially leading to deadlocks. Configuration Accesses The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The Intel 450NX PClIset supports only Mechanism #1. Mechanism #1 defines two I/O-space locations: an address register (CONFIG_ADDRESS) at location OCF8h, and a data register (CONFIG_DATA) at location OCFCh. The Intel 450NX PClset provides a PCI-compatible configuration space for the MIOC, and one for each PCI bus in the PXB. e If the MIOC detects the I/O request is a configuration access to its own configuration space, it will service that request entirely within the MIOC. Reads result in data being returned to the system bus. e Ifthe MIOC detects the I/O request is a configuration access to a PXB configuration space, it will forward the request to the appropriate PXB for servicing. The request is not forwarded to a PCI bus. Reads will result in data being returned by the PXB through the MIOC to the system bus. e If the MIOC detects the I/O request is a configuration access to a third-party agent on the system bus, it will leave the access unclaimed on the system bus. The third-party agent may claim the access, with reads resulting in data being returned by the third-party agent to the system bus. Otherwise, the access is forwarded on to the PXB to be placed on the PCI bus as a Configuration Read or Configuration Write cycle. Reads will result in data being returned through the PXB and MIOC back to the system bus, just as in normal Outbound Read operations. Intel 450NX PClsetArbitration, Buffers & Concurrency | 8 8.1 8.2 PCI Arbitration Scheme The PCI Specification Rev 2.1 requires that the arbiter implement a fairness algorithm to avoid deadlocks and that it assert only a single GNT# signal on any rising clock. The arbitration algorithm is fundamentally not part of the PCI Specification. The PXB contains an internal PCI arbiter. This arbiter can be disabled either when the PXB operates with I/O bridges which include this function, or when a customized PCI arbiter solution is required. The Internal PCI Arbiter has the following features: Support for 6 PCI masters, Host and I/O Bridge 2Level Round Robin Bus Lock Implementation Bus Parking on last agent using the bus e 4-PCI clock grant (FRAME#) time-out e = Multi Transaction Timer (MTT) mechanism PCI arbitration is independent from the system bus arbitration e PIIX4E- compatible protocol (EISA bridges are not supported) PCI Protocol Requirements Host Arbitration Scheme The system bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The processors arbitrate for the system bus as symmetric agents using their own signaling. Symmetric agents implement fair, distributed arbitration using a round-robin algorithm. The MIOC, as an I/O agent, uses a priority agent arbitration protocol to obtain the ownership of the system bus. Priority agents use the BPRI# signal to immediately obtain bus ownership. Besides two classes of arbitration agents (symmetric and priority agents), each bus agent has two mechanisms available that act as arbitration modifiers: the bus lock (LOCK#) and the request stall (BNR#). Intel 450NX PClset 8-18. Arbitration, Buffers & Concurrency 8.2.1 8.3 8.3.1 Third Party Arbitration The Intel 450NX PClset requests the system bus with BPRI#. If multiple bridges or a third party agent is on the system bus, an arbitration method is required to establish bus ownership among multiple requesting bridges (which bridge can drive BPRI#). This arbitration is transparent to the Pentium II Xeon processors or other symmetric bus agents. Only one bridge is allowed to drive BPRI# at a time. South Bridge Support The Intel 450NX PClset is designed to work with the PIIX4E south bridge which connects the PCI bus to ISA bus and I/O APIC components. Note that the protocols described here apply only when the Intel 450NX PClIset is used in internal arbiter mode - use of the PIIX4E in external arbiter configurations is not supported. The Intel 450NX PCIset does not guarantee ISA access latencies of < 2.5 usec. ISA devices which require these latencies to be met (GAT mode timing) are not supported. I/O Bridge Configuration Example. The basic I/O bridge configuration supported by the Intel 450NX PClset is shown in Figure 8- 1. The figure shows the sideband signals that connect the PXB to the PIIX4E, 1/O APIC components and the external arbiter. Note that PHOLD#/PHLDA# are connected between PXB and the PIIX4E, and WSC# output from PXB is connected to the APICACK2# input of the stand-alone I/O APIC component. If the configuration does not have I/O APIC component, then WSC# pin is left unconnected. ages REQ#(0:5] QT) >= PHLDA# EXTARBK NC PHOLD# PXB WSC# ' PCI bus PHOLD# APICREQ# | APICREQ# PHLDA# APICACK# APICACK# APICACK2 PUX4E VO APIC Figure 8-1: ISA bridge with the I/O APIC (internal arbiter) Intel 450NX PClset8.3.2 8.3.3 8.3 South Bridge Support PHOLD#/PHLDA# Protocol The PIIX4E uses only two signals to obtain the ownership of the PCI bus. The PIIX4E will assert PHOLD# to indicate that an ISA master is requesting to run a cycle (DREQ active) or an integrated PCI-IDE bus-mastering device is requesting the PCI bus. l DREQ# | \, l l DGNT# I I I I I I I <PCl req from PIIX> \ | passive bus PHOLD# | \ release PHLDA# <Host-PCl writes disabled> <other PCI trans> Figure 8-2: PHOLD#/PHLDA# protocol showing active and passive bus release WSC# Protocol The WSC# (Write Snoop Complete) is a status signal output from the Intel 450NX PClIset PXB. The WSC# assertion indicates that all necessary snoops for a previously posted PCI-DRAM write have been completed on the system bus. The WSC# signal is primarily used by the I/O APIC device connected to the ISA bridge. The I/O APIC uses this signal to maintain data coherency and ordering of transactions in the system. NOTE The WSC# Handshake only applies if the PXB is in internal arbiter mode. Intel 450NX PClset 8-38. Arbitration, Buffers & Concurrency PCLK * VA VS VS FRAME# LV C/BE# X AD(31:0)# X ef) fl olc IRDY# DEVSEL# \ STOP# TRDY# Vi WSC# / PHOLDA# Figure 8-3: WSC# Signal Functionality 8-4 Intel 450NX PClsetData Integrity & Error Handling | 9 9.1 9.1.1 9.1.2 9.1.3 This chapter describes the data integrity support and general error detection and reporting mechanisms used in the Intel 450NX PClset. DRAM Integrity Both the system data bus and the Intel 450NX PClIsets memory subsystem use a common Error Correcting Code which provides SEC/DED/NED coverage. The ECC used is capable of correcting single-bit errors and detecting 100% of double-bit errors over one code word. ECC Generation When enabled, the DRAM ECC mechanism allows automatic generation of an 8-bit protection code for the 64-bit (Qword) of data during DRAM write operations. Note that when ECC is intended to be enabled, the whole DRAM array must be first initialized by doing writes before the DRAM read operations can be performed. This will establish the correlation between 64-bit data and associated 8-bit ECC code which does not exist after power-on. This function is not provided by hardware. ECC Checking and Correction During DRAM read operations, a full Qword of data (8 bytes) is always transferred from the DRAM to the MIOC regardless of the size of the originally requested data. Both 64-bit data and 8-bit ECC code are transferred simultaneously from the DRAM to the MIOC. The ECC checking logic in the MIOC uses the received 72 bit Data + ECC to generate the check syndrome. If a single-bit error is detected the ECC logic corrects the identified incorrect data bit. ECC Error Reporting When ECC checking is enabled, single-bit and multiple-bit errors detected by the ECC logic are logged in the MIOC. The first two errors detected on reads-from-memory are logged, as are the first two errors detected on data received from the system bus. For memory errors, the error type (single-bit or multi-bit), syndrome, chunk and effective address are logged. The first two memory errors (single-bit or multi-bit) will be logged in the Intel 450NX PClset 9-19. Data Integrity & Error Handling 9.1.4 9.1.5 9.2 MEL and MEA registers. For bus errors, the error type, syndrome and chunk are logged. The first two system bus errors (single-bit or multi-bit) will be logged in the HEL registers. All ECC error logging registers are sticky through reset, allowing software to determine the source of an error after restoring the system to functioning mode. The logging registers hold their values until explicitly cleared by software. Error Signaling Mechanism Single-bit correctable errors are not critical from the point-of-view of presenting the correct value of data to the system. The DRAM (if the cause of error is a DRAM array) will still contain faulty data which will cause the repetition of error detection and recovery for the subsequent accesses to the same location. Multi-bit uncorrectable errors are fatal system errors and will cause the MIOC to assert the BERR# signal if enabled in the ERRCMD register. The uncorrected data is forwarded to its destination. For the first two multi-bit uncorrectable errors, the MIOC will log in the MEA register the row number where the error occurred. This information can be used later to point to a faulty DRAM DIMM. The MEA/MEL registers log only the first two errors. After the first two errors have been logged, the MEA/MEL registers will not be updated. However, normal error detection still continues, the ERR[1:0]# and BERR# signals are still asserted as appropriate, and scrubbing of the memory still continues. Memory Scrubbing The Intel 450NX PClIset provides a scrub-on-error (demand scrubbing) mechanism, wherein corrected data for single-bit errors will be automatically written back into the memory subsystem by the MIOC. Note that this is not the same as walk-through scrubbing, in which every memory location is systematically accessed, checked and corrected on a regular basis. The scrub-on-error mechanism will scrub only those locations accessed during normal operation and thus complements the software controlled walk-through scrubbing. Debug/Diagnostic Support The MIOC supports in-system testing of ECC functions. An ECC Mask Register (ECCMSK) can be programmed with a masking function. Subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of the memory locations written while masked will return an invalid ECC code. If the mask register is left at Oh (the default), the normal computed ECC is written to memory. System Bus Integrity A variety of system bus error detection features are provided by the MIOC. Particularly, the system data bus is checked for ECC errors on Host-DRAM and Host-PCI writes. Intel 450NX PClset9.2.1 9.3 9.4 9.3 PCI Integrity Additionally, the MIOC supports parity checking on the system address and request/response signals. System Bus Control & Data Integrity The MIOC detects errors on the system data bus by checking the ECC provided with data and the parity flag provided with control signals. In turn, the MIOC will generate new ECC with data and parity with control signals so that bus errors can be detected by receiving clients. The request control signals ADS# and REQ#[4:0] are covered with the Request Parity signal RP#, which is computed as even parity. This ensures that it is deasserted when all covered signals are deasserted. The address signals A#[35:3] are covered by the Address Parity signal AP#[1:0], which is also configured for even parity. This ensures that each is deasserted when all covered signals are deasserted. AP#[1] covers A#[35:24] and AP#[0] covers A#[23:3]. Response signals RS#[2:0] are protected by RSP#. RSP# is computed as even parity. This ensures that it is deasserted when all covered signals are deasserted. PCI Integrity The PCI bus provides a single even-parity bit (PAR) that covers the AD[31:0] and C/BE#[3:0] lines. The agent that drives the AD[31:0] lines is responsible for driving PAR. Any undefined signals must still be driven to a valid logic level and included in the parity calculation. Parity generation is not optional on the PCI bus; however, parity error detection and reporting is optional. The PXB will always detect an address parity error, even if it is not the selected target. The PXB will detect data parity errors if it is either the master or the target of a transaction, and will optionally report them to the system. Address parity errors are reported using the SERR# signal. Data parity errors are reported using the PERR# signal. The ERRCMD (Error Command) register provides the capability to configure the PXB to propagate PERR# signaled error conditions onto the SERR# signal. Expander Bus Each Expander bus has a parity bit covering all data and control signals for each clock cycle. Parity is generated at the expander bus interface by the sender, and checked at the expander bus interface in the receiver. Detected parity errors are reported at the receiving component -- outbound packets report parity errors in the PXB, while inbound packets report parity errors in the MIOC. Intel 450NX PClset 9-39. Data Integrity & Error Handling 9-4 Intel 450NX PClsetSystem Initialization |10 10.1 10.1.1 10.1.1.1 Post Reset Initialization Reset Configuration using CVDR/CVCR All system bus devices must sample the following configuration options at reset: Address/request/response parity checking: Enabled or Disabled AERR# detection enable BERR# detection enable BINIT# detection enable FRC mode: Enabled or Disabled Power-on reset vector: 1M or 4G In-Order Queue depth: 1 or 8 APIC cluster ID: 0, 1, 2, or 3 Symmetric agent arbitration ID: 0, 1, 2,3 The MIOC provides both the Symmetric Arbitration ID parameter and other parameters. (Refer to the CVDR register description.) Configuration Protocol A Pentium IT Xeon processor-based system is initialized and configured in the following manner. 1. The system is powered. The power-supply provides resets for the Intel 450NX PClset through the PWRGD signal. The MIOC and PXBs assert their resets while the PWRGD signal is not asserted. PCI reset is driven to tristate the PCI buses in order to prevent PCI output buffers from short circuiting when the PCI power rails are not within the specified tolerances. All Intel 450NX PCIset components are initialized, with their internal registers defaulting to the power-on values. The MIOC will drive the appropriate system bus data lines with the initial configuration values that defaulted in the Configuration Values Driven on Reset (CVDR) register. On the rising edge of RESET#, the MIOC will continue driving the appropriate system bus lines with the configuration values. These values are driven at least one clock after the rising edge of RESET#. Intel 450NX PClset 10-110. System Initialization 10.1.1.2 10-2 All system bus devices will capture the system configuration parameters from the appropriate system bus lines on the rising edge of RESET#. The MIOC captures these values in its Configuration Values Captured on Reset (CVCR) register. (This allows an external device to over-ride the MIOC default parameters.) All system bus devices are now ready for further programming. The MIOC will respond to BIOS code fetches. If a change in the system bus system configuration is desired, the MIOCs CVDR register can be programmed with the desired values. After the CVDR register is programmed, the MIOC must be programmed to do a hard reset, through the Reset Control (RC) register. When the MIOC performs a hard reset, all system bus devices are again reset. This reset repeats steps 2-8, except that the CVDR register is not effected by the reset. This register is only re-initialized by the PWRGD signal. Special Considerations for Third-Party Agents One of the settings available in the CVDR/CVCR registers allows the Bus In-Order Queue Depth to be set to 1, instead of the usual 8. When IOQ Depth=1, there is a case where a Third- Party Agent can starve the system bus. Therefore, any system containing a TPA must either: require that the TPA back-off its BPRI# arbitration requests sufficiently to allow the symmetric agents access to the bus, or not use IOQ depth=1. Intel 450NX PClsetClocking and Reset /|11 11.1 This chapter describes the generation, distribution and interaction between the various clocks in an Intel 450NX PClIset-based system, as well as the various reset functionality supported by the Intel 450NX PCIset. Clocking The Pentium II Xeon processor uses a clock ratio scheme where the system bus clock frequency is multiplied to produce the processors core frequency. The MIOC supports a system bus frequency optimized for 100 MHz. The Intel 450NX PCIset should be used at a bus frequency which provides the required clock frequency for the PCI interfaces. The external clock generator is responsible for generating the system clock. The Intel 450NX PClIsets core clock is equal to the system bus clock rate. The Intel 450NX PClIset is responsible for driving the signals which the processor uses to determine the core to bus clock ratio. The MIOC receives an output of a clock generator on the HCLKIN pin, as illustrated in Figure 11-1. The MIOC uses the HCLKIN signal to drive the host and memory interfaces and the core. This clock is doubled for the MD bus and the Expander buses. External Low Skew Clock Driver System Bus CLK Y2 - Y3 -_ Yn co Y1}__> oo L | HCLKIN ~<Ho MIOC Figure 11-1: Host Clock Generation and Distribution PCI clock distribution is illustrated in Figure 11-2. The PXB provides a PCI bus clock that is generated by dividing the internal host clock frequency by three. The PCI clock is output through the PCLK pin. Externally this PCI clock drives a low skew clock driver which in turn supplies multiple copies of the PCI clock to the PCI bus. One of the outputs of the external clock driver is fed back into the PXB. A PLL in the PXB forces the external PCI clock to phase lock to the internal PCI clock tree. Intel 450NX PClset 11-111. Clocking and Reset 11.2 11.2.1 VCC Pull-up/Pull-down External Low Skew Detect Clock Driver Host CLK/ 3 PCLK A Yy1}4+_ Y2 -_- Y3 -- Yn PCLKFB <}4o0 PXB Figure 11-2: | PCI Clock Generation and Distribution System Reset Five varieties of reset functions are supported by the Intel 450NX PClset. A Power-Good Reset is triggered by an externally generated signal which indicates that the power supplies and clocks are stable. This reset clears all configuration and transaction state in the Intel 450NX PClIset, as well as asserting resets to the processors, PCI buses, and PIIX, if present. - A System Hard Reset is a software-initiated reset that performs nearly the same functions as the power-good reset. The key difference is that the system hard reset does not clear "sticky" error flags in the Intel 450NX PClIset, thus allowing an error handler to determine the cause of a failure that resulted in reset. Also, hard reset may optionally trigger the processors Built-In Self-Test (BIST). - A Soft Reset is another software-initiated reset which affects only the processors. This reset may also be generated by certain I/O activities. - A BINIT Reset results from a catastrophic transaction error on the system bus. The memory and the MIOCs configuration space are untouched. - <A PXB Reset is a software-initiated reset that affects only a single PXB and its dependent PCI buses. This reset may be used in high-availability systems, where it is desirable to allow the processors and one PXB to continue operation in the event of failure of a single PXB. Intel 450NX PCliset Reset Structure Figure 11-3 shows the recommended reset structure for an Intel 450NX PClset-based system including the PIIX4E south bridge. Note that the primary system power-good signal is provided to the MIOC, which then distributes a variety of reset signals to the rest of the system. Intel 450NX PClset11.2 System Reset Good 82C42 Processor Processor f i we & | lee & A20M#, NTE | i 5 z iy 5 z NMI#, IGNE# == it = ; o ; A20M#,IGNE#, INTR,NMIl# frequenc ; select y 1 / lagic if 1 | System Bus CRESET# RESET# Power | PWRGD BINIT# MRESET# } | MIOC PWRGDB 7 oad ' | | [mux] Memory Memory f= a f= Card #0 Card #1 72) 3 s oO cc A a fe _ + o oc x< < x< x PIIXOK# _PIIXOK# spuRST [* PXB #1 PXB #0 el pwrap s co a 2 3 > a | 1 ey | ha fe o ED D a a f f a n f a a 2 o clio ay cia alc Ol, |s2 alto of lo a| fo ot |x ie os o oO oO oa oa oO rs) o o o i aly Figure 11-3: Recommended RESET Distribution for Intel 450NX PClset-Based Systems including a PIIX4E south bridge Power Good The reference system shown here assumes a single "power good" signal that indicates clean power supplies and clocks to the MIOC and both PXBs. For routing convenience and drive capability, the MIOC provides a buffered version of its PWRGD input (PWRGDB), which should be connected to the PWRGD inputs of each PXB. Refer to the Electrical Characteristics for additional PWRGD requirements. RESET# The RESET# signal is directed to the processors. Assertion of this signal puts all processors in a known state, and invalidates their L1 and L2 caches. When this signal is deasserted, the processor begins to execute from address 00_FFFF_FFFOh. The Boot ROM must respond to this address range regardless of where it physically resides in the system. CRESET# The CRESET# signal tracks RESET#, but is held asserted two clocks longer than RESET#. It is provided to allow an external frequency selection mux to drive the system-bus-to-core-clock ratio onto pins LINT[1:0], IGNNE#, and A20M# of the system bus during RESET#. Intel 450NX PClset11. Clocking and Reset MRESET# The MRESET# signal is sent to all RCGs and MUXs in the memory subsystem. When asserted, each RCG and MUxX clears their transaction state and data buffers. Any transactions that may have been in-progress or pending in the memory subsystem are lost. Upon MRESET# deassertion, the MIOC will re-initialize the memory subsystem by issuing 8 CAS- before-RAS refreshes per bank (this does not affect the data held in the memory). Bus CLK wa, SUL, AAU, FULL, FULL, SUL PWRGD Core & Exp. Clocks Internal Reset# MRESET# RESET# CRESET# BNR# tristate X(0,1)RST# Expander held in reset resynch Core Clock PCI CLK relock (1ms) PWRGDB Internal Reset# P(A,B)RST# PIIX4E PWROK RSTDRV CPURST PXB PIIXOK# ems Figure 11-4: Power-Good Reset 11-4 Intel 450NX PClset11.2.2 11.2 System Reset Soft Reset A Soft Reset is a reset directed to the processors on the system bus which does not affect the configuration or transaction state of the Intel 450NX PClset or the dependent PCI buses. To support this function, the system design must externally combine the MIOCs INIT# output with the I/O port 92h and keyboard controller soft reset sources as shown in Figure 11-5. Vec KBC RESET# I/O Port 92 Reset MIOC INIT# INIT# (to processors) 74F07 Figure 11-5: Soft Reset PXB Reset A PXB Reset is a software-initiated reset that affects only a single PXB and its dependent PCI buses. Figure 11-4 illustrates a software-initiated PXB Reset. Reset without disturbing PCI clocks PCICLKA and PCICLKB must be re-phased whenever any type of reset is asserted if the Intel 450NX PClset is to be deterministic relative to that reset. The behavior of these clocks cannot be guaranteed during this re-phasing. A bit in the PXB RC register can be cleared by a configuration write to defeat the PCI clock re-phasing, so that PCICLKA and PCICLKB remain well behaved through resets. Output States During Reset The following tables shows the signal states of the Intel 450NX PCIset components during a Power-Good Reset or System Hard Reset. Inputs are denoted by -. Intel 450NX PClset 11-511. Clocking and Reset CF8/CFC Write to RC to assert System Hard Reset ADS# / CF8/CFC Write to RC to deassert System Hard Reset > 2ms 2ms BNR# ~~ PA Ly X(0,1)RST# Lod L67 Helk Expander Buses > held in reset ( resynch ready I. PCI CLK PT IW, ALN relock (1ms) Internal __ 64 Hclk Reset# PR f P(A,B)RST# ry a) PIIX4E PWROK RSTDRV CP / a CPURST Le PXB PIXORF ems - Figure 11-6: Software-Initiated PXB Reset MIOC Reset State Host Interface A[35:3]# Tristate! | DEP[7:0]# Tristate ADS# Tristate DRDY# Tristate AERR# Tristate HIT# - AP[1 :O]# Tristate HITM# - BERR# Tristate INIT# Tristate? BINIT# Tristate LOCK# - BNR# Tristate REQ[4:0]# Tristate BP[1 :0]# Tristate RP# Tristate BPRI# Tristate RS[2:0]# Tristate BREQ(O|# Asserted* | RSP# Tristate D[63:0]# Tristate DBSY# Tristate TRDY# Tristate DEFER# Tristate Intel 450NX PClset11.2 System Reset Third-Party Agent Interface IOGNT# - TPCTL[1:0] - IOREQ# Tristate Memory Subsystem / External Interface BANK[2:0]# Deasserted | DVALID(a,b)# Deasserted CARD[1 :0]# Deasserted | MA[13:0]# Deasserted CMND[1:0]# Deasserted | MD[71:0]# Tristate CSTB# Deasserted | MRESET# Asserted DCMPLT(a,b)# Tristate PHIT(a,b)# - DOFF[1:0]# Deasserted | ROW# Deasserted DSEL[1:0]# Deasserted | RCMPLT(a,b)# - DSTBN[3:0]# Tristate RHIT(a,b)# - DSTBP[3:0]# Tristate WDEVT# Deasserted Expander Interface (two per MIOC: 0,1) X(0,1)ADS# Tristate X(0,1)HSTBP# Toggling X(0,1)BE[1 :O0]# Tristate X(0,1)PAR# Tristate X(0,1) BLK# Deasserted | X(0,1)RST# Asserted X(0,1)CLK Toggling | X(0,1)RSTB# Asserted X(0,1)CLKB Toggling | X(0,1)RSTFB# - X(0,1)CLKFB - X(0,1)XRTS# - X(0,1)D[15:0]# Tristate X(0,1)XSTBN# - X(0,1JHRTS# Toggling | X(0,1)XSTBP# - X(0,1)HSTBN#F Togegling Common Support Signals CRES[1 :0] Strapped TMS - TCK - TRST# - TDI - VCCA (8) Reference TDO OD VREF (6) Reference Component-Specific Support Signals CRESET# Asserted | PWRGD ERR[1:0}# Tristate PWRGDB De/asserted* HCLKIN Toggling RESET# Asserted INTREQ# Deasserted | SMIACT# Deasserted Notes: 1 The Pentium II Xeon processor allows for configuring a variety of processor and bus variables during the reset sequence. During RESET# assertion, and for one clock past the trailing edge of RESET#, the Intel 450NX PCIset MIOC will drive the contents of its CVDR register onto A[15:3]#. All system bus devices (including the MIOC) are required to sample these address lines using the trailing edge of reset, and modify their internal configuration accordingly. Note the initial value of CVDR may be changed by the boot processor, and the reset process re-engaged. This allows the processors and buses to power-up in a safe state, yet allow re-configuration based on specific system constraints. 2. BREQO# must stay asserted (low) for a minimum of 2 system clocks after the rising edge of RESET#. The MIOC then releases (tristates) the BREQO# signal. 3. INIT# is not asserted during power-up. It may be optionally asserted during system hard reset through the RC register to cause the processors to initiate BIST. 4. The PWRGDB output is asserted if the PWRGD input is asserted (ie., a power-good reset). For a system hard reset, the PWRGDB output is deasserted. Intel 450NX PClset 11-711. Clocking and Reset 11.2.2.2 PXB Reset State PCI Bus Interface (2 per PXB: A,B) P(A,B)AD[81 :0] Tristate P(A,B)PAR Tristate P(A,B)C/BE[38:0]# Tristate P(A,B)PERR# Tristate P(A,B)CLKFB - P(A,B)REQ[5:0]# - (see note) P(A,B)CLK Toggling P(A,B)RST# Asserted P(A,B)DEVSEL# Tristate P(A,B)SERR# Open P(A,B)FRAME# Tristate P(A,B)STOP# Tristate P(A,B)GNT[5:0]# Tristate P(A,B)TRDY# Tristate P(A,B)IRDY# Tristate P(A,B)XARB# Strapped P(A,B)LOCK# Tristate PCI Bus Interface / Non-Duplicated (one set per PXB) ACK64# Tristate PHLDA# Tristate MODE64# Strapped REQ64# Asserted PHOLD# - WSC# Tristate Expander Interface (one per PXB) XADS# Tristate XHSTBP# - XBE[1 :0]# Tristate XIB Deasserted XBLK# - XPAR# Tristate XCLK Toggling |XRST# Asserted XD[15:0]# Tristate XXRTS# Deasserted XHRTS# - XXSTBN# Deasserted XHSTBN# - XXSTBP# Deasserted Common Support Signals CRES[1 :0] Strapped TMS - TCK - TRST# - TDI - VCCA (8) Reference TDO OD VREF (2) Reference Component-Specific Support Signals INTRQ(A,B)# Deasserted | PIIXOK# - LONGXB# Strapped PWRGD - P(A,B)MON[1 :0]# Tristate Note: The P(A,B)REQ[5:0]# signals are inputs to the PXB. During reset, these inputs are ignored. However, these signals become "live" immediately following reset desassertion. All unconnected REQ# inputs should be strapped deasserted. All connected REQ# inputs should have weak pullups. 11-8 Intel 450NX PClset11.2.2.3 11.2.2.4 RCG Reset State 11.2 System Reset Memory Subsystem / External Interface BANK[2:0]# - MRESET# - CARD# - PHIT# Deasserted CMND[1:0]# - RCMPLT# Deasserted CSTB# - RHIT# Deasserted GRCMPLT# Deasserted | ROW# - MA[13:0]# - Memory Subsystem / Internal Interface ADDR{(A,B,C,D)[13:0] Deasserted | LRD# Deasserted AVWP# Deasserted | RAS(A,B,C,D)(a,b,c,d)[1:0]# Deasserted CAS(A,B,C,D)(a,b,c,d)[1:0]# Deasserted | WOME# Deasserted LDSTB# Deasserted | WE(A,B,C,D)(a,b)# Deasserted Common Support Signals CRES[1:0] - TMS - TCK - TRST# - TDI - VCCA Reference TDO Tristate VREF (2) Reference Component-Specific Support Signals BANKID# Strapped |DRSOT# Strapped DR50H# Strapped | HCLKIN Togegling MUX Reset State Memory Subsystem / External Interface DCMPLT# Deasserted | DVALID# - DOFF[1:0]# - GDCMPLT# Deasserted DSEL# - MD[35:0]# Tristate DSTBP[1 :0]# Tristate MRESET# - DSTBN[1:0]# Tristate WDEVT# - Memory Subsystem / Internal Interface AVWP# - Q1D[85:0] Tristate LDSTB# - Q2D[85:0] Tristate LRD# - Q3D[85:0] Tristate QOD[85:0] Tristate WDME# - Common Support Signals CRES[1 :0] Strapped TMS - TCK - TRST# - TDI - VCCA Reference TDO Tristate VREF (2) Reference Component-Specific Support Signals HCLKIN Toggling Intel 450NX PClset11. Clocking and Reset 11-10 Intel 450NX PClsetElectrical Characteristics 12] 12.1 Signal Specifications 12.1.1. Unused Pins For reliable operation, always connect unused inputs to an appropriate signal level. Unused AGTL+ inputs should be connected to V77. Unused active low 3.3V-tolerant inputs should be connected to 3.3V. Unused active high inputs should be connected to ground (Vgg). When tying bidirectional signals to power or ground, a resistor must be used. When tying any signal to power or ground, a resistor will also allow for fully testing the processor and PClset after board assembly. It is suggested that ~10KQ resistors be used for pull-ups and ~1KQ resistors be used as pull- downs. 12.1.2 Signal Groups In order to simplify the following discussion, signals have been combined into groups of like characteristics (see below). Refer to Chapter 2 for a description of the signals and their functions. Table 1: Signal Groups MIOC Pin Group Signals Notes AGTL+ Input LOCK#, PHIT(a,b)#, RCMPLT(a,b)#, RHIT(a,b)#, X(0,1)RSTFB#, X(0,1)XRTS#, X(0,1)XSTBN#, X(0,1)XSTBP#, HIT#, HITM# AGTL+ Output BR[O}#, BANK[2:0]#, BREQ(O]#, CARD[1 :0]#, CMND[1:0]#, CSTB#, DOFF[1:0]#, DSEL[1 :0]#, DVALID(a,b)#, MA[13:0]#, MRESET#, ROW#, X(0,1)BLK#, X(0,1)HRTS#, X(0,1)HSTBN#, X(0,1)HST- BP#, X(0,1)RST#, X(0,1)RSTB#, WOEVT# AGTL+ I/O A[85:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BPRI#, D[63:0]#, DBSY#, DCMPLT(a,b)#, DE- FER#, DEP[7:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, MD[71:0]#, REQ(/4:0]#, RESET#, RP#, RS[2:0]#, RSP#, TRDY#, X(0,1)ADS#, X(0,1)BE[1 :0]#, X(0,1)D[15:0]#, X(0,1)PAR# CMOS 14 mA 2.5V Open Drain Out-} INIT#, TDO put (3.3V Tolerant) CMOS Input 3.3V lIOGNT#, TPCTL[1:0], PWRGD, CMOS Input 2.5V (3.3V Tolerant) HCLKIN, X(0,1)CLKFB, TMS, TDI, TCK, TRST# 1 Intel 450NX PClset 12-112. Electrical Characteristics Table 1: Signal Groups MIOC Output (3.3V Tolerant) CMOS I/O 14mA 2.5V Open Drain BP[1.0]#, ERR[1.O}# CMOS Output 10mA 3.3V CRESET#, INTREG#, IOREQ#, SMIACT#, PWRGDB, X(0,1)CLK, X(0,1)CLKB Analog signals CRES[1.0], VCCA[2:0], VREF[5:0] Notes: 1. HCLKIN is equivalent to the Processor BCLK Table 2: Signal Groups PXB Pin Group Signals Notes AGTL+ Input XBLK#, XHRTS#, XHSTBN#, XHSTBP#, XRST# AGTL+ Output XIB, XXRTS#, XXSTBN#, XXSTBP# AGTL+ I/O XADS#, XBE[1:0], XD[15:0]#, XPAR# CMOS Input 2.5V (3.3V Toler- | XCLK, TMS, TDI, TCK, TRST# ant) CMOS Input 3.3V P(A,B)CLKFB, PIIXOK#, PWRGD CMOS Output 10mA, P(A,B)CLK 3.3V CMOS 14mA 2.5V Open Drain | TDO Output (3.3V Tolerant) CMOS I/O 14mA, 3.3V P(A,B)MON[1 :0]# Open Drain Output Analog Signals CRES[1 :0], VCCA[2:0], VREF[1:0] PCI Signals (Non-Duplicated) | ACK64#, MODE64#, PHOLD#, PHLDA#, REQ64#, WSC# PCI Signals INTRQ(A,B)#, P(A,B)AD[31:0], P(A,B)C/BE#[3:0], P(A,B)DEVSEL#, P(A,B)FRAME#, P(A,B)GNT[5:0]#, P(A,B)IRDY#, P(A,B)LOCK#, P(A,B)PAR, P(A,B)PERR#, P(A,B)REQ(5:0)#, P(A,B)RST#, P(A,B)SERR#, P(A,B)STOP#, P(A,B)TRDY#, P(A,B)XARB# Notes: Table 3: Signal Groups MUX Pin Group Signals Notes AGTL+ Input AVWP#, DOFF[1:0]#, DSEL#, DVALID#, LDSTB#, LRD#, WDEVT#, WDME#, MRESET# AGTL+ I/O DCMPLT#, DSTBP[1 :0]#, DSTBN[1:0]#, GDCMPLT#, MD[85:0]# CMOS Input 2.5V (3.3V Tolerant) HCLKIN, TMS, TDI, TCK, TRST# CMOS 14mA, 2.5V Open Drain Output (3.3V Toler- ant) TDO 12-2 Intel 450NX PClset12.1 Signal Specifications | Table 3: Signal Groups MUX CMOS //O 10mA, 3.3V QOD[35:0], Q1D[35:0], Q2D[35:0], Q3D[35:0] Analog Signals CRES[1:0], VCCA, VREF[1:0] Notes: Table 4: Signal Groups RCG Pin Group Signals Notes AGTL+ Input BANK[2:0]#, CARD#, CMND[1:0]#, CSTB#, MA[13:0]#, MRESET#, ROW# AGTL+ Output AVWP#, LDSTB#, LRD#, PHIT#, RCMPLT#, RHIT#, WDME# AGTL+ I/O GRCMPLT# CMOS Input 3.3V BANKID#, DR50H#, DR50T# CMOS Input 2.5V (3.3V HCLKIN, TMS, TDI, TCK, TRST# Tolerant) CMOS 14mA, 2.5V Open | TDO Drain Output (3.3V Toler- ant) CMOS Output 10mA, 3.3V | ADDA(A,B,C,D)[13:0}#, WE(A,B,C,D)(a,b)#, CAS(A,B,C,D)(a,b,c,d)[1:0]#, RAS(A,B,C,D)(a,b,c,d)[1 :0}# Analog Signals CRES[1:0], VCCA, VREF[1:0] Notes: 12.1.3 The Power Good Signal: PWRGD PWRGD is a 3.3V-tolerant input to the PCI Bridge and memory controller components. It is expected that this signal will be a clean indication that the clocks and the 3.3V, VCC_PCI supplies are within their specifications. Clean implies that PWRGD will remain low, (capable of sinking leakage current) without glitches, from the time that the power supplies are turned on until they become valid. The signal will then have a single low to high transition to a high (3.3V) state with a minimum of 100ns slew rate. Figure 1 illustrates the relationship of PWRGD to HCLKIN and system reset signals. Intel 450NX PClset 12-3 |12. Electrical Characteristics VCC_PCl 7 HCLKIN PWRGD <=100ns> < RESET# / CRESET# / Figure 1: PWRGD Relationship The PWRGD inputs to the Intel 450NX PClset and to the Pentium II Xeon processor(s) should be driven with an AND of Power-Good signals from the 5V, 3.3V and Veceorep Supplies. The output of this logic should be a 3.3V level and should have a pull-down resistor at the output to cover the period when this logic is not receiving power. 12-4 Intel 450NX PClset12.1 Signal Specifications | 12.1.4 LDSTB# Usage xxQData | Latch LDSTB# we D Q [=> EN Enabled DFlop DFlop DQ To Core LRD# Ee D Q EN IN HCLKIN PS LL Figure 2: LDSTB# Usage LDSTB# opens a flow-through latch to enable fine tuning of the read data timing. By adjusting the trace length of the LDSTB# signal it is possible to match the CAS# or RAS# timings (whichever is last) for optimal timing margin on DRAM read cycles. 12.1.5 VCCA Pins The VCCA inputs provide the analog supply voltage used by the internal PLLs. To ensure PLL stability, a filter circuit must be used from the board VCC. Figure 3 shows a recommended circuit. It is important to note that a separate filter for each VCCA pin is necessary to avoid feeding noise from one analog circuit to another. Figure 3: VCCA filter 10 Ohm 1% vec VCCA A Intel 450NX PClset 12-5 |12. Electrical Characteristics 12.2 Maximum Ratings Table 5 contains stress ratings for the Intel 450NX PClset. Functional operation at the absolute maximum and minimum ratings is neither implied nor guaranteed. The Intel 450NX PClset should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Intel 450NX PClset contains protective circuitry to resist damage from static discharge, care should always be taken to avoid high static voltages or electric fields. Table 5: Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Vec3 3.3V Supply Voltage with respect to | -0.5 4.3 Vv Vss Vin AGTL+ Buffer DC Input Voltage with | -0.5 | Vy+0.5 Vv 1 respect to Vgg (not to exceed 3.0) Ving 3.3V Tolerant DC Input Voltage with | -0.5 Vec3 + 0.9 Vv 2 respect to Veg (not to exceed 4.3) Vins 5V Tolerant DC Input Voltage with |-0.5 | Vecpe) + 0.5 Vv 3 respect to Vgs Tstor Storage Temperature -65 150 Notes: Parameter applies to the AGTL+ signal groups only. 2. Parameter applies to 3.3V-tolerant and JTAG signal groups only. 3. Parameter applies to 5V-tolerant signal groups and PCI signals only. Voc_pc is the voltage level on the PCI Bus. 11nSec mn Overvoltage Waveform Voltage Source Impedance +11V R =55 Ohms 11V, p-to- 3.3V Supply (minimum 4nSec 4nSec (max) (max) Input Buffer 62.5nSec (i6Mhz) 5.25V 10.75V, p-to-p Undervoltage Waveform (minimum) Voltage Source | Impedance -5.5V R= 25 Ohms Figure 4: Maximum AC Waveforms for 5V Signaling (PCI Signals) 12-6 Intel 450NX PClset12.3 DC Specifications | Overvoltage Waveform 11nSec (min) Voltage Source Impedance R = 29 Ohms 3.3V Supply Input Buffer ToT 4 Se (max) 4+7.1V 7.1V, p-to- (minimum 4nSec (max) 62.5nSec _ Undervoltage Waveform Voltage Source Impedance R= 28 Ohms TiSMhz) +3.6V | -3.5V 7.1V, p-to- (minimum 2 Figure 5: 12.3. DC Specifications Table 6 through Table 10 list the DC specifications associated with the Intel 450NX PClset. Care should be taken to read any notes associated with each parameter listed. Maximum AC Waveforms for 3.3V Signaling (PCI Signals) Table 6: Intel 450NX PClset Power Parameters Symbol Parameter Min | Typ | Max Unit Notes Vec3 Device Voc 3.13 [3.3 3.46 Vv 1 Vec-pc (3.3) | PCI Vec for 3.3 V PCI Operation 3.0 3.3 3.6 Vv 2,4 Vec-pcy (5) PCI Vcc for 5.0 V PCI Operation 4.5 5.0 5.5 Vv 2,4,5 loc-pcl Clamping Diode Leakage Current 2 mA 3 To Operating Case Temperature 0 85 C Notes: 1. 3.38V +/-5%. 2. The Intel 450NX PClset PXB will support either a 5V or 3.3V PCI Bus. 3. At33MHz. 4. From PCI Specification Rev 2.1. 5. Pin List VCC (A-N). Table 7: Intel 450NX PClset Power Specifications Symbol Parameter Max Unit Notes PMAX Max Power Dissipation PXB 7.8 WwW 1,2,5 MIOC 13.2 WwW 1,2,5 Intel 450NX PClset 12-7 |12. Electrical Characteristics Table 7: Intel 450NX PClset Power Specifications Symbol Parameter Max Unit Notes MUX 3.3 W 1,2,5 RCG 2.5 W 1,5 lees Max Power Supply Current PXB 2.2 A 1,4 MIOC 3.3 A 1,4 MUX 0.87 A 1,4 RCG 0.7 A 1 Iss Max Power Supply Current PXB 3.3 A 1,3 MIOC 18.1 A 1,3 MUX 2.5 A 1,3 RCG 0.8 A 1,3 Notes: 1. Frequency = 100 MHz. 2. This specification is a combination of core power (Icc3), and power dissipated in the AGTL+ outputs and 3. se i the maximum supply current consumption when all AGTL+ signals are low. 4. The Icc Specification does not include the AGTL+ output current to GND. Table 8 lists the nominal specifications for the AGTL+ termination voltage (V77) and the AGTL+ reference voltage (Vref). Table 8: Intel 450NX PClset AGTL+ Bus DC Specifications Symbol Parameter Min Typ Max Unit | Notes Vit Bus Termination Voltage 1.5 Vv 1 VReEF Input Reference Voltage | 2/3 V+7 -2% | 2/3 V+ 2/3 V7 +2% |V 2,3 Notes: 1. +/-9% during maximum di/dt and +/- 3% steady state, as measured at component V+ pins. 2. Where VTT tolerance can range from - 9% to +9%, as noted above. 3. Vper should be created from V77 by a voltage divider of 1% resistors. Some of the signals on the MIOC, PXB, MUX and RCG are in the AGTL+ signal group. These signals are specified to be terminated to 1.5V. The DC specifications for these signals are shown in Table 9. Table 9: Vcc; =3.3V (5%, TCASE =Oto 85C) Intel 450NX PClset DC Specifications (AGTL+ signal groups) Symbol Parameter Min Max Unit Notes Vit Input Low Voltage -0.3 Vrer-0.2 | V 1 Vin Input High Voltage Vrer +0.2 | 2.185 Vv 1 VoL Output Low Voltage 0.6 Vv Vou Output High Voltage 1.2 - Vv lon Output High Current 2 20 mA 12-8 Intel 450NX PClsetTable 9: Vec, =3.3V (5%, TcaASE =Oto 85C) 12.3 DC Specifications | Intel 450NX PClset DC Specifications (AGTL+ signal groups) Symbol Parameter Min Max Unit Notes lot Output Low Current 38 55 mA 2 ly Input Leakage Current +/- 15 uA 4 IREF Reference Voltage Current +/- 15 uA 5 lLo Output Leakage Current +/- 15 uA 6 Cin Input Capacitance 10 pF 7 Co Output Capacitance 10 pF 7 Cvo I/O Capacitance 10 pF 7 Notes: 1. Vper worst case. Noise on Vper should be accounted for. Refer to the Pentium Pro Family Developers Manual for more information on Vref. 2. Parameter measured into a 25 resistor to V77 (1.5V). 3. A high level is maintained by the external pull-up resistors. AGTL+ is an open drain bus. Refer to the Pentium Pro Family Developers Manual for information on V+7. 4. (0 < Vin < Vecs) 5. Total current for all Var pins. 6. (0<Vours Vecs) 7. Total of I/O buffer and package parasitics. Table 10: Vec, =3.3V (5%, TcaASE =Oto 85C) Intel 450NX PClset DC Specifications (Non AGTL+ groups) Symbol | Pin Group Parameter Min Max Unit | Notes/Test Conditions Cin All Input Capacitance 10 pF 1 Co All Output Capacitance 10 pF Cio All /O Capacitance 10 pF Ceik HCLKIN HCLKIN Input Capacitance 10 pF Ctck TCK TCK Input Capacitance 8 pF loL-14 CMOS 2.5V_ | Output Low Current 14.0 mA OD 14mA loL-to CMOS 10mA] Output Low Current 10.0 mA 2 VoL CMOS 10mA| Output Low Voltage 0.45 Vv VoL CMOS 2.5V_ | Output Low Voltage 0.45 Vv 14 OD 14mA Vou CMOS 10mA} Output High Voltage 2.4 Vv 9 Vou CMOS 2.5V_ | Output High Voltage - 8, 11 OD 14mA lLo CMOS 10mA| Output Leakage Current +/-10 uA ly CMOS Input | Input Leakage Current +/-10 uA 4,5 ViL CMOS Input | Input Low Voltage -0.5 0.8 Vv Intel 450NX PClset 12-9 |12. Electrical Characteristics Table 10: Intel 450NX PClset DC Specifications (Non AGTL+ groups) Vec, =3.3V (5%, TcaASE =Oto 85C) Symbol | Pin Group Parameter Min Max Unit | Notes/Test Conditions Vin CMOS Input | Input High Voltage 2.0 3.6 Vv Vit CMOS 2.5V | Input Low Voltage -0.5 0.7 Vv 14 Input Vin CMOS 2.5V_ | Input High Voltage 1.7 3.6 Vv 11 Input ViL-Pcl PCl Input Low Voltage - 0.5 0.8 Vv 6 Vin-Pcl PCI Input High Voltage 2.0 Vec-pcl +0.5 V 6,7 Vo-par | PC! Output Low Voltage 0.55 Vv 6 Vou-pci | PC! Output High Voltage 2.4 Vv 6 loL-Pcl PCl Output Low Current 6.0 mA 6 ILePcl PC| Input Leakage Current +/-70 uA 6 llo-pcl PCl Output Leakage Current +/-10 uA 6 Notes: 1. Except HCLK, TCK 2. Vo. =0.4V 3. (0 < Vout < Vec3) 4. (0 < Vin < Vecs) 5. -100UA for pins with 50K pullups, +100uA for pins with 50K pulldowns. 6. 5V-tolerant 3.3V I/O buffer. 7. Voec-pc| = PC! Bus Voltage. 8. Determined by 2.5V connected through a 150 ohm resistor. 9. Measured with 10ma load. 10. Specifications for PCI are from PCI Specification Rev 2.1. 11. 3.3V-tolerant 2.5V Input or Output buffer. 12-10 Intel 450NX PClset12.4 AC Specifications 12.4 AC Specifications | Figure 6: 1.7V T3 T5 = CLK Rise Time T6 = CLK Fall Time T3 = CLK High Time T4 = CLK Low Time T1 =CLK Period 1.25V 0.7V HCLKIN CLK Waveform Table 11: A T6 A T4 Vv T1 Vcc; =3.3V (5%, TCASE =Oto 85C) Intel 450NX PClset Clock Specifications v Symbol | Parameter Min Max Unit | Notes Host Interface: Bus Frequency 90 100 Mhz T1 CLK Period 10 11.11 ns 1 T2 CLK Period Stability +/-100 ps 1 T3 CLK High Time 3 ns 1 T4 CLK Low Time 3 ns 1 T5 CLK Rise Time 0.5 1.5 ns 1 T6 CLK Fall Time 0.5 1.5 ns 1 T9 TCK Frequency 16.67 Mhz T/2 TCK Hightime 25 ns T73 TCK Lowtime 25 ns T74 TCK rise time 5 ns T/5 TCK fall time 5 ns These specifications apply to all clock inputs for all four Intel 450NX PClset components. Intel 450NX PClset 12-11| 12. Electrical Characteristics Table 12: Vec, =3.3V (5%, TcaASE =Oto 85C) Intel 450NX PClset MIOC AC Specifications Symbol Parameter Setup Min Hold Min Delay Min Delay Max Unit Notes Host Interface: T10A A[35:3]#, ADS#, AERR#, AP[1:0]}#, BERR#, BINIT#, BNR#, BPRI#, D[63:0]#, DBSY#, DEFER#, DEP[7:0}#, DRDY#, REQ|[4:0]#, RP#, RS[2:0]#, RSP#, TRDY# 1.58 0.63 -0.15 2.65 ns T17 BP[1.0] 2.0 0.5 1.0 5.0 ns T14 BRO# -0.15 2.65 ns T13A HIT#, HITM#, LOCK# 1.58 0.63 ns T12 INIT# 1.0 5.0 ns Third-Party Agent Interface: T14 IOREQ# 0.0 3.5 ns T15 lIOGNT# 2.0 0.5 ns T16 TPCTL[1:0] 2.0 0.5 ns Memory Interface: T14 BANK[2.0}#, CARD[1:0}#, CMND[1 :O}#, CSTB#, DOFFT[1:0], DSEL[1 :O}#, DVALID(a,b)#, MA[13:0}#, ROW#, WDEVT# -0.15 2.65 ns T14 MRESET# -0.15 2.65 ns T10 DCMPLt(a,b)# 1.88 0.63 -0.15 2.65 ns T13 PHitT(a,b)#, RCM- PLT(a,b)#, RHIT(a,b)# 1.88 0.63 ns MD(71-0)#, DSTBP(3:0)#, DSTBN(3:0)# 14 14 14 | 12-12 Intel 450NX PClset12.4 AC Specifications | Table 12: Intel 450NX PClset MIOC AC Specifications Vec, =3.3V (5%, TcaASE =Oto 85C) Symbol | Parameter Setup Min | Hold Min | Delay Min| Delay Max | Unit Notes Expander Inter- face (two per MIOC:0,1) T21 X(0,1)RST#, -0.1 3.25 ns 7,8 X(0,1)RSTB# T23 X(0,1)RSTFB#, 1.88 0.63 ns X(0,1)XRTS# T14 X(0,1)HRTS# -0.15 2.65 ns 8 Other T39 CRESET# 1.0 4.1 ns 3 T25 ERR[1:0]# 2.0 0.5 1.0 5.0 ns 10 T70 INTREQ#, SMI- 0.0 3.5 ns 3 ACT# T71 PWRGD 4.0 1.0 ns 1,6 T70 PWRGDB 0.0 3.5 ns 3, 5, 13 T21 RESET# -0.1 3.25 ns 7, 8,12 Testability Signals: T26 TRST# ns 4,6 T27 TMS 5.0 14.0 ns 2 T27 TDI 5.0 14.0 ns 2 T28 TDO 1.0 10.0 ns 2,3 T29 TDO on/off delay 25.0 ns 2,3 Notes: 1. The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD signal. 2. 3.3V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. 3. Min and Max timings are measured with OpF load. 4. TRST# requires a pulse width of 40 ns. 5. This output is asynchronous. 6. This input is asynchronous. 7. Asynchronous assertion with synchronous deassertion. 8. Min and Max timings are measured with Opf and 25 Ohms to Vit. 9. Min and Max timings are measured with Opf and 150 Ohms to 2.5V. 10. Min and Max timings are measured with Opf and 230 Ohm to 3.3V. 11. See Table 16 for source synchronous timings. 12. Minimum pulse width 1.0ms. 13. PWRGDB is the buffered output of PWRGD, and has no relation to HCLKIN. Table 13: Intel 450NX PClset PXB AC Specifications Vcc; =3.3V (5%, TCASE =Oto 85C) Symbol Parameter Setup Min | Hold Min | Delay Min} Delay Max | Unit] Notes | PCI Interface Intel 450NX PClset 12-13 |12. Electrical Characteristics Table 13: Intel 450NX PClset PXB AC Specifications Vec, =3.3V (5%, TcaASE =Oto 85C) Symbol Parameter Setup Min | Hold Min | Delay Min} Delay Max | Unit] Notes T30 P(A,B)AD[81 :0], 7.0 0.0 2.0 11.0 ns 1,3 P(A,B)C/BE[3:0]#, P(A,B)TRDY#, P(A,B)STOP#, P(A,B)LOCK#, P(A,B)DEVSEL#, P(A,B)PAR, P(A,B)IRDY#, P(A,B)FRAME#, P(A,B)PERR#, P(A,B)XARB# T31 P(A,B)REQ[5:0]# 12.0 0.0 ns 1,3 T32 P(A,B)GNT[5:0]# 2.0 12.0 ns 1,3 T34 INTRQ(A,B)#, 2.0 11.0 ns 1,3 P(A,B)RSTH, P(A,B)SERR#, T33 ACK64# 7.0 0.0 2.0 11.0 ns 1,3 T35 PHOLD# 7.0 0.0 ns 1 T36 PHLDA# 2.0 12.0 ns 1,3 T37 REQ64# 7.0 0.0 2.0 11.0 ns 1,3 T38 WSC# 2.0 12.0 ns 1,3 Expander Interface (one per PXB) T40 XRST# 2.8 0.0 ns |6 T14 XXRTS# -0.15 2.65 ns |8 T13 XHRTS# 1.88 0.63 ns OTHER T47 P(A,B)MON|[1 :0]# 5.0 0.5 1.0 6.0 ns 14,8 T46 PIIXOK# 7.0 0.0 ns 1 Testability Signals: T26 TRST# ns |5,7 T27 TMS 5.0 14.0 ns |2 T27 TDI 5.0 14.0 ns |2 T28 TDO 1.0 10.0 ns |2,4 T29 TDO on/off delay 25.0 ns |2,4 Notes: 1. 5V-tolerant. 2. 3.3V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. 3. Min timings are measured with OpF load, Max timings are measured with 50pF load. 4. Min and Max timings are measured with OpF load. 12-14 Intel 450NX PClsetONDA TRST# requires a pulse width of 40 ns. This signal has an asynchronous assertion and a synchronous deassertion. This input is asynchronous. 12.4 AC Specifications | Setup Min time for these signals on B1 and earlier steppings of the PXB is only 4.0ns. PCI Bus Signal Waveforms: All PC! Bus signals are referenced to the PCLK Rising edge. For more information on the PCI Bus signals and waveforms, please refer to the PC/ Specification. Table 14: Intel 450NX PClset RCG AC Specifications Vcc; =3.3V (5%, TCASE =Oto 85C) Symbol Parameter Setup Min | Hold Min | Delay Delay | Unit Notes Min Max Memory Subsystem/Exter- nal Interface T50 BANK[2:0]#, CARD#, 2.80 0.0 ns CMND[1:0]#, CSTB#, MA[13:0]#, ROW# T51 GRCMPLT# 2.80 0.0 -0.15 2.65 ns 6 T52 PHIT#, RCMPLT#, RHIT# -0.15 2.65 ns 6 Memory Subsystem/Inter- nal Interface T52 AVWP#, LRD#, WDME#, LD- -0.15 2.65 ns 6 STB# T53 CAS(A,B,C,D)(a,b,c,d)[1 :0]# 0.0 3.5 ns 3 T54 ADDR(A,B,C,D)[13:0]# 1.0 5.5 ns 3 T53 RAS(A,B,C,D)(a,b,c,d)[1 :0]# 0.0 3.5 ns 3 T53 WE(A,B,C,D)(a,b)# 0.0 3.5 ns 3 Other T50 MRESET# 28 0.0 ns 5 T26 TRST# ns 4,7 T27 TMS 5.0 14.0 ns 2 T27 TDI 5.0 14.0 ns 2 T28 TDO 1.0 10.0 ns 2,3 T29 TDO on/off delay 25.0 ns 2,3 Notes: 1. The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD signal. 2. 3.3- tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. 3. Min and Max timings are measured with OpF load. 4. TRST# requires a pulse width of 40 ns. 5. Max delay timing requirement from MIOC to RCGs and MUxXs is two clock cycles. Asynchronous assertion and synchronous deassertion. 6. Min and Max timings are measured with OpF and 25 to Vit (1.5V). 7. This input is asynchronous. Intel 450NX PClset 12-15 || 12. Electrical Characteristics Table 15: Intel 450NX PClset MUX AC Specifications Vec, =3.3V (5%, TcaASE =Oto 85C) Symbol Parameter Setup Hold Delay Delay | Unit | Notes Min Min Min Max Memory Subsystem/Ex- ternal Interface T60 DCMPLT# 2.8 0.0 -0.15 2.65 ns |6 T61 DOFF[1:0]#, DSEL#, 2.8 0.0 ns DVALID#, WDEVT# T60 GDCMPLT# 2.8 0.0 -0.15 2.65 ns |6 T67 LDSTB# 3.0 1.0 ns Memory Subsystem/In- ternal Interface T62 AVWP#, WDME# 3.5 0.0 ns T62 LRD# 3.5 0.0 ns T68 QOD[35:0], Q1D[35:0], 1.0 4.0 0.0 3.5 ns 2,4 Q2D[35:0], Q3D[35:0] Other T69 MRESET# 2.8 0.0 ns 5 Testability Signals: T26 TRST# ns 3,7 T27 TMS, TDI 5.0 14.0 ns 1 T28 TDO 1.0 10.0 ns 1,2 T29 TDO on/off delay 25.0 ns 1,2 Notes: 1. 3.3V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling. 2. Min and Max timings are measured with OpF load. 3. TRST# requires a pulse width of 40 ns. 4. Input timings are referenced from LDSTB# rising edge. Output timings are referenced from HCLKIN. 5. Max delay timing requirement from MIOC to RCGs and MUxXs is two clock cycles. Asynchronous assertion and synchronous deassertion. Min and Max timings are measured with OpF and 25 to Vit (1.5V). This input is asynchronous. DOFF[1:0]#, DSEL#, WDEVT# max delay timing requirement from MIOC to MUX is two clock cycles. oN | 12-16 Intel 450NX PClsetFigure 7: HCLKIN / 13 qin T63 max T64 DSTBP# . min. Tea X(0,1) HSTBP# max Source Synchronous Strobe Timing / X(0,1)XSTBP# \ \/ T65 max T66 min T66 max 12.4 AC Specifications | / \ DSTBN# X(0,1)HSTBN# X(0,1)XSTBN# \ Table 16: 100Mhz Source Synchronous Timing Symbol Parameter Dela Min y Delay ax Skew Unit Notes T63 DSTBP(3:0)#, X(0,1)HSTBP#, X(0,1)XSTBP# Falling Edge 2.35 5.15 ns 1,2,4 T64 DSTBP(3:0)#, X(0,1)HSTBP#, X(0,1)XSTBP# Rising Edge 7.35 10.15 ns 1,3,4 T65 DSTBN(3:0)#, X(0,1)HSTBN#, X(0,1)XSTBN# Rising Edge 2.35 5.15 ns 1,2,4 Intel 450NX PClset 1217 || 12. Electrical Characteristics Table 16: 100Mhz Source Synchronous Timing Symbol Parameter Delay Delay Skew Unit | Notes Min Max T66 DSTBN(3:0)#, 7.35 10.15 ns 1,3,4 X(0,1)HSTBN#, X(0,1)XSTBN#, Falling Edge NOTES: 1. Relative to HCLKIN Rising edge. 2. Strobe timings are generated from an internal clock which is a multiple of HCLKIN. This enables the strobes to track system timings staying centered within the data window. Numbers given are for 100Mhz operation. Timings for other frequencies can be calculated by Strobe_Min_Time = [-0.15 + (1/Bus_Freq)1/ 4] ns and Strobe_Max_Time = [2.65 + (1/Bus_Freq)1 /4] ns. 3. Strobe timings are generated from an internal clock which is a multiple of HCLKIN. This enables the strobes to track system timings staying centered within the data window. Numbers given are for 100Mhz operation. Timings for other frequencies can be calculated by Strobe_Min_Time = [-0.15 + (1/Bus_Freq)3/4] ns and Strobe_Max_Time = [2.65 + (1/Bus_Freq)3/4] ns. 4. Min and Max timings are measured with OpF and 25 to Vit (1.5V). | 12-18 Intel 450NX PClset12.4 AC Specifications | Table 17: Source Synchronous Signal to Strobe Timings (at source) Symbol Parameter Setup Min|Setup Max |Hold Min |Hold Max | Notes T80 MD(71-0)#, 2.0 2.75 1-5 X(0,1)D[15:0}#, (0,1)ADS#, X(0,1)BE[1:0}#, (0,1) BLK#, (0,1) PAR# T81 MD(71-0)#, 2.0 2.75 1-5 1)D[15:0}#, 1)ADS#, 0,1)BE[1 :0}#, 0,1) 0,1) BLK#, PAR# X(0, X(0, X( X( X( NOTES: 1. MD(71:0)# strobes are single-ended, and the falling edge of the strobe is used to capture data; Expander strobes are differential. 2. Values are guaranteed by design. 3. Setup Max and Hold Max are specified at frequency= 100MHz. 4. Timings for other frequencies can be calculated as follows: T80 Setup_Max = [(1/Bus_Freq)1/4 + .250] ns, T81 Hold Max = [(1/Bus_Freq)1/4 + .250 ] ns, where .250ns represents the error margin around strobe placement. 5. Data delay times relative to HCLK for any bus frequency can be calculated as follows... For First Data: Data_Min_Time = [-0.15 ]Jns and Data_Max_Time = [2.65 ]ns; For Second Data: Data_Min_Time = [-0.15 + (1/Bus Freq)/2 ]ns and Data_Max_Time = [2.65 + (1/Bus Freq)/2 Jns. Intel 450NX PClset 12-19 |Figure 8: 12. Electrical Characteristics DSTBx# XHSTBx# XXSTBx# MD(71:0)# XD(15:0)# XBE[1:0]# XPAR# XADS# XBLK# 12-20 Tso Tet Test Intel 450NX PClset Source Synchronous Signal to Strobe Timings (at source)12.4 AC Specifications | Ss Table 18: 100Mhz Source Synchronous Timing (at destination) Symbol Parameter Setup Hold Unit | Notes Min Min T20 DSTBN(3:0)#, 7.0 ns 1,4 DSTBP(38:0)# X(0,1)XSTBN# X(0,1)XSTBP# T24 MD(71:0)# 1.5 1.5 ns 2 T22 (0,1)D[15:0]# 1.75 1.0 ns 3 X(0,1)ADS#, X(0,1)BE[1 :0]# X(0,1)BLK#, X(0,1)D[15:0]# X(0,1)PAR# NOTES: 1. Setup in relation to capture HCLKIN. 2. With respect to the DSTBs. 3. With respect to the HSTBs. 4. Applies to Expander bus source synchronous signals. For synchronous signals (RTS#) the maximum clock skew between MIOC and PXB plus the flight time must not exceed 4.97nS. AP Launched Here 1P Sampled Here. i__ 1P Capture Range > : : <T20 HCLK ! Data C E 3P \ 3N \ ODD +e evens ODD Figure 9: Source Synchronous Data Transfer Intel 450NX PClset 12-21 |12. Electrical Characteristics 12.5 Source Synchronous Data Transfers A Source Synchronous packet has a two clock period delivery time, and is divided into positive and negative phases of even and odd cycles. During this two clock window, packets are launched synchronously and sampled synchronously. Signals launched with a positive phase even clock are sampled on a positive phase of next even clock. Between launch and sample, signals are captured with source synchronous strobes. HCLKIN 1.25V Ts Th LLLLLL XK = XLLL Ts =Setup Time Th = Hold Time + >- V =1.0V for AGTL+ 1.5V for 3.3V-tolerant CMOS 1.25V for 2.5V CMOS Figure 10: Setup and Hold Timings HCLKIN TX MAX ee Fr [I Tx = Valid Delay Figure 11: Valid Delay Timing 12.6 1/O Signal Simulations: Ensuring I/O Timings It is highly recommended that system designers run extensive simulations on their Pentium |! Xeon processor/Intel 450NX PClset-based designs. These simulations should include the memory subsystem design as well. Please refer to the Pentium Pro Family Developers Manual for more information. 12-22 Intel 450NX PClset12.7 Signal Quality Specifications | 12.7 Signal Quality Specifications Signals driven by any component on the Pentium II Xeon processor bus must meet signal quality specifications to guarantee that the components read data properly, and to ensure that incoming signals do not affect the long term reliability of the components. There are three signal quality parameters defined: Overshoot/Undershoot, Ringback, and Settling Limit, which are discussed in the next sections. 12.7.1. Intela 450NX PClset Ringback Specification This section discusses the ringback specification for the parameters in the AGTL+ signal groups on the Intel 450NX PClset. Case A requires less time than Case B from the Vper crossing until the ringback into the overdrive region. The longer time from Vper crossing until the ringback into the overdrive region required in Case B allows the ringback to be closer to Vagr for a defined period. Table 19: Intel 450NX PClset AGTL+ Signal Groups Ringback Tolerance: Case A Parameter Min | Unit Figure Notes oa Overshoot 100 mV 12813 1 t Minimum Time at High or Low 2.25 | ns 12&13 | 1 P Amplitude of Ringback -100 | mV 12813 1 5 Duration of Squarewave Ringback N/A | ns 12 & 13 1 Final Settling Voltage 100 | mV 12813 | 1 Note: 1. Specified for an edge rate of 0.8-1.3V/ns. See the Pentium Pro Family Developers Manual for the definition of these terms. See Figures 12 and 13 for the generic waveforms. All values are determined by design/characterization. Table 20: Intel 450NX PClset AGTL+ Signal Groups Ringback Tolerance: Case B Parameter Min | Unit Figure Notes o, Overshoot 100 | mV 12&13 1 _ Minimum Time at High 27 |ns 12 1 T Minimum Time at Low 3.7 | ns 13 1 p Amplitude of Ringback -0 mv 12&13 1 5 Duration of Squarewave Ringback 2 ns 12&13 1 6 Final Settling Voltage 100 mv 128138 1 Note: Intel 450NX PClset 12-23 || 12. Electrical Characteristics 1. Specified for an edge rate of 0.8-1.3V/ns. See the Pentium Pro Family Developers Manual for the definition of these terms. See the figures below for the generic waveforms. All values are determined by design/characterization. ne er 1.25V Clk Ref. fT Ls riseffall edges a / Vaer +0.2 Y. of Zo I > V REF | p Vaer -0.2 {> + 5> Clock ra a ! TIME Figure 12: Standard Input Lo-to-Hi Waveform for Characterizing Receiver Ringback Tolerance Vstart Tsu +0.05n: 1.25V Clk Ref. peewee e eee n eee VREF 40.2 \V REF VAEF -0.2 oo ' aN, [* 10ps rise/fall edges Clock TIME > | 12-24 Intel 450NX PClset12.7 Signal Quality Specifications | Figure 13: Standard Input Hi-to-Lo Waveform for Characterizing Receiver Ringback Tolerance 12.7.2 Intelo 450NX PClset Undershoot Specification The undershoot specification for the Intel 450NX PClset components (and Pentium II Xeon processor) is as follows: The Pentium Il Xeon processor bus signals AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM# (only) are capable of sinking an 85mA current pulse at a 2.4% average time duty cycle. This is equivalent to -1.7V applied to a 20 source in series with the device pin for 5.38 ns at 100Mhz with a utilization of 5%. This test covers the AC operating conditions only pers (max) \ +1.7V 3.4V, p-to-p (max) R Voltage source [vy = DUT waveform : 417V \ V ) Undershoot Test Waveforn TT Voltage Source Impedance R = 20 ohms 7.5 ns (max) Average duty cycle of 2.4%. Figure 14: Undershoot Test Setup 12.7.3. Skew Requirements The skew requirement for XoRST# versus XORSTFB#, and XpCLK versus XpCLKFB is +/- 125ps. The electrical length (delay) from the XpCLK signal pin on the MIOC to the clock input of the PXB must match the delay to the XeCLKFB pin on the MIOC by that amount. The same is true with XpRST# and XpRSTFB#. Intel 450NX PClset 12-25 |12. Electrical Characteristics 12.8 Intele 450NX PCliset Thermal Specifications 12.8.1. Thermal Solution Performance The systems thermal solution must adequately control the package temperatures below the maximum and above the minimum specified. The performance of any thermal solution is defined as the thermal resistance between the package and the ambient air around the part (package to ambient). The lower the thermal resistance between the package and the ambient air, the more efficient the thermal solution is. The required @package to ambient is dependent upon the maximum allowed package temperature (T package), the local ambient temperature (TLA), and the package power (PPackage): Package to ambient = (Tpackage TLA)/Ppackage TLA is a function of the system design. Tables 21 and 22 provide the resulting thermal solution performance required for an Intel 450NX PClset at different ambient air temperatures around the parts. Table 21: Example Thermal Solution Performance for MIOC at Package Power of 13.2 Watts Local Ambient Temperature (TLA) 35C 40C 45C @ Package to ambient C/( Watt) 3.79 3.41 3.03 Table 22: Example Thermal Solution Performance for PXB at Package Power of 7.8 Watts Local Ambient Temperature (TLA) 35C 40C 45C 6 Package to ambient C/( Wait) 6.41 5.76 5.13 12-26 The @ package to ambient value is made up of two primary components: the thermal resistance between the package and heatsink (@ package to heatsink) and the thermal resistance between the heatsink and the ambient air around the part (6 heatsink to air). A critical but controllable factor to decrease the value of 6 package to heatsink is management of the thermal interface between the package and heatsink. The other controllable factor (@ heatsink to air) is determined by the design of the heatsink and airflow around the heatsink. Intel 450NX PClset12.9 Mechanical Specifications 12.9.1 Pin Lists Sorted by Pin Number: Table 23: MIOC Pin List Sorted by Pin r ower ower ower Hele] ++ [+ f+ ]4 [tele lt i+ ma Intel 450NX PClset 12.9 Mechanical Specifications | 12-27 || 12. Electrical Characteristics Table 23: MIOC Pin List Sorted by Pin r rna ma ma ma ma ma ma +]+ [+] 4+]+[4]4+]+ + + f+] + [+] + [4 ]+]4]4+]4+]4]+ ma | 12-28 Intel 450NX PClset12.9 Mechanical Specifications | Table 23: MIOC Pin List Sorted by Pin r ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma Intel 450NX PClset 12-29 || 12. Electrical Characteristics Table 23: MIOC Pin List Sorted by Pin r rna ma Yet + [+ + 1+ [+ = + | 12-30 Intel 450NX PClset12.9 Mechanical Specifications | Table 23: MIOC Pin List Sorted by Pin r ma ma ma ma ma Intel 450NX PClset 12-31 || 12. Electrical Characteristics Table 23: MIOC Pin List Sorted by Pin r rna ma ma ma ma ma ma | 12-32 Intel 450NX PClset12.9 Mechanical Specifications | Table 23: MIOC Pin List Sorted by Pin r ower = + + + + + + + + + + r + Intel 450NX PClset 12-33 || 12. Electrical Characteristics Table 23: MIOC Pin List Sorted by Pin r rna ma ma ma + + + + + + + + | 12-34 Intel 450NX PClset12.9 Mechanical Specifications | Table 23: MIOC Pin List Sorted by Pin r ma ma ma ma ower ower + ower ower ower ower + ower ower ower Table 24: PXB Pinlist Sorted by Pin Intel 450NX PClset 12-35 || 12. Electrical Characteristics Table 24: PXB Pinlist Sorted by Pin ower + ower + ower + ower + ower ower | 12-36 Intel 450NX PClset12.9 Mechanical Specifications | Table 24: PXB Pinlist Sorted by Pin Intel 450NX PClset 12-37 || 12. Electrical Characteristics Table 24: PXB Pinlist Sorted by Pin ower + ower + ower + ower + ower + ower + ower ower ower | 12-38 Intel 450NX PClset12.9 Mechanical Specifications | Table 24: PXB Pinlist Sorted by Pin ower ower ower ower ower ower ower ower ower ower ower Intel 450NX PClset 12-39 || 12. Electrical Characteristics Table 24: PXB Pinlist Sorted by Pin ower ower ower ower | 12-40 Intel 450NX PClset12.9 Mechanical Specifications | Table 24: PXB Pinlist Sorted by Pin ower Intek 450NX PClset 12-41 || 12. Electrical Characteristics Table 24: PXB Pinlist Sorted by Pin | 12-42 Intel 450NX PClset12.9 Mechanical Specifications | Table 24: PXB Pinlist Sorted by Pin ower ower ower ower ower ower ower ower ower ower ower ower Intel 450NX PClset 12-43 || 12. Electrical Characteristics Table 24: PXB Pinlist Sorted by Pin Table 25: MUX Pin List Sorted by Pin r ower ower | 12-44 Intel 450NX PClset12.9 Mechanical Specifications | Table 25: MUX Pin List Sorted by Pin r r ma ma ma ma ma ma ma ma ma ma ma ma Intel 450NX PClset 12-45 || 12. Electrical Characteristics Table 25: MUX Pin List Sorted by Pin r ma ma ma ma ma ower | 12-46 Intel 450NX PClset12.9 Mechanical Specifications | Table 25: MUX Pin List Sorted by Pin r r ma ma ma ma ower Intel 450NX PClset 12-47 || 12. Electrical Characteristics Table 25: MUX Pin List Sorted by Pin r ma ma ma ma ma ma ma ma ower | 12-48 Intel 450NX PClset12.9 Mechanical Specifications | Table 25: MUX Pin List Sorted by Pin r r ower + ma ower ower ower + ower ower + ower ower ower + ower ower ower + ower Table 26: RCG Pin List Sorted by Pin r ower Intel 450NX PClset 12-49 || 12. Electrical Characteristics Table 26: RCG Pin List Sorted by Pin ower ower ower ower ower ower ower ower ower ower } 12-50 Intel 450NX PClset12.9 Mechanical Specifications | Table 26: RCG Pin List Sorted by Pin r Intel 450NX PClset 12-51 || 12. Electrical Characteristics Table 26: RCG Pin List Sorted by Pin ma ma ma ma | 12-52 Intel 450NX PClset12.9 Mechanical Specifications | Table 26: RCG Pin List Sorted by Pin r ma ulres extern Intel 450NX PClset 12-53 || 12. Electrical Characteristics Table 26: RCG Pin List Sorted by Pin 12.9.2 Pin Lists Sorted by Signal Pin# Table 27: MIOC Pin List Sorted by Signal BO4 SI A nal /O Driver lype Driver Strength Internal Pullup/Pulldown 12-54 fF /O AGTL+ 55ma Intel 450NX PClset12.9 Mechanical Specifications | Table 27: MIOC Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma a a ma ma ma ma ma ma + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + f+ [+] +] + [+ f+ ]4]t i+ ma Intel 450NX PClset 12-55 || 12. Electrical Characteristics Table 27: MIOC Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma + Yel |] [4 ft + ft ff ft fe] + [fs fe ee ed ede ee ede ds leds ds [+ i4 elt l4 lee lesa lelsielelsielealeleielelele | 12-56 Intel 450NX PClset12.9 Mechanical Specifications | Table 27: MIOC Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma a a +i] ys feds [tle ela de [ties ie ie leis ower Intel 450NX PClset 12-57 || 12. Electrical Characteristics Table 27: MIOC Pin List Sorted by Signal ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower + + | 12-58 Intel 450NX PClset12.9 Mechanical Specifications | Table 27: MIOC Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma HPL ft] [4 ft + ft fle] fee] ds [fs se fs ef de te te ede ds [edd [tle de [dele sleds a lels ie lelsielie ele leie lela Intel 450NX PClset 12-59 || 12. Electrical Characteristics Table 27: MIOC Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma + + + + + + + + + + + + + + + + + + + + Hit] + |e 4+ ls f+ d4 [4 ft ]4 [4/44 ower | 12-60 Intel 450NX PClset12.9 Mechanical Specifications | Table 27: MIOC Pin List Sorted by Signal ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower Intel 450NX PClset 12-61 || 12. Electrical Characteristics Table 27: MIOC Pin List Sorted by Signal ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower +f f+ ft + [4 ft ]+ ft fle [te let lee ale leielelels+ | 12-62 Intel 450NX PClset12.9 Mechanical Specifications | Table 27: MIOC Pin List Sorted by Signal + f+ + fds ft les eds [seis [4 [els [444 [else ie leis Table 28: PXB Pin List Sorted by Signal r Intel 450NX PClset 12-63 || 12. Electrical Characteristics Table 28: PXB Pin List Sorted by Signal r | 12-64 Intel 450NX PClset12.9 Mechanical Specifications | Table 28: PXB Pin List Sorted by Signal r Intel 450NX PClset 12-65 || 12. Electrical Characteristics Table 28: PXB Pin List Sorted by Signal r | 12-66 Intel 450NX PClset12.9 Mechanical Specifications | Table 28: PXB Pin List Sorted by Signal r Intel 450NX PClset 12-67 || 12. Electrical Characteristics Table 28: PXB Pin List Sorted by Signal r ower | 12-68 Intel 450NX PClset12.9 Mechanical Specifications | Table 28: PXB Pin List Sorted by Signal r ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower Intel 450NX PClset 12-69 || 12. Electrical Characteristics Table 28: PXB Pin List Sorted by Signal r ower ower ower ower ower ower ower ower ower ower ower ower | 12-70 Intel 450NX PClset12.9 Mechanical Specifications | Table 28: PXB Pin List Sorted by Signal r ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower +]+]4+]+ + f+] + [+] + [4 ]+]4]4+]4+]4]+ ma Intel 450NX PClset 12-71 || 12. Electrical Characteristics Table 28: PXB Pin List Sorted by Signal r ma ma ma ma +t le] t+ [+ f+ i+ [4 ]4 le fale Table 29: MUX Pin List Sorted by Signal r Stren n ullup/Pulldown +]+]4+[4]4[4+]4]4]+ ower | 12-72 Intel 450NX PClset12.9 Mechanical Specifications | Table 29: MUX Pin List Sorted by Signal r r en n ullu ullaown ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower HY [+ [+] [+] +] ft fs ft fee] ye leds [sede [seaside le iele leis le st ma Intel 450NX PClset 12-73 || 12. Electrical Characteristics Table 29: MUX Pin List Sorted by Signal r r en n ullu ullaown + ma + ma + ma + r | 12-74 Intel 450NX PClset12.9 Mechanical Specifications | Table 29: MUX Pin List Sorted by Signal r r en n ullu ullaown ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma 12-75 Intek 450NX PClset || 12. Electrical Characteristics Table 29: MUX Pin List Sorted by Signal r r en n ullu ullaown ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ower | 12-76 Intel 450NX PClsetTable 29: MUX Pin List Sorted by Signal r ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower r en n ullu Table 30: RCG Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma Intel 450NX PClset 12.9 Mechanical Specifications | ullaown 12-77 || 12. Electrical Characteristics Table 30: RCG Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma equires extern | 12-78 Intel 450NX PClset12.9 Mechanical Specifications | Table 30: RCG Pin List Sorted by Signal ower Intel 450NX PClset 12-79 || 12. Electrical Characteristics Table 30: RCG Pin List Sorted by Signal ower ower + Pe fee eee ed ede + tle [ays owe | 12-80 Intel 450NX PClset12.9 Mechanical Specifications | Table 30: RCG Pin List Sorted by Signal ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ower Intel 450NX PClset 12-81 || 12. Electrical Characteristics Table 30: RCG Pin List Sorted by Signal ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower ower | 12-82 Intel 450NX PClset12.9.3 Package information 12.9.3.1 324 BGA Package Information 12.9 Mechanical Specifications | SEE DETAIL oN // \0127 [A a 2700 010 = _| 2400 020 16 10 REF 45 CHAMFER 4 PLACES 2700 +010 2400 +020 NOTE: PIN #1 CORNER NO RADIUS h= 1610 REF 1/0127 |A Measurements in millimeters PIN #1 ID 10 DIA x 015 DEPTH Figure 15: 324 BGA Dimension Top View Intel 450NX PClset 12-83 || 12. Electrical Characteristics LI7 + U05 eb to0,10 ~~ FIN #1 nee et is te 14 Se 68 4 2 yf COPNEP goo lg 7 IS 7 5 3 1 Fi 0,30 +S] @n30 )| [A =) B (a) | eleke lene lols letelelslelelelelelelelele lain i OOOOOOMFOOMOGGOOODOOM BE COOOOMMOIGOMOIOTOOOODO Je CoOooggoeoeganoooarooooao U TOOAOOMOAOODOOAAOOM Gi E OoogIoon OOooOoo} FP eao00 ao0eo0 |], ooo o0 oO Ooo a2 H Oa AAS OOOO | Ooo Oooad OOOO. oa9o ooaa OOo - Ome Qaaa Om os Lev O OOa | Ooo Oan | Ooon COooo00 i ; OOOOCWOSGOGOC0O C0000 OOOIIoOOOOAICGOOCOO OOMOIOIOMOAOCOOOOD OMOODOGOOWIIOOO AY | OHoooeea0codceceeooo L44 FEF >a i L44 PEF Le7 a2 tuo 3 PLALE Figure 16: 324 BGA Dimensions Bottom View | 12-84 Intel 450NX PClset12.9 Mechanical Specifications | 12.9.3.2 540 PBGA Package Information a Oh tm] bee > oa cI 2 > is) be q Gq q Cc) g L | q g | q : q | gq ' o dq a q q a < rr oT = a gq | g : g | o | | C wl 1 wu q < | Ki a i - & i vw ad m 4 & yy = q i q g u = = ei 0 = Oo a Ae 5 = m oO 3S 2 oF m [i o BIS i C a io * o + Cl I2 2 vu : { 5 = bovdpwoer, FgZazrye ig go =p Fig S=Huryve a) = s =z a a> Poa 2 & OE ans i 3 a_G a 27s HE | RF a= s a Dz th g vl =g = gaqgn00cogoCNGC OOD CNDODGOCONNDOOOOICD me au 65 oggedgogGGgNN NT ONNNNOGONANONRAAON = S ~S 4 ovuesgnoogcoc00cCeon0ngToOCOCOCaCGACCNOCdOO =a amo QIgdGCND ODA ANON OGONNGOOOCAGAOODNNNN z= ze i ggogo0ggcogogoogceeoooceeeoouase9o0n000 =@ cr a oaece oo000 Ce Zaz oaoaa o0co0 = Th 465 gaooo ecaco ae a oac0a | ooocK m a Y o9006 ' oac0o vi Zo g900G | oeucoe S oo000 ' oo00e zg =z q goqaqg | eooae m Cc 5 aoa0s | on00c0 > =Z=z 99000 ' oog00 a wv C0000 2 | a oacao m ea oo0a0e j oo0000 o 5 ana0G : o0000 > a a aq0006 | oca0o = wo oca0g ooa00 m Q a0006 ' ougao GS Fs aac0o | oo000 wo ~ Js ooa0a i oooaa - ou 90000 ocaoo a 2F ooo000 o0000 x =z. oo0ao ooaaa ms o9g000 eoace 4 q me agogooodcogocdo9gn0nao000CCoCag0GC00cCICo x H#OOGAGDNRDODOOIONDNO TONG OOO ACONONDOO a 7 reqaocq0coc000000000n0GCNCCAOngGCCOCOoN00N > vu } NARA ARAM NAA DAN AAA ADNAN AANA AN H Intel 450NX PClset 12-85 |12. Electrical Characteristics 12-86 Table 31: 540 PBGA dimensions Package Dimensions Packages 540 LD Min NOTE: Measurement in millimeters Intel 450NX PClset12.9 Mechanical Specifications | PrP rp PrP Pb > > >BoOoTR RS PEREE rPoooomag? Fe RnR - F270 DA CK EX \ OCOONDDDDONODOCDNDNONOO CONN NOO COO COCO0O000 oo0o0oooo0oe0C0CoCoCo-0CO0oCC0CCCKoOCCOKCOCOoOoOCOCO0O0C0000 CNON0NDNDNOONONCOOOONOOOOCOOONOOCOOOOO0C0O0000 OCOONDDDDONODOCDNDNONOO CONN NOO COO COCO0O000 oo0o0oooo0oe0C0CoCoCo-0CO0oCC0CCCKoOCCOKCOCOoOoOCOCO0O0C0000 O0000 _______ C00 I Ccoo0co | 1 oeese C0000 C0000 eeee | 1 00000 O0000 1 | So000 C0000 C0000 Soo0e | 1 COO00O0 OO00O00 | | So000 C0000 C0000 So000 | 1 OO00O0 C0000 | Soooe C0000 C0000 C0000 | 1 OO00O C0000 , | So00g C0000 C0000 o0000 | 1; COO00O C0000 , | s0000 C0000 C0000 oo00d | ; OOO0O C0000 |} 1 C0000 00000 | 00000 ceo00Ko ceo00Ko oo0o0o0ocooQ0e0c0C0C0CoOo0C0C0CC0C0C0C00C0O0O0O0000000 COONDDDDDNDDDDNDNDDODGCNONONONDO OOO O00 0000 eoo0000COCOOCOOOCOOOOOOOCOOOOOOCOOCO0O0O0O00 oo0o0o0ocooQ0e0c0C0C0CoOo0C0C0CC0C0C0C00C0O0O0O0000000 COONDDDDDNDDDDNDNDDODGCNONONONDO OOO O00 0000 123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bottom View Figure 17: 540 PBGA pin grid Intel 450NX PClset 12-87 || 12. Electrical Characteristics | 12-88 Intel 450NX PClset