DS90UB901Q, DS90UB902Q
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SNLS322E –JUNE 2010–REVISED APRIL 2013
DS90UB901Q/DS90UB902Q 10 - 43MHz 14 Bit Color FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Check for Samples: DS90UB901Q,DS90UB902Q
1FEATURES DESCRIPTION
The DS90UB901Q/DS90UB902Q chipset offers a
2• 10 MHz to 43 MHz Input PCLK Support FPD-Link III interface with a high-speed forward
• 160 Mbps to 688 Mbps Data Throughput channel and a bidirectional control channel for data
• Single Differential Pair Interconnect transmission over a single differential pair. The
Serializer/Deserializer pair is targeted for direct
• Bidirectional Control Interface Channel with connections between automotive camera systems
I2C Support and Host Controller/Electronic Control Unit (ECU).
• Embedded Clock with DC Balanced Coding to The primary transport sends 16 bits of image data
Support AC-Coupled Interconnects over a single high-speed serial stream together with a
• Capable to Drive up to 10 Meters Shielded low latency bidirectional control channel transport that
supports I2C. Included with the 16-bit payload is a
Twisted-Pair selectable data integrity option for CRC (Cyclic
• I2C Compatible Serial Interface Redundancy Check) to monitor transmission link
• Single Hardware Device Addressing Pin errors. Using TI’s embedded clock technology allows
• 16-bit Data Payload with CRC (Cyclic transparent full-duplex communication over a single
differential pair, carrying asymmetrical bidirectional
Redundancy Check) for Checking Data control information without the dependency of video
Integrity blanking intervals. This single serial stream simplifies
• Up to 6 Programmable GPIO's transferring a wide data bus over PCB traces and
• LOCK Output Reporting Pin and AT-SPEED cable by eliminating the skew problems between
BIST Diagnosis Feature to Validate Link parallel data and clock paths. This significantly saves
Integrity system cost by narrowing data paths that in turn
reduce PCB layers, cable width, and connector size
• Integrated Termination Resistors and pins.
• 1.8V- or 3.3V-Compatible Parallel Bus Interface In addition, the Deserializer inputs provide
• Single Power Supply at 1.8V equalization control to compensate for loss from the
• ISO 10605 ESD and IEC 61000-4-2 ESD media over longer distances. Internal DC balanced
Compliant encoding/decoding is used to support AC-Coupled
interconnects.
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified A Serializer standby function provides a low power-
• Temperature Range −40°C to +105°C savings mode with a remote wake up capability for
signaling of a remote device.
• No Reference Clock Required on Deserializer
• Programmable Receive Equalization The Serializer is offered in a 32-pin WQFN (5mm x
5mm) package, and Deserializer is offered in a 40-pin
• EMI/EMC Mitigation WQFN (6mm x 6mm) package.
– DES Programmable Spread Spectrum
(SSCG) Outputs
– DES Receiver Staggered Outputs
APPLICATIONS
• Automotive Vision Systems
• Rear View, Side View Camera
• Lane Departure Warning
• Parking Assistance
• Blind Spot View
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
FPD-Link III
Bidirectional
Control Channel
Image
Sensor
ECU Module
DIN[13:0]
HS, VS
SDA
SCL
DOUT- RIN-
DOUT+ RIN+
Camera Unit
14
YUV/RGB
HSYNC
VSYNC PCLK
Pixel Clock
SDA
SCL
Microcontroller
ROUT[13:0]
HS, VS
SDA
SCL
PCLK
14
YUV/RGB
HSYNC
VSYNC
Pixel Clock
SDA
SCL
Camera Data
DS90UB902Q
Deserializer
DS90UB901Q
Serializer
GPI/O GPIO[1:0]
2
GPI/O
2
GPIO[1:0]
Camera Data
PCLK
DS90UB901Q - SERIALIZER
Clock
Gen
Timing
and
Control
DOUT-
RT
RIN-
DS90UB902Q - DESERIALIZER
DOUT+ RIN+
Timing
and
Control
LOCK
PCLK
Input Latch
FIFO
Decoder
SDA
16 ROUT[13:0] HS, VS
Encoder
Serializer
PLL
I2C Controller
SCL
Encoder
FIFO
Encoder Decoder
Deserializer
Decoder
Output Latch
Clock
Gen
CDR
SDA
SCL
RT RT RT
DIN[13:0] HS, VS 16
GPIO [1:0] 2
PDB
MODE
ID[x]
GPIO [1:0]
2
PDB
MODE
ID[x]
PASS
BISTEN
I2C Controller
Microcontroller/
ECU
DeserializerSerializer
Image
Sensor
FPD-Link III
Bidirectional
Control Channel
Bidirectional
Control Bus Bidirectional
Control Bus
Parallel
Data In
16
22
Parallel
Data Out
16
DS90UB902Q
DS90UB901Q
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Typical Application Diagram
Figure 1. Typical Application Circuit
Block Diagrams
Figure 2. Block Diagram
Figure 3. Application Block Diagram
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1 2 3 4 5 6 7 8
9
24 23 22 21 20 19 18 17
DS90B901Q
Serializer
32-Pin WQFN
(Top View)
VDDIO
VDDD
DIN[8]
DIN[9]
DIN[10]
DIN[11]
DIN[13]
DIN[12]
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]/GPIO[5]
DIN[2]/GPIO[4]
DIN[1]/GPIO[3]
DIN[0]/GPIO[2]
GPIO[1]
GPIO[0]
VDDCML
VDDT
VDDPLL
PDB
DOUT-
DOUT+
HSYNC
VSYNC
PCLK
SCL
SDA
ID[x]
RES
MODE
DAP = GND
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E –JUNE 2010–REVISED APRIL 2013
DS90UB901Q Pin Diagram
Serializer - DS90UB901Q
32 Pin WQFN (Top View)
See Package Number RTV0032A
DS90UB901Q SERIALIZER PIN DESCRIPTIONS
Pin Name Pin No. I/O, Type Description
LVCMOS PARALLEL INTERFACE
DIN[13:0] 32, 31, 30, 29, Inputs, Parallel data inputs.
27, 26, 24, 23, LVCMOS
22, 21, 20, 19, w/ pull down
18, 17
HSYNC 1 Inputs, Horizontal SYNC Input
LVCMOS
w/ pull down
VSYNC 2 Inputs, Vertical SYNC Input
LVCMOS
w/ pull down
PCLK 3 Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/ 20, 19, 18, 17 Input/Output, DIN[3:0] general-purpose pins can be individually configured as either inputs or
GPIO[5:2] LVCMOS outputs; used to control and respond to various commands.
GPIO[1:0] 16, 15 Input/Output, General-purpose pins can be individually configured as either inputs or outputs; used
LVCMOS to control and respond to various commands.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 4 Open Drain SCL requires an external pull-up resistor to VDDIO.
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SNLS322E –JUNE 2010–REVISED APRIL 2013
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DS90UB901Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name Pin No. I/O, Type Description
Input/Output, Data line for the bidirectional control bus communication
SDA 5 Open Drain SDA requires an external pull-up resistor to VDDIO.
I2C Mode select
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Input, LVCMOS
MODE 8 Standby mode and is enabled through remote wakeup by Deserializer)
w/ pull down MODE = H, Slave mode; Device accepts SCL clock input and attached to an I2C
controller master on the bus. Slave mode does not generate the SCL clock, but uses
the clock generated by the Master for the data transfers.
Device ID Address Select
ID[x] 6 Input, analog Resistor to Ground and 10 kΩpull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB 9 PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
RES 7 w/ pull down This pin MUST be tied LOW.
FPD-LINK III INTERFACE
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect
DOUT+ 13 CML must be AC Coupled with a 100 nF capacitor.
DOUT- 12 Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must
CML be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDPLL 10 Power, Analog PLL Power, 1.8V ±5%
VDDT 11 Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML 14 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD 28 Power, Digital Digital Power, 1.8V ±5%
Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO 25 VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS DAP the center of the WQFN package. Connected to the ground plane (GND) with at least
9 vias.
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2 3 4 5 6 7 8 9
110
31
39
38
37
36
35
34
33
32
12
13
14
15
16
17
18
19
20
40
DS90B902Q
Deserializer
40-Pin WQFN
(Top View)
HSYNC
VSYNC
PCLK
SCL
SDA
ID[x]
PASS
VDDCML
PDB
RES/CMLOUTP
RIN+
RIN-
VDDPLL
RES/CMLOUTN
BISTEN
RES
MODE
VDDSSCG
VDDIO3
ROUT[13]
ROUT[12]
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
VDDIO2
ROUT[8]
ROUT[9]
VDDD
ROUT[10]
ROUT[11]
VDDR
LOCK
GPIO[0]
GPIO[1]
VDDIO1
ROUT[0]/GPIO[2]
ROUT[1]/GPIO[3]
ROUT[2]/GPIO[4]
29 28 27 26 25 24 23 22
30 21
ROUT[3]/GPIO[5]
DAP = GND
11
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E –JUNE 2010–REVISED APRIL 2013
DS90UB902Q Pin Diagram
Deserializer - DS90UB902Q
40 Pin WQFN (Top View)
See Package Number RTA0040A
DS90UB902Q DESERIALIZER PIN DESCRIPTIONS
Pin Name Pin No. I/O, Type Description
LVCMOS PARALLEL INTERFACE
ROUT[13:0] 9, 10, 11, 12, Outputs, Parallel data outputs.
14, 15, 17, 18, LVCMOS
19, 20, 21, 22,
23, 24
HSYNC 7 Output, Horizontal SYNC Output
LVCMOS
VSYNC 6 Output, Vertical SYNC Output
LVCMOS
Output, Pixel Clock Output Pin.
PCLK 5 LVCMOS Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT OUTPUT (GPIO)
ROUT[3:0] / Input/Output, ROUT[3:0] general-purpose pins can be individually configured as either inputs or
21, 22, 23, 24
GPIO[5:2] LVCMOS outputs; used to control and respond to various commands.
Input/Output, General-purpose pins can be individually configured as either inputs or outputs; used
GPIO[1:0] 26, 27 LVCMOS to control and respond to various commands.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 3 Open Drain SCL requires an external pull-up resistor to VDDIO.
Input/Output, Data line for bidirectional control bus communication
SDA 2 Open Drain SDA requires an external pull-up resistor to VDDIO.
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DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
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DS90UB902Q DESERIALIZER PIN DESCRIPTIONS (continued)
Pin Name Pin No. I/O, Type Description
I2C Mode select
MODE = L, Master mode; Device generates and drives the SCL clock line, where
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
MODE 40 w/ pull up MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an
I2C controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
Device ID Address Select
ID[x] 1 Input, analog Resistor to Ground and 10 kΩpull-up to 1.8V rail. See Table 4
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
Input, LVCMOS
PDB 29 PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
w/ pull down Down. Programmed control register data are NOT retained and reset to default
values.
LOCK Status Output Pin.
LOCK = H, CDR/PLL is Locked, outputs are active
Output,
LOCK 28 LOCK = L, CDR/PLL is unlocked, the LVCMOS Outputs depend on OSS_SEL control
LVCMOS register, the CDR/PLL is shutdown and IDD is minimized. May be used as Link
Status.
When BISTEN = L; Normal operation
Output,
PASS 31 PASS is high to indicate no errors are detected. The PASS pin asserts low to indicate
LVCOMS a CRC error was detected on the Link.
Reserved
Pin 39: This pin MUST be tied LOW.
RES 32, 33, 39 - Pins 32,33: Route to test point or leave open if unused. See also FPD-LINK III
INTERFACE pin description section.
BIST MODE
BIST Enable Pin.
Input, LVCMOS
BISTEN 37 BISTEN = H, BIST Mode is enabled.
w/ pull down BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
Output, PASS = H, ERROR FREE Transmission
PASS 31 LVCOMS PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
FPD-LINK III INTERFACE
Input/Output, Non-inverting differential input, bidirectional control channel output. The interconnect
RIN+ 35 CML must be AC Coupled with a 100 nF capacitor.
Input/Output, Inverting differential input, bidirectional control channel output. The interconnect must
RIN- 36 CML be AC Coupled with a 100 nF capacitor.
Non-inverting CML Output
CMLOUTP 32 Output, CML Monitor point for equalized differential signal. Test port is enabled via control
registers.
Inverting CML Output
CMLOUTN 33 Output, CML Monitor point for equalized differential signal. Test port is enabled via control
registers.
POWER AND GROUND
SSCG Power, 1.8V ±5%
VDDSSCG 4 Power, Digital Power supply must be connected regardless if SSCG function is in operation.
LVTTL I/O Buffer Power, The single-ended outputs and control input are powered
VDDIO1/2/3 25, 16, 8 Power, Digital from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD 13 Power, Digital Digital Core Power, 1.8V ±5%
VDDR 30 Power, Analog Rx Analog Power, 1.8V ±5%
VDDCML 34 Power, Analog Bidirectional Channel Driver Power, 1.8V ±5%
VDDPLL 38 Power, Analog PLL Power, 1.8V ±5%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS DAP Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
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SNLS322E –JUNE 2010–REVISED APRIL 2013
Absolute Maximum Ratings(1)(2)(3)
Supply Voltage – VDDn (1.8V) −0.3V to +2.5V
Supply Voltage – VDDIO −0.3V to +4.0V
LVCMOS Input Voltage I/O Voltage −0.3V to + (VDDIO + 0.3V)
CML Driver I/O Voltage (VDD)−0.3V to +(VDD + 0.3V)
CML Receiver I/O Voltage (VDD)−0.3V to (VDD + 0.3V)
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Maximum Package Power Dissipation Capacity Package 1/θJA °C/W above +25°
Package Derating:
θJA(based on 9 thermal vias) 34.3 °C/W
DS90UB901Q 32 Lead WQFN θJC(based on 9 thermal vias) 6.9 °C/W
θJA(based on 16 thermal vias) 28.0 °C/W
DS90UB902Q 40 Lead WQFN θJC(based on 16 thermal vias) 4.4 °C/W
ESD Rating (IEC 61000-4-2) RD= 330Ω, CS= 150pF
Air Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±25 kV
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±10 kV
ESD Rating (ISO10605) RD= 330Ω, CS= 150/330pF
ESD Rating (ISO10605) RD= 2KΩ, CS= 150/330pF
Air Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±15 kV
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±10 kV
ESD Rating (HBM) ≥±8 kV
ESD Rating (CDM) ≥±1 kV
ESD Rating (MM) ≥±250 V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
(2) For soldering specifications see product folder at www.ti.com
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions(1)
Min Nom Max Units
Supply Voltage (VDDn) 1.71 1.8 1.89 V
LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V
OR
LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V
VDDn (1.8V) 25 mVp-p
Supply Noise VDDIO (1.8V) 25 mVp-p
VDDIO (3.3V) 50 mVp-p
Operating Free Air Temperature (TA) -40 +25 +105 °C
PCLK Clock Frequency 10 43 MHz
(1) Supply noise testing was done with minimum capacitors (as shown on Figure 39 and Figure 40) on the PCB. A sinusoidal signal is AC
coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the
Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the
other hand shows no error when the noise frequency is less than 750 kHz.
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Electrical Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V
VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.8 V
IIN Input Current VIN = 0V or 3.6V, VIN = 3.0V to 3.6V -20 ±1 +20 µA
VOH High Level Output Voltage VDDIO = 3.0V to 3.6V, IOH = -4 mA 2.4 VDDIO V
VOL Low Level Output Voltage VDDIO = 3.0V to 3.6V, IOL = +4 mA GND 0.4 V
IOS Serializer GPIO -24
Outputs
Output Short Circuit VOUT = 0V mA
Current Deserializer LVCMOS -39
Outputs
TRI-STATE Output PDB = 0V, VOUT = 0V or
IOZ LVCMOS Outputs -20 ±1 +20 µA
Current VDD
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH High Level Input Voltage VIN = 1.71V to 1.89V 0.65 VIN VIN +0.3 V
VIL Low Level Input Voltage VIN = 1.71V to 1.89V GND 0.35 VIN
IIN Input Current VIN = 0V or 1.89V, VIN = 1.71V to 1.89V -20 ±1 +20 µA
VOH VDDIO = 1.71V to 1.89V, Serializer GPIO
IOH =−2 mA Outputs VDDIO -
High Level Output Voltage VDDIO V
0.45
VDDIO = 1.71V to 1.89V, Deserializer LVCMOS
IOH =−4 mA Outputs
VOL VDDIO = 1.71V to 1.89V, Serializer GPIO
IOL = +2 mA Outputs
Low Level Output Voltage GND 0.45 V
VDDIO = 1.71V to 1.89V, Deserializer LVCMOS
IOL = +4 mA Outputs
IOS Serializer GPIO -11
Outputs
Output Short Circuit VOUT = 0V mA
Current Deserializer LVCMOS -20
Outputs
IOZ TRI-STATE Output PDB = 0V, VOUT = 0V or LVCMOS Outputs -20 ±1 +20 µA
Current VDD
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD| Output Differential Voltage RT= 100Ω(Figure 8) 268 340 412 mV
Output Differential Voltage
ΔVOD RL= 100Ω1 50 mV
Unbalance
VOS Output Differential Offset VDD (MIN) - VDD (MAX) -
RL= 100Ω(Figure 8) VDD - VOD V
Voltage VOD (MAX) VOD (MIN)
ΔVOS Offset Voltage Unbalance RL= 100Ω1 50 mV
IOS Output Short Circuit DOUT+/- = 0V, -27 mA
Current
RTDifferential Internal Differential across DOUT+ and DOUT- 80 100 120 Ω
Termination Resistance
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
Differential Threshold High
VTH +90
Voltage (Figure 10) mV
VTL Differential Threshold Low -90
Voltage
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA= +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
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SNLS322E –JUNE 2010–REVISED APRIL 2013
Electrical Characteristics(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
VIN Differential Input Voltage RIN+ - RIN- 180 mV
Range
IIN Input Current VIN = VDD or 0V, VDD = 1.89V -20 ±1 +20 µA
RTDifferential Internal Differential across RIN+ and RIN- 80 100 120 Ω
Termination Resistance
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
IDDT RT= 100Ω
WORST CASE pattern 62 90
Serializer (Tx) VDDn = 1.89V
(Figure 5)
VDDn Supply Current PCLK = 43 MHz mA
RT= 100Ω
(includes load current) Default Registers
RANDOM PRBS-7 55
pattern
IDDIOT VDDIO = 1.89V
PCLK = 43 MHz 2 5
Serializer (Tx) RT= 100ΩDefault Registers
VDDIO Supply Current WORST CASE pattern mA
VDDIO = 3.6V
(includes load current) (Figure 5)PCLK = 43 MHz 7 15
Default Registers
IDDTZ VDDn = 1.89V 370 775
Serializer (Tx) Supply PDB = 0V; All other
IDDIOTZ VDDIO = 1.89V 55 125 µA
Current Power-down LVCMOS Inputs = 0V VDDIO = 3.6V 65 135
IDDR VDDn = 1.89V, CL= 8 pF PCLK = 43 MHz
WORST CASE Pattern, SSCG[3:0] = ON 60 96
Deserializer (Rx) VDDn (Figure 5) Default Registers
Supply Current (includes VDDn = 1.89V, CL= 8 pF
load current) PCLK = 43 MHz
RANDOM PRBS-7 53
Default Registers
Pattern mA
IDDIOR VDDIO = 1.89V, CL= 8 pF PCLK = 43 MHz
WORST CASE Pattern, 16 25
Deserializer (Rx) VDDIO Default Registers
(Figure 5)
Supply Current (includes
load current) VDDIO = 3.6V, CL= 8 pF PCLK = 43 MHz 38 64
WORST CASE Pattern Default Registers
IDDRZ VDDn = 1.89V 42 400
Deserializer (Rx) Supply PDB = 0V; All other
IDDIORZ VDDIO = 1.89V 8 40 µA
Current Power-down LVCMOS Inputs = 0V VDDIO = 3.6V 350 800
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Recommended Serializer Timing for PCLK(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
tTCP Transmit Clock Period 23.3 T 100 ns
tTCIH Transmit Clock Input High 0.4T 0.5T 0.6T ns
Time 10 MHz – 43 MHz
tTCIL Transmit Clock Input Low 0.4T 0.5T 0.6T ns
Time
tCLKT PCLK Input Transition Time 0.5 3 ns
(Figure 11)
fOSC Internal oscillator clock 25 MHz
source
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
tLHT CML Low-to-High Transition RL= 100Ω(Figure 6) 150 330 ps
Time
tHLT CML High-to-Low Transition RL= 100Ω(Figure 6) 150 330 ps
Time
tDIS Data Input Setup to PCLK 2.0 ns
Serializer Data Inputs (Figure 12)
tDIH Data Input Hold from PCLK 2.0 ns
tPLD Serializer PLL Lock Time RL= 100Ω(1)(2) 1 2 ms
tSD RT= 100Ω, PCLK = 10–43 MHz 6.386T +
Serializer Delay Register 0x03h b[0] (TRFB = 1) 6.386T + 5 6.386T + 12 ns
19.7
(Figure 14)
tJIND Serializer output
intrinsic deterministic jitter .
Serializer Output Deterministic Measured (cycle-cycle) with 0.13 UI
Jitter PRBS-7 test pattern
PCLK = 43 MHz(3)(4)
tJINR Serializer output intrinsic random
Serializer Output Random jitter (cycle-cycle). Alternating-1,0 0.04 UI
Jitter pattern.
PCLK = 43 MHz(3)(4)
tJINT Serializer output peak-to-peak jitter
includes deterministic jitter,
random jitter, and jitter transfer
Peak-to-peak Serializer Output from serializer input. Measured 0.396 UI
Jitter (cycle-cycle) with PRBS-7 test
pattern.
PCLK = 43 MHz(3)(4)
λSTXBW Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 1.90 MHz
Function -3 dB Bandwidth (Figure 20)(3)
δSTX Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 0.944 dB
Function (Peaking) (Figure 20)(3)
δSTXf Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 500 kHz
Function (Peaking Frequency) (Figure 20)(3)
(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA= +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
tRCP Receiver Output Clock Period tRCP = tTCP PCLK 23.3 T 100 ns
tPDC Default Registers
PCLK Duty Cycle PCLK 45 50 55 %
SSCG[3:0] = OFF
LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or
tCLH 1.3 2.0 2.8
Time 3.0V to 3.6V,
CL= 8 pF (lumped load) PCLK ns
tCHL LVCMOS High-to-Low Transition Default Registers 1.3 2.0 2.8
Time (Figure 16)(1)
LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or
tCLH 1.6 2.4 3.3
Time 3.0V to 3.6V, ROUT[13:0],
CL= 8 pF (lumped load) ns
tCHL HSYNC, VSYNC
LVCMOS High-to-Low Transition Default Registers 1.6 2.4 3.3
Time (Figure 16)(1)
tROS ROUT Setup Data to PCLK VDDIO: 1.71V to 1.89V or 0.38T 0.5T
3.0V to 3.6V,
tROH ROUT[13:0],
CL= 8 pF (lumped load) ns
HSYNC, VSYNC
ROUT Hold Data to PCLK 0.38T 0.5T
Default Registers
(Figure 18)
Default Registers 4.571T 4.571T 4.571T
tDD Deserializer Delay Register 0x03h b[0] 10 MHz–43 MHz ns
+ 8 + 12 + 16
(RRFB = 1) (Figure 17)
tDDLT Deserializer Data Lock Time (Figure 15)(2) 10 MHz–43 MHz 10 ms
tRJIT (Figure 19,
Receiver Input Jitter Tolerance 43 MHz 0.53 UI
Figure 21)(3)(4)
tRCJ 10 MHz 300 550
PCLK
Receiver Clock Jitter ps
SSCG[3:0] = OFF(1)(5) 43 MHz 120 250
tDPJ 10 MHz 425 600
PCLK
Deserializer Period Jitter ps
SSCG[3:0] = OFF(1)(6) 43 MHz 320 480
tDCCJ 10 MHz 320 500
Deserializer Cycle-to-Cycle Clock PCLK ps
Jitter SSCG[3:0] = OFF(7)(1) 43 MHz 300 500
fdev Spread Spectrum Clocking ±0.5% to
20 MHz–43 MHz %
LVCMOS Output Bus
Deviation Frequency ±2.0%
SSC[3:0] = ON
fmod Spread Spectrum Clocking 9 kHz to
(Figure 22)20 MHz–43 MHz kHz
Modulation Frequency 66 kHz
(1) Specification is by characterization and is not tested in production.
(2) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(4) tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(5) tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(6) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(7) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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Bidirectional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified. See Figure 4.
Symbol Parameter Conditions Min Typ Max Units
RECOMMENDED INPUT TIMING REQUIREMENTS(1)
fSCL SCL Clock Frequency >0 100 kHz
tLOW SCL Low Period 4.7 µs
tHIGH SCL High Period 4.0 µs
Hold time for a start or a repeated start
tHD:STA 4.0 µs
condition
Set Up time for a start or a repeated
tSU:STA 4.7 µs
start condition fSCL = 100 kHz
tHD:DAT Data Hold Time 0 3.45 µs
tSU:DAT Data Set Up Time 250 ns
tSU:STO Set Up Time for STOP Condition 4.0 µs
trSCL & SDA Rise Time 1000 ns
tfSCL & SDA Fall Time 300 ns
CbCapacitive load for bus 400 pF
SWITCHING CHARACTERISTICS(2)
Serializer MODE = 0 – R/W 100
Register 0x05 = 0x40'h
fSCL SCL Clock Frequency kHz
Deserializer MODE = 0 – READ 100
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
tLOW SCL Low Period 4.7 µs
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W
Register 0x05 = 0x40'h
tHIGH SCL High Period 4.0 µs
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Hold time for a start or a repeated start Serializer MODE = 0
tHD:STA 4.0 µs
condition Register 0x05 = 0x40'h
Set Up time for a start or a repeated Serializer MODE = 0
tSU:STA 4.7 µs
start condition Register 0x05 = 0x40'h
tHD:DAT Data Hold Time 0 3.45 µs
tSU:DAT Data Set Up Time 250 ns
tSU:STO Set Up Time for STOP Condition Serializer MODE = 0 4.0 µs
tfSCL & SDA Fall Time 300 ns
Bus free time between a stop and start Serializer MODE = 0
tBUF 4.7 µs
condition Serializer MODE = 1 1
tTIMEOUT NACK Time out ms
Deserializer MODE = 1 25
Register 0x06 b[2:0]=111'b
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
(2) Specification is by design.
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80%
20%
80%
20% Vdiff = 0V
tLHT tHLT
Vdiff
Vdiff = (DOUT+) - (DOUT-)
PCLK
(RFB = H)
DIN/ROUT
Signal PatternDevice Pin Name
T
SCL
SDA
tHD;STA
tLOW
tr
tHD;DAT tHIGH
tf
tSU;DAT
tSU;STA tSU;STO
tf
START REPEATED
START STOP
tHD;STA
START
trtBUF
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Figure 4. Bidirectional Control Bus Timing
Bidirectional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
VIH 0.7 x
Input High Level SDA and SCL VDDIO V
VDDIO
VIL 0.3 x
Input Low Level Voltage SDA and SCL GND V
VDDIO
VHY Input Hysteresis SDA and SCL >50 mV
IOZ TRI-STATE Output Current PDB = 0V, VOUT = 0V or VDD -20 ±1 +20 µA
IIN SDA or SCL,
Input Current -20 ±1 +20 µA
Vin = VDDIO or GND
CIN Input Pin Capacitance <5 pF
VOL SCL and SDA, VDDIO = 3.0V 0.36 V
IOL = 1.5 mA
Low Level Output Voltage SCL and SDA, VDDIO = 1.71V 0.36 V
IOL = 1 mA
AC Timing Diagrams and Test Circuits
Figure 5. “Worst Case” Test Pattern
Figure 6. Serializer CML Output Load and Transition Times
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80%
20%
80%
20%
tCLKT tCLKT
PCLK
VDD
0V
RIN+
RIN-
VCM
GND
RIN+
RIN-
VTH VTL
VID VIN VIN VID
DOUT+
0V
0V
VOD+
VOD+
VOD-
VOD-
VOD
Single Ended
Differential
VOS
DOUT-
(DOUT+)-(DOUT-)
|
PARALLEL-TO-SERIAL
DOUT+
DOUT-
16
DIN/HS/VS RL
PCLK
ZDiff = 100:100:
DOUT+
DOUT-
100 nF
100 nF
SCOPE
BW 8 4.0 GHz
50:
50:
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Figure 7. Serializer CML Output Load and Transition Times
Figure 8. Serializer VOD DC Diagram
Figure 9. Serializer VOD DC Diagram
Figure 10. Differential VTH/VTL Definition Diagram
Figure 11. Serializer Input Clock Transition Times
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80%
20%
80%
20%
tCLH
Deserializer 8 pF
lumped
tCHL
||
LOCK
PDB VDDIO/2
|
TRI-STATE
tDDLT
RIN±
VDDIO/2
||
SYMBOL N
||
SYMBOL N-1
||
SYMBOL N-2
||
SYMBOL N-3SYMBOL N-4
||
DOUT+-
|
PCLK
tSD
DIN/HS/VS SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3
| |
|
|
|
| |
| |
| |
VDDIO/2
0V
VDDIO/2
PCLK
DOUT±Output Active
tPLD
PDB
TRI-STATE TRI-STATE
Setup
VDDIO/2 Hold
tDIH
tDIS
PCLK
DIN/HS/VS
tTCP
0V
VDDIO/2
VDDIO/2 VDDIO/2VDDIO/2
VDDIO
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Figure 12. Serializer Setup/Hold Times
Figure 13. Serializer Data Lock Time
Figure 14. Serializer Delay
Figure 15. Deserializer Data Lock Time
Figure 16. Deserializer LVCMOS Output Load and Transition Times
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-18
-12
-14
-8
-4
-2
2
1.0E+06 1.0E+07
MODULATION FREQUENCY (Hz)
JITTER TRANSFER (dB)
-16
-10
-6
0
1.0E+051.0E+04
tBIT (1 UI)
Sampling
Window Ideal Data
Bit End
Ideal Data Bit
Beginning
RxIN_TOL
Left RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tRJIT = RxIN_TOL (Left + Right)
VTH
VTL
0V
Sampling Window = 1 UI - tRJIT
1/2 VDDIO 0V
VDDIO
0V
VDDIO
tROS tROH
PCLK
ROUT[n],
VS, HS 1/2 VDDIO 1/2 VDDIO
1/2 VDDIO
tRCP
|
|
||
||
SYMBOL N + 2
||
SYMBOL N
RIN±
PCLK
SYMBOL N - 1 SYMBOL N
| |
||
SYMBOL N+1
| |
| |
| |
| |
|
ROUT/
VS/HS
|
|
|
|
VDDIO/2
0V
SYMBOL N + 1 SYMBOL N + 3 SYMBOL N + 3
SYMBOL N - 2SYMBOL N - 3
tDD
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Figure 17. Deserializer Delay
Figure 18. Deserializer Output Setup/Hold Times
Figure 19. Receiver Input Jitter Tolerance
Figure 20. Typical Serializer Jitter Transfer Function Curve at 43 MHz
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1 / fmod
FPCLK+
FPCLK-
fdev
fdev (max)
fdev (min)
FPCLK
Frequency
Time
0.52
0.55
0.54
0.57
0.59
0.60
0.62
1.0E+04 1.0E+06 1.0E+07
JITTER FREQUENCY (Hz)
JITTER AMPLITUDE (UI)
0.53
0.56
0.58
0.61
1.0E+05
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Figure 21. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz
Figure 22. Spread Spectrum Clock Output Profile
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Table 1. DS90UB901Q Control Registers
Addr Name Bits Field R/W Default Description
(Hex)
7-bit address of Serializer; 0x58'h
7:1 DEVICE ID (1011_000X'b) default
0 I2C Device ID RW 0xB0'h 0: Device ID is from ID[x]
0 SER ID SEL 1: Register I2C Device ID overrides ID[x]
7:3 RESERVED 0x00'h Reserved
Standby mode control. Retains control register data.
Supported only when MODE = 0
2 STANDBY RW 0 0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1 Reset 1: Disabled. Standby and wake-up disabled
DIGITAL 0 1: Resets the device to default register values. Does not
1 RW
RESET0 self clear affect device I2C Bus or Device ID
0 1: Digital Reset, retains all register values
0 DIGITAL RESET1 RW self clear
2 Reserved 7:0 RESERVED 0x20'h Reserved
Back Channel CRC Enable
RX CRC 0: Disable
7 CHECKER RW 1 1: Enable
ENABLE For proper CRC operation, on Deserailizer 0x03h b[6]
CRC Fault control register must be Enabled.
Tolerant Foward Channel CRC Enable
Transmission 0: Disable
TX CRC GEN
6 RW 1 1: Enable
ENABLE For proper CRC operation, on Deserailizer 0x03h b[7]
control register must be Enabled.
Auto VDDIO detect
Allows manual setting of VDDIO by register.
VDDIO Control 5 VDDIO CONTOL RW 1 0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
Only used when VDDIOCONTROL = 0
3VDDIO Mode 4 VDDIO MODE RW 1 0: 1.8V
1: 3.3V
I2C Pass-Through
I2C PASS-
I2C Pass-Through 3 RW 1 0: Disabled
THROUGH 1: Enabled
RESERVED 2 RESERVED 0 Reserved
Switch over to internal 25 MHz Oscillator clock in the
absence of PCLK
PCLK_AUTO 1 PCLK_AUTO RW 1 0: Disable
1: Enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
TRFB 0 TRFB RW 1 Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
7:6 RESERVED 10'b Reserved
CRC 5 CRC RESET RW 0 1: CRC Reset.
4Transmission Clears CRC Error counter.
4:0 RESERVED 00000'b Reserved
I2C SCL frequency is determined by the following:
fSCL = 6.25 MHz / Register value (in decimal)
5 I2C Bus Rate 7:0 I2C BUS RATE RW 0x40'h 0x40'h = ~100 kHz SCL (default)
Note: Register values <0x32'h are NOT supported.
RW 0xC0'h Deserializer Device ID = 0x60'h
7:1 DES DEV ID (1100_000X'b) default
6 DES ID 0 RESERVED Reserved
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Table 1. DS90UB901Q Control Registers (continued)
Addr Name Bits Field R/W Default Description
(Hex)
7:1 SLAVE DEV ID RW 0x00'h Slave Device ID. Sets remote slave I2C address.
7 Slave ID 0 RESERVED Reserved
8 Reserved 7:0 RESERVED 0x00'h Reserved
9 Reserved 7:0 RESERVED 0x01'h Reserved
A CRC Errors 7:0 CRC ERROR B0 R 0x00'h Number of CRC errors - 8 LSBs
B CRC Errors 7:0 CRC ERROR B1 R 0x00'h Number of CRC errors - 8 MSBs
Reserved 7:3 RESERVED 0x00'h Reserved
1: Valid PCLK detected
PCLK Detect 2 PCLK DETECT R 0 0: Valid PCLK not detected
CCRC Check 1 DES ERROR R 0 1: CRC error during communication with Deserializer
Cable Link Detect 0: Cable link not detected
0 LINK DETECT R 0
Status 1: Cable link detected
7:4 RESERVED 0001'b Reserved
3:2 RESERVED 00'b Reserved
0: Output
D GPIO[0] Config 1 GPIO0 DIR RW 0 1: Input
0: TRI-STATE
0 GPIO0 EN RW 1 1: Enabled
7:4 RESERVED 0000'b Reserved
3:2 RESERVED 00'b Reserved
0: Output
E GPIO[1] Config 1 GPIO1 DIR RW 0 1: Input
0: TRI-STATE
0 GPIO1 EN RW 1 1: Enabled
7:4 RESERVED 0000'b Reserved
3:2 RESERVED 00'b Reserved
0: Output
F GPIO[2] Config 1 GPIO2 DIR RW 1 1: Input
0: TRI-STATE
0 GPIO2 EN RW 1 1: Enabled
7:4 RESERVED 0000'b Reserved
3:2 RESERVED 00'b Reserved
0: Output
10 GPIO[3] Config 1 GPIO3 DIR RW 1 1: Input
0: TRI-STATE
0 GPIO3 EN RW 1 1: Enabled
7:4 RESERVED 0000'b Reserved
3:2 RESERVED 00'b Reserved
0: Output
11 GPIO[4] Config 1 GPIO4 DIR RW 1 1: Input
0: TRI-STATE
0 GPIO4 EN RW 1 1: Enabled
7:4 RESERVED 0000'b Reserved
3:2 RESERVED 00'b Reserved
0: Output
12 GPIO[5] Config 1 GPIO5 DIR RW 1 1: Input
0: TRI-STATE
0 GPIO5 EN RW 1 1: Enabled
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Table 1. DS90UB901Q Control Registers (continued)
Addr Name Bits Field R/W Default Description
(Hex)
GPCR[7] 0: LOW
GPCR[6] 1: HIGH
GPCR[5]
GPCR[4]
General Purpose
13 7:0 RW 0x00'h
Control Reg GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
Table 2. DS90UB902Q Control Registers
Addr Name Bits Field R/W Default Description
(Hex)
RW 0xC0'h 7-bit address of Deserializer; 0x60h
7:1 DEVICE ID (1100_000X) default
0 I2C Device ID 0: Device ID is from ID[x]
0 DES ID SEL 1: Register I2C Device ID overrides ID[x]
7:3 RESERVED 0x00'h Reserved
Remote Wake-up Select
1: Enable
Generate remote wakeup signal automatically wake-up
2 REM_WAKEUP RW 0 the Serializer in Standby mode
0: Disable
1 Reset Puts the Serializer (MODE = 0) in Standby mode when
Deserializer MODE = 1
0 1: Resets the device to default register values. Does not
1 DIGITALRESET0 RW self clear affect device I2C Bus or Device ID
0 1: Digital Reset, retains all register values
0 DIGITALRESET1 RW self clear
RESERVED 7:6 RESERVED 00'b Reserved
1: Output PCLK or Internal 25 MHz Oscillator clock
Auto Clock 5 AUTO_CLOCK RW 0 0: Only PCLK when valid PCLK present
Output Sleep State Select
OSS Select 4 OSS_SEL RW 0 0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
20100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
SSCG 3:0 SSCG 0000'b 0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
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Table 2. DS90UB902Q Control Registers (continued)
Addr Name Bits Field R/W Default Description
(Hex)
Back Channel CRC Enable
TX CRC 0: Disable
7 CHECKER RW 1 1: Enable
ENABLE For proper CRC operation, on Serailizer 0x03h b[6]
CRC Fault control register must be Enabled.
Tolerant Foward Channel CRC Enable
Transmission 0: Disable
RX CRC GEN
6 RW 1 1: Enable
ENABLE For proper CRC operation, on Serailizer 0x03h b[7]
control register must be Enabled.
Auto voltage control
VDDIO Control 5 VDDIO CONTROL RW 1 0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
3Only used when VDDIOCONTROL = 0
VDDIO Mode 4 VDDIO MODE RW 0 0: 1.8V
1: 3.3V
I2C Pass-Through Mode
I2C PASS-
I2C Pass-Through 3 RW 1 0: Disabled
THROUGH 1: Enabled
0: Disable
Auto ACK 2 AUTO ACK RW 0 1: Enable
CRC Reset 1 CRC RESET RW 0 1: CRC reset
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
RRFB 0 RRFB RW 1 Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
4 EQ Control 7:0 EQ RW 0x00'h 07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
5 RESERVED 7:0 RESERVED 0x00'h Reserved
RESERVED 7 RESERVED 0 Reserved
Prescales the SCL clock line when reading data byte
from a slave device (MODE = 0)
000 : ~100 kHz SCL (default)
001 : ~125 kHz SCL
SCL Prescale 6:4 SCL_PRESCALE RW 000'b 101 : ~11 kHz SCL
110 : ~33 kHz SCL
111 : ~50 kHz SCL
Other values are NOT supported.
Remote NACK Timer Enable
In slave mode (MODE = 1) if bit is set the I2C core will
REM_NACK_TIME automatically timeout when no acknowledge condition
6Remote NACK 3 RW 1
R was detected.
1: Enable
0: Disable
Remote NACK Timeout.
000: 2.0 ms
001: 5.2 ms
010: 8.6 ms
Remote NACK 2:0 NACK_TIMEOUT RW 111'b 011: 11.8 ms
100: 14.4 ms
101: 18.4 ms
110: 21.6 ms
111: 25.0 ms
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Table 2. DS90UB902Q Control Registers (continued)
Addr Name Bits Field R/W Default Description
(Hex)
RW 0xB0'h Serializer Device ID = 0x58'h
7:1 SER DEV ID (1011_000X'b) default
7 SER ID 0 RESERVED Reserved
7:1 ID[0] INDEX RW 0x00'h Target slave Device ID slv_id0 [7:1]
8 ID[0] Index 0 RESERVED Reserved
7:1 ID[1] INDEX Target slave Device ID slv_id1 [7:1]
9 ID[1] Index RW 0x00'h
0 RESERVED Reserved
7:1 ID[2] INDEX Target slave Device ID slv_id2 [7:1]
A ID[2] Index RW 0x00'h
0 RESERVED Reserved
7:1 ID[3] INDEX Target slave Device ID slv_id3 [7:1]
B ID[3] Index RW 0x00'h
0 RESERVED Reserved
7:1 ID[4] INDEX Target slave Device ID slv_id4 [7:1]
C ID[4] Index RW 0x00'h
0 RESERVED Reserved
7:1 ID[5] INDEX Target slave Device ID slv_id5 [7:1]
D ID[5] Index RW 0x00'h
0 RESERVED Reserved
7:1 ID[6] INDEX Target slave Device ID slv_id6 [7:1]
E ID[6] Index RW 0x00'h
0 RESERVED Reserved
7:1 ID[7] INDEX Target slave Device ID slv_id7 [7:1]
F ID[7] Index RW 0x00'h
0 RESERVED Reserved
7:1 ID[0] MATCH Alias to match Device ID slv_id0 [7:1]
10 ID[0] Match RW 0x00'h
0 RESERVED Reserved
7:1 ID[1] MATCH Alias to match Device ID slv_id1 [7:1]
11 ID[1] Match RW 0x00'h
0 RESERVED Reserved
7:1 ID[2] MATCH Alias to match Device ID slv_id2 [7:1]
12 ID[2] Match RW 0x00'h
0 RESERVED Reserved
7:1 ID[3] MATCH Alias to match Device ID slv_id3 [7:1]
13 ID[3] Match RW 0x00'h
0 RESERVED Reserved
7:1 ID[4] MATCH Alias to match Device ID slv_id4 [7:1]
14 ID[4] Match RW 0x00'h
0 RESERVED Reserved
7:1 ID[5] MATCH Alias to match Device ID slv_id5 [7:1]
15 ID[5] Match RW 0x00'h
0 RESERVED Reserved
7:1 ID[6] MATCH Alias to match Device ID slv_id6 [7:1]
16 ID[6] Match RW 0x00'h
0 RESERVED Reserved
7:1 ID[7] MATCH Alias to match Device ID slv_id [7:1]
17 ID[7] Match RW 0x00'h
0 RESERVED Reserved
18 RESERVED 7:0 RESERVED 0x00'h Reserved
19 RESERVED 7:0 RESERVED 0x01'h Reserved
1A CRC Errors 7:0 CRC ERROR B0 R 0x00'h Number of CRC errors 8 LSBs
1B CRC Errors 7:0 CRC ERROR B1 R 0x00'h Number of CRC errors 8 MSBs
RESERVED 7:3 RESERVED 0x00'h Reserved
CRC error during communication with Serializer on
CRC Check 2 SER ERROR R 0 Forward Channel
1C Signal Detect 0: Active signal not detected
1 R 0
Status 1: Active signal detected
0: CDR/PLL Unlocked
LOCK Pin Status 0 R 0 1: CDR/PLL Locked
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SNLS322E –JUNE 2010–REVISED APRIL 2013
Table 2. DS90UB902Q Control Registers (continued)
Addr Name Bits Field R/W Default Description
(Hex)
7:3 RESERVED 00010'b Reserved
1: Configured as GPIO
2 GPIO0 SET RW 1 0: Configured as ROUT data (OSS_SEL controlled)
1D GPIO[0] Config 0: Output
1 GPIO0 DIR 1 1: Input
0: TRI-STATE
0 GPIO0 EN RW 1 1: Enabled
7:3 RESERVED 0x00'h Reserved
1: Configured as GPIO
2 GPIO1 SET RW 1 0: Configured as ROUT data (OSS_SEL controlled)
1E GPIO[1] Config 0: Output
1 GPIO1 DIR RW 1 1: Input
0: TRI-STATE
0 GPIO1 EN RW 1 1: Enabled
7:3 RESERVED 0x00'h Reserved
1: Configured as GPIO
2 GPIO2 SET RW 0 0: Configured as ROUT0 data (OSS_SEL controlled)
1F GPIO[2] Config 0: Output
1 GPIO2 DIR RW 0 1: Input
0: TRI-STATE
0 GPIO2 EN RW 1 1: Enabled
7:3 RESERVED 0x00'h Reserved
1: Configured as GPIO
2 GPIO3 SET RW 0 0: Configured as ROUT1 data (OSS_SEL controlled)
20 GPIO[3] Config 0: Output
1 GPIO3 DIR RW 0 1: Input
0: TRI-STATE
0 GPIO3 EN RW 1 1: Enabled
7:3 RESERVED 0x00'h Reserved
1: Configured as GPIO
2 GPIO4 SET RW 0 0: Configured as ROUT2 data (OSS_SEL controlled)
21 GPIO[4] Config 0: Output
1 GPIO4 DIR RW 0 1: Input
0: TRI-STATE
0 GPIO4 EN RW 1 1: Enabled
7:3 RESERVED 0x00'h Reserved
1: Configured as GPIO
2 GPIO5 SET RW 0 0: Configured as ROUT3 data (OSS_SEL controlled)
22 GPIO[5] Config 0: Output
1 GPIO5 DIR RW 0 1: Input
0: TRI-STATE
0 GPIO5 EN RW 1 1: Enabled
GPCR[7] 0: LOW
GPCR[6] 1: HIGH
GPCR[5]
General Purpose GPCR[4]
23 7:0 RW 0x00'h
Control Reg GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0] BIST Enable
24 BIST 0 BIST_EN RW 0 0: Normal operation
1: Bist Enable
25 BIST_ERR 7:0 BIST_ERR R 0x00'h Bist Error Counter
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Table 2. DS90UB902Q Control Registers (continued)
Addr Name Bits Field R/W Default Description
(Hex)
11: Enable remote wake mode
REM_WAKEUP_E
7:6 RW 00'b 00: Normal operation mode
Remote Wake N
26 Other values are NOT supported.
Enable 5:0 RESERVED RW 0 Reserved
7:6 BCC RW 00'b 11: Normal operation mode
27 BCC 5:0 RESERVED 0 Reserved
7:5 RESERVED 0 Reserved
CMLOUT P/N 1: Disabled (Default)
3F CMLOUT Config 4 RW 1
Enable 0: Enabled
3:0 RESERVED 0 Reserved
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SNLS322E –JUNE 2010–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The DS90UB901Q/902Q FPD-Link III chipset is intended for camera applications. The Serializer/ Deserializer
chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UB901Q transforms a 16-bit wide
parallel LVCMOS data bus along with a bidirectional control bus into a single high-speed differential pair. The
high-speed serial bit stream contains an embedded clock and DC-balance information which enhances signal
quality to support AC coupling. The DS90UB902Q receives the single serial data stream and converts it back into
a 16-bit wide parallel data bus together with the bidirectional control channel data bus.
The bidirectional control channel of the DS90UB901Q/902Q provides bidirectional communication between the
image sensor and Electronic Control Unit (ECU) over the same differential pair used for video data interface. This
interface offers advantages over other chipsets by eliminating the need for additional wires for programming and
control. The bidirectional control channel bus is controlled via an I2C port. The bidirectional control channel offers
asymmetrical communication and is not dependent on video blanking intervals.
SERIAL FRAME FORMAT
The DS90UB901Q/902Q chipset will transmit and receive a pixel of data in the following format:
Figure 23. Serial Bitstream for 28-bit Symbol
The High Speed Forward Channel is a 28-bit symbol composed of 16 bits of data containing camera data &
control information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in
the serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal
transmission over an AC coupled link. Data is randomized, balanced and scrambled. The data payload may be
checked using a 4-bit CRC function. The CRC monitors the link integrity of the serialized data and reports when
an error condition is detected.
The bidirectional control channel data is transferred along with the high-speed forward data over the same serial
link. This architecture provides a full duplex low speed back channel across the serial link together with a high
speed forward channel without the dependence of the video blanking phase.
DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND I2C MODES
The I2C compatible interface allows programming of the DS90UB901Q, DS90UB902Q, or an external remote
device (such as a camera) through the bidirectional control channel. Register programming transactions to/from
the DS90UB901Q/902Q chipset are employed through the clock (SCL) and data (SDA) lines. These two signals
have open-drain I/Os and both lines must be pulled-up to VDDIO by external resistor. Figure 4 shows the timing
relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors or current sources are required on the
SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by driving
the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up externally. The
appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The
DS90UB901Q/902Q I2C bus data rate supports up to 100 kbps according to I2C specification.
To start any data transfer, the DS90UB901Q/902Q must be configured in the proper I2C mode. Each device can
function as an I2C slave proxy or master proxy depending on the mode determined by MODE pin. The Ser/Des
interface acts as a virtual bridge between Master controller (MCU) and the remote device. When the MODE pin
is set to High, the device is treated as a slave proxy; acts as a slave on behalf of the remote slave. When
addressing a remote peripheral or Serializer/Deserializer (not wired directly to the MCU), the slave proxy will
forward any byte transactions sent by the Master controller to the target device. When MODE pin is set to Low,
the device will function as a master proxy device; acts as a master on behalf of the I2C master controller. Note
that the devices must have complementary settings for the MODE configuration. For example, if the Serializer
MODE pin is set to High then the Deserializer MODE pin must be set to Low and vice-versa.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: DS90UB901Q DS90UB902Q
SDA
SCL
S P
START condition, or
START repeat condition STOP condition
SCL
SDA
START STOP
1 2 6 7 891 2 89
MSB
7-bit Slave Address R/W
Direction
BitAcknowledge
from the Device
MSB
Data Byte
*Acknowledge
or Not-ACK
ACK N/ACK
Repeated for the Lower Data Byte
and Additional Data Transfers
LSB LSB
Bus Activity:
Master
SDA Line
Bus Activity:
Slave
Start
Slave
Address
A
C
K
S
Address
A
C
K
S
Start
Slave
Address
A
C
K
N
A
C
K
P
Stop
Data
0 1
Register
7-bit Address 7-bit Address
A
C
K
A
C
K
A
C
K
SP
Stop
Bus Activity:
Slave
SDA Line
Bus Activity:
Master Slave
Address Address Data
Start
0
Register
7-bit Address
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
Figure 24. Write Byte
Figure 25. Read Byte
Figure 26. Basic Operation
Figure 27. START and STOP Conditions
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I2C bus through the bidirectional control
channel, slave clock stretching must be supported by the I2C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
prior to the 9th clock of every I2C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded.
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HOST SER
or
DES
SCL
SDA
RPU RPU
10 k:
RID
SCL
SDA
To other
Devices
ID[x]
1.8V
VDDIO
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E –JUNE 2010–REVISED APRIL 2013
Any remote access involves the clock stretching period following the transmitted byte, prior to completion of the
acknowledge bit. Since each byte transferred to the I2C slave must be acknowledged separately, the clock
stretching will be done for each byte sent by the host controller. For remote accesses, the “Response Delay”
shown is on the order of 12 µs (typical). See Application Note AN-2173 (SNLA131) for more details.
ID[X] ADDRESS DECODER
The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩresistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
Figure 28. Bidirectional Control Bus Connection
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ECU
Module
DS90UB902Q
Deserializer
DS90UB901Q
Serializer
DIN[13:0]
HS,VS
PCLK
CMOS
Image
Sensor
I2C
ROUT[13:0]
HS,VS
PCLK
I2C
SDA
SCL SDA
SCL
PC
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
Table 3. ID[x] Resistor Value – DS90UB901Q
ID[x] Resistor Value - DS90UB901Q Ser
Resistor RID Ω(±0.1%) Address 7'b(1) Address 8'b 0 appended (WRITE)
0, GND 7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0)
2.0k 7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2)
4.7k 7b' 101 1010 (h'5A) 8b' 1011 0100 (h'B4)
8.2k 7b' 101 1011 (h'5B) 8b' 1011 0110 (h'B6)
12.1k 7b' 101 1100 (h'5C) 8b' 1011 1000 (h'B8)
39.0k 7b' 101 1110 (h'5E) 8b' 1011 1100 (h'BC)
(1) Specification is by design.
Table 4. ID[x] Resistor Value – DS90UB902Q
ID[x] Resistor Value - DS90UB902Q Des
Resistor RID Ω(±0.1%) Address 7'b(1) Address 8'b 0 appended (WRITE)
0, GND 7b' 110 0000 (h'60) 8b' 1100 0000 (h'C0)
2.0k 7b' 110 0001 (h'61) 8b' 1100 0010 (h'C2)
4.7k 7b' 110 0010 (h'62) 8b' 1100 0100 (h'C4)
8.2k 7b' 110 0011 (h'63) 8b' 1101 0110 (h'C6)
12.1k 7b' 110 0100 (h'64) 8b' 1101 1000 (h'C8)
39.0k 7b' 110 0110 (h'66) 8b' 1100 1100 (h'CC)
(1) Specification is by design.
CAMERA MODE OPERATION
In Camera mode, I2C transactions originate from the Master controller at the Deserializer side (Figure 29). The
I2C slave core in the Deserializer will detect if a transaction is intended for the Serializer or a slave at the
Serializer. Commands are sent over the bidirectional control channel to initiate the transactions. The Serializer
will receive the command and generate an I2C transaction on its local I2C bus. At the same time, the Serializer
will capture the response on the I2C bus and return the response on the forward channel link. The Deserializer
parses the response and passes the appropriate response to the Deserializer I2C bus.
To configure the devices for camera mode operation, set the Serializer MODE pin to Low and the Deserializer
MODE pin to High. Before initiating any I2C commands, the Deserializer needs to be programmed with the target
slave device addresses and Serializer device address. SER_DEV_ID Register 0x07h sets the Serializer device
address and SLAVE_x_MATCH/SLAVE_x_INDEX registers 0x08h~0x17h set the remote target slave addresses.
In slave mode the address register is compared with the address byte sent by the I2C master. If the addresses
are equal to any of registers values, the I2C slave will acknowledge and hold the bus to propagate the transaction
to the target device otherwise it returns no acknowledge.
Figure 29. Typical Camera System Diagram
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DISPLAY MODE OPERATION
In Display mode, I2C transactions originate from the controller attached to the Serializer. The I2C slave core in
the Serializer will detect if a transaction targets (local) registers within the Serialier or the (remote) registers within
the Deserializer or a remote slave connected to the I2C master interface of the Deserializer. Commands are sent
over the forward channel link to initiate the transactions. The Deserializer will receive the command and generate
an I2C transaction on its local I2C bus. At the same time, the Deserializer will capture the response on the I2C
bus and return the response as a command on the bidirectional control channel. The Serializer parses the
response and passes the appropriate response to the Serializer I2C bus.
The physical device ID of the I2C slave in the Serializer is determined by the analog voltage on the ID[x] input. It
can be reprogrammed by using the DEVICE_ID register and setting the bit . The device ID of the logical I2C
slave in the Deserializer is determined by programming the DES ID in the Serializer. The state of the ID[x] input
on the Deserializer is used to set the device ID. The I2C transactions between Ser/Des will be bridged between
the host controller to the remote slave.
To configure the devices for display mode operation, set the Serializer MODE pin to High and the Deserializer
MODE pin to Low. Before initiating any I2C commands, the Serializer needs to be programmed with the target
slave device address and Serializer device address. DES_DEV_ID Register 0x06h sets the Deserializer device
address and SLAVE_DEV_ID register 0x7h sets the remote target slave address. If the I2C slave address
matches any of registers values, the I2C slave will hold the transaction allowing read or write to target device.
Note: In Display mode operation, registers 0x08h~0x17h on Deserializer must be reset to 0x00.
CRC (CYCLIC REDUNDANCY CHECK) DETECTION
A 4-bit CRC per symbol is reserved for checking the link integrity during transmission. The reporting status pin
(PASS) is provided on the Deserializer side, which flags any mismatch of data transmitted to and from the
remote device. The Deserializer's PLL must first be locked (LOCK pin HIGH) to ensure the PASS status is valid.
This error detection handling generates an interrupt signal onto the PASS output pin; notifying the host controller
as soon as any errors are identified. When an error occurs, the PASS asserts LOW. CRC registers (CRC
ERROR B0/B1) are also available for managing the data error count.
The DS90UB901Q/902Q chipset provides several mechanisms (operations) for ensuring data integrity in long
distance transmission and reception. The data error detection function offers user flexibility and usability of
performing bit-by-bit and data transmission error checking. The error detection operating modes support data
validation of the following signals:
• Bidirectional Channel Control
• Control VSYNC and HSYNC signals across serial link
• Parallel video/pixel data across serial link
PROGRAMMABLE CONTROLLER
An integrated I2C slave controller is embedded in each of the DS90UB901Q Serializer and DS90UB902Q
Deserializer. It must be used to access and program the extra features embedded within the configuration
registers. Refer to Table 1 and Table 2 for details of control registers.
MULTIPLE DEVICE ADDRESSING
Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C
bus. The DS90UB901/902 provides slave ID matching/aliasing to generate different target slave addresses when
connecting more than two identical devices together on the same bus. This allows the slave devices to be
independently addressed. Each device connected to the bus is addressable through a unique ID by programming
of the SLAVE_ID_MATCH register on Deserializer. This will remap the SLAVE_ID_MATCH address to the target
SLAVE_ID_INDEX address; up to 8 ID indexes are supported. The ECU Controller must keep track of the list of
I2C peripherals in order to properly address the target device. In a camera application, the microcontroller is
located on the Deserializer side. In this case, the microcontroller programs the slave address matching registers
and handles all data transfers to and from all slave I2C devices. This is useful in the event where camera
modules are removed or replaced.
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Product Folder Links: DS90UB901Q DS90UB902Q
ECU
Module
DS90UB902Q
DS90UB901Q
DIN[15:0]
PCLK
CMOS
Image
Sensor
I2C
ROUT[15:0]
PCLK
I2C
SDA
SCL SDA
SCL
PC
DES B: ID[x](0xC2)
SLAVE_ID2_MATCH(0xA4)
SLAVE_ID2_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA6)
SLAVE_ID2_INDEX(0xA2)
DS90UB902Q
DS90UB901Q
DIN[15:0]
PCLK
CMOS
Image
Sensor
I2C
ROUT[15:0]
PCLK
I2C
SDA
SCL SDA
SCL
Camera B
Slave ID: (0xA0)
SER A: ID[x](0xB0) DES A: ID[x](0xC0)
SLAVE_ID1_MATCH(0xA0)
SLAVE_ID1_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA2)
SLAVE_ID2_INDEX(0xA2)
Camera A
Slave ID: (0xA0)
Master
SER B: ID[x](0xB2)
Slave ID: (0xA2)
Slave ID: (0xA2)
PC/
EEPROM
PC /
EEPROM
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
For example in the configuration shown in Figure 30:
• ECU is the I2C master and has an I2C master interface
• The I2C interfaces in DES A and DES B are both slave interfaces
• The I2C protocol is bridged from DES A to SER A and from DES B to SER B
• The I2C interfaces in SER A and SER B are both master interfaces
If master controller transmits I2C slave 0xA0, the DES A address 0xC0 will forward the transaction to remote
Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognize that 0xA4 is mapped to
0xA0 and will be transmitted to the remote Camera B. If controller sends command to address 0xA6, the DES B
0xC2 will forward transaction to slave device 0xA2.
The Slave ID index/match is supported only in the camera mode (SER: MODE pin = L; DES: MODE pin = H).
For Multiple device addressing in display mode (SER: MODE pin = H; DES: MODE pin = L), use the I2C pass
through function.
Figure 30. Multiple Device Addressing
I2C PASS THROUGH
I2C pass-through provides an alternative means to independently address slave devices. The mode enables or
disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine
whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus
traffic will continue to pass through and will be received by I2C devices downstream. If disabled, I2C commands
will be blocked to the remote I2C device. The pass through function also provides access and communication to
only specific devices on the remote bus. The feature is effective for both Camera mode and Display mode.
For example in the configuration shown in Figure 31:
If master controller transmits I2C transaction for address 0xA0, the SER A with I2C pass through enabled will
transfer I2C commands to remote Camera A. The SER B with I2C pass through disabled, any I2C commands will
be bypassed on the I2C bus to Camera B.
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Figure 31. I2C Pass Through
SYNCHRONIZING MULTIPLE CAMERAS
For applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the General
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the birectional control channel, there will be a time variation of the GPIO signals arriving at the different target
devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across
multiple links is 25 us.
Note: The user must verify that the timing variations between the different links are within their system and timing
specifications.
For example in the configuration shown in (Figure 32):
The maximum time (t1) between the rising edge of GPIO (i.e. sync signal) arriving at Camera A and Camera B is
25 us.
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Product Folder Links: DS90UB901Q DS90UB902Q
DES A
GPIO[n] Input
DES B
GPIO[n] Input
SER A
GPIO[n] Output
SER B
GPIO[n] Output
t1
||
ECU
Module
DS90UB902Q
DS90UB901Q
CMOS
Image
Sensor
I2CI2C
PC
DS90UB902Q
DS90UB901Q
CMOS
Image
Sensor
I2CI2C
Camera B
Camera A
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
GPIO
GPIO
FSYNC
GPIO
GPIO
FSYNC
DATA
PCLK
DATA
PCLK
FSO FSO
FSIN FSIN
Deserializer A
Serializer A
Deserializer B
Serializer B
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
Figure 32. Synchronizing Multiple Cameras
Figure 33. GPIO Delta Latency
GENERAL PURPOSE I/O (GPIO)
The DS90UB901Q/902Q has up to 6 GPIO (2 dedicated and 4 programmable). GPIO[0] and GPIO[1] are always
available and GPIO[2:5] are available depending on the parallel data bus size. DIN/ROUT[0:3] can be
programmed into GPIOs (GPIO[2:5]) when the parallel data bus is less than 12 bits wide (10-bit data + HS,VS).
Each GPIO can be configured as either an input or output port. The GPIO maximum switching rate is up to 66
kHz when configured for communication between Deserializer GPI to Serializer GPO. Whereas data flow
configured for communication between Serializer GPI to Deserializer GPO is limited by the maximum data rate of
the PCLK.
AT-SPEED BIST (BISTEN, PASS)
An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and
the bidirectional control channel link. Control pins at the Deserializer are used to enable the BIST test mode and
allow the system to initiate the test and set the duration. A HIGH on PASS pin indicates that all payloads
received during the test were error free during the BIST duration test. A LOW on this pin at the conclusion of the
test indicates that one or more payloads were detected with errors.
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Product Folder Links: DS90UB901Q DS90UB902Q
BIST Wait
Step 1: Enable AT SPEED BIST by placing the
Deserializer in BIST by mode setting BISTEN = H
BIST Start
Step 2: Deserializer will setup Serializer and enable BIST
mode through Bidirectional control channel
communication and then reacquire forward channel clock
BIST Stop
Step 3: Stop AT SPEED BIST by turning off BIST
mode with BISTEN = L at the Deserializer.
Step 4: Place System in
Normal Operating Mode
BISTEN = L
Normal
Serializer MODE = 0 and Deserializer MODE = 1
Apply power for Serializer and Deserializer
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E –JUNE 2010–REVISED APRIL 2013
The BIST duration is defined by the width of BISTEN. BIST starts when Deserializer LOCK goes HIGH and
BISTEN is set HIGH. BIST ends when BISTEN goes LOW. Any errors detected after the BIST Duration are not
included in PASS logic.
Note: AT-SPEED BIST is only available in the Camera mode and not the Display mode
The following diagram shows how to perform system AT SPEED BIST:
Figure 34. AT-SPEED BIST System Flow Diagram
Step 1: Place the Deserializer in BIST Mode.
Serializer and Deserializer power supply must be supplied. Enable the AT SPEED BIST mode on the
Deserializer by setting the BISTEN pin High. The 902 GPIO[1:0] pins are used to select the PCLK frequency of
the on-chip oscillator for the BIST test on high speed data path.
Table 5. BIST Oscillator Frequency Select
Des GPIO[1:0] Oscillator Source min (MHz) typ (MHz) max (MHz )
00 External PCLK 10 43
01 Internal 50
10 Internal 25
11 Internal 12.5
The Deserializer GPIO[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer
PCLK input is required. This allows the user to operate BIST under different frequencies other than the
predefined ranges.
Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode.
Deserializer will communicate through the bidirectional control channel to configure Serializer into BIST mode.
Once the BIST mode is set, the Serializer will initiate BIST transmission to the Deserializer.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Links: DS90UB901Q DS90UB902Q
BIST Duration (s)
1 Pixel period (ns) x Total Bits x Total Pixels Transmitted = Total Bits Transmitted
Bit (Pixel) Error Rate
(for passing BIST) =[Total Bits Transmitted] -1
BIST Duration (s) x
=
=[Total Bits Transmitted x Bits/Pixel] -1
fpixel (MHz)
Pixel
BISTEN
Recovered
Pixel Clock
Recovered
Pixel Data
Previous
³&5&´6WDWH
PASS
Case 1: No bit errors
Start Pixel
Recovered
Pixel Data
Previous
³&5&´6WDWH
PASS
Case 2: Bit error(s)
Recovered
Pixel Data
Previous
³&5&´6WDWH
PASS
Case 3: Bit error(s) AFTER BIST
Duration
B B
B
B B
B = Bad Pixel
PE = Payload
Error
E E E E
CRC Status
(when BISTEN=L)
BIST Duration
(when BISTEN=H)
³&5&´6WDWH
³&5&´6WDWH
³&5&´6WDWH
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this
point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an
internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the
interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW
indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits in the serial frame fail, the PASS pin
will toggle ½ clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of
fails on the high speed link. In addition, there is a defined SER and DES register that will keep track of the
accumulated error count. The Serializer 901 GPIO[0] pin will be assigned as a PASS flag error indicator for the
bidirectional control channel link.
Figure 35. BIST Timing Diagram
Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail.
To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by
the BISTEN width and Deserializer LOCK is HIGH; thus the Bit Error Rate is determined by how long the system
holds BISTEN HIGH.
Figure 36. BIST BER Calculation
For instance, if BISTEN is held HIGH for 1 second and the PCLK is running at 43 MHz with 16 bpp, then the Bit
Error Rate is no better than 1.46E-9.
Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer.
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SNLS322E –JUNE 2010–REVISED APRIL 2013
Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to
Normal mode, apply Normal input data into the Serializer.
Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing
PDB. The default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to
the clock and data recovery of the link (whose status is flagged with LOCK pin).
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user seletable to provide compatibility with 1.8V and 3.3V system
interfaces.
REMOTE WAKE UP (Camera Mode)
After initial power up, the Serializer is in a low-power Standby mode. The Deserializer (controlled by ECU/MCU)
'Remote Wake-up' register allows the Deserializer side to generate a signal across the link to remotely wake-up
the Serializer. Once the Serializer detects the wake-up signal Serializer switches from Standby mode to active
mode. In active mode, the Serializer locks onto PCLK input (if present), otherwise the on-chip oscillator is used
as the input clock source. Note the MCU controller should monitor the Deserializer LOCK pin and confirm LOCK
= H before performing any I2C communication across the link.
For Remote Wake-up to function properly:
• The chipset needs to be configured in Camera mode: Serializer MODE = 0 and Deserializer MODE = 1
• Serializer expects remote wake-up by default at power on.
• Configure the control channel driver of the Deserializer to be in remote wake-up mode by setting Deserializer
Register 0x26h = 0xC0h.
• Perform remote wake-up on Serializer by setting Deserializer Register 0x01 b[2] = 1
• Return the control channel driver of the Deserializer to the normal operation mode by setting Deserializer
Register 0x26h = 0x00h
• Configure the control channel driver of the Deserializer to be in normal operation mode by setting Deserializer
Register 0x27h = 0xC0h.
Serializer can also be put into standby mode by programming the Deserializer remote wake-up control register
0x01 b[2] REM_WAKEUP to 0.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host
and is used to disable the Link to save power when the remote device is not operational. An auto mode is also
available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the
PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and
transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (High).
The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system
and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied
High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,
the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the
Data and PCLK outputs are set by the OSS_SEL control register.
POWER UP REQUIREMENTS AND PDB PIN
It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have
settled to the recommended operating voltages. A external RC network can be connected to the PDB pin to
ensure PDB arrives after all the VDD have stabilized.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: DS90UB901Q DS90UB902Q
DIN/
ROUT
PCLK
TRFB/RRFB: 0 TRFB/RRFB: 1
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting. Note this function can be observed at the CMLOUTP/N test port
enabled via the control registers.
EMI REDUCTION
Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
Des Spread Spectrum Clocking
The DS90UB902Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and
±0.5%–±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is
controlled through the SSC control registers.
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the Falling edge of the PCLK.
Figure 37. Programmable PCLK Strobe Select
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Product Folder Links: DS90UB901Q DS90UB902Q
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
HSYNC
VSYNC
PCLK
PDB
DOUT+
DOUT-
VDDCML
DAP (GND)
VDDPLL
VDDT
1.8V
DS90UB901Q (SER)
C4
C10 C5
C6
C1
C2
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k:(@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
LVCMOS
Parallel
Bus
Serial
FPD-Link III
Interface
MODE
ID[X]
VDDIO
RES
C3
LVCMOS
Control
Interface
VDDIO
1.8V
RID
10 k:
C9
C8
C12 C13
FB1 FB2
FB3
FB4
VDDD
C7 FB5
SCL
VDDIO
C15
RPU
C14
RPU
SDA
I2C
Bus
Interface FB6
FB7
GPIO[1]
GPIO[0]
GPIO
Control
Interface
C11
Optional
Optional
DOUT-
DOUT+
D
RIN-
RIN+
R
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E –JUNE 2010–REVISED APRIL 2013
APPLICATIONS INFORMATION
AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 38.
Figure 38. AC-Coupled Connection
For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
TYPICAL APPLICATION CONNECTION
Figure 39 shows a typical connection of the DS90UB901Q Serializer.
Figure 39. DS90UB901Q Typical Connection Diagram — Pin Control
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Links: DS90UB901Q DS90UB902Q
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
HSYNC
VSYNC
PCLK
PDB
DAP (GND)
RIN+
RIN-
VDDR
VDDIO3
VDDIO1
VDDIO2
LVCMOS
Parallel
Bus
VDDIO
DS90UB902Q (DES)
C9
C10
C1
C2
C3
VDDD
MODE
RES_PIN39
C4
1.8V
Serial
FPD-Link III
Interface
LOCK
PASS
C8
C15 C6
C16 C7
VDDPLL
VDDCML
VDDSSCG
RES_PIN32
RES_PIN33
TP_A
TP_B
LVCMOS
Control
Interface
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
C5
C13 C11 C12 C14
FB1 FB6
FB2
FB3
FB4
FB5
SCL
VDDIO
C18
RPU
C17
RPU
SDA
I2C
Bus
Interface FB7
FB8
GPIO[1]
GPIO[0] GPIO
Control
Interface
ID[X]
1.8V
RID
10 k:
Optional
Optional
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
Figure 40 shows a typical connection of the DS90UB902Q Deserializer.
Figure 40. DS90UB902Q Typical Connection Diagram — Pin Control
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link III interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
38 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB901Q DS90UB902Q
0 5 10
0
10
20
30
40
50
60
CABLE LENGTH (m)
PCLK FREQUENCY (MHz)
0
280
560
840
1120
1400
1680
MAX RAW SERIAL RATE (Mbps)
DS90UB901Q/902Q
15 20 25
70 1960
DS90UB901Q, DS90UB902Q
www.ti.com
SNLS322E –JUNE 2010–REVISED APRIL 2013
rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other
cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk
and pair-to-pair skew. The maximum length of cable that can be used is dependant on the quality of the cable
(gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (e.g. power
stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the CMLOUT P/N output. A differential probe should be used to measure across the
termination resistor at the CMLOUT P/N pins.
For obtaining optimal performance, we recommend:
• Use Shielded Twisted Pair (STP) cable
• 100Ωdifferential impedance and 24 AWG (or lower AWG) cable
• Low skew, impedance matched
• Ground and/or terminate unused conductors
Figure 41 shows the Typical Performance Characteristics demonstrating various lengths and data rates using
Rosenberger HSD and Leoni DACAR 538 Cable.
*Note: Equalization is enabled for cable lengths greater than 7 meters
Figure 41. Rosenberger HSD and Leoni DACAR 538 Cable Performance
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Links: DS90UB901Q DS90UB902Q
DS90UB901Q, DS90UB902Q
SNLS322E –JUNE 2010–REVISED APRIL 2013
www.ti.com
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to
ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled
lines will also radiate less.
Information on the WQFN style package is provided in Application Note: AN-1187 “Leadless Leadframe Package
(LLP) Application Report” (literature number SNOA401).
INTERCONNECT GUIDELINES
See Application Notes AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ωcoupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: www.ti.com/lvds
40 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB901Q DS90UB902Q
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www.ti.com
SNLS322E –JUNE 2010–REVISED APRIL 2013
Revision History
04/17/2012
• Added CMLOUT P/N to Deserializer Pin Descriptions
• Added CMLOUT P/N to Deserializer Pin Diagram
• Added ESD CDM and ESD MM values
• Added 3.3V I/O VOH conditions: IOH = -4 mA
• Corrected 3.3V I/O VOL conditions: IOL = +4 mA
• Changed NSID DS90UB901/902QSQX to qty 2500
• Added “Only used when VDDIOCONTROL = 0” note for Deserializer Register 0x03 bit[4] description
• Added Register 0x27 BCC in Deserializer Register table
• Added Register 0x3F CML Output in Deserializer Register table
• Updated SLAVE CLOCK STRETCHING in Functional Description section
• Updated REMOTE WAKE UP (Camera Mode) procedure in Functional Description section
• Updated Des - Receiver Input Equalization (EQ) in Functional Description section
• Updated TRANSMISSION MEDIA in Applications Information section
04/16/2013
• Changed layout of National Data Sheet to TI format
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 41
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PACKAGE OPTION ADDENDUM
www.ti.com 12-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90UB901QSQ/NOPB ACTIVE WQFN RTV 32 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB901SQ
DS90UB901QSQE/NOPB ACTIVE WQFN RTV 32 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB901SQ
DS90UB901QSQX/NOPB ACTIVE WQFN RTV 32 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB901SQ
DS90UB902QSQ/NOPB ACTIVE WQFN RTA 40 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB902QSQ
DS90UB902QSQE/NOPB ACTIVE WQFN RTA 40 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB902QSQ
DS90UB902QSQX/NOPB ACTIVE WQFN RTA 40 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB902QSQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Jun-2014
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90UB901QSQ/NOPB WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
DS90UB901QSQE/NOPB WQFN RTV 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
DS90UB901QSQX/NOPB WQFN RTV 32 2500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
DS90UB902QSQ/NOPB WQFN RTA 40 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1
DS90UB902QSQE/NOPB WQFN RTA 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1
DS90UB902QSQX/NOPB WQFN RTA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-May-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90UB901QSQ/NOPB WQFN RTV 32 1000 210.0 185.0 35.0
DS90UB901QSQE/NOPB WQFN RTV 32 250 210.0 185.0 35.0
DS90UB901QSQX/NOPB WQFN RTV 32 2500 367.0 367.0 35.0
DS90UB902QSQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0
DS90UB902QSQE/NOPB WQFN RTA 40 250 210.0 185.0 35.0
DS90UB902QSQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-May-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
5.15
4.85
5.15
4.85
0.8
0.7
0.05
0.00
2X 3.5
28X 0.5
2X 3.5
32X 0.5
0.3
32X 0.30
0.18
3.1 0.1
(0.1) TYP
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/A 06/2018
0.08 C
0.1 C A B
0.05
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PIN 1 INDEX AREA
SEATING PLANE
PIN 1 ID
SYMM
EXPOSED
THERMAL PAD
SYMM
1
8
916
17
24
25
32
33
SCALE 2.500
A
B
www.ti.com
EXAMPLE BOARD LAYOUT
28X (0.5)
(1.3)
(1.3)
(R0.05) TYP
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
32X (0.6)
32X (0.24)
(4.8)
(4.8)
(3.1)
(3.1)
( 0.2) TYP
VIA
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/A 06/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SYMM
SYMM
SEE SOLDER MASK
DETAIL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
1
8
916
17
24
25
32
33
METAL EDGE
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED) SOLDER MASK DEFINED
SOLDER MASK DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
32X (0.6)
32X (0.24)
28X (0.5)
(4.8)
(4.8)
(0.775) TYP
(0.775) TYP
4X (1.35)
4X (1.35)
(R0.05) TYP
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/A 06/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SYMM
SYMM
1
8
916
17
24
25
32
33
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
40X 0.3
0.2
4.6 0.1
40X 0.5
0.3
0.8 MAX
(0.1) TYP
0.05
0.00
36X 0.5
4X
4.5
A6.1
5.9 B
6.1
5.9 0.5
0.3
0.3
0.2
(0.2) TYP
WQFN - 0.8 mm max heightRTA0040A
PLASTIC QUAD FLATPACK - NO LEAD
4214989/B 02/2017
PIN 1 INDEX AREA
0.08 SEATING PLANE
1
10 21
30
11 20
40 31
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 2.200
DETAIL
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
40X (0.25)
40X (0.6)
( 0.2) TYP
VIA
36X (0.5)
(5.8)
(5.8)
( 4.6)
(R0.05) TYP
(0.74)
TYP
(1.31)
TYP
(0.74) TYP (1.31 TYP)
WQFN - 0.8 mm max heightRTA0040A
PLASTIC QUAD FLATPACK - NO LEAD
4214989/B 02/2017
SYMM
1
10
11 20
21
30
31
40
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
40X (0.6)
40X (0.25)
36X (0.5)
(5.8)
(5.8)
9X ( 1.28)
(1.48)
TYP
(R0.05) TYP
(1.48) TYP
WQFN - 0.8 mm max heightRTA0040A
PLASTIC QUAD FLATPACK - NO LEAD
4214989/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
SYMM
1
10
11 20
21
30
31
40
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