STM32F103xC STM32F103xD STM32F103xE High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces Features FBGA Core: ARM 32-bit CortexTM-M3 CPU - 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access - Single-cycle multiplication and hardware division Memories - 256 to 512 Kbytes of Flash memory - up to 64 Kbytes of SRAM - Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories - LCD parallel interface, 8080/6800 modes Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR, and programmable voltage detector (PVD) - 4-to-16 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC with calibration - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers 3 x 12-bit, 1 s A/D converters (up to 21 channels) - Conversion range: 0 to 3.6 V - Triple-sample and hold capability - Temperature sensor 2 x 12-bit D/A converters DMA: 12-channel DMA controller - Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs Debug mode - Serial wire debug (SWD) & JTAG interfaces - Cortex-M3 Embedded Trace MacrocellTM LFBGA100 10 x 10 mm LFBGA144 10 x 10 mm Up to 112 fast I/O ports - 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant Up to 11 timers - Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 2 x 16-bit motor control PWM timers with dead-time generation and emergency stop - 2 x watchdog timers (Independent and Window) - SysTick timer: a 24-bit downcounter - 2 x 16-bit basic timers to drive the DAC Up to 13 communication interfaces - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed - CAN interface (2.0B Active) - USB 2.0 full speed interface - SDIO interface CRC calculation unit, 96-bit unique ID ECOPACK(R) packages Table 1. Device summary Reference April 2011 WLCSP64 LQFP64 10 x 10 mm, LQFP100 14 x 14 mm, LQFP144 20 x 20 mm Part number STM32F103xC STM32F103RC STM32F103VC STM32F103ZC STM32F103xD STM32F103RD STM32F103VD STM32F103ZD STM32F103xE STM32F103RE STM32F103ZE STM32F103VE Doc ID 14611 Rev 8 1/130 www.st.com 1 Contents STM32F103xC, STM32F103xD, STM32F103xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2/130 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 15 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 21 2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.21 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Contents 2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.30 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 43 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 84 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.3.18 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Doc ID 14611 Rev 8 3/130 Contents 6 STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 121 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11 STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 64 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 65 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 79 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 82 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Doc ID 14611 Rev 8 5/130 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. 6/130 STM32F103xC, STM32F103xD, STM32F103xE I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 112 LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Recommended PCB design rules (0.5mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 117 LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 118 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 119 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24 STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25 STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26 STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27 STM32F103xC and STM32F103xE performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 46 Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 46 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 64 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 65 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 66 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 68 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 75 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 76 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 78 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 79 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Doc ID 14611 Rev 8 7/130 List of figures Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. 8/130 STM32F103xC, STM32F103xD, STM32F103xE NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 81 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 82 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 106 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 107 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 BGA pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 BGA pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 118 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 119 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. Doc ID 14611 Rev 8 9/130 Description 2 STM32F103xC, STM32F103xD, STM32F103xE Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM(R) CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xx high-density performance line family operates in the -40 to +105 C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F103xx high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC. 10/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 2.1 Description Device overview The STM32F103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts Peripherals Flash memory in Kbytes SRAM in Kbytes FSMC Timers STM32F103Rx 256 384 STM32F103Vx 512 64(1) 48 No 256 384 48 256 64 Yes General-purpose 4 Advanced-control 2 Basic 2 SPI(I2S)(3) 512 STM32F103Zx 384 48 (2) 512 64 Yes 3(2) 2C I 2 USART 5 USB 1 CAN 1 SDIO 1 Comm GPIOs 51 80 112 12-bit ADC Number of channels 3 16 3 16 3 21 12-bit DAC Number of channels 2 2 CPU frequency 72 MHz Operating voltage Operating temperatures Package 2.0 to 3.6 V Ambient temperatures: -40 to +85 C /-40 to +105 C (see Table 10) Junction temperature: -40 to + 125 C (see Table 10) LQFP64, WLCSP64 LQFP100, BGA100 LQFP144, BGA144 1. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only. 2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 3. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. Doc ID 14611 Rev 8 11/130 Description STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram Ibus Cortex-M3 CPU Fmax: 48/72 MHz NVIC GP DMA2 FSMC PLL Reset & Clock control AHB2 APB2 GPIO port C PD[15:0] GPIO port D PE[15:0] GPIO port E PF[15:0] GPIO port F PG[15:0] GPIO port G TIM1 VREF- VREF+ @VDD XTAL OSC 4-16 MHz RTC Backup reg AWU Backup interface AHB2 APB1 VSS NRST VDDA VSSA OSC_IN OSC_OUT VBAT =1.8 V to 3.6 V OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT TIM2 4 channels, ETR as AF TIM3 4 channels, ETR as AF TIM4 4 channels, ETR as AF TIM5 USART2 USART3 4 channels as AF RX, TX, CTS, RTS, CK as AF RX, TX, CTS, RTS, CK as AF UART4 RX,TX as AF UART5 RX,TX as AF SPI2 2x(8x16b it) / I2S2 MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF SPI3 2x(8x16b it) / I2S3 MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF TIM8 I2C1 SCL, SDA, SMBA as AF SPI1 SRAM 512 B I2C2 SCL, SDA, SMBA as AF USART1 WWDG bxCAN device USB 2.0 FS device Temp. sensor 8 ADC123_INs common to the 3 ADCs 8 ADC12_INs common to ADC1 & ADC2 5 ADC3_INs on ADC3 PVD XTAL32kHz APB1: Fmax = 24/36 MHz PC[15:0] Int @VDDA Supply supervision POR /PDR Standby interface @VBAT EXT.IT WKUP GPIO port B POR Reset Power Volt. reg. 3.3 V to 1.8 V IWDG PCLK1 PCLK2 HCLK FCLK SDIO GPIO port A RX, TX, CTS, RTS, CK as AF @VDDA RC 8 MHz RC 40 kHz 5 channels PA[15:0] MOSI, MISO, SCK, NSS as AF SRAM 64 KB GP DMA1 PB[15:0] 4 channels 3 compl. channels BKIN, ETR as AF 4 channels 3 compl. channels BKIN, ETR as AF Flash 512 Kbytes 64 bit 7 channels D[7:0] CMD CK as AF 112AF VDD Dbus System A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL (or NADV) as AF Trace controller Pbus Flash obl interface Trace/trig AHB: Fmax = 48/72 MHz NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF @VDD TPIU SW/JTAG Bus Matrix TRACECLK TRACED[0:3] as AS APB2: Fmax = 48/72 MHz Figure 1. STM32F103xC, STM32F103xD, STM32F103xE TIM6 IF 12bit DAC1 IF DAC_OUT1 as AF TIM7 12bit DAC 2 DAC_OUT2 as AF 12-bit ADC1 IF 12-bit ADC2 IF USBDP/CAN_TX USBDM/CAN_RX @VDDA 12-bit ADC3 IF @ VDDA ai14666f 1. TA = -40 C to +85 C (suffix 6, see Table 74) or -40 C to +105 C (suffix 7, see Table 74), junction temperature up to 105 C or 125 C, respectively. 2. AF = alternate function on I/O port pin. 12/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Figure 2. Description Clock tree FLITFCLK to Flash programming interface USB Prescaler /1, 1.5 USBCLK to USB interface 48 MHz I2S3CLK Peripheral clock enable 8 MHz HSI RC I2S2CLK to I2S2 Peripheral clock enable Peripheral clock enable HSI SDIOCLK FSMCCLK Peripheral clock enable 72 MHz max /2 PLLSRC to I2S3 /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..512 max PLLCLK HSE to FSMC HCLK to AHB bus, core, memory and DMA Clock Enable (4 bits) APB1 Prescaler /1, 2, 4, 8, 16 to SDIO to Cortex System timer FCLK Cortex free running clock 36 MHz max PCLK1 to APB1 peripherals Peripheral Clock Enable (20 bits) TIM2,3,4,5,6,7 If (APB1 prescaler =1) x1 else x2 CSS to TIM2,3,4,5,6 and 7 TIMXCLK Peripheral Clock Enable (6 bits) APB2 Prescaler /1, 2, 4, 8, 16 PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2 OSC32_OUT LSE OSC 32.768 kHz to RTC LSE RTCCLK to Independent Watchdog (IWDG) LSI ADC Prescaler /2, 4, 6, 8 /2 RTCSEL[1:0] LSI RC 40 kHz peripherals to APB2 Peripheral Clock Enable (15 bits) TIM1 & 8 timers If (APB2 prescaler =1) x1 else x2 /128 OSC32_IN PCLK2 72 MHz max to TIM1 and TIM8 TIMxCLK Peripheral Clock Enable (2 bit) to ADC1, 2 or 3 ADCCLK HCLK/2 To SDIO AHB interface Peripheral clock enable IWDGCLK Main Clock Output /2 MCO PLLCLK Legend: HSE = High Speed External clock signal HSI HSI = High Speed Internal clock signal HSE LSI = Low Speed Internal clock signal SYSCLK LSE = Low Speed External clock signal MCO ai14752b 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz. 3. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz, 28 MHz or 56 MHz. Doc ID 14611 Rev 8 13/130 Description 2.2 STM32F103xC, STM32F103xD, STM32F103xE Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low-density and high-density devices are an extension of the STM32F103x8/B mediumdensity devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC while remaining fully compatible with the other members of the family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 144 100 64 48 36 2 x USARTs 2 x 16-bit timers 1 x SPI, 1 x I2C, USB, CAN, 1 x PWM timer 2 x ADCs 3 x USARTs 3 x 16-bit timers 2 x SPIs, 2 x I2Cs, USB, CAN, 1 x PWM timer 2 x ADCs High-density devices 256 KB Flash 48 RAM 384 KB Flash 512 KB Flash 64 KB RAM 64 KB RAM 5 x USARTs 4 x 16-bit timers, 2 x basic timers 3 x SPIs, 2 x I2Ss, 2 x I2Cs USB, CAN, 2 x PWM timers 3 x ADCs, 2 x DACs, 1 x SDIO FSMC (100- and 144-pin packages(2)) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. 2. Ports F and G are not available in devices delivered in 100-pin packages. 14/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 2.3 Overview 2.3.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM Description The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory Up to 512 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: The three FSMC interrupt lines are ORed in order to be connected to the NVIC Write FIFO Code execution from external memory except for NAND Flash and PC Card The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz Doc ID 14611 Rev 8 15/130 Description 2.3.6 STM32F103xC, STM32F103xD, STM32F103xE LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 2.3.7 Nested vectored interrupt controller (NVIC) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. 2.3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. 16/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 2.3.10 Description Boot modes At startup, boot pins are used to select one of three boot options: Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes. Boot from system memory Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1. 2.3.11 Power supply schemes VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 12: Power supply scheme. 2.3.12 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.13 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. Doc ID 14611 Rev 8 17/130 Description 2.3.14 STM32F103xC, STM32F103xD, STM32F103xE Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.15 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC. 2.3.16 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a 18/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.17 Timers and watchdogs The high-density STM32F103xx performance line devices include up to two advancedcontrol timers, up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. High-density timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM1, TIM8 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2, TIM3, TIM4, TIM5 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for: Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. Doc ID 14611 Rev 8 19/130 Description STM32F103xC, STM32F103xD, STM32F103xE General-purpose timers (TIMx) There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 2.3.18 A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 20/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 2.3.19 Description Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.20 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.21 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. 2.3.22 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1. 2.3.23 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. Doc ID 14611 Rev 8 21/130 Description 2.3.24 STM32F103xC, STM32F103xD, STM32F103xE Universal serial bus (USB) The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 2.3.25 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.3.26 ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.27 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. 22/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Description This dual digital Interface supports the following features: two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.28 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.29 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.3.30 Embedded Trace MacrocellTM The ARM(R) Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. Doc ID 14611 Rev 8 23/130 Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE 3 Pinouts and pin descriptions Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout 1 2 3 4 5 6 7 8 9 10 11 12 A PC13TAMPER-RTC PE3 PE2 PE1 PE0 PB4 JTRST PB3 JTDO PD6 PD7 PA15 JTDI PA14 JTCK PA13 JTMS B PC14OSC32_IN PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12 C PC15OSC32_OUT VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 NC PA11 D OSC_IN VSS_5 VDD_5 PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9 E OSC_OUT PF3 PF4 PF5 VSS_3 VSS_11 VSS_10 PG9 PD2 PD0 PC9 PA8 F NRST PF7 PF6 VDD_4 VDD_3 VDD_11 VDD_10 VDD_8 VDD_2 VDD_9 PC8 PC7 G PF10 PF9 PF8 VSS_4 VDD_6 VDD_7 VDD_1 VSS_8 VSS_2 VSS_9 PG8 PC6 H PC0 PC1 PC2 PC3 VSS_6 VSS_7 VSS_1 PE11 PD11 PG7 PG6 PG5 J VSSA PA0-WKUP PA4 PC4 PB2/ BOOT1 PG1 PE10 PE12 PD10 PG4 PG3 PG2 K VREF- PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15 L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15 M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13 AI14798b 24/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout 1 A Pinouts and pin descriptions 2 PC14PC13OSC32_IN TAMPER-RTC 3 4 5 6 7 8 9 10 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PC2 PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7 F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6 G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15 H VREF- PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14 J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 AI14601c Doc ID 14611 Rev 8 25/130 Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line LQFP144 pinout 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 5. STM32F103xC, STM32F103xD, STM32F103xE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD_2 VSS_2 NC PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_9 VSS_9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD_8 VSS_8 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14667 26/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE STM32F103xC and STM32F103xE performance line LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 6. Pinouts and pin descriptions LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14391 Doc ID 14611 Rev 8 27/130 Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 7. STM32F103xC, STM32F103xD, STM32F103xE 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 ai14392 28/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Figure 8. Pinouts and pin descriptions STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side 8 7 6 5 4 3 2 1 A VDD_3 VSS_3 BOOT0 PB5 PB3 PD2 PC10 VDD_2 B PC14 PC15 PB9 PB6 PB4 PC11 PA14 BYPASS/ VSS_2 C PC13 NRST VBAT PB7 PC12 PA15 PA12 PA11 PC2 PB8 PA13 PA10 PA9 PC9 D OSC_IN OSC_OUT E PC0 VSSA PA1 PA5 PA8 PC8 PC7 PC6 F PC1 VREF+ PA0WKUP VSS_4 PB1 PB11 PB14 PB15 G VDDA PA3 VDD_4 PA6 PA7 PB10 PB12 PB13 H PA2 PA4 PC4 PC5 PB0 PB2 VSS_1 VDD_1 ai15460b Doc ID 14611 Rev 8 29/130 Pinouts and pin descriptions High-density STM32F103xx pin definitions Alternate functions(4) WLCSP64 LQFP64 LQFP100 LQFP144 Default LFBGA100 Main function(3) (after reset) LFBGA144 Type(1) Pins I / O Level(2) Table 5. STM32F103xC, STM32F103xD, STM32F103xE A3 A3 - - 1 1 PE2 I/O FT PE2 TRACECK/ FSMC_A23 A2 B3 - - 2 2 PE3 I/O FT PE3 TRACED0/FSMC_A19 B2 C3 - - 3 3 PE4 I/O FT PE4 TRACED1/FSMC_A20 B3 D3 - - 4 4 PE5 I/O FT PE5 TRACED2/FSMC_A21 B4 - - 5 5 PE6 I/O FT PE6 TRACED3/FSMC_A22 C2 B2 C6 1 6 6 VBAT A1 A2 C8 2 7 7 B1 A1 B8 3 8 8 C1 B1 B7 4 9 9 C3 - - - - 10 PF0 C4 - - - - 11 D4 - - - - E2 - - - E3 - - E4 - E3 Pin name S PC13-TAMPERI/O RTC(5) VBAT PC13(6) TAMPER-RTC I/O PC14(6) OSC32_IN PC15I/O OSC32_OUT(5) PC15(6) OSC32_OUT I/O FT PF0 FSMC_A0 PF1 I/O FT PF1 FSMC_A1 12 PF2 I/O FT PF2 FSMC_A2 - 13 PF3 I/O FT PF3 FSMC_A3 - - 14 PF4 I/O FT PF4 FSMC_A4 - - - 15 PF5 I/O FT PF5 FSMC_A5 D2 C2 - - 10 16 VSS_5 S VSS_5 D3 D2 - - 11 17 VDD_5 S VDD_5 F3 - - - - 18 PF6 I/O PF6 ADC3_IN4/FSMC_NIORD F2 - - - - 19 PF7 I/O PF7 ADC3_IN5/FSMC_NREG G3 - - - - 20 PF8 I/O PF8 ADC3_IN6/FSMC_NIOWR G2 - - - - 21 PF9 I/O PF9 ADC3_IN7/FSMC_CD G1 - - - - 22 PF10 I/O PF10 ADC3_IN8/FSMC_INTR PC14OSC32_IN(5) D1 C1 D8 5 12 23 OSC_IN I OSC_IN E1 D1 D7 6 13 24 OSC_OUT O OSC_OUT F1 E1 C7 7 14 25 NRST I/O NRST H1 F1 E8 8 15 26 PC0 I/O PC0 ADC123_IN10 H2 F2 F8 9 16 27 PC1 I/O PC1 ADC123_IN11 H3 E2 D6 10 17 28 PC2 I/O PC2 ADC123_IN12 H4 F3 11 18 29 PC3 I/O PC3 ADC123_IN13 J1 G1 E7 12 19 30 VSSA S VSSA 30/130 - Doc ID 14611 Rev 8 Remap STM32F103xC, STM32F103xD, STM32F103xE High-density STM32F103xx pin definitions (continued) - - 20 31 VREF- S VREF- - 21 32 VREF+ S VREF+ M1 K1 G8 13 22 33 VDDA S VDDA K1 H1 L1 J2 J1 F7 (7) LQFP144 LQFP100 Main function(3) (after reset) LQFP64 Type(1) Alternate functions(4) WLCSP64 LFBGA100 LFBGA144 Pins I / O Level(2) Table 5. Pinouts and pin descriptions G2 F6 14 23 34 K2 H2 E6 15 24 35 Pin name PA0-WKUP PA1 I/O I/O Default PA0 WKUP/USART2_CTS(8) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR PA1 USART2_RTS(8) ADC123_IN1/ TIM5_CH2/TIM2_CH2(8) J2 H8 16 25 36 PA2 I/O PA2 USART2_TX(8)/TIM5_CH3 ADC123_IN2/ TIM2_CH3 (8) M2 K2 G7 17 26 37 PA3 I/O PA3 USART2_RX(8)/TIM5_CH4 ADC123_IN3/TIM2_CH4(8) G4 E4 F5 18 27 38 VSS_4 S VSS_4 F4 VDD_4 S VDD_4 L2 F4 G6 19 28 39 Remap G3 H7 20 29 40 PA4 I/O PA4 SPI1_NSS(8)/ USART2_CK(8) DAC_OUT1/ADC12_IN4 K3 H3 E5 21 30 41 PA5 I/O PA5 SPI1_SCK(8) DAC_OUT2 ADC12_IN5 TIM1_BKIN TIM1_CH1N J3 J3 G5 22 31 42 PA6 I/O PA6 SPI1_MISO(8) TIM8_BKIN/ADC12_IN6 TIM3_CH1(8) M3 K3 G4 23 32 43 PA7 I/O PA7 SPI1_MOSI(8)/ TIM8_CH1N/ADC12_IN7 TIM3_CH2(8) J4 G4 H6 24 33 44 PC4 I/O PC4 ADC12_IN14 K4 H4 H5 25 34 45 PC5 I/O PC5 ADC12_IN15 L4 J4 H4 26 35 46 PB0 I/O PB0 ADC12_IN8/TIM3_CH3 TIM8_CH2N TIM1_CH2N M4 K4 F4 27 36 47 PB1 I/O PB1 ADC12_IN9/TIM3_CH4(8) TIM8_CH3N TIM1_CH3N J5 PB2 I/O FT PB2/BOOT1 L3 G5 H3 28 37 48 M5 - - - - 49 PF11 I/O FT PF11 FSMC_NIOS16 L5 - - - - 50 PF12 I/O FT PF12 FSMC_A6 Doc ID 14611 Rev 8 31/130 Pinouts and pin descriptions High-density STM32F103xx pin definitions (continued) Alternate functions(4) LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Main function(3) (after reset) LFBGA144 Type(1) Pins I / O Level(2) Table 5. STM32F103xC, STM32F103xD, STM32F103xE H5 - - - - 51 VSS_6 S VSS_6 G5 - - - - 52 VDD_6 S VDD_6 K5 - - - - 53 PF13 I/O FT PF13 FSMC_A7 M6 - - - - 54 PF14 I/O FT PF14 FSMC_A8 L6 - - - - 55 PF15 I/O FT PF15 FSMC_A9 K6 - - - - 56 PG0 I/O FT PG0 FSMC_A10 J6 - - - - 57 PG1 I/O FT PG1 FSMC_A11 M7 H5 - - 38 58 PE7 I/O FT PE7 FSMC_D4 TIM1_ETR L7 J5 - - 39 59 PE8 I/O FT PE8 FSMC_D5 TIM1_CH1N K7 K5 - - 40 60 PE9 I/O FT PE9 FSMC_D6 TIM1_CH1 H6 - - - - 61 VSS_7 S VSS_7 G6 - - - - 62 VDD_7 S VDD_7 J7 G6 - - 41 63 PE10 I/O FT PE10 FSMC_D7 TIM1_CH2N H8 H6 - - 42 64 PE11 I/O FT PE11 FSMC_D8 TIM1_CH2 J8 J6 - - 43 65 PE12 I/O FT PE12 FSMC_D9 TIM1_CH3N K8 K6 - - 44 66 PE13 I/O FT PE13 FSMC_D10 TIM1_CH3 L8 G7 - - 45 67 PE14 I/O FT PE14 FSMC_D11 TIM1_CH4 M8 H7 - - 46 68 PE15 I/O FT PE15 FSMC_D12 TIM1_BKIN TIM2_CH3 TIM2_CH4 Pin name Default J7 G3 29 47 69 PB10 I/O FT PB10 I2C2_SCL/USART3_TX(8) M10 K7 F3 30 48 70 PB11 I/O FT PB11 I2C2_SDA/USART3_RX(8) H7 E7 H2 31 49 71 VSS_1 S VSS_1 G7 F7 H1 32 50 72 VDD_1 S VDD_1 M9 Remap M11 K8 G2 33 51 73 PB12 I/O FT PB12 SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK(8)/ TIM1_BKIN(8) M12 J8 G1 34 52 74 PB13 I/O FT PB13 SPI2_SCK/I2S2_CK USART3_CTS(8)/ TIM1_CH1N L11 H8 F2 35 53 75 PB14 I/O FT PB14 SPI2_MISO/TIM1_CH2N USART3_RTS(8)/ L12 G8 F1 36 54 76 PB15 I/O FT PB15 SPI2_MOSI/I2S2_SD TIM1_CH3N(8)/ L9 K9 - - 55 77 PD8 I/O FT PD8 FSMC_D13 USART3_TX K9 J9 - - 56 78 PD9 I/O FT PD9 FSMC_D14 USART3_RX 32/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE High-density STM32F103xx pin definitions (continued) Alternate functions(4) LQFP100 J9 H9 - - 57 79 PD10 I/O FT PD10 FSMC_D15 USART3_CK H9 G9 - - 58 80 PD11 I/O FT PD11 FSMC_A16 USART3_CTS L10 K10 - - 59 81 PD12 I/O FT PD12 FSMC_A17 TIM4_CH1 / USART3_RTS K10 J10 - - 60 82 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2 G8 - - - - 83 VSS_8 S VSS_8 F8 - - - - 84 VDD_8 S VDD_8 K11 H10 - - 61 85 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 K12 G10 - - 62 86 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4 J12 - - - - 87 PG2 I/O FT PG2 FSMC_A12 J11 - - - - 88 PG3 I/O FT PG3 FSMC_A13 J10 - - - - 89 PG4 I/O FT PG4 FSMC_A14 H12 - - - - 90 PG5 I/O FT PG5 FSMC_A15 H11 - - - - 91 PG6 I/O FT PG6 FSMC_INT2 H10 - - - - 92 PG7 I/O FT PG7 FSMC_INT3 G11 - - - - 93 PG8 I/O FT PG8 G10 - - - - 94 VSS_9 S VSS_9 F10 - - - - 95 VDD_9 S VDD_9 LQFP144 LQFP64 Remap WLCSP64 Default LFBGA100 Main function(3) (after reset) LFBGA144 Type(1) Pins I / O Level(2) Table 5. Pinouts and pin descriptions Pin name G12 F10 E1 37 63 96 PC6 I/O FT PC6 I2S2_MCK/ TIM8_CH1/SDIO_D6 TIM3_CH1 F12 E10 E2 38 64 97 PC7 I/O FT PC7 I2S3_MCK/ TIM8_CH2/SDIO_D7 TIM3_CH2 F11 F9 E3 39 65 98 PC8 I/O FT PC8 TIM8_CH3/SDIO_D0 TIM3_CH3 E11 E9 D1 40 66 99 PC9 I/O FT PC9 TIM8_CH4/SDIO_D1 TIM3_CH4 E12 D9 E4 41 67 100 PA8 I/O FT PA8 USART1_CK/ TIM1_CH1(8)/MCO D12 C9 D2 42 68 101 PA9 I/O FT PA9 USART1_TX(8)/ TIM1_CH2(8) D11 D10 D3 43 69 102 PA10 I/O FT PA10 USART1_RX(8)/ TIM1_CH3(8) C12 C10 C1 44 70 103 PA11 I/O FT PA11 USART1_CTS/USBDM CAN_RX(8)/TIM1_CH4(8) B12 B10 C2 45 71 104 PA12 I/O FT PA12 USART1_RTS/USBDP/ CAN_TX(8)/TIM1_ETR(8) Doc ID 14611 Rev 8 33/130 Pinouts and pin descriptions High-density STM32F103xx pin definitions (continued) A12 A10 D4 46 72 105 C11 F8 - - Pin name PA13 Type(1) LQFP144 LQFP100 LQFP64 WLCSP64 LFBGA100 LFBGA144 Pins I / O Level(2) Table 5. STM32F103xC, STM32F103xD, STM32F103xE I/O FT 73 106 Alternate functions(4) Main function(3) (after reset) Default JTMSSWDIO Remap PA13 Not connected G9 E6 B1 47 74 107 VSS_2 S VSS_2 F9 F6 A1 48 75 108 VDD_2 S VDD_2 A11 A9 B2 49 76 109 PA14 I/O FT JTCKSWCLK A10 A8 C3 50 77 110 PA15 I/O FT JTDI SPI3_NSS/ I2S3_WS TIM2_CH1_ETR PA15 / SPI1_NSS B11 B9 A2 51 78 111 PC10 I/O FT PC10 UART4_TX/SDIO_D2 USART3_TX B10 B8 B3 52 79 112 PC11 I/O FT PC11 UART4_RX/SDIO_D3 USART3_RX C10 C8 C4 53 80 113 PC12 I/O FT PC12 UART5_TX/SDIO_CK USART3_CK E10 D8 D8 PD0 I/O FT OSC_IN(9) FSMC_D2(10) CAN_RX FSMC_D3(10) CAN_TX 81 114 82 115 PD1 I/O FT OSC_OUT(9) B7 A3 54 83 116 PD2 I/O FT PD2 TIM3_ETR/UART5_RX SDIO_CMD D10 E8 D7 E9 5 PA14 6 D9 C7 - - 84 117 PD3 I/O FT PD3 FSMC_CLK USART2_CTS C9 D7 - - 85 118 PD4 I/O FT PD4 FSMC_NOE USART2_RTS B9 B6 - - 86 119 PD5 I/O FT PD5 FSMC_NWE USART2_TX E7 - - - - 120 VSS_10 S VSS_10 F7 - - - - 121 VDD_10 S VDD_10 A8 C6 - - 87 122 PD6 I/O FT PD6 FSMC_NWAIT USART2_RX A9 D6 - - 88 123 PD7 I/O FT PD7 FSMC_NE1/FSMC_NCE2 USART2_CK E8 - - - - 124 PG9 I/O FT PG9 FSMC_NE2/FSMC_NCE3 D8 - - - - 125 PG10 I/O FT PG10 FSMC_NCE4_1/ FSMC_NE3 C8 - - - - 126 PG11 I/O FT PG11 FSMC_NCE4_2 B8 - - - - 127 PG12 I/O FT PG12 FSMC_NE4 D7 - - - - 128 PG13 I/O FT PG13 FSMC_A24 C7 - - - - 129 PG14 I/O FT PG14 FSMC_A25 E6 - - - - 130 VSS_11 S VSS_11 F6 - - - - 131 VDD_11 S VDD_11 B7 - - - - 132 PG15 34/130 I/O FT PG15 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE High-density STM32F103xx pin definitions (continued) Alternate functions(4) Default Remap I/O FT JTDO SPI3_SCK / I2S3_CK/ PB3/TRACESWO TIM2_CH2 / SPI1_SCK A6 A6 B4 56 90 134 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1 SPI1_MISO B6 C5 A5 57 91 135 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI I2S3_SD TIM3_CH2 / SPI1_MOSI C6 B5 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL(8)/ TIM4_CH1(8) USART1_TX LQFP144 PB3 LQFP100 A7 A4 55 89 133 LQFP64 A7 WLCSP64 LFBGA100 Main function(3) (after reset) LFBGA144 Type(1) Pins I / O Level(2) Table 5. Pinouts and pin descriptions Pin name I2C1_SDA(8) / FSMC_NADV / TIM4_CH2(8) USART1_RX PB8 TIM4_CH3(8)/SDIO_D4 I2C1_SCL/ CAN_RX I/O FT PB9 TIM4_CH4(8)/SDIO_D5 I2C1_SDA / CAN_TX D6 A5 C5 59 93 137 PB7 D5 D5 A6 60 94 138 BOOT0 C5 B4 D5 61 95 139 PB8 I/O FT B5 PB9 A4 B6 62 96 140 I/O FT I PB7 BOOT0 A5 D4 - - 97 141 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0 A4 C4 - - 98 142 PE1 I/O FT PE1 FSMC_NBL1 E5 E5 A7 63 99 143 VSS_3 S VSS_3 F5 F5 A8 64 100 144 VDD_3 S VDD_3 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The VREF+ functionality is provided instead. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 10. For devices delivered in LQFP64 packages, the FSMC function is not available. Doc ID 14611 Rev 8 35/130 Pinouts and pin descriptions Table 6. STM32F103xC, STM32F103xD, STM32F103xE FSMC pin definition FSMC Pins CF CF/IDE LQFP100 BGA100(1) PE2 A23 A23 Yes PE3 A19 A19 Yes PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PF0 A0 A0 A0 - PF1 A1 A1 A1 - PF2 A2 A2 A2 - PF3 A3 A3 - PF4 A4 A4 - PF5 A5 A5 - PF6 NIORD NIORD - PF7 NREG NREG - PF8 NIOWR NIOWR - PF9 CD CD - PF10 INTR INTR - PF11 NIOS16 NIOS16 - PF12 A6 A6 - PF13 A7 A7 - PF14 A8 A8 - PF15 A9 A9 - PG0 A10 A10 - A11 - PG1 36/130 NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM PE7 D4 D4 D4 DA4 D4 Yes PE8 D5 D5 D5 DA5 D5 Yes PE9 D6 D6 D6 DA6 D6 Yes PE10 D7 D7 D7 DA7 D7 Yes PE11 D8 D8 D8 DA8 D8 Yes PE12 D9 D9 D9 DA9 D9 Yes PE13 D10 D10 D10 DA10 D10 Yes PE14 D11 D11 D11 DA11 D11 Yes PE15 D12 D12 D12 DA12 D12 Yes PD8 D13 D13 D13 DA13 D13 Yes Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 6. Pinouts and pin descriptions FSMC pin definition (continued) FSMC Pins NOR/PSRAM/ NOR/PSRAM Mux NAND 16 bit SRAM LQFP100 BGA100(1) CF CF/IDE PD9 D14 D14 D14 DA14 D14 Yes PD10 D15 D15 D15 DA15 D15 Yes PD11 A16 A16 CLE Yes PD12 A17 A17 ALE Yes PD13 A18 A18 Yes PD14 D0 D0 D0 DA0 D0 Yes PD15 D1 D1 D1 DA1 D1 Yes PG2 A12 - PG3 A13 - PG4 A14 - PG5 A15 - PG6 INT2 - PG7 INT3 - PD0 D2 D2 D2 DA2 D2 Yes PD1 D3 D3 D3 DA3 D3 Yes CLK CLK PD3 Yes PD4 NOE NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes PD7 NE1 NE1 NCE2 Yes PG9 NE2 NE2 NCE3 - NE3 NE3 PG10 NCE4_1 NCE4_1 PG11 NCE4_2 NCE4_2 - PG12 NE4 NE4 - PG13 A24 A24 - PG14 A25 A25 - PB7 NADV NADV Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. Doc ID 14611 Rev 8 37/130 Memory mapping 4 STM32F103xC, STM32F103xD, STM32F103xE Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map Reserved FSMC register 0xA000 0000 - 0xA000 0FFF FSMC bank4 PCCARD 0x9000 0000 - 0x9FFF FFFF FSMC bank3 NAND (NAND2) 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC register 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank 3 & bank4 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 0x7000 0000 - 0x7FFF FFFF FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF FSMC bank1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF Reserved 0x4002 4400 - 0x5FFF FFFF Doc ID 14611 Rev 8 0x4002 2000 - 0x4002 23FF RCC 0x4002 1000 - 0x4002 13FF Reserved 0x4002 0400 - 0x4002 0FFF Reserved ADC3 USART1 TIM8 SPI1 TIM1 ADC2 0x4001 400 - 0x4001 7FFF 0x4001 3C00 - 0x4001 3FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF ADC1 Port G Port F Port E Port D Port C Port B Port A EXTI AFIO Reserved DAC PWR BKP Reserved BxCAN Shared USB/CAN SRAM 512 bytes USB registers I2C2 I2C1 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF 512-Mbyte block 0 Code 38/130 0x4002 1400 - 0x4002 1FFF 0x4002 0400 - 0x4002 07FF 0x2000 0000 0x1FFF FFFF Flash Reserved Aliased to Flash or system memory depending on BOOT pins 0x4002 2400 - 0x4002 2FFF 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF 512-Mbyte block 1 SRAM Option Bytes System memory Reserved 0x4002 3000 - 0x4002 33FF Reserved Flash interface Reserved DMA2 0x4000 0000 0x3FFF FFFF Reserved CRC DMA1 Reserved SDIO 512-Mbyte block 3 FSMC bank1 & bank2 SRAM (64 KB aliased by bit-banding) 0x8000 0000 - 0x8FFF FFFF FSMC bank2 NAND (NAND1) 512-Mbyte block 2 Peripherals 0x0000 0000 0xA000 1000 - 0xBFFF FFFF 0x4001 2800 - 0x4001 2BFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF 0x4000 6000 - 0x4000 63FF 0x4000 5C00 - 0x4000 5FFF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF UART5 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF USART3 USART2 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF Reserved 0x4000 4000 - 0x4000 43FF SPI3/I2 S3 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF Reserved IWDG 0x4000 3400 - 0x4000 37FF WWDG 0x4000 2C00 - 0x4000 2FFF RTC 0x4000 2800 - 0x4000 2BFF Reserved 0x4000 1800 - 0x4000 27FF TIM7 0x4000 1400 - 0x4000 17FF 0x4000 3000 - 0x4000 33FF TIM6 0x4000 1000 - 0x4000 13FF TIM5 0x4000 0C00 - 0x4000 0FFF TIM4 0x4000 0800 - 0x4000 0BFF TIM3 0x4000 0400 - 0x4000 07FF TIM2 0x4000 0000 - 0x4000 03FF 0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF F80F 0x1FFF F000- 0x1FFF F7FF 0x1FFF EFFF 0x0808 0000 0x0807 FFFF 0x0800 0000 0x07FF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000 ai14753d STM32F103xC, STM32F103xD, STM32F103xE 5 Electrical characteristics 5.1 Parameter conditions Electrical characteristics Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage STM32F103xx pin C = 50 pF STM32F103xx pin VIN ai14141 Doc ID 14611 Rev 8 ai14142 39/130 Electrical characteristics 5.1.6 STM32F103xC, STM32F103xD, STM32F103xE Power supply scheme Figure 12. Power supply scheme 6"!4 "ACKUP CIRCUITRY /3#+ 24# 7AKE UP LOGIC "ACKUP REGISTERS /54 '0 )/S ). ,EVEL SHIFTER 0O WER SWI TCH 6 )/ ,OGIC +ERNEL LOGIC #05 $IGITAL -EMORIES 6$$ 6$$ 2EGULATOR N& & 633 6$$ 6$$! 62%& N& & N& & 62%& 62%& !$# $!# !NALOG 2#S 0,, 633! AI Caution: In Figure 12, the 4.7 F capacitor must be connected to VDD3. 5.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 40/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 5.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Symbol VDD-VSS VIN(2) |VDDx| |VSSX - VSS| VESD(HBM) Voltage characteristics Ratings Min Max -0.3 4.0 Input voltage on five volt tolerant pin VSS - 0.3 VDD + 4.0 Input voltage on any other pin VSS - 0.3 4.0 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins 50 Variations between all the different ground pins 50 Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum allowed injected current values. Table 8. Symbol IVDD IVSS Current characteristics Ratings Max. Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines 150 (sink)(1) 150 Output current sunk by any I/O and control pin IIO IINJ(PIN)(2) IINJ(PIN) 25 Output current source by any I/Os and control pin - 25 Injected current on five volt tolerant pins(3) -5/+0 Injected current on any other pin(4) Total injected current (sum of all I/O and control pins) Unit mA 5 (5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note 3 below Table 62 on page 105. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Doc ID 14611 Rev 8 41/130 Electrical characteristics Table 9. STM32F103xC, STM32F103xD, STM32F103xE Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Table 10. Value Unit -65 to +150 C 150 C General operating conditions Symbol Parameter fHCLK Min Max Internal AHB clock frequency 0 72 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 Standard operating voltage 2 3.6 2 3.6 2.4 3.6 1.8 3.6 VDD VDDA (1) VBAT PD Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Conditions Must be the same potential as VDD(2) Backup operating voltage Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(3) Unit MHz V V LQFP144 666 LQFP100 434 LQFP64 444 LFBGA100 500 LFBGA144 500 WLCSP64 400 V mW Ambient temperature for 6 suffix version Maximum power dissipation -40 85 Low power dissipation -40 105 Ambient temperature for 7 suffix version Maximum power dissipation -40 105 Low power dissipation -40 125 6 suffix version -40 105 7 suffix version -40 125 (4) C TA TJ (4) C Junction temperature range C 1. When the ADC is used, refer to Table 59: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 120). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 120). 42/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 5.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10. Table 11. Operating conditions at power-up / power-down Symbol Parameter tVDD 5.3.3 Conditions Min Max VDD rise time rate 0 VDD fall time rate 20 Unit s/V Embedded reset and power control block characteristics The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 12. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst(2) PVD hysteresis VPOR/PDR Power on/power down reset threshold VPDRhyst (2) TRSTTEMPO (2) Min Typ Max PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V 100 Unit mV Falling edge 1.8(1) 1.88 1.96 V Rising edge 1.84 2.0 V PDR hysteresis 1.92 40 Reset temporization 1 2.5 mV 4.5 mS 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. Doc ID 14611 Rev 8 43/130 Electrical characteristics 5.3.4 STM32F103xC, STM32F103xD, STM32F103xE Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ -40 C < TA < +105 C 1.16 1.20 1.26 V -40 C < TA < +85 C 1.16 1.20 1.24 V 5.1 17.1(2) s 10 mV 100 ppm/C ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) Max VDD = 3 V 10 mV Temperature coefficient Unit 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 13: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 14, Table 15 and Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. 44/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 14. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions Unit TA = 85 C TA = 105 C 72 MHz 69 70 48 MHz 50 50.5 36 MHz 39 39.5 24 MHz 27 28 16 MHz 20 20.5 8 MHz 11 11.5 72 MHz 37 37.5 48 MHz 28 28.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 22 22.5 16.5 17 16 MHz 12.5 13 8 MHz 8 8 External clock(2), all peripherals enabled IDD fHCLK Supply current in Run mode mA 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 15. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions Supply current in Run mode Unit TA = 85 C TA = 105 C 72 MHz 66 67 48 MHz 43.5 45.5 36 MHz 33 35 24 MHz 23 24.5 16 MHz 16 18 8 MHz 9 10.5 72 MHz 33 33.5 48 MHz 23 23.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 18 18.5 13 13.5 16 MHz 10 10.5 8 MHz 6 6.5 External clock(2), all peripherals enabled IDD fHCLK mA 1. Data based on characterization results, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 14611 Rev 8 45/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 70 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz 60 Consumption (mA) 50 40 30 20 10 0 -45 25 70 85 105 Temperature (C) Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled 35 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz 30 Consumption (mA) 25 20 15 10 5 0 -45 25 70 Temperature (C) 46/130 Doc ID 14611 Rev 8 85 105 STM32F103xC, STM32F103xD, STM32F103xE Table 16. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode fHCLK Unit TA = 85 C TA = 105 C 72 MHz 45 46 48 MHz 31 32 36 MHz 24 25 24 MHz 17 17.5 16 MHz 12.5 13 8 MHz 8 8 72 MHz 8.5 9 48 MHz 7 7.5 36 MHz 6 6.5 24 MHz 5 5.5 16 MHz 4.5 5 8 MHz 4 4 mA External clock(2), all peripherals disabled 1. Based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 14611 Rev 8 47/130 Electrical characteristics Table 17. STM32F103xC, STM32F103xD, STM32F103xE Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = = 2.0 V = 2.4 V = 3.3 V 85 C 105 C Regulator in run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current in OFF (no independent watchdog) Stop mode Regulator in low-power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) IDD Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator Supply current in ON, independent watchdog OFF Standby mode Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF IDD_VBAT Max Backup domain Low-speed oscillator and RTC ON supply current 1.05 34.5 35 379 1130 24.5 25 365 1110 3 3.8 - - 2.8 3.6 - - 1.9 2.1 5(2) 6.5(2) 1.1 1.4 2(2) 2.3(2) Unit A 1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production. Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values 2.5 Consumption (A) 2 1.8 V 1.5 2V 2.4 V 3.3 V 1 3.6 V 0.5 0 -45 25 85 Temperature (C) 48/130 Doc ID 14611 Rev 8 105 ai17337 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values 700 600 Consumption (A) 500 400 300 200 2.4V 2.7V 3.0V 3.3V 3.6V 100 0 -45 25 70 85 105 Temperature (C) #ONSUMPTION ! 6 6 6 6 6 # # # # 4EMPERATURE # AI Doc ID 14611 Rev 8 49/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values 700 600 Consumption (A) 500 400 300 200 2.4V 2.7V 3.0V 3.3V 3.6V 100 0 -45 25 70 85 105 Temperature (C) #ONSUMPTION ! 6 6 6 6 6 # # # 4EMPERATURE # 50/130 Doc ID 14611 Rev 8 # AI STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values 4.5 4 Consumption (A) 3.5 3 2.5 2 1.5 2.4V 2.7V 3.0V 3.3V 3.6V 1 0.5 0 -45 25 70 85 105 Temperature (C) #ONSUMPTION ! 6 6 6 6 6 # # # 4EMPERATURE # Doc ID 14611 Rev 8 # AI 51/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 10. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 Table 18. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 51 30.5 48 MHz 34.6 20.7 36 MHz 26.6 16.2 24 MHz 18.5 11.4 16 MHz 12.8 8.2 8 MHz 7.2 5 4 MHz 4.2 3.1 2 MHz 2.7 2.1 1 MHz 2 1.7 500 kHz 1.6 1.4 125 kHz 1.3 1.2 64 MHz 45 27 48 MHz 34 20.1 36 MHz 26 15.6 24 MHz 17.9 10.8 16 MHz 12.2 7.6 8 MHz 6.6 4.4 4 MHz 3.6 2.5 2 MHz 2.1 1.5 1 MHz 1.4 1.1 500 kHz 1 0.8 125 kHz 0.7 0.6 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 52/130 Doc ID 14611 Rev 8 Unit mA mA STM32F103xC, STM32F103xD, STM32F103xE Table 19. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions Supply current in Sleep mode All peripherals All peripherals enabled(2) disabled 72 MHz 29.5 6.4 48 MHz 20 4.6 36 MHz 15.1 3.6 24 MHz 10.4 2.6 16 MHz 7.2 2 8 MHz 3.9 1.3 4 MHz 2.6 1.2 2 MHz 1.85 1.15 1 MHz 1.5 1.1 500 kHz 1.3 1.05 125 kHz 1.2 1.05 64 MHz 25.6 5.1 48 MHz 19.4 4 36 MHz 14.5 3 24 MHz Running on high 16 MHz speed internal RC (HSI), AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 9.8 2 6.6 1.4 3.3 0.7 2 0.6 1.25 0.55 1 MHz 0.9 0.5 500 kHz 0.7 0.45 125 kHz 0.6 0.45 External clock IDD fHCLK (3) Unit mA 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 14611 Rev 8 53/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 7 Table 20. Peripheral current consumption(1) Peripheral APB1 54/130 Typical consumption at 25 C TIM2 1.2 TIM3 1.2 TIM4 1.2 TIM5 1.2 TIM6 0.4 TIM7 0.4 SPI2 0.2 SPI3 0.2 USART2 0.4 USART3 0.4 UART4 0.5 UART5 0.6 I2C1 0.4 I2C2 0.4 USB 0.65 CAN 0.72 DAC 0.72 Doc ID 14611 Rev 8 Unit mA STM32F103xC, STM32F103xD, STM32F103xE Table 20. Peripheral current consumption(1) (continued) Peripheral APB2 Electrical characteristics Typical consumption at 25 C GPIOA 0.55 GPIOB 0.72 GPIOC 0.72 GPIOD 0.55 GPIOE 1 GPIOF 0.72 GPIOG 1 ADC1(2) 1.9 ADC2 1.7 TIM1 1.8 SPI1 0.4 TIM8 1.7 USART1 0.9 ADC3 1.7 Unit mA 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 21. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 25 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) tr(HSE) tf(HSE) Cin(HSE) 5 ns OSC_IN rise or fall time(1) 20 OSC_IN input capacitance(1) 5 DuCy(HSE) Duty cycle IL V 45 OSC_IN Input leakage current VSS VIN VDD pF 55 % 1 A 1. Guaranteed by design, not tested in production. Doc ID 14611 Rev 8 55/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Low-speed external user clock generated from an external source The characteristics given in Table 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 22. Low-speed external user clock characteristics Symbol Parameter Conditions Min fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 Typ Max Unit 32.768 1000 kHz VDD 0.7VDD V tr(LSE) tf(LSE) Cin(LSE) ns OSC32_IN rise or fall time(1) 50 OSC32_IN input capacitance(1) 5 DuCy(LSE) Duty cycle IL 0.3VDD 30 OSC32_IN Input leakage current VSS VIN VD pF 70 % 1 A D 1. Guaranteed by design, not tested in production. Figure 20. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 56/130 Doc ID 14611 Rev 8 t STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 21. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE EXTER NAL CLOCK SOURC E fLSE_ext STM32F103xx ai14144b Doc ID 14611 Rev 8 57/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. HSE 4-16 MHz oscillator characteristics(1)(2) Symbol fOSC_IN Parameter Conditions Typ Max Unit 4 8 16 MHz Oscillator frequency RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) i2 HSE driving current gm Oscillator transconductance tSU(HSE)(4) Min RS = 30 200 k 30 pF VDD= 3.3 V, VIN = VSS with 30 pF load Startup Startup time 1 25 VDD is stabilized mA mA/V 2 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 22). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 22. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHS E OSC_IN 8 MH z resonator CL2 REXT(1) RF OSC_OU T Bias controlled gain STM32F103xx ai14145 1. REXT value depends on the crystal characteristics. 58/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 24. Symbol RF CL1, CL2 LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Parameter Conditions Min Feedback resistor LSE driving current gm Oscillator transconductance tSU(LSE)(3) Startup time Max 5 Recommended load capacitance versus equivalent serial resistance of the crystal (RS) I2 Typ Unit M RS = 30 k 15 pF VDD = 3.3 V, VIN = VSS 1.4 A 5 VDD is stabilized A/V TA = 50 C 1.5 TA = 25 C 2.5 TA = 10 C 4 TA = 0 C 6 TA = -10 C 10 TA = -20 C 17 TA = -30 C 32 TA = -40 C 60 s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Doc ID 14611 Rev 8 59/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 23. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator Bias controlled gain RF STM32F103xx OSC32_OU T CL2 ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25. Symbol HSI oscillator characteristics(1) Parameter fHSI Frequency DuCy(HSI) Duty cycle Conditions Min Typ Unit 8 45 User-trimmed with the RCC_CR register(2) ACCHSI Max Accuracy of the HSI oscillator Factorycalibrated(4) tsu(HSI)(4) HSI oscillator startup time IDD(HSI)(4) HSI oscillator power consumption MHz 55 % 1(3) % TA = -40 to 105 C -2 2.5 % TA = -10 to 85 C -1.5 2.2 % TA = 0 to 70 C -1.3 2 % TA = 25 C -1.1 1.8 % 1 2 s 100 A 80 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics (1) Symbol fLSI(2) 60/130 Parameter Frequency Doc ID 14611 Rev 8 Min Typ Max Unit 30 40 60 kHz STM32F103xC, STM32F103xD, STM32F103xE Table 26. Electrical characteristics LSI oscillator characteristics (1) Symbol Parameter Min tsu(LSI)(3) LSI oscillator startup time IDD(LSI)(3) LSI oscillator power consumption Typ 0.65 Max Unit 85 s 1.2 A 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 27. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Unit Wakeup from Sleep mode 1.8 s Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low power mode) 5.4 Wakeup from Standby mode 50 s s 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. Doc ID 14611 Rev 8 61/130 Electrical characteristics 5.3.8 STM32F103xC, STM32F103xD, STM32F103xE PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 60 % fPLL_OUT PLL multiplier output clock 16 72 MHz tLOCK PLL lock time 200 s Jitter Cycle-to-cycle jitter 300 ps fPLL_IN 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 29. Symbol tprog tERASE tME IDD Vprog Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = -40 to +105 C 40 52.5 70 s Page (2 KB) erase time TA = -40 to +105 C 20 40 ms Mass erase time TA = -40 to +105 C 20 40 ms Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V 28 mA Write mode fHCLK = 72 MHz, VDD = 3.3 V 7 mA Erase mode fHCLK = 72 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 A 3.6 V Parameter Supply current Conditions Programming voltage 2 1. Guaranteed by design, not tested in production. 62/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 30. Electrical characteristics Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle (2) 10 kcycles at TA = 105 C 10 (2) 20 at TA = 55 C Unit kcycles Years 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous waveforms and timings Figure 24 through Figure 27 represent asynchronous waveforms and Table 31 through Table 34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: AddressSetupTime = 0 AddressHoldTime = 1 DataSetupTime = 1 Doc ID 14611 Rev 8 63/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &3-#?.% T V./%?.% T W./% T H.%?./% &3-#?./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &3-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &3-#?$;= T V.!$6?.% TW.!$6 &3-#?.!$6 -36 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Symbol 64/130 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Parameter Min Max Unit tw(NE) FSMC_NE low time 5tHCLK - 1.5 5tHCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns tw(NOE) FSMC_NOE low time 5tHCLK - 1.5 5tHCLK + 1.5 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time -1.5 tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NOE) Address hold time after FSMC_NOE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 ns tsu(Data_NE) Data to FSMC_NEx high setup time 2tHCLK + 25 ns tsu(Data_NOE) Data to FSMC_NOEx high setup time 2tHCLK + 25 ns th(Data_NOE) Data hold time after FSMC_NOE high 0 ns th(Data_NE) Data hold time after FSMC_NEx high 0 ns Doc ID 14611 Rev 8 ns 0 0.1 ns ns 0 ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Table 31. Symbol Parameter Min Max Unit tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5 ns tw(NADV) FSMC_NADV low time tHCLK + 1.5 ns 1. CL = 15 pF. 2. Based on characterisation, not tested in production. Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 32. Symbol Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK - 1 3tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK - 0.5 tHCLK + 1.5 ns tw(NWE) FSMC_NWE low time tHCLK - 0.5 tHCLK + 1.5 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) FSMC_NEx low to Data valid th(Data_NWE) Data hold time after FSMC_NWE high Doc ID 14611 Rev 8 ns 7.5 tHCLK ns 1.5 tHCLK - 0.5 ns ns tHCLK + 7 tHCLK ns ns ns 65/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Table 32. Symbol Parameter Min Max Unit tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5.5 ns tw(NADV) FSMC_NADV low time tHCLK + 1.5 ns 1. CL = 15 pF. 2. Based on characterisation, not tested in production. Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 33. Symbol 66/130 Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Parameter Min Max Unit tw(NE) FSMC_NE low time 7tHCLK - 2 7tHCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 3tHCLK - 0.5 3tHCLK + 1.5 ns tw(NOE) FSMC_NOE low time 4tHCLK - 1 4tHCLK + 2 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time -1 tv(A_NE) FSMC_NEx low to FSMC_A valid tv(NADV_NE) FSMC_NEx low to FSMC_NADV low tw(NADV) ns 0 ns 3 5 ns FSMC_NADV low time tHCLK -1.5 tHCLK + 1.5 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK ns th(A_NOE) Address hold time after FSMC_NOE high tHCLK ns Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 33. Symbol Electrical characteristics Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) Parameter Min Max 0 Unit th(BL_NOE) FSMC_BL hold time after FSMC_NOE high ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid tsu(Data_NE) Data to FSMC_NEx high setup time 2tHCLK + 24 ns tsu(Data_NOE) Data to FSMC_NOE high setup time 2tHCLK + 25 ns th(Data_NE) Data hold time after FSMC_NEx high 0 ns th(Data_NOE) Data hold time after FSMC_NOE high 0 ns 0 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. Doc ID 14611 Rev 8 67/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 34. Symbol Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Parameter Min Unit tw(NE) FSMC_NE low time 5tHCLK - 1 5tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low 2tHCLK 2tHCLK + 1 ns tw(NWE) FSMC_NWE low time 2tHCLK - 1 2tHCLK + 2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK - 1 tv(A_NE) FSMC_NEx low to FSMC_A valid tv(NADV_NE) FSMC_NEx low to FSMC_NADV low tw(NADV) ns 7 ns 3 5 ns FSMC_NADV low time tHCLK - 1 tHCLK + 1 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK - 3 ns th(A_NWE) Address hold time after FSMC_NWE high 4tHCLK ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high 1.6 tHCLK - 1.5 tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 15 pF. 2. Based on characterization, not tested in production. 68/130 Max Doc ID 14611 Rev 8 ns tHCLK + 1.5 tHCLK - 5 ns ns ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Synchronous waveforms and timings Figure 28 through Figure 31 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: BurstAccessMode = FSMC_BurstAccessMode_Enable; MemoryType = FSMC_MemoryType_CRAM; WriteBurst = FSMC_WriteBurst_Enable; CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual) DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 28. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, T D#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%( TD#,+, ./%, &3-#?./% TD#,+, !$)6 TSU!$6 #,+( TD#,+, !$6 !$;= &3-#?!$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( TH#,+( !$6 $ $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIH Doc ID 14611 Rev 8 69/130 Electrical characteristics Table 35. STM32F103xC, STM32F103xD, STM32F103xE Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 15 pF. 2. Based on characterization, not tested in production. 70/130 Min Doc ID 14611 Rev 8 27.7 ns 1.5 2 ns ns 4 5 ns ns 0 2 ns ns 1 0.5 ns ns 12 ns 8 ns 2 ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 29. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 T D#,+, $ATA TD#,+, $ATA TD#,+, !$6 &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG Doc ID 14611 Rev 8 71/130 Electrical characteristics Table 36. STM32F103xC, STM32F103xD, STM32F103xE Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid td(CLKL-Data) FSMC_A/D[15:0] valid after FSMC_CLK low tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. 72/130 Min Doc ID 14611 Rev 8 27.7 ns 2 2 ns ns 4 5 ns ns 0 2 ns ns 1 1 ns ns 12 3 ns ns 6 ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( TH#,+( $6 $ &3-#?$;= TSU.7!)46 #,+( $ $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIG Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 0...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 0...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6.5 ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 7 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high 7 ns th(CLKH-NWAITV) 2 ns FSMC_NWAIT valid after FSMC_CLK high 27.7 Unit ns 1.5 2 ns ns 4 5 ns ns 0 4 ns ns 1.5 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. Doc ID 14611 Rev 8 73/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 31. Synchronous non-multiplexed PSRAM write timings TW#,+ "53452. TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, $ATA &3-#?$;= TD#,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TD#,+, .",( TH#,+( .7!)46 &3-#?.", AIH Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Max FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 ns 2. Based on characterization, not tested in production. Doc ID 14611 Rev 8 27.7 Unit tw(CLK) 1. CL = 15 pF. 74/130 Min ns 2 2 ns ns 4 5 ns ns 0 2 ns ns 1 1 ns ns 6 ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 32 through Figure 37 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: COM.FSMC_SetupTime = 0x04; COM.FSMC_WaitSetupTime = 0x07; COM.FSMC_HoldSetupTime = 0x04; COM.FSMC_HiZSetupTime = 0x00; ATT.FSMC_SetupTime = 0x04; ATT.FSMC_WaitSetupTime = 0x07; ATT.FSMC_HoldSetupTime = 0x04; ATT.FSMC_HiZSetupTime = 0x00; IO.FSMC_SetupTime = 0x04; IO.FSMC_WaitSetupTime = 0x07; IO.FSMC_HoldSetupTime = 0x04; IO.FSMC_HiZSetupTime = 0x00; TCLRSetupTime = 0; TARSetupTime = 0; Figure 32. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 th(NCEx-AI) tv(NCEx-A) FSMC_A[10:0] th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td(NCE4_1-NOE) tw(NOE) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14895b 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Doc ID 14611 Rev 8 75/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 33. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NREG-NCE4_1) td(NIORD-NCE4_1) FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NWE) tw(NWE) td(NWE-NCE4_1) FSMC_NWE FSMC_NOE MEMxHIZ =1 td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14896b 76/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded). Doc ID 14611 Rev 8 77/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access FSMC_NCE4_1 FSMC_NCE4_2 th(NCE4_1-AI) tv(NCEx-A) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIOWR tw(NIORD) td(NIORD-NCE4_1) FSMC_NIORD tsu(D-NIORD) td(NIORD-D) FSMC_D[15:0] ai14899B 78/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NIOWR tv(NCEx-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) tw(NIOWR) FSMC_NIOWR ATTxHIZ =1 tv(NIOWR-D) th(NIOWR-D) FSMC_D[15:0] ai14900b Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) tv(NCE4_1-A) FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) th(NCEx-AI) th(NCE4_1-AI) FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) td(NREG-NCEx) td(NREG-NCE4_1) FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid th(NCEx-NREG) th(NCE4_1-NREG) FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 tHCLK + 3 high to FSMC_NREG invalid td(NCE4_1-NOE) FSMC_NCE4_1 low to FSMC_NOE low tw(NOE) FSMC_NOE low width 8tHCLK -1.5 td(NOE-NCE4_1 FSMC_NOE high to FSMC_NCE4_1 high 5tHCLK + 2 ns tsu(D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 25 ns th(NOE-D) FSMC_D[15:0] valid data after FSMC_NOE high 15 ns tw(NWE) FSMC_NWE low width 8tHCLK - 1 td(NWE-NCE4_1) FSMC_NWE high to FSMC_NCE4_1 high 5tHCLK + 2 td(NCE4_1-NWE) FSMC_NCE4_1 low to FSMC_NWE low 5tHCLK + 1.5 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid 0 ns th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 11tHCLK ns td(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13tHCLK ns Doc ID 14611 Rev 8 0 2.5 ns ns 5 ns ns 5tHCLK + 2 ns 8tHCLK + 1 ns 8tHCLK + 2 ns ns 79/130 Electrical characteristics Table 39. STM32F103xC, STM32F103xD, STM32F103xE Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max 8tHCLK + 3 th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid th(NCE4_1-NIOWR) FSMC_NCE4_1 high to FSMC_NIOWR invalid ns 5tHCLK +1 11tHCLK td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid ns ns 5tHCLK+3ns 5tHCLK - 5 td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 td(NIORD-NCE4_1) low to FSMC_NIORD valid Unit ns ns 5tHCLK + 2.5 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD invalid th(NCE4_1-NIORD) FSMC_NCE4_1 high to FSMC_NIORD invalid 5tHCLK - 5 ns tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 4.5 ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 9 ns tw(NIORD) FSMC_NIORD low width 8tHCLK + 2 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. NAND controller waveforms and timings Figure 38 through Figure 41 represent synchronous waveforms and Table 40 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: 80/130 COM.FSMC_SetupTime = 0x01; COM.FSMC_WaitSetupTime = 0x03; COM.FSMC_HoldSetupTime = 0x02; COM.FSMC_HiZSetupTime = 0x01; ATT.FSMC_SetupTime = 0x01; ATT.FSMC_WaitSetupTime = 0x03; ATT.FSMC_HoldSetupTime = 0x02; ATT.FSMC_HiZSetupTime = 0x01; Bank = FSMC_Bank_NAND; MemoryDataWidth = FSMC_MemoryDataWidth_16b; ECC = FSMC_ECC_Enable; ECCPageSize = FSMC_ECCPageSize_512Bytes; TCLRSetupTime = 0; TARSetupTime = 0; Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 38. NAND controller waveforms for read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901b Figure 39. NAND controller waveforms for write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE (NRE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14902b Figure 40. NAND controller waveforms for common memory read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) th(NOE-ALE) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14912b Doc ID 14611 Rev 8 81/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 41. NAND controller waveforms for common memory write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) tw(NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913b Table 40. Symbol td(D-NWE)(2) Switching characteristics for NAND Flash read and write cycles(1) Parameter Min FSMC_D[15:0] valid before FSMC_NWE high 5tHCLK + 12 FSMC_NOE low width 4tHCLK - 1.5 tsu(D-NOE)(2) FSMC_D[15:0] valid data before FSMC_NOE high 25 th(NOE-D)(2) FSMC_D[15:0] valid data after FSMC_NOE high 7 tw(NOE) (2) tw(NWE) (2) FSMC_NWE low width tv(NWE-D)(2) FSMC_NWE low to FSMC_D[15:0] valid th(NWE-D)(2) FSMC_NWE high to FSMC_D[15:0] invalid td(ALE-NWE)(3) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE)(3) FSMC_NWE high to FSMC_ALE invalid 4tHCLK - 1 FSMC_NWE high to FSMC_ALE invalid 1. CL = 15 pF. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. 82/130 Doc ID 14611 Rev 8 4tHCLK + 1.5 ns ns ns 4tHCLK + 2.5 ns 0 ns ns 3tHCLK + 1.5 3tHCLK + 4.5 ns ns 3tHCLK + 2 3tHCLK + 4.5 Unit ns 2tHCLK + 4ns td(ALE-NOE)(3) FSMC_ALE valid before FSMC_NOE low th(NOE-ALE)(3) Max ns ns STM32F103xC, STM32F103xD, STM32F103xE 5.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP144, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP144, TA = +25 C, fHCLK = 72 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Doc ID 14611 Rev 8 83/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 42. Symbol SEMI 5.3.12 EMI characteristics Parameter Peak level Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8/48 MHz 8/72 MHz 0.1 to 30 MHz VDD = 3.3 V, TA = 25 C, 30 to 130 MHz LQFP144 package compliant with IEC 130 MHz to 1GHz 61967-2 SAE EMI Level 8 12 31 21 28 33 4 4 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 43. Symbol VESD(HBM) ESD absolute maximum ratings Ratings Conditions Class Maximum value(1) Unit Electrostatic discharge TA = +25 C, conforming 2 voltage (human body model) to JESD22-A114 Electrostatic discharge TA = +25 C, conforming II VESD(CDM) voltage (charge device model) to JESD22-C101 1. Based on characterization results, not tested in production. 84/130 Doc ID 14611 Rev 8 2000 V 500 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 44. Symbol LU 5.3.13 Electrical sensitivities Parameter Static latch-up class Conditions Class TA = +105 C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 45 Table 45. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 Doc ID 14611 Rev 8 Unit mA 85/130 Electrical characteristics 5.3.14 STM32F103xC, STM32F103xD, STM32F103xE I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 46. Symbol VIL VIH Vhys Ilkg I/O static characteristics Parameter Conditions Min Typ Max Unit Standard IO input low level voltage -0.3 0.28*(VDD-2 V)+0.8 V V IO FT(1) input low level voltage -0.3 0.32*(VDD-2 V)+0.75 V V Standard IO input high level voltage 0.41*(VDD-2 V)+1.3 V VDD+0.3 V IO FT(1) input high level voltage 5.5 VDD > 2 V 0.42*(VDD-2 V)+1 V VDD 2 V V 5.2 Standard IO Schmitt trigger voltage hysteresis(2) 200 mV IO FT Schmitt trigger voltage hysteresis(2) 5% VDD(3) mV Input leakage current (4) VSS VIN VDD Standard I/Os 1 VIN= 5 V, I/O FT 3 A RPU Weak pull-up equivalent resistor(5) VIN = VSS 30 40 50 k RPD Weak pull-down equivalent resistor(5) VIN = VDD 30 40 50 k CIO I/O pin capacitance 5 pF 1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 42 and Figure 43 for standard I/Os, and in Figure 44 and Figure 45 for 5 V tolerant I/Os. 86/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 42. Standard I/O input characteristics - CMOS port 6)(6), 6 6 $$ ENT 6 )( #-/3 7)(MIN 7),MAX 6 6 )( $$ QUIREM NDARD RE 6 6), $$ 6 $$ IREMENT 6 ), RD REQU #-/3 STANDA )NPUT RANGE NOT GUARANTEED STA 6$$ 6 AIB Figure 43. Standard I/O input characteristics - TTL port 6)(6), 6 7)(MIN 44, REQUIREMENTS 6)( 6 6 6 )( $$ )NPUT RANGE NOT GUARANTEED 7),MAX 6 ),6 $$ 44, REQUIREMENTS 6),6 6$$ 6 AI Doc ID 14611 Rev 8 87/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 44. 5 V tolerant I/O input characteristics - CMOS port 6)(6), 6 6 $$ TS 6 )( UIREMEN ARD REQ 3 STAND #-/ 6 ),6 $$ T 6 ),6 $$ REQUIRMEN /3 STANDARD #- 6 )(6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AIB Figure 45. 5 V tolerant I/O input characteristics - TTL port 6)(6), 6 44, REQUIREMENT 6 )(6 6 6 )( $$ 7)(MIN 7),MAX )NPUT RANGE NOT GUARANTEED 6 ), 6 $$ 44, REQUIREMENTS 6 ),6 6$$ 6 AI Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: 88/130 The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 47. Symbol VOL(1) VOH (3) VOL (1) VOH (3) Output voltage characteristics Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions CMOS port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V TTL port(2) IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Min Max Unit 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. Doc ID 14611 Rev 8 89/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 46 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48. I/O AC characteristics(1) MODEx[1:0] Symbol bit value(1) Parameter Conditions Min fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw frequency(2) Output high to low level fall time Output low to high level rise time Unit 2 MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 125(3) fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 Max 10 MHz 25(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of external signals detected by the EXTI controller 10 ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 46. 3. Guaranteed by design, not tested in production. 90/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 46. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46). Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 49. NRST pin characteristics Symbol Parameter VIL(NRST)(1) Conditions NRST Input low level voltage Min -0.5 0.8 2 VDD+0.5 NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) RPU VF(NRST)(1) NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse Max Unit V VIH(NRST)(1) NRST Input high level voltage Vhys(NRST) Typ 200 VIN = VSS 30 40 mV 50 k 100 ns 300 ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 47. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset Filter 0.1 F STM32F10xxx ai14132d 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset will not be taken into account by the device. Doc ID 14611 Rev 8 91/130 Electrical characteristics 5.3.16 STM32F103xC, STM32F103xD, STM32F103xE TIM timer characteristics The parameters given in Table 50 are guaranteed by design. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 13.9 ns Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz 0 fTIMxCLK/2 MHz 0 36 MHz 16 bit 65536 tTIMxCLK 910 s 65536 x 65536 tTIMxCLK 59.6 s Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. 92/130 Doc ID 14611 Rev 8 Unit STM32F103xC, STM32F103xD, STM32F103xE 5.3.17 Electrical characteristics Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 10. The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 51. Refer also to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 51. I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(3) 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 s Cb Capacitive load for each bus line s ns 300 s 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Doc ID 14611 Rev 8 93/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 48. I2C bus AC waveforms and measurement circuit VDD VDD 4 .7 k 4 .7 k STM32F103xx 100 SDA I2C bus 100 SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) th(STA) SCL tw(SCLH) tsu(SDA) tw(SCLL) tr(SCL) th(SDA) tw(STO:STA) S TOP tsu(STO) tf(SCL) ai14149c 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 52. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. 94/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 53. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) SPI characteristics Parameter Conditions Min SPI clock rise and fall time 18 Slave mode 18 Capacitive load: C = 30 pF 8 ns 70 % MHz SPI slave input clock duty Slave mode cycle 30 NSS setup time Slave mode 4tPCLK th(NSS)(1) NSS hold time Slave mode 2tPCLK SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 Master mode 5 Slave mode 5 Master mode 5 Slave mode 4 (1) tsu(MI) (1) tsu(SI)(1) th(MI) 60 Data input setup time (1) th(SI)(1) Data input hold time ns ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK tdis(SO)(1)(3) 2 10 Data output disable time Slave mode (1) Data output valid time Slave mode (after enable edge) 25 tv(MO)(1) Data output valid time Master mode (after enable edge) 5 tv(SO) th(SO)(1) th(MO) (1) Unit Master mode SPI clock frequency tsu(NSS)(1) tw(SCKH) tw(SCKL)(1) Max Slave mode (after enable edge) 15 Master mode (after enable edge) 2 Data output hold time 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 14611 Rev 8 95/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 49. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) tSU(NSS) SCK Input CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 96/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 51. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MS BIN tr(SCK) tf(SCK) BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 14611 Rev 8 97/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE I2S characteristics Table 54. Symbol Parameter Conditions DuCy(SCK) I2S slave input clock duty cycle fCK 1/tc(CK) I2S clock frequency tr(CK) tf(CK) I2S clock rise and fall time Capacitive load CL = 50 pF tv(WS) (1) WS valid time Master mode th(WS) (1) WS hold time Master mode tsu(WS) th(WS) Master mode (data: 16 bits, Audio frequency = 48 kHz) Slave mode (1) (1) tw(CKH) Slave mode 1.522 1.525 MHz 0 6.5 8 3 I2S2 2 I2S3 0 0 CK high and low time Master fPCLK= 16 MHz, audio frequency = 48 kHz 312.5 345 I2S2 2 I2S3 6.5 Master receiver Slave receiver 1.5 Master receiver 0 Slave receiver 0.5 Data input hold time tv(SD_ST) (1)(2) Data output valid time Slave transmitter (after enable edge) th(SD_ST) (1) Data output hold time Slave transmitter (after enable edge) tv(SD_MT) (1)(2) Data output valid time Master transmitter (after enable edge) th(SD_MT) (1) Data output hold time Master transmitter (after enable edge) 1. Based on design simulation and/or characterization results, not tested in production. 2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. 98/130 % Slave mode Data input setup time th(SD_SR) 70 WS hold time (1) (1)(2) 30 4 Data input setup time th(SD_MR)(1)(2) Unit Slave mode tsu(SD_MR) (1) tsu(SD_SR) Max WS setup time (1) tw(CKL) (1) Min Doc ID 14611 Rev 8 18 11 3 0 ns STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 52. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 53. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Doc ID 14611 Rev 8 99/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 54. SDIO high-speed mode tf tr tC tW(CKH) tW(CKL) CK tOV tOH D, CMD (output) tISU tIH D, CMD (input) ai14887 Figure 55. SD default mode CK tOVD tOHD D, CMD (output) ai14888 100/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 55. Electrical characteristics SD / MMC characteristics Symbol Parameter Conditions Min Max Unit 48 MHz Clock frequency in data transfer mode CL 30 pF 0 tW(CKL) Clock low time, fPP = 16 MHz CL 30 pF 32 tW(CKH) Clock high time, fPP = 16 MHz CL 30 pF 31 tr Clock rise time CL 30 pF 3.5 tf Clock fall time CL 30 pF 5 fPP ns CMD, D inputs (referenced to CK) tISU Input setup time CL 30 pF 2 tIH Input hold time CL 30 pF 0 ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL 30 pF tOH Output hold time CL 30 pF 6 ns 0.3 CMD, D outputs (referenced to CK) in SD default mode(1) tOVD Output valid default time CL 30 pF tOHD Output hold default time CL 30 pF 7 ns 0.5 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 56. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time Max Unit 1 s 1. Guaranteed by design, not tested in production. Doc ID 14611 Rev 8 101/130 Electrical characteristics Table 57. STM32F103xC, STM32F103xD, STM32F103xE USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD (4) USB operating voltage(2) I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 VDI Differential input sensitivity Output levels VOL Static output level low RL of 1.5 k to 3.6 V(5) VOH Static output level high RL of 15 k to VSS(5) 0.3 V 2.8 3.6 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by characterization, not tested in production. 5. RL is the load connected on the USB drivers Figure 56. USB timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S Table 58. tr tf ai14137 USB: full-speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V trfm VCRS Fall Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 5.3.18 CAN (controller area network) interface Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 102/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 5.3.19 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 59 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Note: It is recommended to perform a calibration after each power-up. Table 59. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 220 A fADC ADC clock frequency 0.6 14 MHz fS(2) Sampling rate 0.05 1 MHz 823 kHz 17 1/fADC VREF+ V 50 k fTRIG(2) VAIN 160(1) fADC = 14 MHz External trigger frequency 0 (VSSA or VREFtied to ground) Conversion voltage range(3) See Equation 1 and Table 60 for details RAIN(2) External input impedance RADC(2) Sampling switch resistance 1 k CADC(2) Internal sample and hold capacitor 8 pF tCAL(2) Calibration time fADC = 14 MHz tlat(2) Injection trigger conversion latency fADC = 14 MHz tlatr(2) Regular trigger conversion latency fADC = 14 MHz tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) 5.9 s 83 1/fADC 0.214 s 3(4) 1/fADC 0.143 s (4) 2 fADC = 14 MHz 0.107 17.1 s 1.5 239.5 1/fADC 1 s 18 s 0 fADC = 14 MHz 1/fADC 1 0 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 59. Doc ID 14611 Rev 8 103/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Equation 1: RAIN max formula TS R AIN < ------------------------------------------------------------- - R ADC N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 60. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (s) RAIN max (k) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 61. Symbol ADC accuracy - limited test conditions(1)(2) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(3) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration VREF+ = VDDA 1.3 2 1 1.5 0.5 1.5 0.7 1 0.8 1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.14 does not affect the ADC accuracy. 3. Based on characterisation, not tested in production. 104/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 62. Electrical characteristics ADC accuracy(1) (2)(3) Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.14 does not affect the ADC accuracy. 4. Based on characterisation, not tested in production. Figure 57. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET (3) 7 (1) 6 5 4 EO EL 3 ED 2 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA Doc ID 14611 Rev 8 ai14395b 105/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 58. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL1 A STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 59 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 59 or Figure 60, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 59. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F103xx VREF+ (see note 1) 1 F // 10 nF VDDA 1 F // 10 nF VSSA /VREF- (see note 1) ai14388b 1. VREF+ and VREF- inputs are available only on 100-pin packages. 106/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 F // 10 nF VREF-/VSSA (See note 1) ai14389 1. VREF+ and VREF- inputs are available only on 100-pin packages. Doc ID 14611 Rev 8 107/130 Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 DAC electrical specifications Table 63. DAC characteristics Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 2.4 3.6 V VREF+ Reference supply voltage 2.4 3.6 V Ground 0 0 V VSSA RLOAD (1) Resistive load with buffer ON 5 Comments VREF+ must always be below VDDA k RO(1) Impedance output with buffer OFF 15 k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M CLOAD(1) Capacitive load 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(1) with buffer ON 0.2 V DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) DAC_OUT Lower DAC_OUT voltage min(1) with buffer OFF DAC_OUT Higher DAC_OUT voltage with buffer OFF max(1) IDDVREF+ DAC DC current consumption in quiescent mode (Standby mode) IDDA DAC DC current consumption in quiescent mode (Standby mode) DNL(2) INL(2) 108/130 Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) VDDA - 0.2 0.5 V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V mV It gives the maximum output excursion of the DAC. VREF+ - 1LSB V 220 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 380 A With no load, middle code (0x800) on the inputs 480 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 0.5 LSB Given for the DAC in 10-bit configuration 2 LSB Given for the DAC in 12-bit configuration 1 LSB Given for the DAC in 10-bit configuration 4 LSB Given for the DAC in 12-bit configuration Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 63. Symbol Offset(2) Gain error(2) DAC characteristics (continued) Parameter Min Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error Settling time (full scale: for a 10-bit input code transition (2) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value 1LSB Update rate(2) Electrical characteristics Typ 3 Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) Max Unit Comments 10 mV Given for the DAC in 12-bit configuration 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V 0.5 % Given for the DAC in 12bit configuration 4 s CLOAD 50 pF, RLOAD 5 k 1 MS/s CLOAD 50 pF, RLOAD 5 k Wakeup time from off state tWAKEUP(2) (Setting the ENx bit in the DAC Control register) 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (1) (to VDDA) (static DC measurement -67 -40 dB No RLOAD, CLOAD = 50 pF 1. Guaranteed by design, not tested in production. 2. Guaranteed by characterization, not tested in production. Figure 61. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. Doc ID 14611 Rev 8 109/130 Electrical characteristics 5.3.21 STM32F103xC, STM32F103xD, STM32F103xE Temperature sensor characteristics Table 64. TS characteristics Symbol Parameter Min Typ Max Unit 1 2 C TL VSENSE linearity with temperature Avg_Slope Average slope 4.0 4.3 4.6 mV/C V25 Voltage at 25 C 1.34 1.43 1.52 V tSTART(1) Startup time 10 s TS_temp(2)(1) ADC sampling time when reading the temperature 17.1 s 4 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 110/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 6 Package characteristics 6.1 Package mechanical data Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Doc ID 14611 Rev 8 111/130 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 62. BGA pad footprint $PAD $SM Table 65. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dimension Recommended values Dpad = 0.37 mm Dsm = 0.52 mm typ. (depends on solder mask registration tolerance) Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print 112/130 -36 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 63. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline C Seating plane A2 ddd A4 C A A3 A1 B D D1 e A F M F E1 E e Ob (144 balls) Ball A1 O eee M C A O fff M B C X3_ME 1. Drawing is not to scale. Table 66. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data inches(1) millimeters Symbol Min Typ A A1 Max Typ Min 1.70 0.21 Max 0.0669 0.0083 A2 1.07 0.0421 A3 0.27 0.0106 A4 0.85 0.0335 b 0.35 0.40 0.45 0.0138 0.0157 0.0177 D 9.85 10.00 10.15 0.3878 0.3937 0.3996 D1 E 8.80 9.85 10.00 0.3465 10.15 0.3878 0.3937 E1 8.80 0.3465 e 0.80 0.0315 F 0.60 0.0236 ddd 0.10 0.0039 eee 0.15 0.0059 fff 0.08 0.0031 0.3996 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14611 Rev 8 113/130 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 64. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline 1. Drawing is not to scale. Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ A A1 Max Min 1.700 0.270 Max 0.0669 0.0106 A2 1.085 0.0427 A3 0.30 0.0118 A4 0.80 0.0315 b 0.45 0.50 0.55 0.0177 0.0197 0.0217 D 9.85 10.00 10.15 0.3878 0.3937 0.3996 D1 E 7.20 9.85 10.00 0.2835 10.15 0.3878 0.3937 0.3996 E1 7.20 0.2835 e 0.80 0.0315 F 1.40 0.0551 ddd 0.12 0.0047 eee 0.15 0.0059 fff 0.08 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 114/130 Typ Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 65. WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline e1 A1 ball corner e D A1 ball corner e A H Detail A B C D e1 E E F Notch G L F H aaa Marking area A2 L G Wafer back side 8 A 7 6 5 4 Ball side 3 2 1 Side view Ball eee A1 b Seating plane (see note 2) Detail A rotated 90 CR_ME 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the ball. Table 68. WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.535 0.585 0.635 0.0211 0.0230 0.0250 A1 0.205 0.230 0.255 0.0081 0.0091 0.0100 A2 0.330 0.355 0.380 0.0130 0.0140 0.0150 0.290 0.320 0.350 0.0114 0.0126 0.0138 (2) b e 0.500 0.0197 e1 3.500 0.1378 F 0.447 0.0176 G 0.483 0.0190 D 4.446 4.466 4.486 0.1750 0.1758 0.1766 E 4.375 4.395 4.415 0.1722 0.1730 0.1738 H 0.250 0.0098 L 0.200 0.0079 eee 0.05 0.0020 aaa 0.10 0.0039 Number of balls 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum ball diameter parallel to primary datum Z. Doc ID 14611 Rev 8 115/130 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 66. BGA pad footprint $PAD $SM Table 69. Recommended PCB design rules (0.5mm pitch BGA) Dimension Recommended values Dpad = 300 m (circular) - 250 m recommended Dsm = 340 m min (for 300 m diameter pad) PCD pad size Cu - Ni (2-6 m) - Au (0.2 m max) - Non solder mask defined - Micro via under bump allowed 116/130 -36 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline(1) Figure 68. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C 108 109 D 73 1.35 72 0.35 k D1 0.5 A1 D3 L 73 108 L1 17.85 19.9 22.6 72 109 144 E1 E 37 1 36 E3 19.9 22.6 ai149 144 Pin 1 identification 37 36 1 e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 70. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 D 21.80 D1 Max 0.063 0.15 0.002 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 22.00 22.20 0.8583 0.8661 0.874 19.80 20.00 20.20 0.7795 0.7874 0.7953 E 21.80 22.00 22.20 0.8583 0.8661 0.874 E1 19.80 20.00 20.20 0.7795 0.7874 0.7953 D3 17.50 0.0059 0.0079 0.689 E3 17.50 0.689 e 0.50 0.0197 L 0.45 L1 k ccc 0.60 0.75 0.0177 1.00 0 3.5 0.0236 0.0295 0.0394 7 0.08 0 3.5 7 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14611 Rev 8 117/130 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 69. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) Figure 70. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE k 75 51 D L D1 76 L1 D3 51 75 50 0.5 C 76 50 0.3 16.7 14.3 b E3 E1 E 100 26 1.2 100 26 Pin 1 1 identification 1 25 ccc 25 C 12.3 e A1 16.7 ai14906b A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 71. LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 D 15.80 D1 13.80 D3 Max 0.063 0.15 0.002 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 16.00 16.20 0.622 0.6299 0.6378 14.00 14.20 0.5433 0.5512 0.5591 12.00 0.0059 0.0079 0.4724 E 15.80 16.00 16.20 0.622 0.6299 0.6378 E1 13.80 14.00 14.20 0.5433 0.5512 0.5591 E3 12.00 e L 0.50 0.45 L1 k ccc 0.4724 0.60 0.0197 0.75 1.00 0 3.5 0.0236 0.0295 0.0394 7 0.08 0 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 118/130 0.0177 Doc ID 14611 Rev 8 7 STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 72. Recommended footprint(1)(2) Figure 71. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline(1) 48 33 D 0.3 ccc C D1 A A2 D3 33 48 49 32 49 12.7 32 0.5 10.3 b L1 10.3 E3 E1 E 64 L A1 K 1.2 64 1 17 Pin 1 identification 16 1 17 c 16 7.8 5W_ME 12.7 ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 72. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 11.800 D1 9.800 D. Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 12.000 12.200 0.4646 0.4724 0.4803 10.000 10.200 0.3858 0.3937 0.4016 0.0079 7.500 E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197 k 0 3.5 7 0 3.5 7 L 0.450 0.600 0.75 0.0177 0.0236 0.0295 L1 1.000 0.0394 ccc 0.080 0.0031 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14611 Rev 8 119/130 Package characteristics 6.2 STM32F103xC, STM32F103xD, STM32F103xE Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 42. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 73. Package thermal characteristics Symbol JA 6.2.1 Parameter Value Thermal resistance junction-ambient LFBGA144 - 10 x 10 mm / 0.8 mm pitch 40 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 30 Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm / 0.8 mm pitch 40 Unit C/W Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient WLCSP64 50 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 120/130 Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE 6.2.2 Package characteristics Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 74: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xC, STM32F103xD and STM32F103xE at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 73 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 82 C + (46 C/W x 447 mW) = 82 C + 20.6 C = 102.6 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 74: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Doc ID 14611 Rev 8 121/130 Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Using the values obtained in Table 73 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 115 C + (46 C/W x 134 mW) = 115 C + 6.2 C = 121.2 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 74: Ordering information scheme). Figure 73. LQFP100 PD max vs. TA 700 PD (mW) 600 500 Suffix 6 400 Suffix 7 300 200 100 0 65 75 85 95 105 115 TA (C) 122/130 Doc ID 14611 Rev 8 125 135 STM32F103xC, STM32F103xD, STM32F103xE 7 Part numbering Part numbering Table 74. Ordering information scheme Example: STM32 F 103 R C T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package H = BGA T = LQFP Y = WLCSP64 Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 14611 Rev 8 123/130 Revision history 8 STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 75. Document revision history Date Revision 07-Apr-2008 1 Initial release. 2 Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 2 added in Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts on page 11. LQPF100/BGA100 column added to Table 6: FSMC pin definition on page 36. Values and Figures added to Maximum current consumption on page 44 (see Table 14, Table 15, Table 16 and Table 17 and see Figure 14, Figure 15, Figure 17, Figure 18 and Figure 19). Values added to Typical current consumption on page 52 (see Table 18, Table 19 and Table 20). Table 19: Typical current consumption in Standby mode removed. Note 4 and Note 1 added to Table 57: USB DC electrical characteristics and Table 58: USB: full-speed electrical characteristics on page 102, respectively. VUSB added to Table 57: USB DC electrical characteristics on page 102. Figure 68: Recommended footprint(1) on page 117 corrected. Equation 1 corrected. Figure 73: LQFP100 PD max vs. TA on page 122 modified. Tolerance values corrected in Table 66: LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data on page 113. 22-May-2008 124/130 Changes Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 75. Revision history Document revision history Date 21-Jul-2008 Revision Changes 3 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 15 modified. Number of complementary channels corrected in Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram. Power supply supervisor on page 17 modified and VDDA added to Table 10: General operating conditions on page 42. Table notes revised in Section 5: Electrical characteristics. Capacitance modified in Figure 12: Power supply scheme on page 40. Table 52: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) updated. Table 53: SPI characteristics modified, th(NSS) modified in Figure 49: SPI timing diagram - slave mode and CPHA = 0 on page 96. Minimum SDA and SCL fall time value for Fast mode removed from Table 51: I2C characteristics on page 93, note 1 modified. IDD_VBAT values and some IDD values with regulator in run mode added to Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 48. Table 30: Flash memory endurance and data retention on page 63 updated. tsu(NSS) modified in Table 53: SPI characteristics on page 95. EO corrected in Table 62: ADC accuracy on page 105. Figure 58: Typical connection diagram using the ADC on page 106 and note below corrected. Typical TS_temp value removed from Table 64: TS characteristics on page 110. Section 6.1: Package mechanical data on page 111 updated. Small text changes. Doc ID 14611 Rev 8 125/130 Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 75. Document revision history Date 12-Dec-2008 126/130 Revision Changes 4 Timers specified on page 1 (motor control capability mentioned). Section 2.2: Full compatibility throughout the family updated. Table 4: High-density timer feature comparison added. General-purpose timers (TIMx) and Advanced-control timers (TIM1 and TIM8) on page 19 updated. Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram modified. Note 10 added, main function after reset and Note 5 on page 35 updated in Table 5: High-density STM32F103xx pin definitions. Note 2 modified below Table 7: Voltage characteristics on page 41, |VDDx| min and |VDDx| min removed. Note 2 and PD values for LQFP144 and LFBGA144 packages added to Table 10: General operating conditions on page 42. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 44. Max values at TA = 85 C and TA = 105 C updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 48. Section 5.3.10: FSMC characteristics on page 63 updated. Data added to Table 42: EMI characteristics on page 84. IVREF added to Table 59: ADC characteristics on page 103. Table 73: Package thermal characteristics on page 120 updated. Small text changes. Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 75. Revision history Document revision history Date 30-Mar-2009 Revision Changes 5 I/O information clarified on page 1. Figure 4: STM32F103xC and STM32F103xE performance line BGA100 ballout corrected. I/O information clarified on page 1. In Table 5: High-density STM32F103xx pin definitions: - I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15 updated - PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column PG14 pin description modified in Table 6: FSMC pin definition. Figure 9: Memory map on page 38 modified. Note modified in Table 14: Maximum current consumption in Run mode, code with data processing running from Flash and Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 17, Figure 18 and Figure 19 show typical curves (titles changed). Table 21: High-speed external user clock characteristics and Table 22: Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 25: HSI oscillator characteristics. FSMC configuration modified for Asynchronous waveforms and timings. Notes modified below Figure 24: Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms and Figure 25: Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms. tw(NADV) values modified in Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings and Table 34: Asynchronous multiplexed PSRAM/NOR write timings. th(Data_NWE) modified in Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings In Table 36: Synchronous multiplexed PSRAM write timings and Table 38: Synchronous non-multiplexed PSRAM write timings: - tv(Data-CLK) renamed as td(CLKL-Data) - td(CLKL-Data) min value removed and max value added - th(CLKL-DV) / th(CLKL-ADV) removed Figure 28: Synchronous multiplexed NOR/PSRAM read timings, Figure 29: Synchronous multiplexed PSRAM write timings and Figure 31: Synchronous non-multiplexed PSRAM write timings modified. Figure 52: I2S slave timing diagram (Philips protocol)(1) and Figure 53: I2S master timing diagram (Philips protocol)(1) modified. WLCSP64 package added (see Figure 8: STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side, Table 5: High-density STM32F103xx pin definitions, Figure 65: WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline and Table 68: WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data). Small text changes. Doc ID 14611 Rev 8 127/130 Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 75. Document revision history Date 21-Jul-2009 24-Sep-2009 128/130 Revision Changes 6 Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram updated. Note 5 updated and Note 4 added in Table 5: High-density STM32F103xx pin definitions. VRERINT and TCoeff added to Table 13: Embedded internal reference voltage. Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM modified. fHSE_ext min modified in Table 21: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Note 1 modified below Figure 22: Typical application with an 8 MHz crystal. Table 25: HSI oscillator characteristics modified. Conditions removed from Table 27: Low-power mode wakeup timings. Jitter added to Table 28: PLL characteristics. Figure 47: Recommended NRST pin protection modified. In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings: th(BL_NOE) and th(A_NOE) modified. In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings: th(A_NWE) and th(Data_NWE) modified. In Table 33: Asynchronous multiplexed PSRAM/NOR read timings: th(AD_NADV) and th(A_NOE) modified. In Table 34: Asynchronous multiplexed PSRAM/NOR write timings: th(A_NWE) modified. In Table 35: Synchronous multiplexed NOR/PSRAM read timings: th(CLKH-NWAITV) modified. In Table 40: Switching characteristics for NAND Flash read and write cycles: th(NOE-D) modified. Table 53: SPI characteristics modified. Values added to Table 54: I2S characteristics and Table 55: SD / MMC characteristics. CADC and RAIN parameters modified in Table 59: ADC characteristics. RAIN max values modified in Table 60: RAIN max for fADC = 14 MHz. Table 63: DAC characteristics modified. Figure 61: 12-bit buffered /nonbuffered DAC added. Figure 64: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline and Table 67: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data updated. 7 Number of DACs corrected in Table 3: STM32F103xx family. IDD_VBAT updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes. Figure 16: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.11: EMC characteristics on page 83. Table 63: DAC characteristics modified. Small text changes. Doc ID 14611 Rev 8 STM32F103xC, STM32F103xD, STM32F103xE Table 75. Revision history Document revision history Date 19-Apr-2011 Revision Changes 8 Updated package choice for 103Rx in Table 2 Updated footnotes below Table 7: Voltage characteristics on page 41 and Table 8: Current characteristics on page 41 Updated tw min in Table 21: High-speed external user clock characteristics on page 55 Updated startup time in Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 59 Updated note 2 in Table 51: I2C characteristics on page 93 Updated Figure 48: I2C bus AC waveforms and measurement circuit Updated Figure 47: Recommended NRST pin protection Updated Section 5.3.14: I/O port characteristics Updated Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings on page 64 Updated FSMC Figure 28 thru Figure 31 Updated Figure 41: NAND controller waveforms for common memory write access and Table 40: Switching characteristics for NAND Flash read and write cycles on page 82 Added Section 5.3.13: I/O current injection characteristics on page 85 Updated Figure 66 and added Table 69: Recommended PCB design rules (0.5mm pitch BGA) on page 116 LQFP64 package mechanical data updated: see Figure 71: LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline and Table 72: LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data. 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