UNDERSTANDING INTERGRATED CIRCUIT PACKAGE POWER CA - National Semiconductor

Appendix E: Understanding Integrated Circuit Package

Power Capabilities

INTRODUCTION

The short and long term reliability of National Semiconduc-

tor’s interface circuits, like any integrated circuit, is very de-

pendent on its environmental condition. Beyond the

mechanical/environmental factors, nothing has a greater in-

fluence on this reliability than the electrical and thermal

stress seen by the integrated circuit. Both of these stress is-

sues are specifically addressed on every interface circuit

data sheet, under the headings of Absolute Maximum Rat-

ings and Recommended Operating Conditions.

However, through application calls, it has become clear that

electrical stress conditions are generally more understood

than the thermal stress conditions. Understanding the impor-

tance of electrical stress should never be reduced, but

clearly, a higher focus and understanding must be placed on

thermal stress. Thermal stress and its application to interface

circuits from National Semiconductor is the subject of this

application note.

FACTORS AFFECTING DEVICE

RELIABILITY

Figure 1

shows the well known “bathtub” curve plotting fail-

ure rate versus time. Similar to all system hardware (me-

chanical or electrical) the reliability of interface integrated cir-

cuits conform to this curve. The key issues associated with

this curve are infant mortality, failure rate, and useful life.

Infant mortality, the high failure rate from time t0 to t1 (early

life), is greatly influenced by system stress conditions other

than temperature, and can vary widely from one application

to another. The main stress factors that contribute to infant

mortality are electrical transients and noise, mechanical mal-

treatment and excessive temperatures. Most of these fail-

ures are discovered in device test, burn-in, card assembly

and handling, and initial system test and operation.Although

important, much literature is available on the subject of infant

mortality in integrated circuits and is beyond the scope of this

application note.

Failure rate is the number of devices that will be expected to

fail in a given period of time (such as, per million hours). The

mean time between failure (MTBF) is the average time (in

hours) that will be expected to elapse after a unit has failed

before the next unit failure will occur. These two primary

“units of measure” for device reliability are inversely related:

Although the “bathtub” curve plots the overall failure rate ver-

sus time, the useful failure rate can be defined as the per-

centage of devices that fail per-unit-time during the flat por-

tion of the curve. This area, called the useful life, extends

between t1 and t2 or from the end of infant mortality to the

onset of wearout. The useful life may be as short as several

years but usually extends for decades if adequate design

margins are used in the development of a system.

Many factors influence useful life including: pressure, me-

chanical stress, thermal cycling, and electrical stress. How-

ever, die temperature during the device’s useful life plays an

equally important role in triggering the onset of wearout.

FAILURE RATES vs TIME AND

TEMPERATURE

The relationship between integrated circuit failure rates and

time and temperature is a well established fact. The occur-

rence of these failures is a function which can be repre-

sented by the Arrhenius Model. Well validated and predomi-

nantly used for accelerated life testing of integrated circuits,

the Arrhenius Model assumes the degradation of a perfor-

mance parameter is linear with time and that MTBF is a func-

tion of temperature stress. The temperature dependence is

an exponential function that defines the probability of occur-

rence. This results in a formula for expressing the lifetime or

MTBF at a given temperature stress in relation to another

MTBF at a different temperature. The ratio of these two MT-

BFs is called the acceleration factor F and is defined by the

following equation:

Where: X1 = Failure rate at junction temperature T1

X2 = Failure rate at junction temperature T2

T = Junction temperature in degrees Kelvin

E = Thermal activation energy in electron volts (ev)

K = Boltzman’s constant

However, the dramatic acceleration effect of junction tem-

perature (chip temperature) on failure rate is illustrated in a

plot of the above equation for three different activation ener-

gies in

Figure 2

. This graph clearly demonstrates the impor-

MS009312-1

FIGURE 1. Failure Rate vs Time

April 2000

Appendix E Understanding Integrated Circuit Package Power Capabilities

FAILURE RATES vs TIME AND

TEMPERATURE (Continued)

tance of the relationship of junction temperature to device

failure rate. For example, using the 0.99 ev line, a 30˚ rise in

junction temperature, say from 130˚C to 160˚C, results in a

10 to 1 increase in failure rate.

DEVICE THERMAL CAPABILITIES

There are many factors which affect the thermal capability of

an integrated circuit. To understand these we need to under-

stand the predominant paths for heat to transfer out of the in-

tegrated circuit package. This is illustrated by

Figure 3

and

Figure 4

Figure 3

shows a cross-sectional view of an assembled inte-

grated circuit mounted into a printed circuit board.

Figure 4

is a flow chart showing how the heat generated at

the power source, the junctions of the integrated circuit flows

from the chip to the ultimate heat sink, the ambient environ-

ment. There are two predominant paths. The first is from the

die to the die attach pad to the surrounding package material

to the package lead frame to the printed circuit board and

then to the ambient. The second path is from the package di-

rectly to the ambient air.

Improving the thermal characteristics of any stage in the flow

chart of

Figure 4

will result in an improvement in device ther-

mal characteristics. However, grouping all these characteris-

tics into one equation determining the overall thermal capa-

bility of an integrated circuit/package/environmental

condition is possible. The equation that expresses this rela-

tionship is: T

(θ

)

Where: T

= Die junction temperature

= Ambient temperature in the vicinity device

= Total power dissipation (in watts)

= Thermal resistance junction-to-ambient

, the thermal resistance from device junction-to-ambient

temperature, is measured and specified by the manufactur-

ers of integrated circuits. National Semiconductor utilizes

special vehicles (e.g. thermal test dies) and methods to mea-

sure and monitor this parameter. All circuit data sheets

specify the thermal characteristics and capabilities of the

packages available for a given device under specific

conditions—these package power ratings directly relate to

thermal resistance junction-to-ambient or θ

Although National provides these thermal ratings, it is critical

that the end user understand how to use these numbers to

improve thermal characteristics in the development of his

system using IC components.

MS009312-2

FIGURE 2. Failure Rate as a Function

of Junction Temperature

MS009312-3

FIGURE 3. Integrated Circuit Soldered into a Printed Circuit Board (Cross-Sectional View)

MS009312-4

FIGURE 4. Thermal Flow (Predominant Paths)

Appendix E

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DETERMINING DEVICE

OPERATING JUNCTION

TEMPERATURE

From the above equation the method of determining actual

worst-case device operating junction temperature becomes

straightforward. Given a package thermal characteristic, θ

worst-case ambient operating temperature, T

(max), the

only unknown parameter is device power dissipation, P

.In

calculating this parameter, the dissipation of the integrated

circuit due to its own supply has to be considered, the dissi-

pation within the package due to the external load must also

be added. The power associated with the load in a dynamic

(switching) situation must also be considered. For example,

the power associated with an inductor or a capacitor in a

static versus dynamic (say, 1 MHz) condition is significantly

different.

The junction temperature of a device with a total package

power of 600 mW at 70˚C in a package with a thermal resis-

tance of 63˚C/W is 108˚C.

= 70˚C + (63˚C/W) x (0.6W) = 108˚C

The next obvious question is, “how safe is 108˚C?”

MAXIMUM ALLOWABLE

JUNCTION TEMPERATURES

What is an acceptable maximum operating junction tempera-

ture is in itself somewhat of a difficult question to answer.

Many companies have established their own standards

based on corporate policy. However, the semiconductor in-

dustry has developed some defacto standards based on the

device package type. These have been well accepted as

numbers that relate to reasonable (acceptable) device life-

times, thus failure rates.

National Semiconductor has adopted these industry-wide

standards. For devices fabricated in a molded package, the

maximum allowable junction temperature is 150˚C. For

these devices assembled in ceramic or cavity DIP packages,

the maximum allowable junction temperature is 175˚C. The

numbers are different because of the differences in package

types. The thermal strain associated with the die package in-

terface in a cavity package is much less than that exhibited

in a molded package where the integrated circuit chip is in di-

rect contact with the package material.

Let us use this new information and our thermal equation to

construct a graph which displays the safe thermal (power)

operating area for a given package type.

Figure 5

is an ex-

ample of such a graph. The end points of this graph are eas-

ily determined. For a 16-pin molded package, the maximum

allowable temperature is 150˚C; at this point no power dissi-

pation is allowable. The power capability at 25˚C is 1.98W as

given by the following calculation:

The slope of the straight line between these two points is mi-

nus the inversion of the thermal resistance. This is referred

to as the derating factor.

As mentioned,

Figure 5

is a plot of the safe thermal operating

area for a device in a 16-pin molded DIP. As long as the in-

tersection of a vertical line defining the maximum ambient

temperature (70˚C in our previous example) and maximum

device package power (600 mW) remains below the maxi-

mum package thermal capability line the junction tempera-

ture will remain below 150˚C—the limit for a molded pack-

age. If the intersection of ambient temperature and package

power fails on this line, the maximum junction temperature

will be 150˚C.Any intersection that occurs above this line will

result in a junction temperature in excess of 150˚C and is not

an appropriate operating condition.

The thermal capabilities of all integrated circuits are ex-

pressed as a power capability at 25˚C still air environment

with a given derating factor. This simply states, for every de-

gree of ambient temperature rise above 25˚C, reduce the

package power capability stated by the derating factor which

is expressed in mW/˚C. For our example—a θ

of 63˚C/W

relates to a derating factor of 15.9 mW/˚C.

FACTORS INFLUENCING

PACKAGE THERMAL

RESISTANCE

As discussed earlier, improving any portion of the two pri-

mary thermal flow paths will result in an improvement in

overall thermal resistance junction-to-ambient. This section

discusses those components of thermal resistance that can

be influenced by the manufacturer of the integrated circuit. It

also discusses those factors in the overall thermal resistance

that can be impacted by the end user of the integrated cir-

cuit. Understanding these issues will go a long way in under-

standing chip power capabilities and what can be done to in-

sure the best possible operating conditions and, thus, best

overall reliability.

Die Size

Figure 6

shows a graph of our 16-pin DIP thermal resistance

as a function of integrated circuit die size. Clearly, as the chip

size increases the thermal resistance decreases—this re-

lates directly to having a larger area with which to dissipate

a given power.

MS009312-5

FIGURE 5. Package Power Capability

vs Temperature

Appendix E

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Die Size (Continued)

Pin Count

For higher pin count packages such as Plastic Quad Flat

Packages (PQFPs),

Figure 7

shows the range of thermal re-

sistances for a number of different package pin counts, from

44 to 160-lead. Better thermal dissipation is achieved with

the larger packages. The values observed depend on the die

and corresponding paddle sizes.

Lead Frame Material

Figure 8

shows the influence of lead frame material (both die

attach and device pins) on thermal resistance. This graph

compares our same 16-pin DIP with a copper lead frame, a

Kovar lead frame, and finally an Alloy 42 type lead

frame—these are lead frame materials commonly used in

the industry. Obviously the thermal conductivity of the lead

frame material has a significant impact in package power ca-

pability. Molded interface circuits from National Semiconduc-

tor use the copper lead frame exclusively.

Board vs Socket Mount

One of the major paths of dissipating energy generated by

the integrated circuit is through the device leads. As a result

of this, the graph of

Figure 9

comes as no surprise. This

compares the thermal resistance of our 16-pin package sol-

dered into a printed circuit board (board mount) compared to

the same package placed in a socket (socket mount).Adding

a socket in the path between the PC board and the device

adds another stage in the thermal flow path, thus increasing

the overall thermal resistance. The thermal capabilities of

National Semiconductor’s interface circuits are specified as-

suming board mount conditions. If the devices are placed in

a socket the thermal capabilities should be reduced by ap-

proximately 5% to 10%.

An example of the thermal resistance observable for board

mounted packages is illustrated in

Figure 10

. In this case,

the typical thermal resistance is shown for three TO-263

packages mounted on a PC board with 1 oz copper. A rapid

drop in thermal resistance is observed, albeit the gain has di-

minishing returns as the copper surface area is enlarged.

MS009312-6

FIGURE 6. Thermal Resistance vs Die Size

MS009312-18

FIGURE 7. Thermal resistance for the PQFP family of

packages. The bars on the data points indicate the

variation of the thermal resistance. This variation is

dependent on the device size and the die attach

paddle size.

MS009312-7

FIGURE 8. Thermal Resistance vs

Lead Frame Material

MS009312-8

FIGURE 9. Thermal Resistance vs

Board or Socket Mount

Appendix E

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Board vs Socket Mount (Continued)

Air Flow

When a high power situation exists and the ambient tem-

perature cannot be reduced, the next best thing is to provide

air flow in the vicinity of the package. Forced convection

around packages mounted on boards can be divided into

laminar flow and turbulent flow. The transition from laminar to

turbulent occurs at a typical velocity of 180 feet per minute

(180 LFPM). In laminar flow, the fluid particles follow a

smooth path, while on the other hand, turbulent flow is char-

acterized by irregular motion of fluid ″eddies″in which par-

ticles are continuously re-arranged and mixed. Greater heat

transfer is obtained with turbulent flow.

Figure 11

and

Figure

illustrate the impact of air flow on the thermal resistance

of a 16-pin DIP and a 100-pin PQFP, respectively. The ther-

mal ratings on National Semiconductor’s interface circuits

data sheets relate to the still air environment.

Other Factors

A number of other factors influence thermal resistance. The

most important of these is using thermal epoxy in mounting

ICs to the PC board and heat sinks. Generally these tech-

niques are required only in the very highest of power applica-

tions.

Some confusion exists between the difference in thermal re-

sistance junction-to-ambient (θ

) and thermal resistance

junction-to-case (θ

). The best measure of actual junction

temperature is the junction-to-ambient number since nearly

all systems operate in an open air environment. The only

situation where thermal resistance junction-to-case is impor-

tant is when the entire system is immersed in a thermal bath

and the environmental temperature is indeed the case tem-

perature. This is only used in extreme cases and is the ex-

ception to the rule and, for this reason, is not addressed in

this application note.

TO-263 (S Package) Board Mount, Still Air

MS009312-13

*For products with high current ratings (>3A), thermal resistance may be lower. Consult product datasheet for more information.

FIGURE 10. Thermal Resistance (typ.*) for 3-, 5-,

and 7-L TO-263 packages mounted on 1 oz.

(0.036mm) PC board foil

MS009312-9

FIGURE 11. Thermal Resistance vs Air Flow (16-pin

DIP)

MS009312-19

FIGURE 12. Effect of air flow on a 100 lead PQFP

mounted on a JEDEC thermal board. The package has

a die attach paddle size of 260x260 mil. The data also

shows the effect on two different device sizes.

Appendix E

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NATIONAL SEMICONDUCTOR

PACKAGE CAPABILITIES

Figure 13

and

Figure 14

show composite plots of the thermal

characteristics of the most common package types in the

National Semiconductor Linear Circuits product family.

Fig-

ure 13

is a composite of the copper lead frame molded pack-

age.

Figure 14

is a composite of the ceramic (cavity) DIP us-

ing poly die attach. These graphs represent board mount still

air thermal capabilities. Another, and final, thermal resis-

tance trend will be noticed in these graphs.As the number of

device pins increase in a DIP the thermal resistance de-

creases. Referring back to the thermal flow chart, this trend

should, by now, be obvious.

RATINGS ON INTEGRATED

CIRCUITS DATA SHEETS

In conclusion, all National Semiconductor Linear Products

define power dissipation (thermal) capability. This informa-

tion can be found in the Absolute Maximum Ratings section

of the data sheet. The thermal information shown in this ap-

plication note represents average data for characterization

of the indicated package. Actual thermal resistance can vary

from ±10% to ±15% due to fluctuations in assembly quality,

die shape, die thickness, distribution of heat sources on the

die, etc. The numbers quoted in the linear data sheets reflect

a 15% safety margin from the average numbers found in this

application note. Insuring that total package power remains

under a specified level will guarantee that the maximum

junction temperature will not exceed the package maximum.

The package power ratings are specified as a maximum

power at 25˚C ambient with an associated derating factor for

ambient temperatures above 25˚C. It is easy to determine

the power capability at an elevated temperature. The power

specified at 25˚C should be reduced by the derating factor

for every degree of ambient temperature above 25˚C. For

example, in a given product data sheet the following will be

found:

Maximum Power Dissipation (Note 1) at 25˚C

Cavity Package 1509 mW

Molded Package 1476 mW

Note 1: Derate cavity package at 10 mW/˚C above 25˚C; derate molded

package at 11.8 mW/˚C above 25˚C.

If the molded package is used at a maximum ambient tem-

perature of 70˚C, the package power capability is 945 mW.

@70˚C = 1476 mW−(11.8 mW/˚C)x(70˚C−25˚C)

= 945 mW

Molded (N Package) DIP*Copper Leadframe—HTP Die

Attach Board Mount— Still Air

MS009312-10

*Packages from 8- to 20-pin 0.3 mil width

22-pin 0.4 mil width

24- to 40-pin 0.6 mil width

FIGURE 13. Thermal Resistance vs Die Size

vs Package Type (Molded Package)

Cavity (J Package) DIP*Poly Die Attach Board

Mount—Still Air

MS009312-11

*Packages from 8- to 20-pin 0.3 mil width

22-pin 0.4 mil width

24- to 48-pin 0.6 mil width

FIGURE 14. Thermal Resistance vs Die Size

vs Package Type (Cavity Package)

Appendix E

www.national.com 6

Notes

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whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

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safety or effectiveness.

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www.national.com

Appendix E Understanding Integrated Circuit Package Power Capabilities

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.