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October 2013
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDPC8016S Rev.C7
GR GR
PIN1
Top Bottom
Power Clip 5X6
PIN1
V+
LSG
SW
SW
SW
V+
HSG
SW
LSG
SW
SW
SW
V+
V+
HSG
PAD9
GND(LSS)
PAD10
V+(HSD)
FDPC8016S
PowerTrench® Power Clip
25V Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
Max rDS(on) = 3.8 mΩ at VGS = 10 V, ID = 20 A
Max rDS(on) = 4.7 mΩ at VGS = 4.5 V, ID = 18 A
Q2: N-Channel
Max rDS(on) = 1.4 mΩ at VGS = 10 V, ID = 35 A
Max rDS(on) = 1.7 mΩ at VGS = 4.5 V, ID = 32 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
dual package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck
converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Symbol Parameter Q1 Q2 Units
VDS Drain to Source Voltage 25Note5 25 V
VGS Gate to Source Voltage ±12 ±12 V
ID
Drain Current -Continuous TC = 25 °C 60 100 A -Continuous TA = 25 °C 20Note1a 35Note1b
-Pulsed TA = 25 °C (Note 4) 75 140
EAS Single Pulse Avalanche Energy (Note 3) 73 216 mJ
PDPower Dissipation for Single Operation TC = 25 °C 21 42 W
Power Dissipation for Single Operation TA = 25 °C 2.1Note1a 2.3 Note1b
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction to Case 6.0 3.0 °C/WRθJA Thermal Resistance, Junction to Ambient 60Note1a 55Note1b
RθJA Thermal Resistance, Junction to Ambient 130Note1c 120Note1d
Pin Name Description Pin Name Description Pin Name Description
1 H S G H i g h S i d e G a t e 3,4,10 V+(HSD) High Side Drain 8 LSG Low Side Gate
2 GR Gate Return 5,6,7 SW Switching Node, Low Side Drain 9 GND(LSS) Low Side Source
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corp oration 2 www.fairchildsemi.com
FDPC8016S Rev.C7
Package Marking and Ordering Information
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristics
On Characte ri st ic s
Dynamic Characterist ic s
Switching Characteristics
Device Marking Device Package Reel Size Tape Width Quantity
05OD/15OD FDPC8016S Power Clip 56 13 ” 12 mm 3000 units
Symbol Parameter Test Conditions Type Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V Q1
Q2 25
25 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C Q1
Q2 24
28 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V
VDS = 20 V, VGS = 0 V Q1
Q2 1
500 μA
μA
IGSS Gate to Source Leakage Current VGS = 12 V/-8 V, VDS= 0 V
VGS = 12 V/-8 V, VDS= 0 V Q1
Q2
±100
±100 nA
nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA Q1
Q2 0.8
1.1 1.3
1.5 2.5
2.5 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C Q1
Q2 -4
-3 mV/°C
rDS(on) Drain to Source On Resistance
VGS = 10V, ID = 20 A
VGS = 4.5 V, ID = 18 A
VGS = 10 V, ID = 20 A,TJ =125 °C Q1 2.8
3.4
3.9
3.8
4.7
5.3 mΩ
VGS = 10V, ID = 35 A
VGS = 4.5 V, ID = 32 A
VGS = 10 V, ID = 35 A ,TJ =125 °C Q2 1.1
1.3
1.5
1.4
1.7
1.9
gFS Forward Transconductance VDS = 5 V, ID = 20 A
VDS = 5 V, ID = 35 A Q1
Q2 182
241 S
Ciss Input Capacitance Q1:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2 1695
4715 2375
6600 pF
Coss Output Capacitance Q1
Q2 495
1195 710
1675 pF
Crss Reverse Transfer Capacitance Q1
Q2 54
159 100
290 pF
RgGate Resistance Q1
Q2 0.1
0.1 0.4
0.5 1.2
1.5 Ω
td(on) Turn-On Delay Time Q1:
VDD = 13 V, ID = 20 A, RGEN = 6 Ω
Q2:
VDD = 13 V, ID = 35 A, RGEN = 6 Ω
Q1
Q2 8
13 16
24 ns
trRise Time Q1
Q2 2
410
10 ns
td(off) Turn-Off Delay Time Q1
Q2 24
38 38
61 ns
tfFall Time Q1
Q2 2
310
10 ns
QgTotal Gate Charge VGS = 0 V to 10 V Q1
VDD = 13 V, ID
= 20 A
Q2
VDD = 13 V, ID
= 35 A
Q1
Q2 25
67 35
94 nC
QgTotal Gate Charge VGS = 0 V to 4.5 V Q1
Q2 11
31 16
44 nC
Qgs Gate to Source Gate Charge Q1
Q2 3.4
10 nC
Qgd Gate to Drain “Miller” Charge Q1
Q2 2.2
6.3 nC
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corp oration 3 www.fairchildsemi.com
FDPC8016S Rev.C7
Electrical Characteristics TJ = 25 °C unless otherwise noted
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Type Min Typ Max Units
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 20 A (Note 2)
VGS = 0 V, IS = 35 A (Note 2) Q1
Q2 0.8
0.8 1.2
1.2 V
trr Reverse Recovery Time Q1
IF = 20 A, di/dt = 100 A/μs
Q2
IF = 35 A, di/dt = 200 A/μs
Q1
Q2 25
33 40
53 ns
Qrr Reverse Recovery Charge Q1
Q2 10
31 20
50 nC
Notes:
1.RθJA is deter min ed w it h th e d evi ce mounted on a 1 in2 pad 2 oz copp er pa d o n a 1. 5 x 1.5 in. board of FR-4 material . RθJC is gu ar an tee d by design while RθCA is determi ne d by
the user's board design.
2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Q1 :EAS of 73 mJ is based on starting TJ = 25 oC; N-ch: L = 3 mH, IAS = 7 A, VDD = 30 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 24 A.
Q2: EAS of 216 mJ is based on starting TJ = 25 oC; N-ch: L = 3 mH, IAS = 12 A, VDD = 25 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 39 A.
4. Pulsed Id limited by junction temperature, td<=10 us. Please refer to SOA curve for more details.
5. The continuous VDS rating is 25 V; However, a pulse of 30 V peak voltage for no longer than 100 ns duration at 600 KHz frequency can be applied.
a. 60 °C/W when mounted on
a 1 in2 pad of 2 oz copper
c. 130 °C/W when mounted on a
minimum pad of 2 oz copper
b. 55 °C/W when mounted on
a 1 in2 pad of 2 oz copper
d. 120 °C/W when moun ted on a
minimum pad of 2 oz copper
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com
FDPC8016S Rev.C7
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
Figure 1.
0.00.20.40.60.81.0
0
15
30
45
60
75
VGS = 3.5 V
VGS = 3 V
PULSE DU R ATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 4.5 V
On Region Characteristics Figure 2.
0 1530456075
0
1
2
3
4
5
VGS = 3 V
PULSE DUR A TION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 3.5 V VGS = 4.5 V
VGS = 2.5 V
VGS = 10 V
Normalized On-Resista nce
vs. Drain Current and Gate Voltage
Figure 3. Normalized On Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
ID = 20 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERA TU R E (oC)
vs. Junction Temperature Figure 4.
12345678910
0
3
6
9
12
TJ = 125 oC
ID = 20 A
TJ = 25 oC
VGS, GA TE TO SOURCE VOLTAGE (V)
rDS(on), DR AIN T O
SOURCE ON-RESISTA NCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs. Gate to
Source Voltage
Figure 5. Transfer Characteristics
1.0 1.5 2.0 2.5 3.0
0
15
30
45
60
75
TJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO S OU R CE V OLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0
0.001
0.01
0.1
1
10
100
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs. Source Current
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com
FDPC8016S Rev.C7
Figure 7.
0 6 12 18 24 30
0
2
4
6
8
10 ID = 20 A
VDD = 15 V
VDD = 10 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHA R GE (nC)
VDD = 13 V
Gate Charge Characteristics Figure 8.
0.1 1 10 25
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (p F )
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capacitance vs. Dra in
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100
1
10
30
TJ = 100 oC
TJ = 25 oC
TJ = 12 5 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
Un cla mpe d Indu ctiv e
Switching Capability Figure 10.
25 50 75 100 125 150
0
10
20
30
40
50
60
70
VGS = 4.5 V
RθJC = 6.0 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
Maximum Continuous Drain
Current vs. Case Temperature
Figure 11. Forward Bias Safe
Operating Area
0.1 1 10 80
0.1
1
10
100
500
CURVE BENT TO
MEASURED DATA
10 μs
10 ms
DC
100 μs
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
TH IS AR EA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 6.0 oC/W
TC = 25 oC
Figure 12. Single Pulse Maximum
Power Dissipation
10-5 10-4 10-3 10-2 10-1 1
10
100
1000
5000
P(PK), PEAK TRANSIENT POWER (W)
SINGLE P U LS E
RθJC = 6.0 oC/W
TC = 25 oC
t, PU L S E WIDT H (s e c)
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com
FDPC8016S Rev.C7
Figure 13. Junction-to-Case Transient Thermal Response Curve
10-5 10-4 10-3 10-2 10-1 1
0.005
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t) , NORMALIZED EFF ECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1t2
NOTES:
DUTY FACTOR: D = t
1
/ t
2
T
J
-
T
C
= P
DM
x Z
θ
JC
(t)
Z
θ
JC
(t) = r(t) x R
θ
Jc
R
θ
JC
= 6.0
o
C/W
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corp oration 7 www.fairchildsemi.com
FDPC8016S Rev.C7
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
Figure 14. O n- R egion Characteristics Figur e 15. Normalized on-Resistance vs. Drain
Current and Gate Voltage
Figure 16. Normalized On-Resistance
vs. Junction Temper ature Figure 17. On-Resistance vs. Gate to
Source Voltage
Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode
Forward Voltage vs. Source Current
0.0 0.2 0.4 0.6 0.8
0
20
40
60
80
100
120
140
VGS = 3.5 V
VGS = 3 V
VGS = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% M A X
VGS = 2.5 V
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRA IN TO SOURCE VOLTAGE (V)
0 20 40 60 80 100 120 140
0.0
1.5
3.0
4.5
6.0
VGS = 3 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 3.5 V VGS = 4.5 V
VGS = 2.5 V
VGS = 10 V
-75 -50 -25 0 25 50 75 100 125 150
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
ID = 35 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNC TION TEMPER A TU R E (oC)
12345678910
0
1
2
3
4
5
TJ = 125 oC
ID = 35 A
TJ = 25 oC
VGS, GA TE TO SOURCE VOLTAGE (V)
rDS(on), DR AIN T O
SOURCE ON-RESISTA NCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
1234
0
20
40
60
80
100
120
140
TJ = 125 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO S OU RC E V OLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0
0.001
0.01
0.1
1
10
100
200
TJ = -55 oC
TJ = 25 oC
TJ = 125 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corp oration 8 www.fairchildsemi.com
FDPC8016S Rev.C7
Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted
Figure 20. Gate Charge Characteristics Figure 21. Capacitanc e vs. D rain
to Source Voltage
Figure 22. Unc lamped Inductive
Switching Capability Figure 23. Maximum Continuous Drain
Current vs. Case Temperature
Figure 24. Forward Bias Safe
Operating Area Figure 25. Single Pulse Maximum
Power Dissipation
0 20406080
0
2
4
6
8
10
ID = 35 A
VDD = 15 V
VDD = 10 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 13 V
0.1 1 10 25
10
100
1000
10000
f = 1 M H z
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
0.001 0.01 0.1 1 10 100 1000
1
10
50
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
25 50 75 100 125 150
0
20
40
60
80
100
120
140
160
Limited by Package
VGS = 4.5 V
RθJC = 3.0 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
0.1 1 10 80
0.1
1
10
100
1000
10 μs
CURVE BENT TO
MEASURED DATA
100 μs
10 m s
DC
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 3.0 oC/W
TC = 25 oC
10-5 10-4 10-3 10-2 10-1 1
10
100
1000
10000
P(PK), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJC = 3.0 oC/W
TC = 25 oC
t, PULSE WIDTH (sec)
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
Figure 26. Junction-to-Case Transient Thermal Response Curve
10-5 10-4 10-3 10-2 10-1 1
0.003
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURA TION (sec)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
PDM
t1t2
NOTES:
DUTY FAC TOR: D = t
1
/ t
2
T
J
-
T
C
= P
DM
x Z
θ
JC
(t)
Z
θ
JC
(t) = r(t) x R
θ
Jc
R
θ
JC
= 3.0
o
C/W
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com
FDPC8016S Rev.C7
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com
FDPC8016S Rev.C7
SyncFETTM Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench® MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverses recovery
characteristic of the FDPC8016S.
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
Figure 27. FDPC8016S SyncFETTM Body
Diode Reverse Recovery Cha racteristic
50 100 150 200 250 300 350 400
-5
0
5
10
15
20
25
30
35
40
di / dt = 200 A/μS
CURRENT (A)
TIME (ns)
Figure 28. SyncFETTM Body Diode Reverse
Leakage vs. Drain-source Voltage
0 5 10 15 20 25
10-6
10-5
10-4
10-3
10-2
TJ = 125 oC
TJ = 100 oC
TJ = 25 oC
IDSS, REV E RSE LEAKAGE CURRENT (A)
VDS, REVERSE VOLTAGE (V)
Typical Characteristics (continued)
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com
FDPC8016S Rev.C7
Dimensional Outline and Pad Layout
C
L
L
C
PKG
PKG
5.10
4.90
6.10
5.90
C
5.00±.05
3.81
1.57±.05
TOP VIEW
SIDE VIEW
BOTTOM VIEW
58
41
4 3 2 1
567
0.10 C A B
0.05 C
1.37±.05
0.49±.05
NOTES: UNLESS OTHERWISE SPECIFIED
A) DOES NOT FULLY CONFORM TO
JEDEC REGISTRATION, MO-229,
DATED 11/2001.
B) ALL DIMENSIONS ARE IN
MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE
BURRS OR MOLD FLASH. MOLD
FLASH OR BURRS DOES NOT
EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
SEE
DETAIL A
(SCALE: 2X)
0.05
0.00
0.30
0.20
0.08 C
PIN #1
INDICATOR
SEATING
PLANE
0.10 C
0.80
0.70
RECOMMENDED LAND PATTERN
5678
1
2
3
4
1.27
0.65±.05
0.48±.05
A
0.10 C
2X
B
0.10 C
2X
0.51±.05
2.46±.05
8
3.90±.05
0.53±.05
0.91±.05
0.51
6.60
0.75
4.22±.05
3.15±.05
0.00
0.00
1.43
3.30
2.08
2.48
3.30
2.48
1.53
1.01
1.08
1.48
1.53
2.29
0.83
5.00
0.82
1.01
0.40
2.65
1.98
4.56
4.20
1.27
0.65±.05
E) DRAWING FILE NAME:
FDPC8016S PowerTrench® Power Clip
©2013 Fairchild Semiconductor Corporation 12 www.fairchildsemi.com
FDPC8016S Rev.C7
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