MCP6241UT-E/OT - MICROCHIP

MCP6241/1R/1U/2/4

Features

• Gain Bandwidth Product: 550 kHz (typical)

• Supply Current: IQ = 50 µA (typical)

• Supply Voltage: 1.8V to 5.5V

• Rail-to-Rail Input/Outp ut

• Extended Temperature Range: -40°C to +125°C

• Available in 5-pin SC-70 and SOT-23 packages

Applications

• Automotive

• Portable Equipment

• Photodiode (Transimpedance) Amplifier

• Analog Filters

• Notebooks and PDAs

• Battery-Powered Systems

Design Aids

• SPICE Macro Models

• Mindi™ Circui t Designer & Simulator

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Typical Application

Description

The Microchip Technology Inc. MCP6241/1R/1U/2/4

operational amplifiers (op amps) provide wide

bandwidth for the quiescent current. The MCP6241/1R/

1U/2/4 has a 550 kHz gain bandwidth product and 68°

(typical) phase margin. This family operates from a

single supply voltage as low as 1.8V, while drawing

50 µA (typical) quiescent current. In addition, the

MCP6241/1R/1U/2/4 family supports rail-to-rail input

and output swing, with a common mode input voltage

range of VDD +300mV to V

SS – 300 mV. These op

amps are designed in one of Microchip’s advanced

CMOS processes.

Package Types

MCP6241 VOUT

VIN2

–

VIN1

RG2

RG1

VDD

Summing Amplifier Circuit

MCP6241

–

5VDD

VIN–

VOUT

VSS

VIN+

SOT-23-5

5VDD

VOUT

VSS

MCP6241R

SOT-23-5

–

5VSS

VIN–

VOUT

VDD

VIN+

MCP6241U

SC-70-5, SOT-23-5

–

5VDD

VOUT

VIN+

VSS

VIN–

VIN+

VIN–

MCP6241

VSS

VDD

VOUT

–

PDIP, SOIC, MSOP

MCP6242

PDIP, SOIC, MSOP

VINA_

VINA+

VSS

VOUTA

VOUTB

VDD

VINB_

VINB+

MCP6244

VINA+

VINA–

VSS

VOUTA +-

VDD

VOUTD

VIND–

VIND+

VOUTB

VINB–

VINB+VINC+

VINC–

VOUTC

PDIP, SOIC, TSSOP

MCP6241

2x3 DFN*

VIN+

VIN–

VSS

VDD

VOUT

5NC

NCNC

* Includes Exposed Thermal Pad (EP); see Table 3-1.

50 µA, 550 kHz Rail-to-Rail Op Amp

MCP6241/1R/1U/2/4

NOTES:

MCP6241/1R/1U/2/4

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD –V

SS ........................................................................7.0V

Current at Analog Input Pins (VIN+, VIN–).....................±2 mA

Analog Inputs (VIN+, VIN–) ††........ VSS –1.0VtoV

DD +1.0V

All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V

Difference Input Voltage ...................................... |VDD –V

SS|

Output Short Circuit Current ................................Continuous

Current at Output and Supply Pins ............................±30 mA

Storage Temperature ..................................–65° C to +150°C

Maximum Junction Temperature (TJ)..........................+150°C

ESD Protection On All Pins (HBM; MM).............. ≥ 4 k V; 300V

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

†† See Section 4.1.2 “Input Voltage and Current Limits”.

DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND,

VCM = VDD/2, RL = 10 0 kΩ to VDD/2 and VOUT ≈VDD/2.

Parameters Sym Min Typ Max Units Conditions

Input Offset

Input Offset Voltage VOS -5.0 — +5.0 mV VCM = VSS

Extended Temperature VOS -7.0 — +7.0 mV TA= -40°C to +125°C,

VCM = VSS (Note 1)

Input Offset Drift with

Temperature ΔVOS/ΔTA— ±3.0 — µV/°C TA= -40°C to +125°C,

VCM = VSS

Power Supply Rejection PSRR — 83 — dB VCM = VSS

Input Bias Current and Impedance

Input Bias Current: IB—±1.0—pA

At Temperature IB—20—pAT

A = +85°C

At Temperature IB— 1100 — pA TA = +125°C

Input Offset Current IOS —±1.0—pA

Common Mode Input Impedance ZCM —10

13||6 — Ω||pF

Differential Input Impedance ZDIFF —10

13||3 — Ω||pF

Common Mode

Common Mode Input Range VCMR VSS – 0.3 — VDD + 0.3 V

Common Mode Rejection Ratio CMRR 60 75 — dB VCM = -0.3V to 5.3V, VDD = 5V

Open-Loop Gain

DC Open-Loop Gain

(large signal) AOL 90 110 — dB VOUT = 0.3V to VDD – 0.3V,

VCM =V

Output

Maximum Output Voltage Swing VOL, VOH VSS + 35 — VDD – 35 mV RL = 10 kΩ, 0.5V Input

Overdrive

Output Short-Circuit Current ISC —±6—mAV

DD = 1.8V

ISC —±23—mAV

DD = 5.5V

Power Supply

Supply Voltage VDD 1.8 — 5.5 V

Quiescent Current per Amplifier IQ30 50 70 µA IO = 0, VCM = VDD – 0.5V

Note 1: The SC-70 package is only tested at +25°C.

MCP6241/1R/1U/2/4

AC ELECTRICAL CHARACTERISTICS

TEMPERATURE CHARACTERISTICS

1.1 Test Circuits

The test circuits used for the DC and AC tests are

shown in Figure 1-1 and Figure 1-2. The bypass

capacitors are laid out according to the rules discussed

in Section 4.6 “PCB Surface Leakage”.

FIGURE 1-1: AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

FIGURE 1-2: AC and DC Test Circuit for

Most Inverting Gain Conditions.

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.

Parameters Sym Min Typ Max Units Conditions

AC Response

Gain Bandwidth Product GBWP — 550 — kHz

Phase Margin PM — 68 — ° G = +1 V/V

Slew Rate SR — 0.30 — V/µs

Noise

Input Noise Voltage Eni —10—µV

P-P f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —45—nV/√Hz f = 1 kHz

Input Noise Current Density ini —0.6—fA/√Hz f = 1 kHz

Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Extended Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 °C (Note)

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SC70 θJA —331 —°C/W

Thermal Resistance, 5L-SOT-23 θJA —256 —°C/W

Thermal Resistance, 8L-DFN (2x3) θJA — 84.5 — °C/W

Thermal Resistance, 8L-MSOP θJA —206—°C/W

Thermal Resistance, 8L-PDIP θJA —85—°C/W

Thermal Resistance, 8L-SOIC θJA —163—°C/W

Thermal Resistance, 14L-PDIP θJA —70—°C/W

Thermal Resistance, 14L-SOIC θJA —120—°C/W

Thermal Resistance, 14L-TSSOP θJA —100—°C/W

Note: The internal Junction Temperature (T J) must not exceed the Absolute Maximum specification of +150°C.

VDD

MCP624X

RGRF

RNVOUT

VIN

VDD/2

1µF

CLRL

0.1 µF

VDD

MCP624X

RGRF

RNVOUT

VDD/2

VIN

1µF

CLRL

0.1 µF

MCP6241/1R/1U/2/4

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

RL = 100 kΩ to VDD/2 and CL = 60 pF.

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: PSRR, CMRR vs.

Frequency.

FIGURE 2-3: Input Bias Current at +85°C.

FIGURE 2-4: CMRR, PSRR vs. Ambient

Temperature.

FIGURE 2-5: Open-Loop Gain, Phase vs.

Frequency.

FIGURE 2-6: Input Bias Current at

+125°C.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provide d for informational purposes only. The performance characteristics listed here in

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified pow er supply range) and therefore outside the warranted range.

10%

12%

14%

16%

18%

20%

-5

-4

-3

-2

-1

Input Offset Voltage (mV)

Percentage of Occurrences

630 Samples

VCM = VSS

100

110

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

PSRR, CMRR (dB)

10 1k 10k 100k100

PSRR+

PSRR-

CMRR

10%

15%

20%

25%

Input Bias Current (pA)

Percentage of Occurrences

180 Samples

VCM = VDD/2

TA = +85°C

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CMRR, PSRR (dB)

PSRR (VCM = VSS)

CMRR (VCM = -0.3V to +5.3V,

VDD = 5.0V)

-20

100

120

1.E-

1.E+

Frequency (Hz)

Open-Loop Gain (dB)

-210

-180

-150

-120

-90

-60

-30

Open-Loop Phase (°)

RL = 10.0 kΩ

VCM = VDD/2

0.1 1 10 100 1k 10k 100k 1M 10M

Gain

Phase

10%

15%

20%

25%

30%

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Input Bias Current (nA)

Percentage of Occurrences

180 Samples

VCM = VDD/2

TA = +125°C

MCP6241/1R/1U/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

RL = 100 kΩ to VDD/2 and CL = 60 pF.

FIGURE 2-7: Input Noise Voltage Density

vs. Frequency.

FIGURE 2-8: Input Offset Voltage vs.

Common Mode Input Voltage at VDD = 1.8V.

FIGURE 2-9: Input Offset Voltage vs.

Common Mode Input Voltage at VDD = 5.5V.

FIGURE 2-10: Input Offset Voltage Drift.

FIGURE 2-11: Input Offset Voltage vs.

Output Voltage.

FIGURE 2-12: Output Short-Circuit Current

vs. Ambient Temperature.

100

1,000

10,000

1.E-01 1.E+0

1.E+0

Frequency (Hz)

Input Noise Voltage Density

(nV/√Hz)

0.1 100 1k 10k 100k101

-300

-200

-100

100

200

300

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

Common Mode Input Voltage (V)

Input Offset Voltage (µV)

VDD = 1.8V

TA = -40°C

TA = +25°C

TA = +85°C

= +125°C

-200

-100

100

200

300

400

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Offset Voltage (µV)

VDD

= 5.5

TA = -40°C

TA = +25°C

TA = +85°C

= +125°C

10%

12%

14%

16%

18%

20%

-12

-10

-8

-6

-4

-2

Input Offset Voltage Drift (µV/°C)

Percentage of Occurrences

628 Samples

VCM = VSS

TA = -40°C to +125°C

300

350

400

450

500

550

600

650

700

0.00.51.01.52.02.53.03.54.04.55.05.5

Output Voltage (V)

Input Offset Voltage (µV)

VDD = 1.8V

VCM = VSS

VDD = 5.5V

-35

-30

-25

-20

-15

-10

-5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Short Circuit Current (mA)

TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

+ISC

-ISC

MCP6241/1R/1U/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

RL = 100 kΩ to VDD/2 and CL = 60 pF.

FIGURE 2-13: Slew Rate vs. Ambient

Temperature.

FIGURE 2-14: Output Voltage Headroom

vs. Output Current Magnitude.

FIGURE 2-15: Maximum Output Voltage

Swing vs. Frequency.

FIGURE 2-16: Small-Signal, Non-Inverting

Pulse Response.

FIGURE 2-17: Large-Signal, Non-Inverting

Pulse Response.

FIGURE 2-18: Quiescent Current vs.

Power Supply Voltage.

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

-50-250 255075100125

Ambient Temperature (°C)

Slew Rate (V/µs)

Falling Edge

Rising Edge

VDD = 1.8V

VDD = 5.5V

100

1,000

1.E-02 1.E-01 1.E+00 1.E+01

Output Current Magnitude (A)

Output Voltage Headroom

(mV)

VDD – VOH

10m1m

VOL – VSS

100µ10µ

0.1

1.E+03 1.E+04 1.E+05 1.E+06

Frequency (Hz)

Output Voltage Swing (VP-P)

VDD = 5.5V

VDD = 1.8V

1k 10k 100k 1M

Time (1 µs/div)

Output Voltage (10 mV/div)

G = +1 V/V

RL = 10 kΩ

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Time (10 µs/div)

Output Voltage (V)

VDD = 5.0V

G = +1 V/V

0.00.51.01.52.02.53.03.54.04.55.05.5

Power Supply Voltage (V)

Quiescent Current

per Amplifier (µA)

VCM = 0.9VDD

TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

MCP6241/1R/1U/2/4

Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,

RL = 100 kΩ to VDD/2 and CL = 60 pF.

FIGURE 2-19: Measured Input Current vs.

Input Voltage (below VSS).

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Input Current Magnitude (A)

+125°C

+85°C

+25°C

-40°C

10m

100µ

10µ

1µ

100n

10n

100p

10p

MCP6241/1R/1U/2/4

3.0 PIN DESCRIPTIONS

Description s of the pi ns are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).

TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS

TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS

3.1 Analog Outputs

The output pins are low-impedance voltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs are high-

impedance CMOS inputs with low bias currents.

3.3 Power Supply (VSS and VDD)

The positive power supply (VDD) is 1.8V to 5.5V higher

than the negative power supply (VSS). For normal

operation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need bypass capacitors.

3.4 Exposed Thermal Pad (EP)

There is an internal ele ctrical connection between the

Exposed Thermal Pad (EP) and the VSS pin; they must

be connected to the same potential on the Printed

Circuit Board (PCB).

MCP6241 MCP6241R MCP6241U

Symbol Description

DFN MSOP, PDIP,

SOIC SOT-23-5 SOT-23-5 SOT-23-5,

SC-70

6611 4V

OUT Analog Output

2244 3V

IN– Inverting Input

3333 1V

IN+ Non-inverting Input

7752 5V

DD Positive Power Supply

4425 2V

SS Negative Power Supply

1, 5, 8 1, 5, 8 — — — NC No Internal Connection

9————EP

Exposed Thermal Pad (EP);

must be connected to VSS.

MCP6242 MCP6244

Symbol Description

MSOP, PDIP, SOIC PDIP, SOIC, TSSOP

11V

OUTA Analog Output (op amp A)

22V

INA– Inverting Input (op amp A)

33V

INA+ Non-inverting Input (op amp A)

84V

DD Positive Power Supply

55V

INB+ Non-inverting Input (op amp B)

66V

INB– Inverting Input (op amp B)

77V

OUTB Analog Output (op amp B)

—8V

OUTC Analog Output (op amp C)

—9V

INC– Inverting Input (op amp C)

—10V

INC+ Non-inverting Input (op amp C)

411V

SS Negative Power Supply

—12V

IND+ Non-inverting Input (op amp D)

—13V

IND– Inverting Input (op amp D)

—14V

OUTD Analog Output (op amp D)

MCP6241/1R/1U/2/4

NOTES:

MCP6241/1R/1U/2/4

4.0 APPLICATION INFORMATION

The MCP6241/1R/1U/2/4 family of op amps is manu-

factured using Microchip’s state-of-the-art CMOS

process and is specifically designed for low-power and

general-purpose applications. The low supply voltage,

low quiescent current and wide bandwidth makes the

MCP6241/1R/1U/2/4 ideal for battery-powered

applications.

4.1 Rail-to-Rail Inputs

4.1.1 PHASE REVERSAL

The MCP6241/1R/1U/2/4 op amp is designed to

prevent phase reversal when the input pins exceed the

supply voltages. Figure 4-1 shows the input voltage

exceeding the supply voltage without any phase

reversal.

FIGURE 4-1: The MCP6241/1R/1U/2/4

Show No Phase Reversa l.

4.1.2 INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-2. This structure was chosen to

protect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

FIGURE 4-2: Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these op amps, the circuit they are in must limit the

currents and voltages at the VIN+ and VIN– pins (see

Absolute Maximum Ratings † at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-3

shows the recommended approach to protecting these

inputs. The internal ESD diodes preven t the input pins

(VIN+ and VIN–) from going too far below ground, and

the resistors R1 and R2 limit the possible current drawn

out of the input pins. Diodes D1 and D2 prevent the

input pins (VIN+ and VIN–) from going too far above

VDD, and dump any currents onto VDD. When

implemented as shown, resistors R1 and R2 also limit

the current through D1 and D2.

FIGURE 4-3: Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of

resistors R1 and R2. In this case, current through the

diodes D1 and D2 needs to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN–) should be very small.

-1

Time (1 ms/div)

Input, Output Voltage (V)

VOUT

VIN

VDD = 5.0V

G = +2 V/V

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage Bond

Pad VIN–

MCP624X

VDD

R1>VSS – (minimum expected V1)

2mA

R2>VSS – (minimum expected V2)

2mA

V2R2

MCP6241/1R/1U/2/4

A significant amount of current can flow out of the

inputs when the common mode voltage (VCM) is below

ground (VSS); see Figure 2-19. Applications that are

high impedance may need to limit the use able voltage

range.

4.1.3 NORMAL OPER ATION

The input stage of the MCP6241/1R/1U/2/4 op amps

use two differential CMOS input stages in parallel. One

operates at low common mode input voltage (VCM),

while the other operates at high VCM. WIth this topol-

ogy, the device operates with VCM up to 0.3V above

VDD and 0.3V below VSS.

4.2 Rail-to-Rail Output

The output voltage range of the MCP6241/1R/1U/2/4

op amps is VDD –35mV (maximum) and V

SS +35mV

(minimum) when RL=10kΩ is connected to VDD/2 and

VDD = 5.5V. Refer to Figure 2-14 for more information.

4.3 Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage-feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produce s gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity-gain buffer (G = +1) is the most

sensitive to capacitive loads, but all gains show the

same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 70 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-4) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-4: Output Resistor, RISO

stabilizes large capacitive loads.

Figure 4-5 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

signal gain are equal. For inverting gains, GN is

1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).

FIGURE 4-5: Recommended RISO V alues

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Evaluation on the bench and

simulations with the MCP6241/1R/1U/2/4 SPICE

macro model are very helpful. Modify RISO’s valu e until

the response is reasonable.

4.4 Supply Bypass

With this op amp, the power supply pin (VDD for

single-supply) should have a local bypass capacitor

(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-

frequency performance. It can use a bulk capacitor

(i.e., 1 µF or larger) within 100 mm to provide large,

slow currents. This bulk capacitor can be shared with

other nearby analog parts.

4.5 Unused Op Amps

An unused op amp in a quad package (MCP6244)

should be configured as shown in Figure 4-6. Both

circuits prevent the output from toggling and causing

crosstalk. Circuit A can use any reference voltage

between the supplies, provid es a buffered DC voltage,

and minimizes the supply current draw of the unused

op amp. Circuit B minimizes the number of

components, but may draw a little more supply current

for the unuse d op amp .

FIGURE 4-6: Unused Op Amps.

VIN

RISO VOUT

MCP624X

–

1.E+02

1.E+03

1.E+04

1.E+01 1.E+02 1.E+03 1.E+04

Normalized Load Capacitance; CL/GN (F)

Recommended RISO (Ω)

10p 100p 1n 10n

10k

100

GN = +1 V/V

GN ≥ +2 V/V

VDD

¼ MCP6244 (A) ¼ MCP6244 (B)

VDD

VREF

VREF VDD R2

R1R2

------------------

⋅=

MCP6241/1R/1U/2/4

4.6 PCB Surface Leakage

In applications where low input bias current is critical,

PCB (printed circuit board) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6241/1R/1U/2/4 family’s bias current at 25°C

(1 pA, typical).

The easiest way to reduce surface leaka ge is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-7.

FIGURE 4-7: Example Guard Ring Layout

for Inverting Gain.

1. Non-inverting Gain and Unity-Gain Buffer:

a. Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

b. Connect the guard ring to the inverting input

pin (VIN–). This biases the guard ring to the

common mode input voltage.

2. Inverting Gain and Transimpedance Amplifiers

(convert current to voltage, such as photo

detectors):

a. Connect the guard ring to th e non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., VDD/2 or ground).

b. Conne ct the inverting pin (VIN–) to the input

with a wire that does not touch the PCB

surface.

4.7 Application Circuits

4.7.1 MATCHING THE IMPEDANCE AT

THE INPUTS

To minimize the effect of offset voltage in an amplifier

circuit, the impedances at the inverting and non-

inverting inputs need to be matched. This is done by

choosing the circuit resistor values so that the total

resistance at each input is the same. Figure 4-8 shows

a summing amplifier circuit.

FIGURE 4-8: Summing Amplifier Circuit.

To match the inputs, set all voltage sources to ground

and calculate the total resistance at the input nodes. In

this summing amplifier circuit, the resistance at the

inverting input is calculated by setting VIN1, VIN2 and

VOUT to ground. In this case, RG1, RG2 and RF are in

parallel. The total resistance at the inverting input is:

At the non-inverting input, VDD is the only voltage

source. When VDD is set to ground, both RX and RY are

in parallel. The total resistance at the non-inverting

input is:

To minimize offset voltage and increase circuit

accuracy, the resistor values need to meet the

condition:

Guard Rin g

VSS

VIN-V

IN+

MCP6241 VOUT

VIN2

–

VIN1

RG2

RG1

VDD

RVIN–1

RG1

--------- 1

RG2

--------- 1

------++

⎝⎠

⎛⎞

---------------------------------------------=

Where:

RVIN– = total resist ance at the inverting input

RVIN+1

------ 1

------+

⎝⎠

⎛⎞

------------------------- RZ

Where:

RVIN+ = total resistance at the inverting

input

RVIN+RVIN–=

MCP6241/1R/1U/2/4

4.7.2 COMPENSATING FOR THE

PARASITIC CAPACITANCE

In analog circuit design, the PCB parasitic capacitance

can compromise the circuit behavior; Figure 4-9 shows

a typical scenario. If the input of an amplifier sees

parasitic capacitance of several picofarad (CPARA,

which includes the common mode capacitance of 6 pF,

typical) and large RF and RG, the frequency response

of the circuit will include a zero. This parasitic zero

introduces gain peaking and can cause circuit

instability.

FIGURE 4-9: Effect of Parasitic

Capacitance at the Input.

One solution is to use smaller resistor values to push

the zero to a higher frequency. Another solution is to

compensate by introducing a pole at the point at which

the zero occurs. This can be done by adding CF in

parallel with the feedback resistor (RF). CF needs to be

selected so that the ratio CPARA:CF is equal to the ratio

of RF:RG.

VOUT

VDC

–

VAC

RGRF

CPARA

CFCPARA RG

-------

•=

MCP624X

MCP6241/1R/1U/2/4

5.0 DESIGN AIDS

Microchip provides the basic design tools needed for

the MCP6241/1R/1U/2/4 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for the MCP6241/1R/

1U/2/4 op amps is available on the Microchip web site

at www .microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear

region of operation over the temperature range. See

the model file for information on its capabilities.

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

5.2 Mindi™ Circuit Designer &

Simulator

Microchip’s Mindi™ Circuit Designer & Simulator aids

in the design of various circuits useful for active filter,

amplifier and power-management applications. It is a

free online circuit designer & simulator available from

the Microchip web site at www.microchip.com/mindi.

This interactive circuit designer & simulator enables

designers to quickly generate circuit diagrams, simu-

late circuits. Circuits developed using the Mindi Circuit

Designer & Simulator can be downloaded to a personal

computer or workstation.

5.3 Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps semiconductor

professionals efficiently identify Microchip devices that

fit a particular design requirement. Available at no cost

from the Microchip web site at www.microchip.com/

maps, the MAPS is an overall selection tool for

Microchip’s product portfolio that includes Analog,

Memory, MCUs and DSCs. Using this tool you can

define a filter to sort features for a parametric search of

devices and export side-by-side technical comparison

reports. Helpful links are also provided for Data sheets,

Purchase, and Sampling of Microchip parts.

5.4 Analog Demonstration and

Evaluation Boards

Microchip offers a broad spectrum of Analog Demon-

stration and Evaluation Boards that are designed to

help you achieve faster time to market. For a complete

listing of these boards and their corresponding user ’s

guides and technical information, visit the Microchip

web site at www.microchip.com/analogtools.

Two of our boards that are especially useful are:

•P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP

Evaluation Board

•P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP

Evaluation Board

5.5 Application Notes

The following Microchip Application Notes are avail-

able on the Microchip web site at www.microchip. com/

appnotes and are recommended a s supplemental ref-

erence resources.

ADN003: “Select the Right Operational Amplifier for

your Filtering Circuits”, DS21821

AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

AN723: “Operational Amplifier AC Specifications and

Applications”, DS00723

AN884: “Driving Capacitive Loads With Op Amps”,

DS00884

AN990: “Analog Sensor Conditioning Circuits – An

Overview”, DS00990

These application notes and others are listed in the

design guide:

“Signal Chain Design Guide”, DS21825

MCP6241/1R/1U/2/4

NOTES:

MCP6241/1R/1U/2/4

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

123

5-Lead SOT-23 (MCP6241, MCP6241R, MCP6241U) Example:

XXNN

123

BQ25

Device Code

MCP6241 BQNN

MCP6241RBRNN

MCP6241U BSNN

Note: Applies to 5-Lead SOT-23.

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil)

MCP6242

E/P ^^256

0834

8-Lead MSOP Example:

XXXXXX

YWWNNN

6242E

834256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

5-Lead SC-70 (MCP6241U Only) Example:

XXNN AT25

8-Lead DFN (2x3) (MCP6241 Only) Example:

XXX

YWW

AER

834

Example:

MCP6242

E/P256

0818 OR

MCP6241/1R/1U/2/4

Package Marking Information (Continued)

14-Lead PDIP (300 mil) (MCP6244)Example:

14-Lead TSSOP (MCP6244)Example:

14-Lead SOIC (150 mil) (MCP6244)Example:

XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXX

YYWWNNN

XXXXXXXX

YYWW

NNN

MCP6244

0546256

6244E

0546

256

XXXXXXXXXX MCP6244

0546256

E/P^^

E/SL^^

8-Lead SOIC (150 mil)

XXXXXXXX

XXXXYYWW

NNN

MCP6242E

SN^^ 0834

256

Example:

MCP6242

E/SN0818

256 OR

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EXPOSED PAD

NOTE 1

A3 A1

NOTE 2

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 6LJQLILFDQW&KDUDFWHULVWLF

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 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

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1XPEHURI3LQV 1 

3LWFK H %6&

7RSWR6HDWLQJ3ODQH $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

%DVHWR6HDWLQJ3ODQH $  ± ±

6KRXOGHUWR6KRXOGHU:LGWK (   

0ROGHG3DFNDJH:LGWK (   

2YHUDOO/HQJWK '   

7LSWR6HDWLQJ3ODQH /   

/HDG7KLFNQHVV F   

8SSHU/HDG:LGWK E   

/RZHU/HDG:LGWK E   

2YHUDOO5RZ6SDFLQJ H% ± ± 

NOTE 1

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP6241/1R/1U/2/4

/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@

1RWHV

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 6LJQLILFDQW&KDUDFWHULVWLF

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 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

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5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $  ± ±

6WDQGRII



$  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

&KDPIHURSWLRQDO K  ± 

)RRW/HQJWK /  ± 

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

0ROG'UDIW$QJOH7RS  ± 

0ROG'UDIW$QJOH%RWWRP  ± 

NOTE 1

12 3

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP6241/1R/1U/2/4

/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

MCP6241/1R/1U/2/4

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1RWHV

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 6LJQLILFDQW&KDUDFWHULVWLF

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%DVHWR6HDWLQJ3ODQH $  ± ±

6KRXOGHUWR6KRXOGHU:LGWK (   

0ROGHG3DFNDJH:LGWK (   

2YHUDOO/HQJWK '   

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/HDG7KLFNQHVV F   

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2YHUDOO5RZ6SDFLQJ H% ± ± 

NOTE 1

123

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP6241/1R/1U/2/4

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1RWHV

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 6LJQLILFDQW&KDUDFWHULVWLF

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

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1XPEHURI3LQV 1 

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0ROGHG3DFNDJH7KLFNQHVV $  ± ±

6WDQGRII $  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

&KDPIHURSWLRQDO K  ± 

)RRW/HQJWK /  ± 

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

0ROG'UDIW$QJOH7RS  ± 

0ROG'UDIW$QJOH%RWWRP  ± 

NOTE 1

123

hα

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP6241/1R/1U/2/4

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

MCP6241/1R/1U/2/4

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1RWHV

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 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

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3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

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2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK (   

0ROGHG3DFNDJH/HQJWK '   

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

NOTE 1

L1 L

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

MCP6241/1R/1U/2/4

NOTES:

MCP6241/1R/1U/2/4

APPENDIX A: REVISION HISTORY

Revision D (October 2008)

The following is the list of modificatio ns:

1. Changed Heading “Available Tools” to “Design

Aids”.

2. Design Aids: Name change for Mindi Simulator

Tool.

3. Package Types: Added DFN to MCP6231

Device.

4. Absolute Maximum Ratings: Numerous

changes in this section.

5. Updated notes to Section 1.0 “Electrical Char-

acteristics”.

6. Added Figure 2-19.

7. Numerous changes to Section 3.0 “Pin

Descriptions”.

8. Added Section 4.1.1 “Phase Reversal”,

Section 4.1.2 “Input Voltage and Current

Limits”, and Section 4.1.3 “Normal Opera-

tion”.

9. Replaced Section 5.0 “Design Aids” with

additional information.

10. Added 2x3 DFN package to Section 6.0 “Pack-

aging Information” and updated Package Out-

line Drawings.

1 1. Added 2x3 DFN package to Product Identifica-

tion System section.

Revision C (March 2005)

The following is the list of modificatio ns:

1. Added the MCP6244 quad op amp.

2. Re-compensated parts. Specifications that

change are: Gain Bandwidth Product (BWP)

and Phase Margin (PM) in AC Electrical

Characteristics table.

3. Corrected plots in Section 2.0 “Typical Perfor-

mance Curves”.

4. Added Section 3.0 “Pin Descriptions”.

5. Added new SC-70 package markings. Added

PDIP-14, SOIC-14, and TSSOP-14 packages

and corrected package marking information

(Section 6.0 “Packaging Information”).

6. Added Appendix A: “Revision History”.

Revision B (August 2004)

Undocumented changes.

Revision A (March 2004)

• Original Release of this Document.

MCP6241/1R/1U/2/4

NOTES:

MCP6241/1R/1U/2/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP6241: Single Op Amp (MSOP, PDIP, SOIC)

MCP6241T: Single Op Amp (Tape and Reel)

(MSOP, SOIC, SOT-23)

MCP6241RT: Single Op Amp (Tape and Reel)

(SOT-23)

MCP6241UT: Single Op Amp (Tape and Reel)

(SC-70, SOT-23)

MCP6242: Dual Op Amp

MCP6242T: Dual Op Amp (Tape and Reel)

(MSOP, SOIC)

MCP6244: Quad Op Amp

MCP6244T: Quad Op Amp (Tape and Reel)

(SOIC, TSSOP)

Temperature Range: E = -40° C to +125° C

Package: LT = Plastic Package (SC-70), 5-lead (MCP6241U only)

MC = Plastic Dual Flat, No Lead (DFN), 8-lead,

(MCP6241 only)

MS = Plastic Micro Small Outline (MSOP), 8-lead

P = Plastic DIP (300 mil Body), 8-lead, 14-lead

OT = Plastic Small Outline Transistor (SOT-23), 5-lead

(MCP6241, MCP6241R, MCP6241U)

SN = Plastic SOIC (150 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

ST = Plastic TSSOP (4.4 mil Body), 14-lead

PART NO. -X /XX

PackageTemperature

Range

Device

Examples:

a) MCP6241-E/SN: Extended Temp.,

8LD SOIC package.

b) MCP6241-E/MS: Extended Temp.,

8LD MSOP package.

c) MCP6241-E/P: Extended Temp.,

8LD PDIP package.

d) MCP6241-E/MC: Extended Temp.,

8LD DFN package.

e) MCP6241RT-E/OT: Tape and Reel,

Extended Temp.,

5LD SOT-23 package

f) MCP6241UT-E/OT: Tape and Reel,

Extended Temp.,

5LD SOT-23 package.

g) MCP6241UT-E/LT: Tape and Reel,

Extended Temp.,

5LD SC-70 package.

a) MCP6242-E/SN: Extended Temp.,

8LD SOIC package.

b) MCP6242-E/MS: Extended Temp.,

8LD MSOP package.

c) MCP6242-E/P: Extended Temp.,

8LD PDIP package.

d) MCP6242T-E/SN: Tape and Reel,

Extended Temp.,

8LD SOIC package.

a) MCP6244-E/P: Extended Temp.,

14LD PDIP package.

b) MCP6244-E/SL: Extended Temp.,

14LD SOIC package.

c) MCP6244-E/ST: Extended Temp.,

14LD TSSOP

package.

d) MCP6244T-E/SL: Tape and Reel,

Extended Temp.,

14LD SOIC package.

e) MCP6244T-E/ST: Tape and Reel,

Extended Temp.,

14LD TSSOP

package.

Tape and Reel

Alternate Pinout

and/or

MCP6241/1R/1U/2/4

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defen d, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt a nd UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and

analog product s. In addition, Microchip ’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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01/02/08