MCP6241/1R/1U/2/4 50 A, 550 kHz Rail-to-Rail Op Amp Features Description * * * * * * The Microchip Technology Inc. MCP6241/1R/1U/2/4 operational amplifiers (op amps) provide wide bandwidth for the quiescent current. The MCP6241/1R/ 1U/2/4 has a 550 kHz gain bandwidth product and 68 (typical) phase margin. This family operates from a single supply voltage as low as 1.8V, while drawing 50 A (typical) quiescent current. In addition, the MCP6241/1R/1U/2/4 family supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. These op amps are designed in one of Microchip's advanced CMOS processes. Gain Bandwidth Product: 550 kHz (typical) Supply Current: IQ = 50 A (typical) Supply Voltage: 1.8V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in 5-pin SC-70 and SOT-23 packages Applications * * * * * * Automotive Portable Equipment Photodiode (Transimpedance) Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems Package Types MCP6241 VOUT 1 Design Aids VSS 2 SPICE Macro Models MindiTM Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes + * * * * * MCP6241 PDIP, SOIC, MSOP SOT-23-5 NC 1 VIN- 2 - 7 VDD 4 VIN- VIN+ 3 + 6 VOUT - VIN+ 3 8 NC VSS 4 MCP6241R SOT-23-5 5 NC MCP6242 PDIP, SOIC, MSOP 5 VSS VOUT 1 + VDD 2 Typical Application 5 VDD VOUTA 1 VINA_ 2 - VIN+ 3 4 VIN- VINA+ 3 8 VDD 7 VOUTB - + 6 VINB_ + - VSS 4 RG2 5 VINB+ VIN2 RG1 VIN1 RF MCP6244 PDIP, SOIC, TSSOP 5 VDD VIN+ 1 - RX MCP6241 + RZ + VDD RY MCP6241U SC-70-5, SOT-23-5 VSS 2 VOUT - VIN- 3 - + + - 13 VIND- 4 VOUT VINA+ 3 12 VIND+ MCP6241 2x3 DFN* VIN- 2 VIN+ 3 VSS 4 8 NC EP 9 14 VOUTD VINA- 2 VDD 4 NC 1 Summing Amplifier Circuit VOUTA 1 VINB+ 5 11 VSS VINB- 6 10 VINC+ - + +- 9 V - INC VOUTB 7 8 VOUTC 7 VDD 6 VOUT 5 NC * Includes Exposed Thermal Pad (EP); see Table 3-1. (c) 2008 Microchip Technology Inc. DS21882D-page 1 MCP6241/1R/1U/2/4 NOTES: DS21882D-page 2 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 1.0 ELECTRICAL CHARACTERISTICS VDD - VSS ........................................................................7.0V Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Analog Input Pins (VIN+, VIN-).....................2 mA See Section 4.1.2 "Input Voltage and Current Limits". Absolute Maximum Ratings Analog Inputs (VIN+, VIN-) ........ VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................30 mA Storage Temperature .................................. -65 C to +150C Maximum Junction Temperature (TJ)......................... .+150C ESD Protection On All Pins (HBM; MM) .............. 4 kV; 300V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 k to VDD/2 and VOUT VDD/2. Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS -5.0 -- +5.0 mV VCM = VSS Extended Temperature VOS -7.0 -- +7.0 mV TA= -40C to +125C, VCM = VSS (Note 1) VOS/TA -- 3.0 -- PSRR -- 83 -- dB IB -- 1.0 -- pA At Temperature IB -- 20 -- pA TA = +85C At Temperature IB -- 1100 -- pA TA = +125C Input Offset Current IOS -- 1.0 -- pA Common Mode Input Impedance ZCM -- 1013||6 -- ||pF Differential Input Impedance ZDIFF -- 1013||3 -- ||pF Common Mode Input Range VCMR VSS - 0.3 -- VDD + 0.3 V Common Mode Rejection Ratio CMRR 60 75 -- dB VCM = -0.3V to 5.3V, VDD = 5V AOL 90 110 -- dB VOUT = 0.3V to VDD - 0.3V, VCM = VSS -- VDD - 35 mV RL = 10 k, 0.5V Input Overdrive Input Offset Input Offset Drift with Temperature Power Supply Rejection V/C TA= -40C to +125C, VCM = VSS VCM = VSS Input Bias Current and Impedance Input Bias Current: Common Mode Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short-Circuit Current VOL, VOH VSS + 35 ISC -- 6 -- mA VDD = 1.8V ISC -- 23 -- mA VDD = 5.5V VDD 1.8 -- 5.5 V IQ 30 50 70 A Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: IO = 0, VCM = VDD - 0.5V The SC-70 package is only tested at +25C. (c) 2008 Microchip Technology Inc. DS21882D-page 3 MCP6241/1R/1U/2/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions GBWP -- 550 -- kHz Phase Margin PM -- 68 -- Slew Rate SR -- 0.30 -- V/s Input Noise Voltage Eni -- 10 -- VP-P Input Noise Voltage Density eni -- 45 -- nV/Hz f = 1 kHz Input Noise Current Density ini -- 0.6 -- fA/Hz f = 1 kHz AC Response Gain Bandwidth Product G = +1 V/V Noise f = 0.1 Hz to 10 Hz TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Extended Temperature Range TA -40 -- +125 C Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Thermal Resistance, 5L-SC70 JA -- 331 -- C/W Thermal Resistance, 5L-SOT-23 JA -- 256 -- C/W Thermal Resistance, 8L-DFN (2x3) JA -- 84.5 -- C/W Thermal Resistance, 8L-MSOP JA -- 206 -- C/W Thermal Resistance, 8L-PDIP JA -- 85 -- C/W Thermal Resistance, 8L-SOIC JA -- 163 -- C/W Thermal Resistance, 14L-PDIP JA -- 70 -- C/W Thermal Resistance, 14L-SOIC JA -- 120 -- C/W Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W (Note) Thermal Package Resistances Note: 1.1 The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-1 and Figure 1-2. The bypass capacitors are laid out according to the rules discussed in Section 4.6 "PCB Surface Leakage". VDD VDD/2 RN VDD VIN RN VOUT MCP624X 0.1 F 1 F CL VOUT MCP624X CL VDD/2 RG 0.1 F 1 F RL RF VIN RG RL RF VL FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. VL FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. DS21882D-page 4 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 90 85 PSRR (VCM = VSS) 80 75 CMRR (VCM = -0.3V to +5.3V, VDD = 5.0V) 5 -50 -25 Input Offset Voltage (mV) FIGURE 2-4: Temperature. 110 Open-Loop Gain (dB) 40 30 20% 15% 10% 5% 42 36 30 24 18 0% 12 -150 0 -180 FIGURE 2-5: Frequency. 180 Samples VCM = VDD/2 TA = +85C 6 20 -20 -210 0.1 1.E+ 1 1.E+ 10 1.E+ 100 1.E+ 1k 1.E+ 10k 100k 1M 10M 1.E1.E+ 1.E+ 1.E+ 01 00 01 Frequency 02 03 (Hz) 04 05 06 07 100k 1.E+05 PSRR, CMRR vs. 30% 25% 20% Input Bias Current at +85C. (c) 2008 Microchip Technology Inc. Open-Loop Gain, Phase vs. 180 Samples VCM = VDD/2 TA = +125C 15% 10% 5% 0% Input Bias Current (nA) Input Bias Current (pA) FIGURE 2-3: -120 0.6 25% 0 Percentage of Occurrences FIGURE 2-2: Frequency. 1k 10k 1.E+03 1.E+04 Frequency (Hz) 40 0.0 100 1.E+02 Percentage of Occurrences 20 10 1.E+01 -90 Phase 2.0 50 -30 1.8 60 0 -60 60 1.0 PSRR+ 80 0.4 70 RL = 10.0 k VCM = VDD/2 Gain 0.8 CMRR 80 100 0.2 PSRR, CMRR (dB) PSRR- 90 125 CMRR, PSRR vs. Ambient 120 100 100 1.6 Input Offset Voltage. 1.4 FIGURE 2-1: 0 25 50 75 Ambient Temperature (C) 1.2 4 3 2 1 0 -1 -2 -3 70 Open-Loop Phase () CMRR, PSRR (dB) 630 Samples VCM = VSS -4 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -5 Percentage of Occurrences Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. FIGURE 2-6: +125C. Input Bias Current at DS21882D-page 5 MCP6241/1R/1U/2/4 FIGURE 2-7: vs. Frequency. Input Noise Voltage Density FIGURE 2-10: VDD = 1.8V 200 100 0 TA = -40C TA = +25C TA = +85C TA = +125C -100 -200 500 450 400 100 TA = -40C TA = +25C TA = +85C TA = +125C -100 Common Mode Input Voltage (V) FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -200 DS21882D-page 6 12 10 8 6 4 VDD = 5.5V VDD = 1.8V 350 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Short Circuit Current (mA) 200 0 2 550 FIGURE 2-11: Output Voltage. VDD = 5.5V 300 0 600 Output Voltage (V) FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. 400 -2 VCM = VSS 300 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -300 -4 Input Offset Voltage Drift. 650 Common Mode Input Voltage (V) Input Offset Voltage (V) -6 Input Offset Voltage Drift (V/C) 700 300 Input Offset Voltage (V) -8 10 0.1 1.E+0 1 10 100 1.E+0 1k 1.E+0 10k 1.E+0 100k 1.E-01 1.E+0 1.E+0 Frequency 0 1 2 (Hz) 3 4 5 628 Samples VCM = VSS TA = -40C to +125C -10 100 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -12 1,000 Percentage of Occurrences 10,000 Input Offset Voltage (V) Input Noise Voltage Density (nV/Hz) Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. 35 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 Input Offset Voltage vs. +ISC TA = +125C TA = +85C TA = +25C TA = -40C -ISC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. 0.50 Slew Rate (V/s) 0.40 Falling Edge 0.35 0.30 0.25 0.20 VDD = 1.8V 0.15 Rising Edge 0.10 -50 -25 FIGURE 2-13: Temperature. 0 25 50 75 100 Ambient Temperature (C) 125 Time (1 s/div) Slew Rate vs. Ambient FIGURE 2-16: Pulse Response. VDD - VOH VOL - VSS 10 1 10 1.E-02 3.5 3.0 2.5 2.0 1.5 1.0 100 1m 1.E-01 1.E+00 Output Current Magnitude (A) 10m 1.E+01 0.0 Time (10 s/div) FIGURE 2-17: Pulse Response. 80 10 70 Quiescent Current per Amplifier (A) Output Voltage Swing (VP-P ) VDD = 5.0V G = +1 V/V 4.5 4.0 0.5 FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. VDD = 5.5V 1 VDD = 1.8V Large-Signal, Non-Inverting VCM = 0.9VDD 60 50 40 30 20 10 0.1 1k 1.E+03 Small-Signal, Non-Inverting 5.0 Output Voltage (V) Output Voltage Headroom (mV) 1,000 100 G = +1 V/V RL = 10 k Output Voltage (10 mV/div) VDD = 5.5V 0.45 TA = TA = TA = TA = +125C +85C +25C -40C 0 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. (c) 2008 Microchip Technology Inc. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. DS21882D-page 7 MCP6241/1R/1U/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. Input Current Magnitude (A) 1.E-02 10m 1.E-03 1m 1.E-04 100 1.E-05 10 1.E-06 1 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 +125C +85C +25C -40C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). DS21882D-page 8 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6241 MCP6241U DFN MSOP, PDIP, SOIC SOT-23-5 SOT-23-5 SOT-23-5, SC-70 6 6 1 1 4 2 2 4 4 3 3 3 3 7 7 5 4 4 2 1, 5, 8 1, 5, 8 9 -- TABLE 3-2: 3 VIN- Inverting Input 1 VIN+ Non-inverting Input 2 5 VDD Positive Power Supply 5 2 VSS Negative Power Supply -- -- -- NC No Internal Connection -- -- -- EP Exposed Thermal Pad (EP); must be connected to VSS. PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MSOP, PDIP, SOIC PDIP, SOIC, TSSOP Symbol Description 1 1 VOUTA Analog Output (op amp A) 2 2 VINA- Inverting Input (op amp A) 3 3 VINA+ Non-inverting Input (op amp A) 8 4 VDD Positive Power Supply 5 5 VINB+ Non-inverting Input (op amp B) 6 6 VINB- Inverting Input (op amp B) 7 7 VOUTB Analog Output (op amp B) -- 8 VOUTC Analog Output (op amp C) -- 9 VINC- Inverting Input (op amp C) -- 10 VINC+ Non-inverting Input (op amp C) 4 11 VSS -- 12 VIND+ Non-inverting Input (op amp D) -- 13 VIND- Inverting Input (op amp D) -- 14 VOUTD Analog Output (op amp D) Analog Outputs The output pins are low-impedance voltage sources. Analog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 Description Analog Output MCP6244 3.2 Symbol VOUT MCP6242 3.1 MCP6241R Power Supply (VSS and VDD) The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. (c) 2008 Microchip Technology Inc. Negative Power Supply Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. 3.4 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). DS21882D-page 9 MCP6241/1R/1U/2/4 NOTES: DS21882D-page 10 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 4.0 APPLICATION INFORMATION The MCP6241/1R/1U/2/4 family of op amps is manufactured using Microchip's state-of-the-art CMOS process and is specifically designed for low-power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6241/1R/1U/2/4 ideal for battery-powered applications. 4.1 Rail-to-Rail Inputs 4.1.1 The MCP6241/1R/1U/2/4 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. Input, Output Voltage (V) VOUT 5 4 VIN+ Bond Pad Bond V - IN Pad Input Stage VSS Bond Pad PHASE REVERSAL 6 VDD Bond Pad VDD = 5.0V G = +2 V/V VIN 3 2 1 0 -1 FIGURE 4-2: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the VIN+ and VIN- pins (see Absolute Maximum Ratings at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-3 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. Time (1 ms/div) VDD FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal. 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-2. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. D1 D2 V1 R1 MCP624X V2 R2 R3 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > FIGURE 4-3: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, current through the diodes D1 and D2 needs to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. (c) 2008 Microchip Technology Inc. DS21882D-page 11 MCP6241/1R/1U/2/4 4.1.3 NORMAL OPERATION 1.E+03 1k The input stage of the MCP6241/1R/1U/2/4 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM), while the other operates at high VCM. WIth this topology, the device operates with VCM up to 0.3V above VDD and 0.3V below VSS. 4.2 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage-feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, but all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 70 pF when G = +1), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. - VIN MCP624X + GN = +1 V/V GN +2 V/V 100 1.E+02 10p 100p 1n 10n 1.E+01 1.E+02 1.E+03 1.E+04 Normalized Load Capacitance; CL/GN (F) FIGURE 4-5: Recommended RISO Values for Capacitive Loads. Rail-to-Rail Output The output voltage range of the MCP6241/1R/1U/2/4 op amps is VDD - 35 mV (maximum) and VSS + 35 mV (minimum) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-14 for more information. 4.3 1.E+04 10k Recommended R ISO () A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); see Figure 2-19. Applications that are high impedance may need to limit the useable voltage range. RISO VOUT CL After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Evaluation on the bench and simulations with the MCP6241/1R/1U/2/4 SPICE macro model are very helpful. Modify RISO's value until the response is reasonable. 4.4 Supply Bypass With this op amp, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good highfrequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts. 4.5 Unused Op Amps An unused op amp in a quad package (MCP6244) should be configured as shown in Figure 4-6. Both circuits prevent the output from toggling and causing crosstalk. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage, and minimizes the supply current draw of the unused op amp. Circuit B minimizes the number of components, but may draw a little more supply current for the unused op amp. 1/4 MCP6244 (A) 1/4 MCP6244 (B) VDD FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-5 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the signal gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). R1 VDD VDD R2 R2 V REF = V DD -----------------R1 + R2 FIGURE 4-6: DS21882D-page 12 VREF Unused Op Amps. (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 4.6 PCB Surface Leakage 4.7 In applications where low input bias current is critical, PCB (printed circuit board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6241/1R/1U/2/4 family's bias current at 25C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. VIN- VIN+ Application Circuits 4.7.1 MATCHING THE IMPEDANCE AT THE INPUTS To minimize the effect of offset voltage in an amplifier circuit, the impedances at the inverting and noninverting inputs need to be matched. This is done by choosing the circuit resistor values so that the total resistance at each input is the same. Figure 4-8 shows a summing amplifier circuit. RG2 VIN2 RG1 VIN1 RF VDD VSS - RX MCP6241 VOUT + RY Guard Ring FIGURE 4-7: for Inverting Gain. 1. 2. Example Guard Ring Layout Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. RZ FIGURE 4-8: Summing Amplifier Circuit. To match the inputs, set all voltage sources to ground and calculate the total resistance at the input nodes. In this summing amplifier circuit, the resistance at the inverting input is calculated by setting VIN1, VIN2 and VOUT to ground. In this case, RG1, RG2 and RF are in parallel. The total resistance at the inverting input is: 1 R VIN - = -------------------------------------------1 + ----1- 1 + -------- --------R R R G1 G2 F Where: RVIN- = total resistance at the inverting input At the non-inverting input, VDD is the only voltage source. When VDD is set to ground, both RX and RY are in parallel. The total resistance at the non-inverting input is: 1 R VIN + = ------------------------ + RZ 1- 1- + ---- ----R X RY Where: RVIN+ = total resistance at the inverting input To minimize offset voltage and increase circuit accuracy, the resistor values need to meet the condition: R VIN + = R VIN - (c) 2008 Microchip Technology Inc. DS21882D-page 13 MCP6241/1R/1U/2/4 4.7.2 COMPENSATING FOR THE PARASITIC CAPACITANCE In analog circuit design, the PCB parasitic capacitance can compromise the circuit behavior; Figure 4-9 shows a typical scenario. If the input of an amplifier sees parasitic capacitance of several picofarad (CPARA, which includes the common mode capacitance of 6 pF, typical) and large RF and RG , the frequency response of the circuit will include a zero. This parasitic zero introduces gain peaking and can cause circuit instability. + VAC MCP624X - RG VOUT RF VDC CPARA CF RG C F = C PARA * ------RF FIGURE 4-9: Effect of Parasitic Capacitance at the Input. One solution is to use smaller resistor values to push the zero to a higher frequency. Another solution is to compensate by introducing a pole at the point at which the zero occurs. This can be done by adding CF in parallel with the feedback resistor (RF). CF needs to be selected so that the ratio CPARA:CF is equal to the ratio of RF:RG . DS21882D-page 14 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6241/1R/1U/2/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6241/1R/ 1U/2/4 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 MindiTM Circuit Designer & Simulator Microchip's MindiTM Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.3 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. (c) 2008 Microchip Technology Inc. 5.4 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/analogtools. Two of our boards that are especially useful are: * P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board * P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.5 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/ appnotes and are recommended as supplemental reference resources. ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 AN723: "Operational Amplifier AC Specifications and Applications", DS00723 AN884: "Driving Capacitive Loads With Op Amps", DS00884 AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 These application notes and others are listed in the design guide: "Signal Chain Design Guide", DS21825 DS21882D-page 15 MCP6241/1R/1U/2/4 NOTES: DS21882D-page 16 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC-70 (MCP6241U Only) Example: XXNN AT25 5-Lead SOT-23 (MCP6241, MCP6241R, MCP6241U) 5 4 XXNN 1 2 3 Device Code MCP6241 BQNN MCP6241R BRNN MCP6241U BSNN Note: Example: 5 4 BQ25 Applies to 5-Lead SOT-23. 8-Lead DFN (2x3) (MCP6241 Only) 1 2 3 Example: XXX YWW NN AER 834 25 Example: 8-Lead MSOP XXXXXX 6242E YWWNNN 834256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Legend: XX...X Y YY WW NNN e3 * Note: Example: MCP6242 E/P256 0818 OR MCP6242 3 E/P e^^256 0834 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2008 Microchip Technology Inc. DS21882D-page 17 MCP6241/1R/1U/2/4 Package Marking Information (Continued) 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 14-Lead PDIP (300 mil) (MCP6244) Example: MCP6242 E/SN0818 256 OR Example: MCP6244 e3 E/P^^ 0546256 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6244) MCP6242E e3 0834 SN^^ 256 Example: MCP6244 e3 E/SL^^ 0546256 XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6244) Example: XXXXXXXX YYWW 6244E 0546 NNN 256 DS21882D-page 18 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 /HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU /7 >6&@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D b 3 1 2 E1 E 4 e A e 5 A2 c A1 L 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / /HDG7KLFNQHVV F /HDG:LGWK E 1RWHV 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% (c) 2008 Microchip Technology Inc. DS21882D-page 19 MCP6241/1R/1U/2/4 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS21882D-page 20 (c) 2008 Microchip Technology Inc. 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DS21882D-page 21 MCP6241/1R/1U/2/4 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH 0& [[PP%RG\>')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 NOTE 1 1 2 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ 6WDQGRII $ &RQWDFW7KLFNQHVV $ 5() 2YHUDOO/HQJWK ' %6& 2YHUDOO:LGWK ( ([SRVHG3DG/HQJWK ' ([SRVHG3DG:LGWK ( E &RQWDFW/HQJWK / &RQWDFWWR([SRVHG3DG . &RQWDFW:LGWK %6& %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ && DS21882D-page 22 (c) 2008 Microchip Technology Inc. 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DS21882D-page 23 MCP6241/1R/1U/2/4 /HDG3ODVWLF0LFUR6PDOO2XWOLQH3DFNDJH 06 >0623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b A2 A c L L1 A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( %6& 2YHUDOO/HQJWK ' %6& )RRW/HQJWK / )RRWSULQW / %6& 5() )RRW$QJOH /HDG7KLFNQHVV F /HDG:LGWK E 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS21882D-page 24 (c) 2008 Microchip Technology Inc. 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DS21882D-page 25 MCP6241/1R/1U/2/4 /HDG3ODVWLF6PDOO2XWOLQH 61 1DUURZPP%RG\>62,&@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D e N E E1 NOTE 1 1 2 3 h b h A2 A c L A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( %6& 2YHUDOO/HQJWK ' %6& %6& &KDPIHU RSWLRQDO K )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 6LJQLILFDQW&KDUDFWHULVWLF 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS21882D-page 26 (c) 2008 Microchip Technology Inc. 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DS21882D-page 27 MCP6241/1R/1U/2/4 /HDG3ODVWLF'XDO,Q/LQH 3 PLO%RG\>3',3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RSWR6HDWLQJ3ODQH $ 0ROGHG3DFNDJH7KLFNQHVV $ %DVHWR6HDWLQJ3ODQH $ 6KRXOGHUWR6KRXOGHU:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' 7LSWR6HDWLQJ3ODQH / /HDG7KLFNQHVV F E E H% 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKWKHKDWFKHGDUHD 6LJQLILFDQW&KDUDFWHULVWLF 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS21882D-page 28 (c) 2008 Microchip Technology Inc. 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MCP6241/1R/1U/2/4 APPENDIX A: REVISION HISTORY Revision D (October 2008) The following is the list of modifications: 1. Changed Heading "Available Tools" to "Design Aids". 2. Design Aids: Name change for Mindi Simulator Tool. 3. Package Types: Added DFN to MCP6231 Device. 4. Absolute Maximum Ratings: Numerous changes in this section. 5. Updated notes to Section 1.0 "Electrical Characteristics". 6. Added Figure 2-19. 7. Numerous changes to Section 3.0 "Pin Descriptions". 8. Added Section 4.1.1 "Phase Reversal", Section 4.1.2 "Input Voltage and Current Limits", and Section 4.1.3 "Normal Operation". 9. Replaced Section 5.0 "Design Aids" with additional information. 10. Added 2x3 DFN package to Section 6.0 "Packaging Information" and updated Package Outline Drawings. 11. Added 2x3 DFN package to Product Identification System section. Revision C (March 2005) The following is the list of modifications: 1. 2. 3. 4. 5. 6. Added the MCP6244 quad op amp. Re-compensated parts. Specifications that change are: Gain Bandwidth Product (BWP) and Phase Margin (PM) in AC Electrical Characteristics table. Corrected plots in Section 2.0 "Typical Performance Curves". Added Section 3.0 "Pin Descriptions". Added new SC-70 package markings. Added PDIP-14, SOIC-14, and TSSOP-14 packages and corrected package marking information (Section 6.0 "Packaging Information"). Added Appendix A: "Revision History". Revision B (August 2004) Undocumented changes. Revision A (March 2004) * Original Release of this Document. (c) 2008 Microchip Technology Inc. DS21882D-page 33 MCP6241/1R/1U/2/4 NOTES: DS21882D-page 34 (c) 2008 Microchip Technology Inc. MCP6241/1R/1U/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Tape and Reel and/or Alternate Pinout Device: -X /XX Temperature Package Range MCP6241: MCP6241T: MCP6241RT: MCP6241UT: MCP6242: MCP6242T: MCP6244: MCP6244T: Single Op Amp (MSOP, PDIP, SOIC) Single Op Amp (Tape and Reel) (MSOP, SOIC, SOT-23) Single Op Amp (Tape and Reel) (SOT-23) Single Op Amp (Tape and Reel) (SC-70, SOT-23) Dual Op Amp Dual Op Amp (Tape and Reel) (MSOP, SOIC) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC, TSSOP) Temperature Range: E Package: LT = Plastic Package (SC-70), 5-lead (MCP6241U only) MC = Plastic Dual Flat, No Lead (DFN), 8-lead, (MCP6241 only) MS = Plastic Micro Small Outline (MSOP), 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6241, MCP6241R, MCP6241U) SN = Plastic SOIC (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4 mil Body), 14-lead Examples: a) b) c) d) e) f) g) = -40 C to +125 C (c) 2008 Microchip Technology Inc. MCP6241-E/SN: Extended Temp., 8LD SOIC package. MCP6241-E/MS: Extended Temp., 8LD MSOP package. MCP6241-E/P: Extended Temp., 8LD PDIP package. MCP6241-E/MC: Extended Temp., 8LD DFN package. MCP6241RT-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 package MCP6241UT-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 package. MCP6241UT-E/LT: Tape and Reel, Extended Temp., 5LD SC-70 package. a) MCP6242-E/SN: b) MCP6242-E/MS: c) MCP6242-E/P: d) MCP6242T-E/SN: a) MCP6244-E/P: b) MCP6244-E/SL: c) MCP6244-E/ST: d) MCP6244T-E/SL: e) MCP6244T-E/ST: Extended Temp., 8LD SOIC package. Extended Temp., 8LD MSOP package. Extended Temp., 8LD PDIP package. Tape and Reel, Extended Temp., 8LD SOIC package. Extended Temp., 14LD PDIP package. Extended Temp., 14LD SOIC package. Extended Temp., 14LD TSSOP package. Tape and Reel, Extended Temp., 14LD SOIC package. Tape and Reel, Extended Temp., 14LD TSSOP package. DS21882D-page 35 MCP6241/1R/1U/2/4 NOTES: DS21882D-page 36 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. DS21882D-page 37 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS21882D-page 38 (c) 2008 Microchip Technology Inc.