XC6403 Series
High Speed LDO Regulators, Low ESR Cap. Compatible, Voltage Detector Function
!OPERATIONAL EXPLANATION
<Output voltage regulator control>
<Detector function with the XC6403 series>
Delay Time Rdelay standard : 1.0 ~ 3.5MΩTYP : 2.0MΩ
<Low ESR Capacitors>
Output Capacitor
<Current Limiter, Short-Circuit Protection>
1.8 ~ 5.6V
more than 1.0µF
Cdelay DELAY TIME (TYP.) DELAY TIME (TYP.)
0.01 µF14 msec 7.0 ~ 24.5 msec
0.047 µF65.8 msec 32.9 ~ 115.15 msec
0.1 µF140 msec 70.0 ~ 245.0 msec
0.022 µF30.8 msec 15.4 ~ 53.9 msec
0.22 µF308 msec 154.0 ~ 539.0 msec
0.47 µF658 msec 329.0 ~ 1151.5 msec
more than 4.7µF more than 2.2µF
1 µF1400 msec 700.0 ~ 2450.0 msec
VROUT
The XC6403 series regulator offers a combination of current limit and circuit protection by means of a built-in fixed current limiter circuit and a foldback
circuit. When the load current reaches the current limit level, the fixed current limiter circuit operates and output voltage drops. As a result of this drop in
output voltage, the foldback circuit operates, the output voltage drops further and output current decreases. When the output pin is shorted, a current of
about 50mA flows.
CL
0.9 ~1.2V 1.3 ~ 1.7V
The voltage, divided by resistors R1 & R2 which are connected to the VROUT pin is compared with the internal reference voltage by the error amplifier.
The P-Channel MOSFET, which is connected to the VROUT pin, is then driven by the subsequent output signal. The output voltage at the VROUT pin is
controlled & stabilized by negative feedback.
The current limit circuit and short circuit protection operate in relation to the level of output current. Further, the voltage regulator's internal circuitry can be
shutdown via the EN or CE pin's signal.
With the XC6403 series regulator, a stable output voltage is achievable even if low ESR capacitors are used, as a phase compensation circuit is built-in
to the regulator. In order to ensure the effectiveness of the phase compensation, we suggest that an output capacitor (CL) be connected as close as
possible, between the output pin (VROUT) and the VSS pin. Please use an output capacitor (CL) with a capacitance, based on the chart below. We also
suggest an input capacitor (CIN) of 1µF : this should be connected between VIN and VSS in order to stabilize input power source.
For the XC6403A, B, C type, in stand-by, if a voltage of the recovery voltage is present at the VROUT pin (from another power source), the VDOUT pin
will be high impedance mode, and the pull up voltage will be output at VDOUT. By connecting the Cdelay pin to a capacitor (Cd), the XC6403F series
can apply a delay time to VDOUT voltage when releasing voltage. The delay time can be calculated from the internal resistance, Rdelay (2MΩ fixed) and
the value of Cd as per the following equation.
Delay Time = Cdelay x Rdelay x 0.7
The series' detector function monitors the voltage divided by resistors R3 & R4 which are connected to the VROUT pin or the VIN pin or the VSEN pin, as
well as monitoring the voltage of the internal reference voltage source via the comparator. The VDSEN pin has options (please refer to the Selection
Guide, item 4 on page 2). A 'High' or 'Low' signal level can be output from the VDOUT pin when the VD pin voltage level goes below the detect voltage.
The VD output logic has options (please refer to the Selection Guide, item 5 on page 2). As VDOUT is an open-drain N-channel output, a pull-up resistor
of about 220KΩ is needed to achieve a voltage output. Because of hysteresis at the detector function, output at the VDOUT pin will invert when the
detect voltage level increases above the release voltage (105% of the detect voltage). Even when the XC6403A, B, C, series are in stand-by mode, the
voltage detector function operates and the output voltage at VDOUT will output according to the voltage level at VDSENSE voltage.
S emi conductor Ltd.
Data Sheet 24