NXP Semiconductors Data Sheet: Advance Information Document Number: MC33903_4_5 Rev. 14.0, 2/2018 SBC Gen2 with CAN high speed and LIN interface 33903/ 33903/4/5 The 33903/4/5 is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional integrated circuits such as sensors and CAN transceivers. It has a built-in enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus failure diagnostics, protection, and fail-safe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wake-up input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Low-power (LP) modes, with very low-current consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. The 33903/4/5 also implements an innovative and advanced fail-safe state machine and concept solution. SYSTEM BASIS CHIP EK Suffix (Pb-free) 98ASA10556D 32-PIN SOIC Features Applications * Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with possibility of usage external PNP to extend current capability and share power dissipation * Voltage, current, and temperature protection * Extremely low quiescent current in LP modes * Fully-protected embedded 5.0 V regulator for the CAN driver * Multiple undervoltage detections to address various MCU specifications and system operation modes (i.e. cranking) * Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection * MUX output pin for device internal analog signal monitoring and power supply monitoring * Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. * Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and VDD overcurrent detection. * ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s * Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 * * * * * * * * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) NXP B.V. 2018. EK Suffix (Pb-free) 98ASA10506D 54-PIN SOIC Aircraft and marine systems Automotive and robotic systems Farm equipment Industrial actuator controls Lamp and inductive load controls DC motor control applications requiring diagnostics Applications where high-side switch control is required Table of Contents 1. Simplified application diagrams ..................................................................................................................................................... 3 2. Orderable part ................................................................................................................................................................................ 7 3. Internal block diagrams .................................................................................................................................................................. 9 4. Pin Connections ........................................................................................................................................................................... 11 4.1. Pinout diagram ....................................................................................................................................................................... 11 5. Electrical characteristics .............................................................................................................................................................. 16 5.1. Maximum ratings .................................................................................................................................................................... 16 5.2. Static electrical characteristics ............................................................................................................................................... 18 5.3. Dynamic electrical characteristics .......................................................................................................................................... 26 5.4. Timing diagrams .................................................................................................................................................................... 29 6. Functional description .................................................................................................................................................................. 32 6.1. Introduction ............................................................................................................................................................................ 32 6.2. Functional pin description ...................................................................................................................................................... 32 7. Functional device operation ......................................................................................................................................................... 36 7.1. Mode and state description .................................................................................................................................................... 36 7.2. LP modes ............................................................................................................................................................................... 37 7.3. State diagram ......................................................................................................................................................................... 39 7.4. Mode change ......................................................................................................................................................................... 40 7.5. Watchdog operation ............................................................................................................................................................... 40 7.6. Functional block operation versus mode ............................................................................................................................... 43 7.7. Illustration of device mode transitions .................................................................................................................................... 44 7.8. Cyclic sense operation during LP modes ............................................................................................................................... 45 7.9. Cyclic INT operation during LP VDD on mode ....................................................................................................................... 47 7.10. Behavior at power up and power down ................................................................................................................................ 48 7.11. Fail-safe operation ............................................................................................................................................................... 51 8. CAN interface .............................................................................................................................................................................. 55 8.1. CAN interface description ...................................................................................................................................................... 55 8.2. CAN bus fault diagnostic ........................................................................................................................................................ 58 9. LIN block ...................................................................................................................................................................................... 62 9.1. LIN interface description ........................................................................................................................................................ 62 9.2. LIN operational modes ........................................................................................................................................................... 63 10. Serial peripheral interface .......................................................................................................................................................... 64 10.1. High level overview .............................................................................................................................................................. 64 10.2. Detail operation .................................................................................................................................................................... 64 10.3. Detail of control bits and register mapping ........................................................................................................................... 68 10.4. Flags and device status ....................................................................................................................................................... 84 11. Typical applications ................................................................................................................................................................... 92 12. Packaging ................................................................................................................................................................................ 100 12.1. SOIC 32 package dimensions ........................................................................................................................................... 100 12.2. SOIC 54 package dimensions ........................................................................................................................................... 103 13. Revision history ....................................................................................................................................................................... 106 33903/4/5 2 NXP Semiconductors SIMPLIFIED APPLICATION DIAGRAMS 1 Simplified application diagrams 33905D VBAT D1 * = Optional (5.0 V/3.3 V) Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG VDD RST INT GND VSENSE MOSI SCLK MISO CS MUX-OUT I/O-0 I/O-1 SPI MCU A/D 5V-CAN CANH TXD SPLIT CAN Bus CANL LIN-TERM 1 LIN Bus LIN-1 LIN-TERM 2 LIN Bus LIN-2 RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 Figure 1. 33905D simplified application diagram 33905S VBAT D1 Q2 * = Optional (5.0 V/3.3 V) Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG GND VSENSE I/O-0 I/O-1 VDD RST INT MOSI SCLK MISO CS MUX-OUT SPI MCU A/D 5V-CAN CANH CAN Bus VBAT LIN Bus SPLIT TXD CANL LIN-T RXD TXD-L RXD-L LIN I/O-3 Figure 2. 33905S simplified application diagram 33903/4/5 NXP Semiconductors 3 SIMPLIFIED APPLICATION DIAGRAMS 33904 VBAT D1 * = Optional (5.0 V/3.3 V) Q2 Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE DBG VDD RST INT GND VSENSE MOSI SCLK MISO CS MUX-OUT I/O-0 I/O-1 SPI MCU A/D 5V-CAN CANH VBAT TXD SPLIT CAN Bus RXD CANL I/O-2 I/O-3 Figure 3. 33904 simplified application diagram 33903 VBAT D1 VSUP1 DBG RST INT GND MOSI SCLK MISO CS CANH SPLIT CANL VDD VDD SAFE I/O-0 CAN Bus VSUP2 SPI MCU 5V-CAN TXD RXD Figure 4. 33903 simplified application diagram 33903/4/5 4 NXP Semiconductors SIMPLIFIED APPLICATION DIAGRAMS 33903D VBAT D1 * = Optional Q1* VSUP VE VB VDD VDD RST SAFE DBG INT GND VSENSE MOSI SCLK MISO CS MUX-OUT IO-0 CANH SPI MCU A/D 5V-CAN SPLIT TXD CANL LIN-T1/I/O-2 CAN Bus LIN Bus RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 LIN-1 LIN-T2/IO-3 LIN Bus LIN-2 Figure 5. 33903D simplified application diagram 33903S VBAT D1 * = Optional Q1* VSUP SAFE DBG GND VSENSE IO-0 CANH VE VB VDD VDD RST INT MOSI SCLK MISO CS MUX-OUT SPI MCU A/D 5V-CAN SPLIT VBAT CAN Bus LIN Bus CANL LIN-T1/I/O-2 LIN-1 TXD RXD TXD-L1 RXD-L1 I/O-3 Figure 6. 33903S simplified application diagram 33903/4/5 NXP Semiconductors 5 SIMPLIFIED APPLICATION DIAGRAMS 33903P VBAT D1 * = Optional Q1* VSUP SAFE DBG GND VSENSE IO-0 CANH SPLIT CAN Bus VDD VDD RST INT MOSI SCLK MISO CS MUX-OUT SPI MCU A/D 5V-CAN CANL TXD VBAT VBAT VE VB RXD I/O-2 I/O-3 Figure 7. 33903P simplified application diagram 33903/4/5 6 NXP Semiconductors ORDERABLE PART 2 Orderable part Table 1. MC33905 orderable part variations - (all devices rated at TA = -40 C TO 125 C) NXP part number Version (1), (2), (3) VDD output voltage LIN interface(s) Wake-up input / LIN master termination Package VAUX VSENSE MUX MC33905D (Dual LIN) MCZ33905BD3EK/R2 B MCZ33905CD3EK/R2 C MCZ33905DD3EK/R2 D 3.3 V MCZ33905D5EK/R2 MCZ33905BD5EK/R2 B MCZ33905CD5EK/R2 C MCZ33905DD5EK/R2 D 2 2 Wake-up + 2 LIN terms or 3 Wake-up + 1 LIN terms or 4 Wake-up + no LIN terms SOIC 54-pin exposed pad Yes Yes Yes 1 3 Wake-up + 1 LIN terms or 4 Wake-up + no LIN terms SOIC 32-pin exposed pad Yes Yes Yes 5.0 V MC33905S (Single LIN) MCZ33905BS3EK/R2 B MCZ33905CS3EK/R2 C MCZ33905DS3EK/R2 D 3.3 V MCZ33905S5EK/R2 MCZ33905BS5EK/R2 B MCZ33905CS5EK/R2 C MCZ33905DS5EK/R2 D 5.0 V Notes 1. Design changes in the `B' version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. `B' version has an errata linked to the SPI operation. 2. Design changes in the `C' version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature. 3. 'C' versions are no longer recommended for new design. 'D' versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes. Table 2. MC33904 orderable part variations - (all devices rated at TA = -40 C TO 125 C) NXP part number Version (4), (5), (6) VDD output voltage LIN interface(s) Wake-up input / LIN master termination Package VAUX VSENSE MUX 4 Wake-up SOIC 32 pin exposed pad Yes Yes Yes MC33904 MCZ33904B3EK/R2 B MCZ33904C3EK/R2 C MCZ33904D3EK/R2 D MCZ33904A5EK/R2 A MCZ33904B5EK/R2 B MCZ33904C5EK/R2 C MCZ33904D5EK/R2 D 3.3 V 0 5.0 V Notes 4. Design changes in the "B" version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. `B' version has an errata linked to the SPI operation. 5. Design changes in the "C" version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature. 6. 'C' versions are no longer recommended for new design. 'D' versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes. 33903/4/5 NXP Semiconductors 7 ORDERABLE PART Table 3. MC33903 orderable part variations - (all devices rated at TA = -40 C TO 125 C) NXP part number Version (8), (9), (10) VDD output voltage LIN interface(s) Wake-up input / LIN master termination Package VAUX VSENSE MUX 0 1 Wake-up SOIC 32 pin exposed pad No No No 2 1 Wake-up + 2 LIN terms or 2 Wake-up + 1 LIN terms or 3 Wake-up + no LIN terms SOIC 32 pin exposed pad No Yes Yes 1 2 Wake-up + 1 LIN terms or 3 Wake-up + no LIN terms SOIC 32 pin exposed pad No Yes Yes 0 3 Wake-up SOIC 32 pin exposed pad No Yes Yes MC33903 MCZ33903B3EK/R2 B MCZ33903C3EK/R2 C MCZ33903D3EK/R2 D MCZ33903B5EK/R2 B MCZ33903C5EK/R2 C MCZ33903D5EK/R2 D 3.3 V(7) 5.0 V(7) MC33903D (Dual LIN) MCZ33903BD3EK/R2 B MCZ33903CD3EK/R2 C MCZ33903DD3EK/R2 D MCZ33903BD5EK/R2 B MCZ33903CD5EK/R2 C MCZ33903DD5EK/R2 D 3.3 V 5.0 V MC33903S (Single LIN) MCZ33903BS3EK/R2 B MCZ33903CS3EK/R2 C MCZ33903DS3EK/R2 D MCZ33903BS5EK/R2 B MCZ33903CS5EK/R2 C MCZ33903DS5EK/R2 D 3.3 V 5.0 V MC33903P MCZ33903CP5EK/R2 C MCZ33903DP5EK/R2 D MCZ33903CP3EK/R2 C MCZ33903DP3EK/R2 D 5.0 V 3.3 V Notes 7. VDD does not allow usage of an external PNP on the 33903. 8. 9. 10. Design changes in the `B' version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. `B' version has an errata linked to the SPI operation. Design changes in the "C" version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature. 'C' versions are no longer recommended for new design. 'D' versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes. 33903/4/5 8 NXP Semiconductors INTERNAL BLOCK DIAGRAMS 3 Internal block diagrams VBAUX VCAUX VAUX VSUP2 VSUP1 5 V Auxiliary Regulator VBAUX VCAUX VAUX VE VB RST Fail-safe SCLK SPI Signals Condition & Analog MUX CANH CANL 5 V-CAN LIN Term #1 LIN-T1 CANL MISO CS MUX-OUT 5 V-CAN TXD RXD VS2-INT LIN Term #1 LIN-T RXD-L1 TXD-L LIN 2.1 Interface - #1 LIN RXD-L 33905S TXD-L2 LIN 2.1 Interface - #2 5 V-CAN Regulator Enhanced High Speed CAN Physical Interface SPLIT TXD-L1 LIN 2.1 Interface - #1 VS2-INT LIN Term #2 CANH RXD LIN1 LIN-T2 I/O-1 TXD SCLK VS2-INT Configurable Input-Output I/O-3 VS2-INT MOSI SPI Signals Condition & Analog MUX I/O-0 5 V-CAN Regulator State Machine Analog Monitoring MUX-OUT Enhanced High Speed CAN Physical Interface SPLIT Oscillator VSENSE VS2-INT I/O-1 VDD INT Power Management GND MISO CS Analog Monitoring Configurable Input-Output Fail-safe DBG MOSI State Machine Oscillator I/O-0 VDD Regulator RST SAFE INT Power Management DBG VSENSE VE VB VS2-INT VS2-INT SAFE GND 5 V Auxiliary Regulator VSUP2 VDD VDD Regulator VSUP1 RXD-L2 LIN2 33905D Figure 8. 33905 internal block diagram VBAUX VCAUX VAUX VSUP2 VSUP1 5 V Auxiliary Regulator VE VB VDD Regulator VDD VS2-INT RST SAFE Fail-safe GND VSENSE Oscillator State Machine Analog Monitoring Signals Condition & Analog MUX I/O-0 I/O-1 I/O-2 I/O-3 CANH SPLIT CANL INT Power Management DBG Configurable Input-Output VS2-INT 5 V-CAN Regulator Enhanced High Speed CAN Physical Interface MOSI SPI SCLK MISO CS MUX-OUT 5 V-CAN TXD RXD Figure 9. 33904 internal block diagram 33903/4/5 NXP Semiconductors 9 INTERNAL BLOCK DIAGRAMS VSUP VSUP1 VDD Regulator VSUP2 VDD VS2-INT INT Power Management State Machine DBG I/O-0 MOSI SPI Oscillator Configurable Input-Output CANH VS2-INT CANL SCLK MISO CS RST SAFE Fail-safe GND Analog Monitoring Signals Condition & Analog MUX TXD RXD CANH MUX-OUT 5 V-CAN Enhanced High Speed CAN Physical Interface VB TXD RXD 33903P VDD VDD Regulator VSUP VE VB RST SAFE Fail-safe INT Power Management DBG Oscillator VSENSE State Machine Analog Monitoring SCLK SAFE MISO CS DBG GND IO-0 RST Fail-safe State Machine Oscillator VSENSE 5 V-CAN Regulator INT Power Management MUX-OUT VS-INT Configurable Input-Output VDD VDD Regulator VS-INT MOSI SPI Signals Condition & Analog MUX MOSI SPI Analog Monitoring 5 V-CAN Signals Condition & Analog MUX SCLK MISO CS MUX-OUT VS-INT CANH Enhanced High-speed CAN Physical Interface SPLIT CANL VS-INT LIN Term #1 LIN-T1 VS-INT LIN Term #2 TXD I/O-0 RXD I/O-3 TXD-L1 LIN 2.1 Interface - #1 LIN1 LIN-T2 5 V-CAN Regulator Configurable Input-Output CANL GND SCLK MISO CS VS-INT I/O-0 I/O-2 SPLIT VS-INT SPI 5 V-CAN 33903 VE MOSI State Machine Oscillator I/O-3 VSUP INT Power Management DBG VSENSE 5 V-CAN Regulator Enhanced High Speed CAN Physical Interface SPLIT VDD VDD Regulator VS-INT RST SAFE GND VE VB RXD-L1 CANH LIN2 RXD-L2 Enhanced High Speed CAN Physical Interface SPLIT CANL 5 V-CAN TXD RXD VS-INT TXD-L2 LIN 2.1 Interface - #2 5 V-CAN Regulator Configurable Input-Output LIN-T LIN Term #1 TXD-L LIN 2.1 Interface - #1 LIN 33903D RXD-L 33903S Figure 10. 33903 internal block diagram 33903/4/5 10 NXP Semiconductors PIN CONNECTIONS 4 Pin Connections 4.1 Pinout diagram MC33905D NC NC NC VSUP1 VSUP2 LIN-T2/I/O-3 LIN-T1/I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT V-BAUX V-CAUX V-AUX MUX-OUT I/O-0 DBG NC NC NC TXD-L2 GND RXD-L2 LIN-2 NC 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 GROUND 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 24 32 25 30 31 26 29 27 28 MC33905S NC NC NC VB VE RXD TXD VDD MISO MOSI SCLK CS INT RST I/O-1 VSENSE RXD-L1 TXD-L1 LIN-1 NC NC NC NC GND NC NC NC VSUP1 VSUP2 I/O-3 LIN-T/I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT V-BAUX V-CAUX V-AUX MUX-OUT I/O-0 DBG VB VE RXD TXD VDD MISO MOSI SCLK CS INT RST I/O-1 VSENSE NC NC NC VSUP1 VSUP2 NC NC SAFE 5V-CAN CANH CANL GND CAN SPLIT NC NC NC NC I/O-0 DBG 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 GROUND 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VB VE RXD TXD VDD MISO MOSI SCLK CS INT RST I/O-1 VSENSE RXD-L TXD-L LIN GND - LEAD FRAME 32 pin exposed package GND - LEAD FRAME 54 pin exposed package MC33904 VSUP1 VSUP2 I/O-3 I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT V-BAUX V-CAUX V-AUX MUX-OUT I/O-0 DBG MC33903 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 GROUND 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 GROUND 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 GND - LEAD FRAME GND - LEAD FRAME 32 pin exposed package 32 pin exposed package NC NC RXD TXD VDD MISO MOSI SCLK CS INT RST NC NC NC NC NC Note: MC33905D, MC33905S, MC33904 and MC33903 are footprint compatible, Figure 11. 33905D, MC33905S, MC33904 and MC33903 pin connections 33903/4/5 NXP Semiconductors 11 PIN CONNECTIONS MC33903D VB VSUP LIN-T2 / I/O-3 LIN-T1 / I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT MUX-OUT IO-0 DBG TXD-L2 GND RXD-L2 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 GROUND 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 MC33903S VE RXD TXD VDD MISO MOSI SCLK CS INT RST VSENSE RXD-L1 TXD-L1 LIN1 GND LIN2 VB VSUP I/O-3 LIN-T / I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT MUX-OUT I/O-0 DBG NC GND NC 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 GROUND 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VE RXD TXD VDD MISO MOSI SCLK CS INT RST VSENSE RXD-L TXD-L LIN GND NC GND - LEAD FRAME GND - LEAD FRAME 32 pin exposed package 32 pin exposed package MC33903P VB VSUP I/O-3 I/O-2 SAFE 5V-CAN CANH CANL GND CAN SPLIT MUX-OUT I/O-0 DBG NC GND NC 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 GROUND 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VE RXD TXD VDD MISO MOSI SCLK CS INT RST VSENSE N/C N/C N/C GND NC GND - LEAD FRAME 32 pin exposed package Note: MC33903D, MC33903S, and MC33903P are footprint compatible. Figure 12. 33905D, MC33905S, MC33904 and MC33903 pin connections 33903/4/5 12 NXP Semiconductors PIN CONNECTIONS 4.2 Pin definitions A functional description of each pin can be found in the Functional pin description section beginning on page 32. Table 4. 33903/4/5 pin definitions 54 Pin 32 Pin 32 Pin 33905D 33905S 33904 1-3, 2022, 2730, 3235, 5254 N/A N/A N/A 4 5 6 1 2 3 32 Pin 32 Pin 32 Pin 32 Pin Pin Name 33903 33903D 33903S 33903P 3-4,1117, 18, 14, 1721, 31, 19 32 N/A 1 2 3 N/A 1 2 N/A N/A N/A 2 N/A 3 N/A N/A 14, 16, 14, 16, 17, 1917 21 2 N/A 3 2 N/A 3 Pin Function Formal Name N/C No Connect - N/C No Connect VSUP/1 VSUP2 LIN-T2 or I/O-3 4 4 N/A 4 4 Connect to GND. Do NOT connect the N/C pins to GND. Leave these pins Open. Power Battery Voltage Supply 1 Supply input for the device internal supplies, power on reset circuitry and the VDD regulator. VSUP and VSUP1 supplies are internally connected on part number MC33903BDEK and MC33903BSEK Power Battery Voltage Supply 2 Supply input for 5 V-CAN regulator, VAUX regulator, I/O and LIN pins. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK Output or Input/ Output 33903D and 33905D - Output pin for the LIN2 master node termination resistor. or 33903P, 33903S, 33903D, 33904, 33905S and LIN 33905D - Configurable pin as an input or HS Termination 2 output, for connection to external circuitry or (switched or small load). The input can be used Input/Output as a programmable Wake-up input in (LP) mode. When used as a HS, no 3 overtemperature protection is implemented. A basic short to GND protection function, based on switch drain-source overvoltage detection, is available. LIN-T1 or 7 Definition LIN-T Output or or Input/ Output 4 LIN Termination 1 or Input/Output 2 I/O-2 33905D - Output pin for the LIN1 master node termination resistor. or 33903P, 33903S, 33903D, 33904, 33905S and 33905D - Configurable pin as an input or HS output, for connection to external circuitry (switched or small load). The input can be used as a programmable Wake-up input in (LP) mode. When used as a HS, no overtemperature protection is implemented. A basic short to GND protection function, based on switch drain-source overvoltage detection, is available. Output of the safe circuitry. The pin is asserted Safe Output LOW if a fault event occurs (e.g.: software (Active LOW) watchdog is not triggered, VDD low, issue on the RST pin, etc.). Open drain structure. 8 5 5 5 5 5 5 SAFE Output 9 6 6 6 6 6 6 5 V-CAN Output 5V-CAN 10 7 7 7 7 7 7 CANH Output CAN High CAN high output. 11 8 8 8 8 8 8 CANL Output CAN Low CAN low output. 12 9 9 9 9 9 9 GND-CAN Ground GND-CAN Power GND of the embedded CAN interface 13 10 10 10 10 10 10 SPLIT Output SPLIT Output Output voltage for the embedded CAN interface. A capacitor must be connected to this pin. Output pin for connection to the middle point of the split CAN termination 33903/4/5 NXP Semiconductors 13 PIN CONNECTIONS Table 4. 33903/4/5 pin definitions (continued) 54 Pin 32 Pin 32 Pin 33905D 33905S 33904 32 Pin 32 Pin 32 Pin 32 Pin Pin Name 33903 33903D 33903S 33903P Pin Function Formal Name Definition 14 11 11 N/A N/A N/A N/A VBAUX Output VB Auxiliary Output pin for external path PNP transistor base 15 12 12 N/A N/A N/A N/A VCAUX Output VCOLLECT OR Auxiliary Output pin for external path PNP transistor collector 16 13 13 N/A N/A N/A N/A VAUX Output VOUT Auxiliary Output pin for the auxiliary voltage. Multiplex Output Multiplexed output to be connected to an MCU A/D input. Selection of the analog parameter available at MUX-OUT is done via the SPI. A switchable internal pull-down resistor is integrated for VDD current sense measurements. Input/Output 0 Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and via the MUX output pin. The input can be used as a programmable Wake-up input in LP mode. In LP, when used as an output, the High-side (HS) or Low-side (LS) can be activated for a cyclic sense function. 17 18 14 15 14 15 N/A 15 11 12 11 12 11 12 MUX-OUT I/O-0 Output Input/ Output 19 16 16 16 13 13 13 DBG Input Debug 23 N/A N/A N/A 14 N/A N/A TXD-L2 Input LIN Transmit Data 2 24,31 N/A N/A N/A 15, 18 15, 18 15, 18 GND Ground Ground Input to activate the Debug mode. In Debug mode, no watchdog refresh is necessary. Outside of Debug mode, connection of a resistor between DBG and GND allows the selection of Safe mode functionality. LIN bus transmit data input. Includes an internal pull-up resistor to VDD. Ground of the IC. 25 N/A N/A N/A 16 N/A N/A RXD-L2 Output LIN Receive Data 26 N/A N/A N/A 17 N/A N/A LIN2 Input/ Output LIN bus LIN bus input output connected to the LIN bus. Input/ Output LIN bus LIN bus input output connected to the LIN bus. LIN bus receive data output. 36 17 N/A N/A 19 19 N/A 33903D/5D LIN-1 33903S/5S LIN 37 18 N/A N/A 20 20 N/A 33903D/5D TXD-L11 33903S/5S TXD-L Input LIN Transmit Data LIN bus transmit data input. Includes an internal pull-up resistor to VDD. Output LIN Receive Data LIN bus receive data output. Input Sense input Direct battery voltage input sense. A serial resistor is required to limit the input current during high voltage transients. Input Output 1 Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and the MUX output pin. The input can be used as a programmable Wake-up input in (LP) mode. It can be used in association with I/O-0 for a cyclic sense function in (LP) mode. 38 19 N/A N/A 21 21 N/A 33903D/5D RXD-L1 33903S/5S RXD-L 39 20 20 N/A 22 22 22 VSENSE 40 21 21 N/A N/A N/A N/A I/O-1 Input/ Output 33903/4/5 14 NXP Semiconductors PIN CONNECTIONS Table 4. 33903/4/5 pin definitions (continued) 54 Pin 32 Pin 32 Pin 33905D 33905S 33904 32 Pin 32 Pin 32 Pin 32 Pin Pin Name 33903 33903D 33903S 33903P Pin Function Formal Name Definition 41 22 22 22 23 23 23 RST Output This is the device reset output whose main function is to reset the MCU. This pin has an Reset Output internal pull-up to VDD. The reset input voltage (Active LOW) is also monitored in order to detect external reset and safe conditions. 42 23 23 23 24 24 24 INT Output This output is asserted low when an enabled Interrupt interrupt condition occurs. This pin is an open Output drain structure with an internal pull up resistor (Active LOW) to VDD. 43 24 24 24 25 25 25 CS Input Chip select pin for the SPI. When the CS is low, Chip Select the device is selected. In (LP) mode with VDD (Active LOW) ON, a transition on CS is a Wake-up condition 44 25 25 25 26 26 26 SCLK Input Serial Data Clock Clock input for the Serial Peripheral Interface (SPI) of the device 45 26 26 26 27 27 27 MOSI Input Master Out / Slave In SPI data received by the device 46 27 27 27 28 28 28 MISO Output Master In / Slave Out SPI data sent to the MCU. When the CS is high, MISO is high-impedance 47 28 28 28 29 29 29 VDD Output Voltage Digital Drain 5.0 or 3.3 V output pin of the main regulator for the Microcontroller supply. 48 29 29 29 30 30 30 TXD Input Transmit Data CAN bus transmit data input. Internal pull-up to VDD 49 30 30 30 31 31 31 RXD Output 50 31 31 N/A 32 32 32 VE 51 32 32 N/A 1 1 1 VB GND EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD Receive Data CAN bus receive data output Voltage Emitter Connection to the external PNP path transistor. This is an intermediate current supply source for the VDD regulator Output Voltage Base Base output pin for connection to the external PNP pass transistor Ground Ground Ground 33903/4/5 NXP Semiconductors 15 ELECTRICAL CHARACTERISTICS 5 Electrical characteristics 5.1 Maximum ratings Table 5. Maximum ratings All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Electrical Ratings Value Unit Notes ratings(11) VSUP1/2 VSUP1/2TR Supply Voltage at VSUP/1 and VSUP2 Normal Operation (DC) Transient Conditions (Load Dump) -0.3 to 28 -0.3 to 40 V VBUSLIN VBUSLINTR DC voltage on LIN/1 and LIN2 Normal Operation (DC) Transient Conditions (Load Dump) -28 to 28 -28 to 40 V VBUS VBUSTR DC voltage on CANL, CANH, SPLIT Normal Operation (DC) Transient Conditions (Load Dump) -28 to 28 -32 to 40 V VSAFE VSAFETR DC Voltage at SAFE Normal Operation (DC) Transient Conditions (Load Dump) -0.3 to 28 -0.3 to 40 V VI/O VI/OTR DC Voltage at I/O-0, I/O-1, I/O-2, I/O-3 (LIN-T Pins) Normal Operation (DC) Transient Conditions (Load Dump) -0.3 to 28 -0.3 to 40 V VDIGLIN DC voltage on TXD-L, TXD-L1 TXD-L2, RXD-L, RXD-L1, RXD-L2 -0.3 to VDD +0.3 V VDIG DC voltage on TXD, RXD -0.3 to VDD +0.3 V VINT DC Voltage at INT -0.3 to 10 V VRST DC Voltage at RST -0.3 to VDD +0.3 V VRST DC Voltage at MOSI, MSIO, SCLK and CS -0.3 to VDD +0.3 V VMUX DC Voltage at MUX-OUT -0.3 to VDD +0.3 V VDBG DC Voltage at DBG -0.3 to 10 V ILH 200 mA VREG DC voltage at VDD, 5V-CAN, VAUX, VCAUX -0.3 to 5.5 V VREG DC voltage at VBASE and VBAUX -0.3 to 40 V (12) DC voltage at VE -0.3 to 40 V (13) DC voltage at VSENSE -28 to 40 V VE VSENSE Continuous current on CANH and CANL (13) Notes 11. The voltage on non-VSUP pins should never exceed the VSUP voltage at any time or permanent damage to the device may occur. 12. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external VDD ballast current sharing functionality may be damaged. 13. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON. 33903/4/5 16 NXP Semiconductors ELECTRICAL CHARACTERISTICS Table 5. Maximum ratings (continued) All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes ESD Capability AECQ100(14) Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 ) VESD1-1 VESD1-2 CANH and CANL. LIN1 and LIN2, Pins versus all GND pins all other Pins including CANH and CANL Charge Device Model - JESD22/C101 (CZAP = 4.0 pF) VESD2-1 VESD2-2 750 500 Corner Pins (Pins 1, 16, 17, and 32) All other Pins (Pins 2-15, 18-31) Tested per IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 ) VESD3-1 VESD3-2 VESD3-3 Device unpowered, CANH and CANL pin without capacitor, versus GND Device unpowered, LIN, LIN1 and LIN2 pin, versus GND Device unpowered, VS1/VS2 (100 nF to GND), versus GND Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor on VSUP/1/2 pins (See Typical applications on page 92) CANH, CANL without bus filter LIN, LIN1 and LIN2 with and without bus filter I/O with external components (22 k - 10 nF) VESD4-1 VESD4-2 VESD4-3 8000 2000 15000 15000 15000 V 9000 12000 7000 Thermal ratings TJ Junction temperature 150 C TA Ambient temperature -40 to 125 C TST Storage temperature -50 to 150 C 50 C/W (17) Note 16 C (15), (16) Thermal resistance RJA TPPRT Thermal resistance junction to ambient Peak package reflow temperature during reflow Notes 14. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Charge Device Model (CDM), and Robotic (CZAP = 4.0 pF). 15. 16. 17. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. NXP's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics. This parameter was measured according to Figure 13: PCB 100mm x 100mm Top side, 300 sq. mm (20mmx15mm) Bottom side 20mm x 40mm Bottom view Figure 13. PCB with top and bottom layer dissipation area (dual layer) 33903/4/5 NXP Semiconductors 17 ELECTRICAL CHARACTERISTICS 5.2 Static electrical characteristics Table 6. Static electrical characteristics Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Power input VSUP1/VSUP2 Nominal DC Voltage Range 5.5 - 28 V (18) VSUP1/VSUP2 Extended DC Low Voltage Range 4.0 - 5.5 V (19) VS1_LOW Undervoltage Detector Thresholds, at the VSUP/1 pin, Low threshold (VSUP/1 ramp down) High threshold (VSUP/1 ramp up) Hysteresis Note: function not active in LP mode 5.5 0.22 6.0 0.35 6.5 6.6 0.5 V VS2_LOW Undervoltage Detector Thresholds, at the VSUP2 pin: Low threshold (VSUP2 ramp down) High threshold (VSUP2 ramp up) Hysteresis Note: function not active in LP modes 5.5 0.22 6.0 0.35 6.5 6.6 0.5 V VS_HIGH VSUP Overvoltage Detector Thresholds, at the VSUP/1 pin: Not active in LP modes 16.5 17 18.5 V BATFAIL Battery loss detection threshold, at the VSUP/1 pin. 2.0 2.8 4.0 V VSUP-TH1 VSUP/1 to turn VDD ON, VSUP/1 rising - 4.1 4.5 150 180 - 2.0 0.05 4.0 0.85 - 2.8 - 4.5 5.0 5.5 8.0 - 15 - 35 50 A 20 40 - 65 85 A - 5.0 9.0 8.0 - 10 VSUP-TH1HYST ISUP1 ISUP1+2 ILPM_OFF ILPM_ON VSUP/1 to turn VDD ON, hysteresis (Guaranteed by design) Supply current - from VSUP/1 - from VSUP2, (5V-CAN VAUX, I/O OFF) Supply current, ISUP1 + ISUP2, Normal mode, VDD ON - 5 V-CAN OFF, VAUX OFF - 5 V-CAN ON, CAN interface in Sleep mode, VAUX OFF - 5 V-CAN OFF, Vaux ON - 5 V-CAN ON, CAN interface in TXD/RXD mode, VAUX OFF, I/O-x disabled LP mode VDD OFF. Wake-up from CAN, I/O-x inputs VSUP 18 V, -40 to 25 C VSUP 18 V, 125 C LP mode VDD ON (5.0 V) with VDD undervoltage and VDD overcurrent monitoring, Wake-up from CAN, I/O-x inputs VSUP 18 V, -40 to 25 C, IDD = 1.0 A VSUP 18 V, -40 to 25 C, IDD = 100 A VSUP 18 V, 125 C, IDD = 100 A IOSC LP mode, additional current for oscillator (used for: cyclic sense, forced Wake-up, and in LP VDD ON mode cyclic interruption and watchdog) VSUP 18 V, -40 to 125 C VDBG Debug mode DBG voltage range - V mV mA (20), (21) mA A V Notes 18. All parameters in spec (ex: VDD regulator tolerance). 19. 20. 21. Device functional, some parameters could be out of spec. VDD is active, device is not in Reset mode if the lowest VDD undervoltage reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational. In Run mode, CAN interface in Sleep mode, 5 V-CAN and VAUX turned OFF. IOUT at VDD < 50 mA. Ballast: turned OFF or not connected. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, ISUP1 and ISUP2 cannot be measured individually. 33903/4/5 18 NXP Semiconductors ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes 4.9 4.9 3.234 5.0 5.0 3.3 5.1 5.15 3.4 V (22) - 330 - 450 500 mV (23) - 350 500 mV (23) 4.0 4.0 - - V External ballast versus internal current ratio (I_BALLAST = K x Internal current) 1.5 2.0 2.5 150 350 550 mA - 140 - C VDD Voltage regulator, VDD pin VOUT-5.0 VOUT-5.0-EMC VOUT-3.3 VDROP Output Voltage VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA VDD = 5.0 V, under EMC immunity test condition VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA Drop voltage without external PNP pass transistor VDD = 5.0 V, IOUT = 100 mA VDD = 5.0 V, IOUT = 150 mA VDROP-B Drop voltage with external transistor IOUT = 200 mA (I_BALLAST + I_INTERNAL) VSUP1-3.3 VSUP/1 to maintain VDD within VOUT-3.3 specified voltage range VDD = 3.3 V, IOUT = 150 mA VDD = 3.3 V, IOUT = 200 mA, external transistor implemented K ILIM Output Current limitation, without external transistor TPW Temperature pre-warning (Guaranteed by design) TSD Thermal shutdown (Guaranteed by design) 160 - - C CEXT Range of decoupling capacitor (Guaranteed by design) 4.7 - 100 F VDDLP LP mode VDD ON, IOUT 50 mA (time limited) VDD = 5.0 V, 5.6 V VSUP 28 V 4.75 3.135 5.0 3.3 5.25 3.465 V - - 50 mA 1.0 0.1 3.0 1.0 - mA - 200 400 mV 5.5 - - V - - 0.3 V 3.0 - - V LP-IOUTDC LP-ITH VDD = 3.3 V, 5.6 V VSUP 28 V LP mode VDD ON, dynamic output current capability (Limited duration. Ref. to device description). LP VDD ON mode: Overcurrent Wake-up threshold. Hysteresis LP-VDROP LP mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration. Ref. to device description) LP-MINVS LP mode VDD ON, min VSUP operation (Below this value, a VDD, undervoltage reset may occur) VDD_OFF VDD when VSUP < VSUP-TH1, at I_VDD 10 A (Guaranteed by design) VDD_START UP VDD when VSUP VSUP-TH1, at I_VDD 40 mA (Guaranteed with parameter VSUP-TH1 (24) (23) Notes 22. Guaranteed by design. During immunity tests, according to IEC62132-4, with RF injection applied to CAN or LIN pins. No filter components on CAN or LIN pins. When immunity tests are performed with a CAN filter component (common mode choke) or LIN filter component (capacitor), the VDD specification is 5.0 V 2%. 23. 24. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout voltage parameter cannot be specified. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance. 33903/4/5 NXP Semiconductors 19 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Voltage regulator for CAN interface supply, 5.0 V-CAN pin 5V-C OUT Output voltage, VSUP/2 = 5.5 to 40 V IOUT 0 to 160 mA 4.75 5.0 5.25 V 5V-C ILIM Output Current limitation 160 280 - mA 5V-C UV Undervoltage threshold 4.1 4.5 4.7 V 5V-CTS Thermal shutdown (Guaranteed by design) 160 - - C External capacitance (Guaranteed by design) 1.0 - 100 F 4.75 3.135 5.0 3.3 5.25 3.465 V 4.2 0.06 2.75 4.5 3.0 4.70 0.12 3.135 CEXT-CAN (25) V auxiliary output, 5.0 and 3.3 V selectable pin VB-Aux, VC-Aux, Vaux VAUX VAUX-UVTH VAUX output voltage VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX undervoltage detector (VAUX configured to 5.0 V) Low Threshold Hysteresis VAUX undervoltage detector (VAUX configured to 3.3 V, default value) V VAUX-ILIM VAUX overcurrent threshold detector VAUX set to 3.3 V VAUX set to 5.0 V 250 230 360 330 450 430 mA VAUX CAP External capacitance (Guaranteed by design) 2.2 - 100 F VDD undervoltage threshold down - 90% VDD (VDD 5.0 V) VDD undervoltage threshold up - 90% VDD (VDD 5.0 V) VDD undervoltage threshold down - 90% VDD (VDD 3.3 V) VDD undervoltage threshold up - 90% VDD (VDD 3.3 V) 4.5 2.75 - 4.65 3.0 - 4.85 4.90 3.135 3.135 V (26), (28) VRST-TH2-5 VDD undervoltage reset threshold down - 70% VDD (VDD 5.0 V) 2.95 3.2 3.45 V (27), (28) VRST-HYST Hysteresis for threshold 90% VDD, 5.0 V device for threshold 70% VDD, 5.0 V device 20 10 - 150 150 mV Hysteresis 3.3 V VDD for threshold 90% VDD, 3.3 V device 10 - 150 4.0 2.75 4.5 3.0 4.85 3.135 V Undervoltage reset and reset function, RST pin VRST-TH1 VRST-LP VOL IRESET LOW RPULL-UP Notes 25. 26. 27. 28. VDD undervoltage reset threshold down - LP VDD ON mode (Note: device change to Normal Request mode). VDD 5.0 V (Note: device change to Normal Request mode). VDD 3.3 V Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V (26), (28) - 300 500 mV Current limitation, Reset activated, VRESET = 0.9 x VDD 2.5 7.0 10 mA Pull-up resistor (to VDD pin) 8.0 11 15 k Current limitation will be reported by setting a flag. Generate a Reset or an INT. SPI programmable Generate a Reset In Non-LP modes 33903/4/5 20 NXP Semiconductors ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes 2.5 - - V (29) 1.5 0.99 - - 3.5 2.31 0.5 1.0 1.5 V Undervoltage reset and reset function, RST PIN (continued) VSUP-RSTL VSUP to guaranteed reset low level VRST-VTH Reset input threshold Low threshold, VDD = 5.0 V High threshold, VDD = 5.0 V VHYST Low threshold, VDD = 3.3 V High threshold, VDD = 3.3 V Reset input hysteresis V I/O pins when function selected is output VI/O-0 HSDRP I/O-0 HS switch drop @ I = -12 mA, VSUP = 10.5 V - 0.5 1.4 V VI/O-2-3 HSDRP I/O-2 and I/O-3 HS switch drop @ I = -20 mA, VSUP = 10.5 V - 0.5 1.4 V VI/O-1 HSDRP I/O-1, HS switch drop @ I = -400 A, VSUP = 10.5 V - 0.4 1.4 V VI/O-01 LSDRP I/O-0, I/O-1 LS switch drop @ I = 400 A, VSUP = 10.5 V - 0.4 1.4 V II/O_LEAK Leakage current, I/O-x VSUP - 0.1 3.0 A I/O pins when function selected is input VI/O_NTH Negative threshold 1.4 2.0 2.9 V VI/O_PTH Positive threshold 2.1 3.0 3.8 V VI/O_HYST Hysteresis 0.2 1.0 1.4 V II/O_IN Input current, I/O VSUP/2 -5.0 1.0 5.0 A RI/O-X I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in register, 2.0 V < VI/O-X <16 V (Guaranteed by design). - 100 - k 8.1 0.1 8.6 0.25 9.0 9.1 0.5 - 125 - VSENSE input VSENSE_TH RVSENSE VSENSE undervoltage threshold (Not active in LP modes) Low Threshold High threshold Hysteresis Input resistor to GND. In all modes except in LP modes. (Guaranteed by design). V k Notes 29. Reset must be kept low 33903/4/5 NXP Semiconductors 21 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Analog MUX output VOUT_MAX Output Voltage Range, with external resistor to GND >2.0 k 0.0 - VDD - 0.5 V RMI Internal pull-down resistor for regulator output current sense 0.8 1.9 2.8 k CMUX External capacitor at MUX OUTPUT (Guaranteed by design) - - 1.0 nF Chip temperature sensor coefficient (Guaranteed by design and device characterization) VDD = 5.0 V VDD = 3.3 V 20 13.2 21 13.9 22 14.6 Chip temperature: MUX-OUT voltage VDD = 5.0 V, TA = 125 C VDD = 3.3 V, TA = 125 C 3.6 2.45 3.75 2.58 3.9 2.65 0.12 1.5 0.07 1.08 0.30 1.65 0.19 1.14 0.48 1.8 0.3 1.2 VSENSE GAIN Gain for VSENSE, with external 1.0 k 1% resistor VDD = 5.0 V VDD = 3.3 V 5.42 8.1 5.48 8.2 5.54 8.3 VSENSE OFFSET Offset for VSENSE, with external 1.0 k 1% resistor -20 - 20 5.335 7.95 5.5 8.18 5.665 8.45 3.8 5.6 - 4.0 2.0 5.8 1.3 4.2 6.2 - Internal reference voltage VDD = 5.0 V VDD = 3.3 V 2.45 1.64 2.5 1.67 2.55 1.7 Current ratio between VDD output & IOUT at MUX-OUT (IOUT at MUX-OUT = IDD out / IDD_RATIO) At IOUT = 50 mA I_OUT from 25 to 150 mA 80 62.5 97 97 115 117 SAFE low level, at I = 500 A 0.0 0.2 1.0 V - 0.0 1.0 A TEMP-COEFF VTEMP VTEMP(GD) Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) TA = -40 C, VDD = 5.0 V TA = 25 C, VDD = 5.0 V TA = -40 C, VDD = 3.3 V TA = 25 C, VDD = 3.3 V VSUP/1 RATIO VI/O RATIO VREF IDD_RATIO Divider ratio for VSUP/1 VDD = 5.0 V VDD = 3.3 V Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0) VDD = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) VDD = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0) (30) mv/C V V mV V SAFE output VOL ISAFE-IN Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 28 V. Notes 30. When C is higher than CMUX, a serial resistor must be inserted 33903/4/5 22 NXP Semiconductors ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit - 0.2 1.0 V 14 k Notes Interrupt VOL Output low voltage, IOUT = 1.5 mA RPU Pull-up resistor 6.5 10 Output high level in LP VDD ON mode (Guaranteed by design) 3.9 4.3 - 35 100 A 2.5 6.0 10 mA 1.0 V VOH-LPVDDON VMAX Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin) I SINK Sink current, VINT > 5.0 V, INT low state V MISO, MOSI, SCLK, CS pins VOL Output low voltage, IOUT = 1.5 mA (MISO) VOH Output high voltage, IOUT = -0.25 mA (MISO) - - VDD -0.9 - V VIL Input low voltage (MOSI, SCLK,CS) - - 0.3 x VDD VIH Input high voltage (MOSI, SCLK,CS) 0.7 x VDD - - V V IHZ Tri-state leakage current (MISO) -2.0 - 2.0 A IPU Pull-up current (CS) 200 370 500 A CAN logic input pins (TXD) VIH High Level Input Voltage 0.7 x VDD - VDD + 0.3 V VIL Low Level Input Voltage -0.3 - 0.3 x VDD V -850 -500 -650 -250 -200 -175 A IPDWN Pull-up Current, TXD, VIN = 0 V VDD = 5.0 V VDD = 3.3 V CAN data output pins (RXD) VOUTLOW Low Level Output Voltage IRXD = 5.0 mA 0.0 - 0.3 x VDD VOUTHIGH High Level Output Voltage IRX = -3.0 mA 0.7 x VDD - VDD IOUTHIGH High Level Output Current VRXD = VDD - 0.4 V 2.5 5.0 9.0 IOUTLOW Low Level Input Current VRXD = 0.4 V 2.5 5.0 9.0 V V mA mA 33903/4/5 NXP Semiconductors 23 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit -12 - 12 V Differential input voltage threshold 500 - 900 mV Differential input hysteresis 50 - - mV Input resistance 5.0 - 50 k Differential input resistance 10 - 100 k Input resistance matching -3.0 0.0 3.0 % VCANH CANH output voltage (45 < RBUS < 65 ) TXD dominant state TXD recessive state 2.75 2.0 3.5 2.5 4.5 3.0 V VCANL CANL output voltage (45 < RBUS < 65 ) TXD dominant state TXD recessive state 0.5 2.0 1.5 2.5 2.25 3.0 V VOH-VOL Differential output voltage (45 < RBUS < 65 ) TXD dominant state TXD recessive state 1.5 -0.5 2.0 0.0 3.0 0.05 V ICANH CAN H output current capability - Dominant state - - -30 mA ICANL CAN output pins (CANH, CANL) VCOM Bus pins common mode voltage for full functionality VCANH-VCANL VDIFF-HYST RIN RIN-DIFF RIN-MATCH CAN L output current capability - Dominant state 30 - - mA ICANL-OC CANL overcurrent detection - Error reported in register 75 120 195 mA ICANH-OC CANH overcurrent detection - Error reported in register -195 -120 -75 mA RINSLEEP CANH, CANL input resistance to GND, device supplied, CAN in Sleep mode, V_CANH, V_CANL from 0 to 5.0 V 5.0 - 50 k VCANLP CANL, CANH output voltage in LP VDD OFF and LP VDD ON modes Notes -0.1 0.0 0.1 V ICAN-UN_SUP1 CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered (VSUP, VDD, 5V-CAN: open). - 3.0 10 A (31) ICAN-UN_SUP2 CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device unpowered (VSUP, VDD, 5V-CAN: open). - - 250 A (31) VDIFF-R-LP Differential voltage for recessive bit detection in LP mode - - 0.4 V (32) VDIFF-D-LP Differential voltage for dominant bit detection in LP mode 1.15 - - V (32) CANH and CANL diagnostic information VLG CANL to GND detection threshold 1.6 1.75 2.0 V VHG CANH to GND detection threshold 1.6 1.75 2.0 V VLVB CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V - VSUP -2.0 - V VHVB CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V - VSUP -2.0 - V VL5 CANL to VDD detection threshold 4.0 VDD -0.43 - V VH5 CANH to VDD detection threshold 4.0 VDD -0.43 - V Notes 31. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization. 32. Guaranteed by design and device characterization. 33903/4/5 24 NXP Semiconductors ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit 0.3 x VDD 0.45 x VDD 0.5 x VDD 0.5 x VDD 0.7 x VDD 0.55 x VDD V - 0.0 - 5.0 200 A - 1.0 1.4 V Notes SPLIT VSPLIT ILSPLIT Output voltage Loaded condition ISPLIT = 500 A Unloaded condition Rmeasure > 1.0 M Leakage current -12 V < VSPLIT < +12 V -22 to -12 V < VSPLIT < +12 to +35 V LIN terminals (LIN-T/1, LIN-T2) VLT_HSDRP LIN-T1, LIN-T2, HS switch drop @ I = -20 mA, VSUP > 10.5 V LIN1 & LIN2 33903D/5D pin - LIN 33903S/5S pin (parameters guaranteed for VSUP/1, VSUP2 7.0 V VSUP 18 V) VBAT Operating Voltage Range 8.0 - 18 V VSUP Supply Voltage Range 7.0 - 18 V Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V 40 90 200 mA -1.0 - - mA IBUS_LIM IBUS_PAS_DOM Input Leakage Current at the receiver Driver off; VBUS = 0 V; VBAT = 12 V IBUS_PAS_REC Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS VBAT - - 20 IBUS_NO_GND Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (Guaranteed by design) -1.0 - 1.0 mA IBUSNO_BAT VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition). (Guaranteed by design) - - 100 A VBUSDOM Receiver Dominant State - - 0.4 VSUP VBUSREC Receiver Recessive State 0.6 - - VSUP VBUS_CNT Receiver Threshold Center (VTH_DOM + VTH_REC)/2 0.475 0.5 0.525 VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) - - 0.175 VSUP VBUSWU LIN Wake-up threshold from LP VDD ON or LP VDD OFF mode - 5.3 5.8 V RSLAVE LIN Pull-up Resistor to VSUP 20 30 60 k TLINSD Overtemperature Shutdown (Guaranteed by design) 140 160 180 C - 10 - C VHYS TLINSD_HYS Overtemperature Shutdown Hysteresis (Guaranteed by design) A 33903/4/5 NXP Semiconductors 25 ELECTRICAL CHARACTERISTICS 5.3 Dynamic electrical characteristics Table 7. Dynamic electrical characteristics Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes SPI timing FREQ SPI Operation Frequency (MISO cap = 50 pF) 0.25 - 4.0 MHz tPCLK SCLK Clock Period 250 - N/A ns tWSCLKH SCLK Clock High Time 125 - N/A ns tWSCLKL SCLK Clock Low Time 125 - N/A ns tLEAD Falling Edge of CS to Rising Edge of SCLK `C' and `D' versions All others 30 550 - N/A N/A ns tLEAD Falling Edge of CS to Rising Edge of SCLK when CS_low flag is set to `1' `C' and `D' versions All others 0.030 0.55 - 2.5 2.5 tLAG Falling Edge of SCLK to Rising Edge of CS 30 - N/A ns tSISU MOSI to Falling Edge of SCLK 30 - N/A ns tSIH Falling Edge of SCLK to MOSI 30 - N/A ns tRSO MISO Rise Time (CL = 50 pF) - - 30 ns tFSO MISO Fall Time (CL = 50 pF) - - 30 ns tSOEN tSODIS Time from Falling to MISO Low-impedance Time from Rising to MISO High-impedance - - 30 30 ns tVALID Time from Rising Edge of SCLK to MISO Data Valid - - 30 ns s tCSLOW Delay between falling and rising edge on CS `C' and `D' versions All others 1.0 5.5 - N/A N/A s tCS-TO CS Chip Select Low Timeout Detection 2.0 - - ms Supply, voltage regulator, reset VSUP undervoltage detector threshold deglitcher 30 50 100 s tRISE-ON Rise time at turn ON. VDD from 1.0 to 4.5 V. 2.2 F at the VDD pin. 50 250 800 s tRST-DGLT Deglitcher time to set RST pin low 20 30 40 s VDD undervoltage (SPI selectable) short, default at power on when BATFAIL bit set medium medium long long 0.9 4.0 8.5 17 1.0 5.0 10 20 1.4 6.0 12 24 Watchdog reset 0.9 1.0 1.4 ms Deglitcher time (Guaranteed by design) 19 30 41 s Undervoltage deglitcher time 30 - 100 s tVS_LOW1/2_DGLT Reset pulse duration tRST-PULSE tRST-WD ms I/O input tIODT VSENSE input tBFT 33903/4/5 26 NXP Semiconductors ELECTRICAL CHARACTERISTICS Table 7. Dynamic electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit INT pulse duration (refer to SPI for selection. Guaranteed by design) short (25 to 125 C) short (-40 C) long (25 to 125 C) long (-40 C) 20 20 90 90 25 25 100 100 35 40 130 140 tD_NM Delay for SPI Timer A, Timer B or Timer C write command after entering Normal mode (No command should occur within tD_NM. tD_NM delay definition: from CS rising edge of "Go to Normal mode (i.e. 0x5A00)" command to CS falling edge of "Timer write" command) 60 - - s tTIMING-ACC Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense period and active time, Cyclic Interrupt period, LP mode overcurrent (unless otherwise noted) -10 - 10 % Notes Interrupt tINT-PULSE s State diagram timings (36) CAN dynamic characteristics tDOUT TXD Dominant State Timeout 300 600 1000 s tDOM Bus dominant clamping detection 300 600 1000 s tLRD Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) 60 120 210 ns tTRD Propagation delay TXD to CAN, recessive to dominant - 70 110 ns tRRD Propagation delay CAN to RXD, recessive to dominant - 45 140 ns tLDR Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) 100 120 200 ns tTDR Propagation delay TXD to CAN, dominant to recessive - 75 150 ns tRDR Propagation delay CAN to RXD, dominant to recessive - 50 140 ns tLOOP-MSL Loop time TXD to RXD, Medium Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive - 200 200 - ns tLOOP-SSL Loop time TXD to RXD, Slow Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive - 300 300 - ns tCAN-WU1-F CAN Wake-up filter time, single dominant pulse detection (See Figure 35) 0.5 2.0 5.0 s (33) tCAN-WU3-F CAN Wake-up filter time, 3 dominant pulses detection 300 - - ns (34) - - 120 s (35) tCAN-WU3-TO CAN Wake-up filter time, 3 dominant pulses detection timeout (See Figure 36) Notes 33. No Wake-up for single pulse shorter than tCAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max. 34. Each pulse should be greater than tCAN-WU3-F min. Guaranteed by design, and device characterization. 35. The 3 pulses should occur within tCAN-WU3-TO. Guaranteed by design, and device characterization. 36. Guaranteed by design. 33903/4/5 NXP Semiconductors 27 ELECTRICAL CHARACTERISTICS Table 7. Dynamic electrical characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 28 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes LIN physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec according to lin physical layer specification Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . See Figure 18, page 30. D1 Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 s, 7.0 V VSUP 18 V D2 0.396 - - - - 0.581 Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 s, 7.6 V VSUP 18 V LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec according to lin physical layer specification Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds. See Figure 19, page 31. D3 Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 s, 7.0 V VSUP 18 V D4 0.417 - - - - 0.590 - 20 - Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 s, 7.6 V VSUP 18 V LIN physical layer: driver characteristics for fast slew rate SRFAST LIN Fast Slew Rate (Programming Mode) V / s LIN physical layer: characteristics and wake-up timings. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . See Figure 18, page 30. t REC_PD t REC_SYM t PROPWL Propagation Delay and Symmetry (See Figure 18, page 30 and Figure 19, page 31) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See Figure 20, page 30 for LP VDD OFF mode and Figure 21, page 31 for LP mode) s - 2.0 4.2 - 6.0 2.0 42 70 95 t WAKE_LPVDDOFF Bus Wake-up Event Reported From LP VDD OFF mode - - 1500 t WAKE_LPVDDON From LP VDD ON mode 1.0 - 12 0.65 1.0 1.35 t TXDDOM TXD Permanent Dominant State Delay (Guaranteed by design) s s s 33903/4/5 28 NXP Semiconductors ELECTRICAL CHARACTERISTICS 5.4 Timing diagrams tPCLK CS tWCLKH tLEAD tLAG SCLK tWCLKL tSISU MOSI Undefined tSIH Di 0 Di n Don't Care Don't Care tVALID tSODIS tSOEN MISO Do 0 Do n tCSLOW Figure 14. SPI timing tLRD TXD 0.7 x VDD tLDR 0.3 x VDD RXD 0.7 x VDD 0.3 x VDD Figure 15. CAN signal propagation loop delay TXD to RXD TXD tTRD 0.7 x VDD tTDR 0.3 x VDD VDIFF RXD 0.9 V tRRD 0.3 x VDD 0.5 V tRDR 0.7 x VDD Figure 16. CAN signal propagation delays TXD to CAN and CAN to RXD 33903/4/5 NXP Semiconductors 29 ELECTRICAL CHARACTERISTICS . 12 V 10 F VSUP 5 V_CAN 22 F 100 nF CANH Signal generator TXD RBUS 60 CBus 100 pF CANL RXD 15 pF GND SPLIT All pins are not shown Figure 17. Test circuit for CAN timing characteristics TXD tBIT tBIT tBUS_DOM(MAX) VLIN_REC THREC(MAX) 74.4% VSUP THDOM(MAX) 58.1% VSUP tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) Thresholds of receiving node 2 42.2% VSUP 28.4% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 18. LIN timing measurements for normal slew rate 33903/4/5 30 NXP Semiconductors ELECTRICAL CHARACTERISTICS TXD tBIT tBIT tBUS_DOM(MAX) VLIN_REC THREC(MAX) 77.8% VSUP THDOM(MAX) 61.6% VSUP tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) Thresholds of receiving node 2 38.9% VSUP 25.1% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDF(2) tREC_PDR(2) Figure 19. LIN timing measurements for slow slew rate V REC V BUSWU LIN 0.4 V SUP Dominant level 3V VDD T PROPWL T WAKE Figure 20. LIN wake-up LP VDD off mode timing V LIN_REC LIN V BUSWU 0.4 V SUP Dominant level IRQ T PROPWL T WAKE IRQ stays low until SPI reading command Figure 21. LIN Wake-up LP VDD ON Mode Timing 33903/4/5 NXP Semiconductors 31 FUNCTIONAL DESCRIPTION 6 Functional description 6.1 Introduction The MC33903_4_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for the additional ICs such as sensors, CAN transceiver. - Built in enhanced high speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostic, protection, and fail-safe operation mode. - Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection. - Innovative hardware configurable fail-safe state machine solution. - Multiple LP modes, with low current consumption. - Family concept with pin compatibility; with and without LIN interface devices. 6.2 Functional pin description 6.2.1 Power supply (VSUP/1 and VSUP2) Note: VSUP1 and VSUP2 supplies are externally available on all devices except the 33903D, 33903S, and 33903P, where these are connected internally. VSUP1 is the input pin for the internal supply and the VDD regulator. VSUP2 is the input pin for the 5 V-CAN regulator, LIN's interfaces and I/O functions. The VSUP block includes over and undervoltage detections which can generate interrupt. The device includes a loss of battery detector connected to VSUP/1. Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset). 6.2.2 VDD voltage regulator (VDD) The regulator has two main modes of operation (Normal mode and LP mode). It can operate with or without an external PNP transistor. In Normal mode, without external PNP, the max DC capability is 150 mA. Current limitation, temperature pre-warning flag and overtemperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0 V is controlled. Output voltage is 5.0 V. A 3.3 V option is available via dedicated part number. If current higher than 150 mA is required, an external PNP transistor must be connected to VE (PNP emitter) and VB (PNP base) pins, in order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See External transistor Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature, maximum supply and thermal resistance. Typically, above 100-200 mA, an external ballast transistor is recommended. 6.2.3 VDD regulator in LP mode When the device is set in LP VDD ON mode, the VDD regulator is able to supply the MCU with a DC current below typically 1.5 mA (LPTransient current can also be supplied up to a tenth of a mA. Current in excess of 1.5 mA is detected, and this event is managed by the device logic (Wake-up detection, timer start for overcurrent duration monitoring or watchdog refresh). ITH). 6.2.4 External transistor Q1 (VE and VB) The device has a dedicated circuit to allow usage of an external "P" type transistor, with the objective to share the power dissipation between the internal transistor of the VDD regulator and the external transistor. The recommended bipolar PNP transistor is MJD42C or BCP52-16. When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI. The device is able to operate without an external transistor. In this case, the VE and VB pins must remain open. 33903/4/5 32 NXP Semiconductors FUNCTIONAL DESCRIPTION 6.2.5 5 V-CAN voltage regulator for CAN and analog MUX This regulator is supplied from the VSUP/2 pin. A capacitor is required at 5 V-CAN pin. Analog MUX and part of the LIN interfaces are supplied from 5 V-CAN. Consequently, the 5 V-CAN must be ON in order to have Analog MUX operating and to have the LIN interface operating in TXD/RXD mode. The 5 V-CAN regulator is OFF by default and must be turned ON by SPI. In Debug mode, the 5 V-CAN is ON by default. 6.2.6 V auxiliary output, 5.0 and 3.3 V selectable (VB-Aux, VC-Aux, and VCaux) - Q2 The VAUX block is used to provide an auxiliary voltage output, 5.0 or 3.3 V, selectable by the SPI. It uses an external PNP pass transistor for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16. An overcurrent and undervoltage detectors are provided. VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and overcurrent information will disable VAUX, and are reported in the SPI and can generate INT. VAUX is OFF by default and must be turned ON by the SPI. 6.2.7 Undervoltage reset and reset function (RST) The RST pin is an open drain structure with an internal pull-up resistor. The LS driver has limited current capability when asserted low, in order to tolerate a short to 5.0 V. The RST pin voltage is monitored in order to detect failure (e.g. RST pin shorted to 5.0 V or GND). The RST pin reports an undervoltage condition to the MCU at the VDD pin, as a RST failure in the watchdog refresh operation. VDD undervoltage reset also operates in LP VDD ON mode. Two VDD undervoltage thresholds are included. The upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected by the SPI. When "RST-TH2-5"is selected, in Normal mode, an INT is asserted when VDD falls below "RST-TH1-5", then, when VDD falls below "RST-TH2-5" a Reset will occur. This will allow the MCU to operate in a degraded mode (i.e., with 4.0 V VDD). 6.2.8 I/O pins (I/O-0: I/O-3) I/Os are configurable input/output pins. They can be used for small loads or to drive external transistors. When used as output drivers, the I/Os are either a HS or LS type. They can also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set as inputs. They include overload protection by temperature or excess of a voltage drop. When I/O-0/-1/-2/-3 voltage is greater than VSUP/2 voltage, the leakage current (II/O_LEAK) parameter is not applicable * I/O-0 and I/O-1 will have current flowing into the device through three diodes limited by an 80 kOhm resistor (in series). * I/O-2 and I/O-3 will have unlimited current flowing into the device through one diode. In LP mode, the state of the I/O can be turned ON or OFF, with extremely low power consumption (except when there is a load). Protection is disabled in LP mode. When cyclic sense is used, I/O-0 is the HS/LS switch, I/O-1, -2 and -3 are the wake inputs. I/O-2 and I/O-3 pins share the LIN Master pin function. 6.2.9 VSENSE input (VSENSE) This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to GND. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin. 6.2.10 MUX-output (MUXOUT) The MUX-OUT pin (Figure 22) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX-OUT is selected via the SPI, from one of the following functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V reference, die temperature sensor, VDD current copy. Voltage divider or amplifier is inserted in the chain, as shown in Figure 22. For the VDD current copy, a resistor must be added to the MUX-OUT pin, to convert current into voltage. Device includes an internal 2.0 k resistor selectable by the SPI. Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to VDD (max 3.3 V for 3.3 V part numbers). The MUX-OUT buffer is supplied from 5 V-CAN regulator, so the 5 V-CAN regulator must be ON in order to have: 33903/4/5 NXP Semiconductors 33 FUNCTIONAL DESCRIPTION 1) MUX-OUT functionality and 2) SPI selection of the analog function. If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND and the SPI command that selects one of the analog inputs is ignored. Delay must be respected between SPI commands for 5 V-CAN turned ON and SPI to select MUX-OUT function. The delay depends mainly upon the 5 V-CAN capacitor and load on 5 V-CAN. The delay can be estimated using the following formula: delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN. C = cap at 5 V-CAN regulator, U = 5.0 V, I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator (parameter 5 V-C ILIM). Note: As there is no link between 5VCAN and VDD, the 5VCAN can starts after both the VDD and RSTB are released. To ensure the MCU can use MUXOUT output information, it must verify the presence of the 5VCAN. This can be done for instance by checking the 5VCAN undervoltage flag (bit4 of the 0xDF00 SPI command). VBAT D1 S_in VDD-I_COPY Multiplexer VSUP/1 VSENSE S_iddc S_in 5 V-CAN 5 V-CAN RSENSE 1.0 k MCU MUX-OUT I/O-0 A/D in buffer S_in S_g3.3 S_g5 S_I/O_att I/O-1 S_in Temp VREF: 2.5 V S_I/O_att RMI S_ir RM(*) (*)Optional All swicthes and resistor are configured and controlled via the SPI RM: internal resistor connected when VREG current monitor is used S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions S_iddc to select VDD regulator current copy S_in1 for LP mode resistor bridge disconnection S_ir to switch on/off of the internal RMI resistor S_I/O_att for I/O-0 and I/O-1 attenuation selection Figure 22. Analog multiplexer block diagram 6.2.11 DGB (DGB) and debug mode 6.2.11.1 Primary function It is an input used to set the device in Debug mode. This is achieved by applying a voltage between 8.0 and 10 V at the DEBUG pin and then, powering up the device (See State diagram). When the device leaves the INIT Reset mode and enters into INIT mode, it detects the voltage at the DEBUG pin to be between a range of 8.0 to 10 V, and activates the Debug mode. When Debug mode is detected, no Watchdog SPI refresh commands are necessary. This allows an easy debug of the hardware and software routines (i.e. SPI commands). When the device is in Debug mode it is reported by the SPI flag. While in Debug mode, and the voltage at DBG pin falls below the 8.0 to 10 V range, the Debug mode is left, and the device starts the watchdog operation, and expects the proper watchdog refresh. The Debug mode can be left by SPI. This is recommended to avoid staying in Debug mode when an unwanted Debug mode selection (FMEA pin) is present. The SPI command has a higher priority than providing 8.0 to 10 V at the DEBUG pin. 33903/4/5 34 NXP Semiconductors FUNCTIONAL DESCRIPTION 6.2.11.2 Secondary function The resistor connected between the DBG pin and the GND selects the Fail-Safe mode operation. DBG pin can also be connected directly to GND (this prevents the usage of Debug mode). Flexibility is provided to select SAFE output operation via a resistor at the DBG pin or via a SPI command. The SPI command has higher priority than the hardware selection via Debug resistor. When the Debug mode is selected, the SAFE modes cannot be configured via the resistor connected at DBG pin. 6.2.12 SAFE 6.2.12.1 Safe output pin This pin is an output and is asserted low when a fault event occurs. The objective is to drive electrical safe circuitry and set the ECU in a known state, independent of the MCU and SBC, once a failure has been detected. The SAFE output structure is an open drain, without a pull-up. 6.2.13 Interrupt (INT) The INT output pin is asserted low or generates a low pulse when an interrupt condition occurs. The INT condition is enabled in the INT register. The selection of low level or pulse and pulse duration are selected by SPI. No current will flow inside the INT structure when VDD is low, and the device is in LP VDD OFF mode. This allows the connection of an external pull-up resistor and connection of an INT pin from other ICs without extra consumption in unpowered mode. INT has an internal pull-up structure to VDD. In LP VDD ON mode, a diode is inserted in series with the pull-up, so the high level is slightly lower than in other modes. 6.2.14 CANH, CANL, SPLIT, RXD, TXD These are the pins of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is provided in the document. 6.2.15 LIN, LIN-T, TXDL and RXDL These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces. The MC33903, MC33903P, and MC33904 do not have a LIN interface. However, the MC33903S/5S (S = Single) and MC33903D/5D (D=Dual) contain 1 and 2 LIN interfaces, respectively. LIN, LIN1 and LIN2 pins are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TXD, TXD-L1 and TXD-L2 and RXD, RXD-L1 and RXD-L2 pins. The device also includes one or two HS switches to VSUP/2 pin which can be used as a LIN master termination switch. Pins LINT, LINT1 and LINT-2 pins are the same as I/O-2 and I/O-3. 33903/4/5 NXP Semiconductors 35 FUNCTIONAL DEVICE OPERATION 7 Functional device operation 7.1 Mode and state description The device has several operation modes. The transitions and conditions to enter or leave each mode are illustrated in the state diagram. 7.1.1 INIT reset This mode is automatically entered after the device is "powered on". In this mode, the RST pin is asserted low, for a duration of typically 1.0 ms. Control bits and flags are `set' to their default reset condition. The BATFAIL is set to indicate the device is coming from an unpowered condition, and all previous device configurations are lost and "reset" the default value. The duration of the INIT reset is typically 1.0 ms. INIT reset mode is also entered from INIT mode if the expected SPI command does not occur in due time (Ref. INIT mode), and if the device is not in the debug mode. 7.1.2 INIT This mode is automatically entered from the INIT Reset mode. In this mode, the device must be configured via SPI within a time of 256 ms max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be, and can only be configured during INIT mode. Other registers can be written in this and other modes. Once the INIT register configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal mode. If the SPI watchdog refresh does not occur within the 256 ms period, the device will return into INIT Reset mode for typically 1.0 ms, and then re enter into INIT mode. Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration. When INIT mode is left by a SPI watchdog refresh command, it is only possible to re-enter the INIT mode using a secured SPI command. In INIT mode, the CAN, LIN1, LIN2, VAUX, I/O_x and Analog MUX functions are not operating. The 5 V-CAN is also not operating, except if the Debug mode is detected. 7.1.3 Reset In this mode, the RST pin is asserted low. Reset mode is entered from Normal mode, Normal Request mode, LP VDD on mode and from the Flash mode when the watchdog is not triggered, or if a VDD low condition is detected. The duration of reset is typically 1.0 ms by default. You can define a longer Reset pulse activation only when the Reset mode is entered following a VDD low condition. Reset pulse is always 1.0 ms, when reset mode is entered due to wrong watchdog refresh command. Reset mode can be entered via the secured SPI command. 7.1.4 Normal request This mode is automatically entered after RESET mode, or after a Wake-up from LP VDD ON mode. A watchdog refresh SPI command is necessary to transition to NORMAL mode. The duration of the Normal request mode is 256 ms when Normal Request mode is entered after RESET mode. Different durations can be selected by SPI when normal request is entered from LP VDD ON mode. If the watchdog refresh SPI command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter into RESET mode for a duration of typically 1.0 ms. Note: in init reset, init, reset and normal request modes as well as in LP modes, the VDD external PNP is disabled. 7.1.5 Normal In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request mode, or from INIT mode. During Normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. When an incorrect or missing watchdog refresh command is initiated, the device will enter into Reset mode. While in Normal mode, the device can be set to LP modes (LP VDD ON or LP VDD OFF) using the SPI command. Dedicated, secured SPI commands must be used to enter from Normal mode to Reset mode, INIT mode or Flash mode. 33903/4/5 36 NXP Semiconductors FUNCTIONAL DEVICE OPERATION 7.1.6 Flash In this mode, the software watchdog period is extended up to typically 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to refresh the watchdog. The flash mode is entered by Secured SPI command and is left by SPI command. Device will enter into Reset mode. When an incorrect or missing watchdog refresh command device will enter into Reset mode. An interrupt can be generated at 50% of the watchdog period. CAN interface operates in Flash mode to allow flash via CAN bus, inside the vehicle. 7.1.7 Debug Debug is a special operation mode of the device which allows for easy software and hardware debugging. The debug operation is detected after power up if the DBG pin is set to 8.0 to 10 V range. When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT mode, watchdog refresh of Normal mode and Flash mode, Normal Request time out (256 ms or user defined value) are not operating and will not lead to transition into INIT reset or Reset mode. When the device is in Debug mode, the SPI command can be sent without any time constraints with respect to the watchdog operation and the MCU program can be "halted" or "paused" to verify proper operation. Debug can be left by removing 8 to 10 V from the DEBUG pin, or by the SPI command (Ref. to MODE register). The 5 V-CAN regulator is ON by default in Debug mode. 7.2 LP modes The device has two main LP modes: LP mode with VDD OFF, and LP mode with VDD ON. Prior to entering into LP mode, I/O and CAN Wake-up flags must be cleared (Ref. to mode register). If the Wake-up flags are not cleared, the device will not enter into LP mode. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared, in order to meet the LP current consumption specification. 7.2.1 LP - VDD off In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered using SPI. It can also be entered by an automatic transition due to fail-safe management. 5 V-CAN and VAUX regulators are also turned OFF. When the device is in LP VDD OFF mode, it monitors external events to Wake-up and leave the LP mode. The Wake-up events can occur from: * CAN * LIN interface, depending upon device part number * Expiration of an internal timer * I/O-0, and I/O-1 inputs, and depending upon device part number and configuration, I/O-2 and/or -3 input * Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and -3 input, associated by I/O-0 activation When a Wake-up event is detected, the device enters into Reset mode and then into Normal Request mode. The Wake-up sources are reported to the device SPI registers. In summary, a Wake-up event from LP VDD OFF leads to the VDD regulator turned ON, and the MCU operation restart. 7.2.2 LP - VDD ON In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to 100 A or a few mA, as the ECU is in reduced power operation mode. During this mode, the 5 V-CAN and VAUX regulators are OFF. The optional external PNP at VDD will also be automatically disabled when entering this mode. The same Wake-up events as in LP VDD OFF mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP VDD on mode. In addition, two additional Wake-up conditions are available. * Dedicated SPI command. When device is in LP VDD ON mode, the Wake-up by SPI command uses a write to "Normal Request mode", 0x5C10. * Output current from VDD exceeding LP-ITH threshold. 33903/4/5 NXP Semiconductors 37 FUNCTIONAL DEVICE OPERATION In LP VDD ON mode, the device is able to source several tenths of mA DC. The current source capability can be time limited, by a selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceed the output current threshold typically 1.5 mA. This allows for instance, a periodic activation of the MCU, while the device remains in LP VDD on mode. If the duration exceed the selected time (ex 32 ms), the device will detect a Wake-up. Wake-up events are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation. 7.2.2.1 Watchdog function in LP VDD on mode It is possible to enable the watchdog function in LP VDD ON mode. In this case, the principle is timeout. Refresh of the watchdog is done either by: * a dedicated SPI command (different from any other SPI command or simple CS activation which would Wake-up - Ref. to the previous paragraph) * or by a temporary (less than 32 ms max) VDD over current Wake-up (IDD > 1.5 mA typically). As long as the watchdog refresh occurs, the device remains in LP VDD on mode. 7.2.2.2 Mode transitions Mode transitions are either done automatically (i.e. after a timeout expired or voltage conditions), or via a SPI command, or by an external event such as a Wake-up. Some mode changes are performed using the Secured SPI commands. 33903/4/5 38 NXP Semiconductors FUNCTIONAL DEVICE OPERATION 7.3 State diagram VSUP/1 rise > VSUP-TH1 & VDD > VDD_UVTH VSUP fall POWER DOWN INIT Reset start T_IR (T_IR = 1.0 ms) T_INIT expired or VDD<VDD_UVTH VSUP fall watchdog refresh by SPI T_IR expired INIT FLASH start T_WDF (config) Ext reset SPI secured or T_WDF expired or VDD<VDD_UVTH start T_INIT (T_INIT = 256ms) SPI secured (3) SPI write (0x5A00) (watchdog refresh) SPI secured (3) NORMAL (4) RESET Wake-up Debug mode detection start T_R (1.0 ms or config) VDD<VDD_UVTH or T_WD expired or watchdog failure (1) or SPI secured or VDD TSD T_NR expired T_R expired & VDD>VDD_UVTH start T_WDN (T_WDN = config) SPI write (0x5A00) (watchdog refresh) NORMAL REQUEST start T_NR (256 ms or config) watchdog refresh by SPI SPI LP VDD ON Wake-up (5) if enable watchdog refresh by SPI start T_WDL (2) T_OC expired or Wake-up I-DD<IOC (1.5 mA) VDD<VDD_UVTHLP LP VDDON IDD > 1.5 mA I-DD>IOC (1.5 mA) start T_OC time T_WDL expired or VDD<VDD_UVTHLP SPI LP VDD OFF (1) watchdog refresh in closed window or enhanced watchdog refresh failure FAIL-SAFE DETECTED (2) If enable by SPI, prior to enter LP VDD ON mode (3) Ref. to "SPI secure" description (4) VDD external PNP is disable in all mode except Normal and Flash modes. (5) Wake-up from LP VDD ON mode by SPI command is done by a SPI mode change: 0X5C10 Figure 23. State diagram 33903/4/5 NXP Semiconductors 39 FUNCTIONAL DEVICE OPERATION 7.4 Mode change 7.4.1 `Secured SPI' description A request is done by a SPI command, the device provide on MISO an unpredictable `random code'. Software must perform a logical change on the code and return it to the device with the new SPI command to perform the desired action. The `random code' is different at every exercise of the secured procedure and can be read back at any time. The secured SPI uses the Special MODE register for the following transitions: - from Normal mode to INT mode - from Normal mode to Flash mode - from Normal mode to Reset mode (reset request). "Random code" is also used when the `advance watchdog' is selected. 7.4.2 Changing of device critical parameters Some critical parameters are configured one time at device power on only, while the batfail flag is set in the INIT mode. If a change is required while device is no longer in INIT mode, device must be set back in INIT mode using the "SPI secure" procedure. 7.5 Watchdog operation 7.5.1 In normal request mode In Normal Request mode, the device expects to receive a watchdog configuration before the end of the normal request time out period. This period is reset to a long (256 ms) after power on and when BATFAIL is set. The device can be configured to a different (shorter) time out period which can be used after Wake-up from LP VDD on mode. After a software watchdog reset, the value is restored to 256 ms, in order to allow for a complete software initialization, similar to a device power up. In Normal Request mode the watchdog operation is "timeout" only and can be triggered/observed any time within the period. 7.5.2 Watchdog type selection Three types of watchdog operation can be used: - Window watchdog (default) - Timeout operation - Advanced The selection of watchdog is performed in INIT mode. This is done after device power up and when the BATFAIL flag is set. The Watchdog configuration is done via the SPI, then the Watchdog mode selection content is locked and can be changed only via a secured SPI procedure. 7.5.2.1 Window watchdog operation The window watchdog is available in Normal mode only. The watchdog period selection can be kept (SPI is selectable in INIT mode), while the device enters into LP VDD ON mode. The watchdog period is reset to the default long period after BATFAIL. The period and the refresh of watchdog are done by the SPI. A refresh must be done in the open window of the period, which starts at 50% of the selected period and ends at the end of the period. If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters into Reset mode. 7.5.2.2 Watchdog in debug mode When the device is in Debug mode (entered via the DBG pin), the watchdog continues to operate but does not affect the device operation by asserting a reset. For the user, operation appears without the watchdog. When Debug mode is left by software (SPI mode reg), the watchdog period starts at the end of the SPI command. When Debug mode is left by hardware (DBG pin below 8-10 V), the device enters into Reset mode. 33903/4/5 40 NXP Semiconductors FUNCTIONAL DEVICE OPERATION 7.5.2.3 Watchdog in flash mode During Flash mode, watchdog can be set to a long timeout period. Watchdog is timeout only and an INT pulse can be generated at 50% of the time window. 7.5.2.4 Advance watchdog operation When the Advance watchdog is selected (at INIT mode), the refresh of the watchdog must be done using a random number and with 1, 2, or 4 SPI commands. The number for the SPI command is selected in INIT mode. The software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. The random byte write can be performed in 1, 2, or 4 different SPI commands. If one command is selected, all eight bits are written at once. If two commands are selected, the first write command must include four of the eight bits of the inverted random byte. The second command must include the next four bits. This completes the watchdog refresh. If four commands are selected, the first write command must include two of the eight bits of the inverted random byte. The second command must include the next two bits, the 3rd command must include the next two, and the last command, must include the last two. This completes the watchdog refresh. When multiple writes are used, the most significant bits are sent first. The latest SPI command needs to be done inside the open window time frame, if window watchdog is selected. 7.5.3 Detail SPI operation and SPI commands for all watchdog types. All SPI commands and examples do not use parity functions. In INIT mode, the watchdog type (window, timeout, advance and number of SPI commands) is selected using the register Init watchdog, bits 1, 2 and 3. The watchdog period is selected using the TIM_A register. The watchdog period selection can also be done in Normal mode or in Normal Request mode. Transition from INIT mode to Normal mode or from Normal Request mode to Normal mode is done using a single watchdog refresh command (SPI 0x 5A00). While in Normal mode, the Watchdog Refresh Command depends upon the watchdog type selected in INIT mode. They are detailed in the paragraph below: 7.5.3.1 Simple watchdog The Refresh command is 0x5A00. It can be send any time within the watchdog period, if the timeout watchdog operation is selected (INITwatchdog register, bit 1 WD N/Win = 0). It must be send in the open window (second half of the period) if the Window Watchdog operation was selected (INIT-watchdog register, bit 1 WD N/Win = 1). 7.5.3.2 Advance watchdog The first time the device enters into Normal mode (entry on Normal mode using the 0x5A00 command), Random (RNDM) code must be read using the SPI command, 0x1B00. The device returns on MISO second byte the RNDM code. The full 16 bits MISO is called 0x XXRD. RD is the complement of the RD byte. 7.5.3.3 Advance watchdog, refresh by 1 SPI command The refresh command is 0x5ARD. During each refresh command, the device will return on MISO, a new Random Code. This new Random Code must be inverted and send along with the next refresh command. It must be done in an open window, if the Window operation was selected. 7.5.3.4 Advance watchdog, refresh by two SPI commands The refresh command is split in two SPI commands. The first partial refresh command is 0x5Aw1, and the second is 0x5Aw2. Byte w1 contains the first four inverted bits of the RD byte plus the last four bits equal to zero. Byte w2 contains four bits equal to zero plus the last four inverted bits of the RD byte. During this second refresh command the device returns on MISO a new Random Code. This new random code must be inverted and send along with the next two refresh commands and so on. The second command must be done in an open window if the Window operation was selected. 33903/4/5 NXP Semiconductors 41 FUNCTIONAL DEVICE OPERATION 7.5.3.5 Advance watchdog, refresh by four SPI commands The refresh command is split into four SPI commands. The first partial refresh command is 0x5Aw1, the second is 0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4. Byte w1 contains the first two inverted bits of the RD byte, plus the last six bits equal to zero. Byte w2 contains two bits equal to zero, plus the next two inverted bits of the RD byte, plus four bits equal to zero. Byte w3 contains four bits equal to zero, plus the next two inverted bits of the RD byte, plus two bits equal to zero. Byte w4 contains six bits equal to zero, plus the next two inverted bits of the RD byte. During this fourth refresh command, the device will return, on MISO, a new Random Code. This new Random Code must be inverted and send along with the next four refresh commands. The fourth command must be done in an open window if the Window operation was selected. 7.5.4 Proper response to INT During a device detect upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within two watchdog periods. This feature must be enabled by SPI using the INIT watchdog register bit 7. 33903/4/5 42 NXP Semiconductors FUNCTIONAL DEVICE OPERATION 7.6 Functional block operation versus mode Table 8. Device block operation for each state State VDD 5 V-CAN I/O-X VAUX CAN LIN1/2 Power down OFF OFF OFF OFF High-impedance High-impedance OFF OFF: CAN termination 25 k to GND Transmitter / receiver /Wake-up OFF OFF: internal 30 k pull-up active. Transmitter: receiver / Wake-up OFF. LIN term OFF Init Reset ON OFF HS/LS off Wake-up disable INIT ON OFF (38) WU disable OFF OFF OFF Reset ON Keep SPI config WU disable OFF OFF OFF Normal Request ON Keep SPI config WU disable OFF OFF OFF Normal ON SPI config SPI config WU SPI config SPI config SPI config SPI config LP VDD OFF OFF OFF user defined WU SPI config OFF OFF + Wake-up en/dis OFF + Wake-up en/dis LP VDD ON ON(37) OFF user defined WU SPI config OFF OFF + Wake-up en/dis OFF + Wake-up en/dis SAFE output low: Safe case A safe case A:ON safe case B: OFF A: Keep SPI config, B: OFF HS/LS off Wake-up by change state OFF OFF + Wake-up enable OFF + Wake-up enable FLASH ON SPI config SPI config OFF SPI config OFF Notes 37. 38. 39. 40. 41. (39)(40)(41) (39)(40)(41) (39)(40)(41) With limited current capability 5 V-CAN is ON in Debug mode. I/O-0 and I/O-1, configured as an output high-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request. I/O-0, configured as an output low-side switch and ON in Normal mode will turn OFF when entering Reset mode, resume operation in Normal mode. I/O-1, configured as an output low-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request. The 5 V-CAN default is ON when the device is powered-up and set in Debug mode. It is fully controllable via the SPI command. 33903/4/5 NXP Semiconductors 43 FUNCTIONAL DEVICE OPERATION Illustration of device mode transitions VSUP Power up to Normal Mode B B C VDD-UV (4.5 V typically) B VDD-UV VDD VAUX RST RST RST INT INT INT MODE RESET BATFAIL INIT s_1: go to Normal mode s_11: write INT registers legend: NORMAL s_2 VAUX s_12 VAUX s_1 5V-CAN s_11 5V-CAN SPI D VDD 5V-CAN SPI Normal to LP VDD ON Mode VSUP VSUP >4.0 V VDD Normal to LP VDD OFF Mode SPI NORMAL LP VDD OFF s_2: go to LP VDD OFF mode s_12: LP Mode configuration s_3 A s_13 7.7 NORMAL LP VDD On s_3: go to LP mode s_13: LP Mode configuration Series of SPI Single SPI Figure 24. Power up normal and LP modes 33903/4/5 44 NXP Semiconductors FUNCTIONAL DEVICE OPERATION Wake-up from LP VDD OFF Mode C Wake-up from LP VDD ON Mode D VSUP VSUP VDD-UV (4.5 V typically) VDD VDD 5V-CAN Based on reg configuration 5V-CAN VAUX Based on reg configuration VAUX Based on reg configuration Based on reg configuration LP VDD_OFF MODE RESET NORMAL REQUEST CAN Wake-up pattern LIN Bus LIN Wake-up filter I/O-x toggle FWU timer Start . s_14 SPI MODE NORMAL Available Wake-up events (exclusive) CAN bus INT s_4 s_14 INT SPI NORMAL REQUEST LP VDD ON NORMAL CAN bus CAN Wake-up pattern LIN Bus LIN Wake-up filter I/O-x toggle FWU timer Stop Start FWU timer duration (50-8192 ms) SPI selectable FWU timer duration (50-8192 ms) SPI selectable Wake-up detected s_4 RST RST IDD current IDD-OC (3.0 mA typically) IDD OC deglitcher or timer (100 us typically, 3 -32 ms) SPI Wake-up detected Figure 25. Wake-up from LP modes 7.8 Cyclic sense operation during LP modes This function can be used in both LP modes: VDD OFF and VDD ON. Cyclic sense is the periodic activation of I/O-0 to allow biasing of external contact switches. The contact switch state can be detected via I/O-1, -2, and -3, and the device can Wake-up from either LP mode. Cyclic sense is optimized and designed primarily for closed contact switch in order to minimize consumption via the contact pull-up resistor. 33903/4/5 NXP Semiconductors 45 FUNCTIONAL DEVICE OPERATION 7.8.1 Principle A dedicated timer provides an opportunity to select a cyclic sense period from 3.0 to 512 ms (selection in timer B). At the end of the period, the I/O-0 will be activated for a duration of T_CSON (SPI selectable in INIT register, to 200 s, 400 s, 800 s, or 1.6 ms). The I/O-0 HS transistor or LS transistor can be activated. The selection is done by the state of I/O-0 prior to entering in LP mode. During the T-CSON duration, the I/O-x's are monitored. If one of them is high, the device will detect a Wake-up. (Figure 26). Cyclic sense period is selected by the SPI configuration prior to entering LP mode. Upon entering LP mode, the I/O-0 should be activated. The level of I/O-1 is sense during the I/O-0 active time, and is deglitched for a duration of typically 30 s. This means that I/O-1 should be in the expected state for a duration longer than the deglitch time. The diagram below (Figure 26) illustrates the cyclic sense operation, with I/O-0 HS active and I/O-1 Wake-up at high level. I/O-0 HS active in Normal mode I/O-0 HS active during cyclic sense active time I/O-0 S1 S1 closed Zoom S1 open Cyclic sense active time (ex 200 us) I/O-1 I/O-0 I/O-1 high => Wake-up I/O-1 Cyclic sense period state of I/O-1 low => no Wake-up I/O-1 deglitcher time (typically 30 us) Cyclic sense active time NORMAL MODE LP MODE RESET or NORMAL REQUEST MODE Wake-up event detected Wake-up detected. R R R R R R I/O-0 I/O-0 I/O-1 I/O-1 S1 S1 I/O-2 I/O-2 S2 S2 I/O-3 S3 Upon entering in LP mode, all 3 contact switches are closed. S3 I/O-3 In LP mode, 1 contact switch is open. High level is detected on I/O-x, and device wakes up. Figure 26. Cyclic sense operation - switch to GND, wake-up by open switch 33903/4/5 46 NXP Semiconductors FUNCTIONAL DEVICE OPERATION 7.9 Cyclic INT operation during LP VDD on mode 7.9.1 Principle This function can be used only in LP VDD ON mode (LP VDD ON). When Cyclic INT is selected and device is in LP VDD ON mode, the device will generate a periodic INT pulse. Upon reception of the INT pulse, the MCU must acknowledge the INT by sending SPI commands before the end of the next INT period in order to keep the process going. When Cyclic INT is selected and operating, the device remains in LP VDD ON mode, assuming the SPI commands are issued properly. When no/improper SPI commands are sent, the device will cease Cyclic INT operation and leave LP VDD ON mode by issuing a reset. The device will then enter into Normal Request mode. VDD current capability and VDD regulator behavior is similar as in LP VDD ON mode. 7.9.1.1 Operation Cyclic INT period selection: register timer B SPI command in hex 0x56xx [example; 0x560E for 512ms cyclic Interrupt period (SPI command without parity bit)]. This command must be send while the device is in Normal mode. SPI commands to acknowledge INT: (2 commands) - read the Random code via the watchdog register address using the following command: MOSI 0x1B00 device report on MISO second byte the RNDM code (MISO bit 0-7). - write watchdog refresh command using the random code inverted: 0x5A RNDb. These commands can occur at any time within the period. Initial entry in LP mode with Cyclic INT: after the device is set in LP VDD ON mode, with cyclic INT enable, no SPI command is necessary until the first INT pulse occurs. The acknowledge process must start only after the 1st INT pulse. Leave LP mode with Cyclic INT: This is done by a SPI Wake-up command, similar to SPI Wake-up from LP VDD ON mode: 0x5C10. The device will enter into Normal Request mode. Improper SPI command while Cyclic INT operates: When no/improper SPI commands are sent, while the device is in LP VDD ON mode with Cyclic INT enable, the device will cease Cyclic INT operation and leave LP VDD ON mode by issuing a reset. The device will then enter into Normal Request mode. Figure 27 describes the complete Cyclic Interrupt operation. 33903/4/5 NXP Semiconductors 47 FUNCTIONAL DEVICE OPERATION Prepare LP VDD ON with Cyclic INT Leave LP VDD ON Mode In LP VDD ON with Cyclic INT INT LP VDD ON mode SPI Timer B Cyclic INT period 1st period Cyclic INT period NORMAL MODE 2nd period Cyclic INT period 3rd period Cyclic INT period NORMAL REQUEST MODE LP VDD ON MODE Legend for SPI commands Leave LP VDD ON and Cyclic INT due to improper operation Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E) Write Device mode: LP VDD ON with Cyclic INT enable (example: 0x5C90) Read RNDM code INT SPI Improper or no acknowledge SPI command Write RNDM code inv. SPI Wake-up: 0x5C10 RST Cyclic INT period LP VDD ON MODE RESET and NORMAL REQUEST MODE Figure 27. Cyclic interrupt operation 7.10 Behavior at power up and power down 7.10.1 Device power up This section describe the device behavior during ramp up, and ramp down of VSUP/1, and the flexibility offered mainly by the Crank bit and the two VDD undervoltage reset thresholds. The figures below illustrate the device behavior during VSUP/1 ramp up. As the Crank bit is by default set to 0, VDD is enabled when VSUP/1 is above VSUP TH 1 parameters. 33903/4/5 48 NXP Semiconductors FUNCTIONAL DEVICE OPERATION VSUP_NOMINAL (ex 12 V) VDD NOMINAL (ex 5.0 V) VSUP slew rate VBAT D1 VDD_UV TH (typically 4.65 V) VSUP/1 VDD VSUP_TH1 3390X VDD_START UP I_VDD 90% VDD_START UP VSUP/1 Gnd 10% VDD_START UP VDD VDD_OFF RST 1.0 ms Figure 28. VDD start-up versus VSUP/1 tramp 7.10.2 Device power down The figures below illustrate the device behavior during VSUP/1 ramp down, based on Crank bit configuration, and VDD undervoltage reset selection. 7.10.2.1 Crank bit reset (INIT watchdog register, Bit 0 =0) Bit 0 = 0 is the default state for this bit. During VSUP/1 ramp down, VDD remain ON until device enters in Reset mode due to a VDD undervoltage condition (VDD < 4.6 V or VDD < 3.2 V typically, threshold selected by the SPI). When device is in Reset, if VSUP/1 is below "VSUP_TH1", VDD is turned OFF. 7.10.2.2 Crank bit set (INIT watchdog register, Bit 0 =1) The bit 0 is set by SPI write. During VSUP/1 ramp down, VDD remains ON until device detects a POR and set BATFAIL. This occurs for a VSUP/1 approx 3.0 V. VBAT VSUP_NOMINAL (ex 12 V) VBAT VSUP_NOMINAL (ex 12 V) VSUP1 VSUP_TH1 (4.1V) VSUP_TH1 (4.1V) VSUP1 minVSUP (2.8 V) VDD VDD (3.3 V) VDD_UV TH (typ 3.0 V) RESET Case 1: VDD 3.3V, "VDD UV TH 3.0 V", with bit Crank =0 (default value) VDD VDD (3.3 V) VDD_UV TH (typ 3.0 V) RESET Case 2: VDD 3.3V, "VDD UV TH 3.0 V", with bit Crank =1 33903/4/5 NXP Semiconductors 49 FUNCTIONAL DEVICE OPERATION VBAT VSUP_NOMINAL (ex 12 V) VBAT VSUP_NOMINAL (ex 12 V) VSUP/1 VSUP/1 VDD (5.0 V) VSUP_TH1 (4.1 V) VDD (5.0 V) VDD_UV TH (typically 4.65 V) VDD_UV TH (typically 4.65 V) VDD VDD RST RST Case 3: "VDD UV TH 4.6V", with bit Crank = 0 (default value) VBAT VSUP_NOMINAL (ex 12 V) BATFAIL (3.0 V) Case 4: "VDD UV 4.6V", with bit Crank = 1 VBAT VSUP_NOMINAL (ex 12 V) VSUP/1 VSUP/1 VSUP_TH1 (4.1 V) VDD (5.0 V) VDD (5.0 V) VDD_UV TH (typically 4.65 V) VDD_UV TH (typically 4.65 V) VDD VDD VDD_UV TH2 (typically 3.2 V) BATFAIL (3.0 V) VDD_UV TH2 (typically 3.2 V) (2) INT RST INT (1) RST (1) reset then (2) VDD turn OFF Case 5: "VDD UV TH 3.2V", with bit Crank = 0 (default value) Case 6: "VDD UV 3.2V", with bit Crank = 1 Figure 29. VDD behavior during VSUP/1 ramp down 33903/4/5 50 NXP Semiconductors FUNCTIONAL DEVICE OPERATION 7.11 Fail-safe operation 7.11.1 Overview Fail-safe mode is entered when specific fail conditions occur. The `Safe state' condition is defined by the resistor connected at the DGB pin. Safe mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin. Exiting the safe state is always possible by a Wake-up event: in the safe state, the device can automatically be awakened by CAN and I/O (if configured as inputs). Upon Wake-up, the device operation is resumed: enter in Reset mode. 7.11.2 Fail-safe functionality Upon dedicated event or issue detected at a device pin (i.e. RST short to VDD), the Safe mode can be entered. In this mode, the SAFE pin is active low. 7.11.2.1 Description Upon activation of the SAFE pin, and if the failure condition that make the SAFE pin activated have not recovered, the device can help to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in LP mode. Two main cases are available: 7.11.2.2 Mode A Upon SAFE activation, the MCU remains powered (VDD stays ON), until the failure condition recovers (i.e. S/W is able to properly control the device and properly refresh the watchdog). 7.11.2.3 Modes B1, B2 and B3 Upon SAFE activation, the system continues to monitor external event, and disable the MCU supply (turn VDD OFF). The external events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3. Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low level detection can also indicate that the vehicle is being shutdown, if the I/O-1 pin is connected for instance to a switched battery signal (ignition key on/off signal). The selection of the monitored events is done by hardware, via the resistor connected at DBG pin, but can be over written by software, via a specific SPI command. By default, after power up the device detect the resistor value at DBG pin (upon transition from INIT to Normal mode), and, if no specific SPI command related to Debug resistor change is send, operates according to the detected resistor. The INIT MISC register allow you to verify and change the device behavior, to either confirm or change the hardware selected behavior. Device will then operate according to the SAFE mode configured by the SPI. Table 9 illustrates the complete options available: Table 9. Fail-safe options Resistor at DBG pin SPI coding - register INIT MISC bits [2,1,0] (higher priority that Resistor coding) Safe mode code VDD status <6.0 k bits [2,1,0) = [111]: verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE mode A A remains ON typically 15 k bits [2,1,0) = [110]: verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE mode B1 B1 Turn OFF 8.0 s after CAN traffic bus idle detection. typically 33 k bits [2,1,0) = [101]: verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE mode B2 B2 Turn OFF when I/O-1 low level detected. typically 68 k bits [2,1,0) = [100]: verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE mode B3 B3 Turn OFF 8.0 s after CAN traffic bus idle detection AND when I/O-1 low level detected. 33903/4/5 NXP Semiconductors 51 FUNCTIONAL DEVICE OPERATION 7.11.2.4 Exit of safe mode Exit of the safe state with VDD OFF is always possible by a Wake-up event: in this safe state the device can automatically awakened by CAN and I/O (if I/O Wake-up was enable by the SPI prior to enter into SAFE mode). Upon Wake-up, the device operation is resumed, and device enters in Reset mode. The SAFE pin remains active, until there is a proper read and clear of the SPI flags reporting the SAFE conditions. . SAFE Operation Flow Chart Legend: Failure events RESET Device state: NR RESET bit 4, INIT watchdog = 1 (1) bit 4, INIT watchdog = 0 (1) SAFE high Reset: 1.0 ms pulse SAFE low Reset: 1.0 ms pulse detection of 2nd consecutive watchdog failure SAFE low a) Evaluation of Resistor detected at DBG pin during power up, or SPI watchdog failure VDD low: VDD <VDD_UVTH INIT, Normal Request Normal, FLASH register content - Reset low - SAFE low - VDD ON Rst s/c GND: Rst <2.5 V, t >100 ms RESET b) ECU external signal monitoring (7): - bus idle time out - I/O-1 monitoring safe state B SPI (3) safe state A 8 consecutive watchdog failure (5) SAFE pin release (SAFE high) (6) State A: RDBG <6.0 k AND watchdog failure - SAFE low - VDD ON - Reset: 1.0 ms periodic pulse State A: RDBG <6.0 k AND (VDD low or RST s/c GND) failure - SAFE low - VDD ON - Reset low State B1: RDBG = 15 k AND Bus idle timeout expired State B2: RDBG = 33 k AND I/O-1 low State B3: RDBG = 47 k AND I/O-1 low AND Bus idle time out expired - SAFE low - Reset low - VDD OFF Wake-up (2), VDD ON, SAFE pin remains low failure recovery, SAFE pin remains low 1) bit 4 of INIT Watchdog register 2) Wake-up event: CAN, LIN or I/O-1 high level (if I/O-1 Wake-up previously enabled) 3) SPI commands: 0x1D80 or 0xDD80 to release SAFE pin 4) Recovery: reset low condition released, VDD low condition released, correct SPI watchdog refresh 5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256 ms. 6) Dynamic behavior: 1.0 ms reset pulse every 256 ms, due to no watchdog refresh SPI command, and device state transition between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes. 7) 8 second timer for bus idle timeout. I/O-1 high to low transition. Figure 30. Safe operation flow chart 7.11.2.5 Conditions to set SAFE pin active low Watchdog refresh issue: SAFE activated at 1st reset pulse or at the second consecutive reset pulse (selected by bit 4, INIT watchdog register). VDD low: VDD < RST-TH. SAFE pin is set low at the same time as the RST pin is set low. The RST pin is monitored to verify that reset is not clamped to a low level preventing the MCU to operate. If this is the case, the Safe mode is entered. 33903/4/5 52 NXP Semiconductors FUNCTIONAL DEVICE OPERATION 7.11.2.6 SAFE mode A illustration Figure 31 illustrates the event and consequences when SAFE mode A is selected via the appropriate debug resistor or SPI configuration. Behavior Illustration for Safe State A (RDG < 6.0 kohm), or Selection by the SPI step 2: Consequence on VDD, RST and SAFE step 1: Failure illustration VDD failure event, i.e. watchdog VDD 8th 2nd 1st RST SAFE RST SAFE OFF state ON state 8 x 256 ms delay time to enter in SAFE mode to evaluate resistor at DBG pin and monitor ECU external events failure event, VDD low VDD VDD_UV TH VDD GND RST RST SAFE VDD < VDD_UV TH GND SAFE OFF state ON state 100ms 100 ms delay time to enter in SAFE mode to evaluate resistor at DBG pin and monitor ECU external events failure event, Reset s/c GND VDD VDD SAFE RST 2.5 V RST ON state OFF state SAFE 100ms 100 ms deglitcher time to activate SAFE and enter in SAFE mode to evaluate resistor at the DBG pin and monitor ECU external events Figure 31. SAFE mode A behavior illustration 33903/4/5 NXP Semiconductors 53 FUNCTIONAL DEVICE OPERATION 7.11.2.7 SAFE mode B1, B2 and B3 illustration Figure 32 illustrates the event, and consequences when SAFE mode B1, B2, or B3 is selected via the appropriate debug resistor or SPI configuration. Behavior illustration for the safe state B (RDG > 10 kohm) CAN bus DBG resistor => safe state B1 step 2: Exclusive detection of ECU external event to disable VDD based on RDBG resistor or SPI configuration CAN bus idle time I/O-1 I/O-1 high to low transition DBG resistor => safe state B2 CAN bus DBG resistor => safe state B3 CAN bus idle time I/O-1 I/O-1 high to low transition step 1: Failure illustration step 3: Consequences for VDD VDD failure event, i.e. watchdog VDD 8th 2nd 1st RST SAFE RST SAFE OFF state ON state 8 x 256 ms delay time to enter in SAFE mode to evaluate resistor at the DBG pin and monitor ECU external events failure event, VDD low If VDD failure recovered VDD VDD_UV TH VDD GND VDD VDD 2.5 V OFF state eup If Reset s/c GND recovered failure event, Reset s/c GND RST ak and monitor ECU external events W 100 ms E m CU et e = > xte V rna D l D di con sa d bl i t i o e n SAFE OFF state ON state 100 ms delay time to enter in SAFE mode to evaluate resistor at DBG pin SAFE VDD OFF RST RST SAFE VDD < VDD_UV TH GND VDD OFF RST 100 ms ON state SAFE 100 ms deglitcher time to activate SAFE and enter in SAFE mode to evaluate resistor at DBG pin and monitor ECU external events Figure 32. SAFE modes B1, B2, or B3 behavior illustration 33903/4/5 54 NXP Semiconductors CAN INTERFACE 8 CAN interface 8.1 CAN interface description The figure below is a high level schematic of the CAN interface. It exist in a LS driver between CANL and GND, and a HS driver from CANH to 5 V-CAN. Two differential receivers are connected between CANH and CANL to detect a bus state and to Wake-up from CAN Sleep mode. An internal 2.5 V reference provides the 2.5 V recessive levels via the matched RIN resistors. The resistors can be switched to GND in CAN Sleep mode. A dedicated split buffer provides a low-impedance 2.5 V to the SPLIT pin, for recessive level stabilization. VSUP/2 Pattern SPI & State machine Detection Wake-up Receiver 5 V-CAN Driver QH RIN 2.5 V CANH Differential Receiver RXD RIN CANL 5 V-CAN TXD Driver SPI & State machine SPI & State machine Thermal Failure Detection QL 5 V-CAN Buffer SPLIT & Management Figure 33. CAN interface block diagram 8.1.1 Can interface supply The supply voltage for the CAN driver is the 5 V-CAN pin. The CAN interface also has a supply pass from the battery line through the VSUP/2 pin. This pass is used in CAN Sleep mode to allow Wake-up detection. During CAN communication (transmission and reception), the CAN interface current is sourced from the 5 V-CAN pin. During CAN LP mode, the current is sourced from the VSUP/2 pin. 8.1.2 TXD/RXD mode In TXD/RXD mode, both the CAN driver and the receiver are ON. In this mode, the CAN lines are controlled by the TXD pin level and the CAN bus state is reported on the RXD pin. The 5 V-CAN regulator must be ON. It supplies the CAN driver and receiver.The SPLIT pin is active and a 2.5 V biasing is provided on the SPLIT output pin. 33903/4/5 NXP Semiconductors 55 CAN INTERFACE 8.1.2.1 Receive only mode This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN state on the RXD pin. The TXD pin has no effect on CAN bus lines. The 5 V-CAN regulator must be ON. The SPLIT pin is active and a 2.5 V biasing is provided on the SPLIT output pin. 8.1.2.2 Operation in TXD/RXD mode The CAN driver will be enabled as soon as the device is in Normal mode and the TXD pin is recessive. When the CAN interface is in Normal mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin. When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with 5 V-CAN divided by 2, or approx. 2.5 V. When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is pulled low and CANH is pulled high. The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV). If "CANH minus CANL" is below the threshold, the bus is recessive and RXD is set high. If "CANH minus CANL" is above the threshold, the bus is dominant and RXD is set low. The SPLIT pin is active and provides a 2.5 V biasing to the SPLIT output. 8.1.2.3 TXD/RXD mode and slew rate selection The CAN signal slew rate selection is done via the SPI. By default and if no SPI is used, the device is in the fastest slew rate. Three slew rates are available. The slew rate controls the recessive to dominant, and dominant to recessive transitions. This also affects the delay time from the TXD pin to the bus and from the bus to the RXD. The loop time is thus affected by the slew rate selection. 8.1.2.4 Minimum baud rate The minimum baud rate is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). The shortest TXD dominant detection time of 300 s lead to a single bit time of: 300 s / 12 = 25 s. So the minimum Baud rate is 1 / 25 s = 40 kBaud. 8.1.2.5 Sleep mode Sleep mode is a reduced current consumption mode. CANH and CANL drivers are disabled and CANH and CANL lines are terminated to GND via the RIN resistor, the SPLIT pin is high-impedance. In order to monitor bus activities, the CAN Wake-up receiver can be enabled. It is supplied internally from VSUP/2. Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI and by INT pulse, and results in a device Wake-up if the device was in LP mode. When the device is set back into Normal mode, CANH and CANL are set back into the recessive level. This is illustrated in Figure 34. 33903/4/5 56 NXP Semiconductors CAN INTERFACE . TXD Dominant state Recessive state CANH-DOM CANH 2.5 V CANL/CANH-REC CANH-CANL CANL CANL-DOM High ohmic termination (50 kohm) to GND RXD SPLIT 2.5 V Bus Driver High-impedance Receiver (bus dominant set by other IC) Go to sleep, Sleep or Stand-by mode Normal or Listen Only mode Normal or Listen Only mode Figure 34. Bus signal in TXD/RXD and LP mode 8.1.2.6 Wake-up When the CAN interface is in Sleep mode with Wake-up enabled, the CAN bus traffic is detected. The CAN bus Wake-up is a pattern Wake-up. The Wake-up by the CAN is enabled or disabled via the SPI. CAN bus Dominant Pulse # 1 CANH Dominant Pulse # 2 CANL Internal differential Wake-up receiver signal Internal Wake-up signal tCAN WU1-F Can Wake-up detected Figure 35. Single dominant pulse wake-up 8.1.2.7 Pattern wake-up In order to Wake-up the CAN interface, the Wake-up receiver must receive a series of three consecutive valid dominant pulses, by default when the CANWU bit is low. CANWU bit can be set high by SPI and the Wake-up will occur after a single pulse duration of 2.0 s (typically). A valid dominant pulse should be longer than 500 ns. The three pulses should occur in a time frame of 120 s, to be considered valid. When three pulses meet these conditions, the wake signal is detected. This is illustrated by the following figure. 33903/4/5 NXP Semiconductors 57 CAN INTERFACE . CAN bus Dominant Pulse # 1 CANH Dominant Pulse # 3 Dominant Pulse # 2 CANL Dominant Pulse # 4 Internal differential Wake-up receiver signal Internal Wake-up signal Can Wake-up detected tCAN WU3-F tCAN WU3-F tCAN WU3-F tCAN WU3-TO Dominant Pulse # n: duration 1 or multiple dominant bits Figure 36. Pattern wake-up - multiple dominant detection 8.1.3 BUS termination The device supports the two main types of bus terminations: * Differential termination resistors between CANH and CANL lines. * SPLIT termination concept, with the mid point of the differential termination connected to GND through a capacitor and to the SPLIT pin. * In application, the device can also be used without termination. * Figure 37 illustrates some of the most common terminations. CANH SPLIT CANH No connect 120 CANL SPLIT CAN bus No connect CANL ECU connector CAN bus ECU connector No termination Standard termination CANH 60 SPLIT CAN bus 60 CANL ECU connector Figure 37. Bus termination options 8.2 CAN bus fault diagnostic The device includes diagnostic of bus short-circuit to GND, VBAT, and internal ECU 5.0 V. Several comparators are implemented on CANH and CANL lines. These comparators monitor the bus level in the recessive and dominant states. The information is then managed by a logic circuitry to properly determine the failure and report it. 33903/4/5 58 NXP Semiconductors CAN INTERFACE Vr5 H5 Hb TXD Diag Logic Hg VBAT (12-14 V) Vrvb Vrg Lg L5 VRVB (VSUP-2.0 V) CANH CANL Vrg Lb VDD VDD (5.0 V) VR5 (VDD-.43 V) CANH dominant level (3.6 V) Recessive level (2.5 V) VRG (1.75 V) Vrvb CANL dominant level (1.4 V) Vr5 GND (0.0 V) Figure 38. CAN bus simplified structure truth table for failure detection The following table indicates the state of the comparators when there is a bus failure, and depending upon the driver state. Table 10. Failure detection truth table Failure description Driver recessive state Lg (threshold 1.75 V) Hg (threshold 1.75 V) Driver dominant state Lg (threshold 1.75 V) Hg (threshold 1.75 V) No failure 1 1 0 1 CANL to GND 0 0 0 1 CANH to GND 0 0 0 0 Lb (threshold VSUP -2.0 V) Hb (threshold VSUP -2.0 V) Lb (threshold VSUP -2.0 V) Hb (threshold VSUP -2.0 V) No failure 0 0 0 0 CANL to VBAT 1 1 1 1 CANH to VBAT 1 1 0 1 L5 (threshold VDD -0.43 V) H5 (threshold VDD -0.43 V) L5 (threshold VDD -0.43 V) H5 (threshold VDD -0.43 V) No failure 0 0 0 0 CANL to 5.0 V 1 1 1 1 CANH to 5.0 V 1 1 0 1 8.2.1 Detection principle In the recessive state, if one of the two bus lines are shorted to GND, VDD (5.0 V), or VBAT, the voltage at the other line follows the shorted line, due to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage measured by the Hg comparator is also close to zero. In the recessive state, the failure detection to GND or VBAT is possible. However, it is not possible with the above implementation to distinguish which of the CANL or CANH lines are shorted to GND or VBAT. A complete diagnostic is possible once the driver is turned on, and in the dominant state. 8.2.1.1 Number of samples for proper failure detection The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error will be fully detected after five cycles of the recessive-dominant states. As long as the failure detection circuitry has not detected the same error for five recessive-dominant cycles, the error is not reported. 8.2.2 Bus clamping detection If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI. This condition could occur when the CANH line is shorted to a high-voltage. In this case, current will flow from the high-voltage shortcircuit, through the bus termination resistors (60 ), into the SPLIT pin (if used), and into the device CANH and CANL input resistors, which are terminated to internal 2.5 V biasing or to GND (Sleep mode). 33903/4/5 NXP Semiconductors 59 CAN INTERFACE Depending upon the high-voltage short-circuit, the number of nodes, usage of the SPLIT pin, RIN actual resistor and mode state (Sleep or Active) the voltage across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL, and the RXD pin will be low. This would prevent start of any CAN communication and thus, proper failure identification requires five pulses on TXD. The bus dominant clamp circuit will help to determine such failure situation. 8.2.3 RXD permanent recessive failure (does not apply to `C' and `D' versions) The aim of this detection is to diagnose an external hardware failure at the RXD output pin and ensure that a permanent failure at RXD does not disturb the network communication. If RXD is shorted to a logic high signal, the CAN protocol module within the MCU will not recognize any incoming message. In addition, it will not be able to easily distinguish the bus idle state and can start communication at any time. In order to prevent this, RXD failure detection is necessary. When a failure is detected, the RXD high flag is set and CAN switches to receive only mode. TXD CANL&H Diag TXD driver Logic Diff output VDD/2 VDD Sampling VDD Rxsense RXD RXD driver 60 Diff CANL RXD short to VDD RXD flag latched RXD output CANH Sampling RXD flag Prop delay The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 39. RXD path simplified schematic, RXD short to VDD detection 8.2.3.1 Implementation for detection The implementation senses the RXD output voltage at each low to high transition of the differential receiver. Excluding the internal propagation delay, the RXD output should be low when the differential receiver is low. When an external short to VDD at the RXD output, RXD will be tied to a high level and can be detected at the next low to high transition of the differential receiver. As soon as the RXD permanent recessive is detected, the RXD driver is deactivated. Once the error is detected the driver is disabled and the error is reported via SPI in CAN register. 8.2.3.2 Recovery condition The internal recovery is done by sampling a correct low level at TXD as shown in the following illustration. CANL&H Diff output Sampling RXD output Sampling RXD short to VDD RXD flag latched RXD no longer shorted to VDD RXD flag The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 40. RXD path simplified schematic, RXD short to VDD detection 33903/4/5 60 NXP Semiconductors CAN INTERFACE 8.2.4 8.2.4.1 TXD permanent dominant Principle If the TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The device has a TXD permanent timeout detector. After the timeout (TDOUT), the bus driver is disabled and the bus is released into a recessive state. The TXD permanent flag is set. 8.2.4.2 Recovery The TXD permanent dominant is used and activated when there is a TXD short to RXD. The recovery condition for a TXD permanent dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal mode controlled by the MCU or when TXD is recessive while RXD change from recessive to dominant. 8.2.5 8.2.5.1 TXD to RXD short-circuit Principle When TXD is shorted to RXD during incoming dominant information, RXD is set to low. Consequently, the TXD pin is low and drives CANH and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible. 8.2.5.2 Detection and recovery The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure 8.2.6 Important information for bus driver reactivation The driver stays disabled until the failure is/are removed (TXD and/or RXD is no longer permanent dominant or recessive state or shorted) and the failure flags cleared (read). The CAN driver must be set by SPI in TXD/RXD mode in order to re enable the CAN bus driver. 33903/4/5 NXP Semiconductors 61 LIN BLOCK 9 LIN block 9.1 LIN interface description The physical interface is dedicated to automotive LIN sub-bus applications. The interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior when a LIN bus short-to-ground, or a LIN bus leakage during LP mode. Digital inputs are related to the device VDD pin. 9.1.1 Power supply pin (VSUP/2) The VSUP/2 pin is the supply pin for the LIN interface. To avoid a false bus message, an undervoltage on VSUP/2 disables the transmission path (from TXD to LIN) when VSUP/2 falls below 6.1 V. 9.1.2 Ground pin (GND) When there is a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus pin when in the recessive state. 9.1.3 LIN bus pin (LIN, lin1, lin2) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal mode. 9.1.3.1 Driver characteristics The LIN driver is a LS MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 k must be added when the device is used in the master node. The 1.0 k pull-up resistor can be connected to the LIN pin or to the ECU battery supply. The LIN pin exhibits no reverse current from the LIN bus line to VSUP/2, even in the event of a GND shift or VSUP/2 disconnection. The transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI. 9.1.3.2 Receiver characteristics The receiver thresholds are ratiometric with the device VSUP/2 voltage. If the VSUP/2 voltage goes below typically 6.1 V, the LIN bus enters into a recessive state even if communication is sent on TXD. If LIN driver temperature reaches the overtemperature threshold, the transceiver and receiver are disabled. When the temperature falls below the overtemperature threshold, LIN driver and receiver will be automatically enabled. 9.1.4 Data input pin (TXD-L, TXD-L1, TXD-L2) The TXD-L,TXD-L1 and TXD-L2 input pin is the MCU interface to control the state of the LIN output. When TXD-L is LOW (dominant), LIN output is LOW. When TXD-L is HIGH (recessive), the LIN output transistor is turned OFF. This pin has an internal pull-up current source to VDD to force the recessive state if the input pin is left floating. If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register. 9.1.5 Data output pin (RXD-L, RXD-L1, RXD-L2) This output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage on RXD, LIN LOW (dominant) is reported by a low voltage on RXD. 33903/4/5 62 NXP Semiconductors LIN BLOCK 9.2 LIN operational modes The LIN interface have two operational modes, Transmit receiver and LIN disable modes. 9.2.1 Transmit receive In the TXD/RXD mode, the LIN bus can transmit and receive information. When the 20 kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1. When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. The LIN interface can be set by the SPI command in TXD/RXD mode, only when TXD-L is at a high level. When the SPI command is send while TXD-L is low, the command is ignored. 9.2.2 Sleep mode This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP/2 is very low (typically 3.0 A). LIN bus is monitor to detect Wake-up event. In the Sleep mode, the internal 725 kOhm pull-up resistor is connected and the 30 kOhm disconnected. The LIN block can be awakened from Sleep mode by detection of LIN bus activity. 9.2.2.1 LIN bus activity detection The LIN bus Wake-up is recognized by a recessive to dominant transition, followed by a dominant level with a duration greater than 70 s, followed by a dominant to recessive transition. This is illustrated in Figures 20 and 21. Once the Wake-up is detected, the event is reported to the device state machine. An INT is generated if the device is in LP VDD ON mode, or VDD will restart if the device was in LP VDDOFF mode. The Wake-up can be enable or disable by the SPI. Fail-safe Features Table 11 describes the LIN block behavior when there is a failure. Table 11. LIN block failure Fault Functionnal mode LIN supply Undervoltage TXD Pin Permanent Dominant TXD RXD LIN Thermal Shutdown TXD RXD Condition Consequence Recovery LIN supply voltage < 6.0 V (typically) LIN transmitter in recessive State Condition gone TXD pin low for more than t TXDDOM LIN transmitter in recessive State Condition gone LIN driver temperature > 160 C (typically) LIN transmitter and receiver disabled HS turned off Condition gone 33903/4/5 NXP Semiconductors 63 SERIAL PERIPHERAL INTERFACE 10 Serial peripheral interface 10.1 High level overview The device uses a 16 bits SPI, with the following arrangements: MOSI, Master Out Slave In bits: * bits 15 and 14 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of the control bits, read of device flag). * bit 13 to 9 (A4 to A0) to select the register address. * bit 8 (P/N) has two functions: parity bit in write mode (optional, = 0 if not used), Next bit ( = 1) in read mode. * bit 7 to 0 (D7 to D0): control bits MISO, Master In Slave Out bits: * bits 15 to 8 (S15 to S8) are device status bits * bits 7 to 0 (Do7 to Do0) are either extended device status bits, device internal control register content or device flags. The SPI implementation does not support daisy chain capability. Figure 41 is an overview of the SPI implementation. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 MOSI C1 C0 A4 S15 S14 A2 A1 A0 register address control bits MISO A3 S13 S12 S11 S10 Bit 8 Bit 7 Bit 6 P/N D7 D6 Bit 5 D5 Parity (optional) or Next bit = 1 S9 S8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D4 D2 D1 D0 Do2 Do1 Do0 D3 data Do7 Do6 Do5 Do4 Do3 Extended Device Status, Register Control bits or Device Flags Device Status CS active low. Must rise at end of 16 clocks, for write commands, MOSI bits [15, 14] = [0, 1] CS SCLK SCLK signal is low outside of CS active MOSI Don't Care MISO Tri-state C1 S15 C0 D0 S14 Do0 Don't Care Tri-state MOSI and MISO data changed at SCLK rising edge and sampled at falling edge. Msb first. MISO tri-state outside of CS active SPI Wave Form, and Signals Polarity Figure 41. SPI overview 10.2 Detail operation The SPI operation deviation (does not apply to `C' and `D' versions). In some cases, the SPI write command is not properly interpreted by the device. This results in either a `non received SPI command' or a `corrupted SPI command'. Important: Due to this, the tLEAD and tCSLOW parameters must be carefully acknowledged. Only SPI write commands (starting with bits 15,14 = 01) are affected. The SPI read commands (starting with bits 15,14 = 00 or 11) are not affected. The occurrence of this issue is extremely low and is caused by the synchronization between internal and external signals. In order to guarantee proper operation, the following steps must be taken. 1. Ensure the duration of the Chip Select Low (tCSLOW) state is >5.5 s. Note: In data sheet revisions prior to 7.0, this parameter is not specified and is indirectly defined by the sum of 3 parameters, tLEAD + 16 x tPCLK + tLAG (sum = 4.06 s). 33903/4/5 64 NXP Semiconductors SERIAL PERIPHERAL INTERFACE 2. Ensure SPI timing parameter tLEAD is a min. of 550 ns. Note: In data sheet revisions prior to 7.0, the tLEAD parameter is a min of 30 ns. 3. Make sure to include a SPI read command after a SPI write command. In case a series of SPI write commands is used, only one additional SPI read is necessary. The recommended SPI read command is "device ID read: 0x2580" so device operation is not affected (ex: clear flag). Other SPI read commands may also be used. When the previous steps are implemented, the device will operate as follows: For a given SPI write command (named SPI write `n'): * In case the SPI write command `n' is not accepted, the following SPI command (named SPI `n+1') will finish the write process of the SPI write `n', thanks to step 2 (tLAG > 550 ns) and step 3 (which is the additional SPI command `n+1'). * By applying steps 1, 2, and 3, no SPI command is ignored. Worst case, the SPI write `n' is executed at the time the SPI `n+1' is sent. This will lead to a delay in device operation (delay between SPI command `n' and `n+1'). Note: Occurrence of an incorrect command is reduced, thanks to step 1 (extension of tCSLOW duration to >5.5 s). Sequence examples: Example 1: * 0x60C0 (CAN interface control) - in case this command is missed, next write command will complete it * 0x66C0 (LIN interface control) - in case this command is missed, next read command will complete it * 0x2580 (read device ID) - Additional command to complete previous LIN command, in case it was missed Example 2: * 0x60C0 (CAN interface control) - in case this command is missed, next write command will complete it * 0x66C0 (LIN interface control) - in case this command is missed, next read command will complete it * 0x2100 (read CAN register content) - this command will complete previous one, in case it was missed * 0x2700 (read LIN register content) SPI Operation if the CSB low flag is set to '1' (All product versions) When the `CSB low' flag is set (Bit 4 = '1' using the 0xE300 SPI command), the next SPI write commands are executed by the device only if the SPI tLEAD time is between 30 ns and 2.5 s maximum for the `C' and `D' versions, and 550 ns and 2.5 s maximum for others versions. The occurrence of the CSB flag set to `1' is extremely low and is directly linked to an intermittent short to ground on the board trace or a CSB driven low by the MCU. In both cases, the CSB pin must be asserted low for more than 2.0 ms to set the flag. The tLEAD time is represented in the SPI timing diagram (Figure 14) and corresponds to the time between CSB high to low transition and first SCLK signal. Note: If the flag is cleared by a read command and the fault is no longer present, the 2.5 s maximum of tLEAD time does not apply, but can also be respected. This means if all the SPI write commands use a maximum tLEAD time of 2.5 s, they are all interpreted by the device, whatever the indication of the `CSB low' flag. 33903/4/5 NXP Semiconductors 65 SERIAL PERIPHERAL INTERFACE 10.2.1 Bits 15, 14, and 8 functions Table 12 summarizes the various SPI operation, depending upon bit 15, 14, and 8. Table 12. SPI operations (bits 8, 14, & 15) Control Bits MOSI[15-14], C1-C0 Type of Command Parity/Next MOSI[8] P/N Note for Bit 8 P/N 00 Read back of register content and block (CAN, I/O, INT, LINs) real time state. See Table 39. 1 Bit 8 must be set to 1, independently of the parity function selected or not selected. 01 Write to register address, to control the device operation 0 If bit 8 is set to "0": means parity not selected OR parity is selected AND parity = 0 1 if bit 8 is set to "1": means parity is selected AND parity = 1 1 Bit 8 must be set to 1, independently of the parity function selected or not selected. 10 Reserved 11 Read of device flags form a register address 10.2.2 Bits 13-9 functions The device contains several registers coded on five bits (bits 13 to 9). Each register controls or reports part of the device's function. Data can be written to the register to control the device operation or to set the default value or behavior. Every register can also be read back in order to ensure that it's content (default setting or value previously written) is correct. In addition, some of the registers are used to report device flags. 10.2.2.1 Device status on MISO When a write operation is performed to store data or control bits into the device, the MISO pin reports a 16 bit fixed device status composed of 2 bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO will report the Fixed device status (bits 15 to 8) and the next eight bits will be the content of the selected register. 10.2.3 Register adress table Table 13 is a list of device registers and addresses, coded with bits 13 to 9. Table 13. Device registers with corresponding address Address MOSI[13-9] A4...A0 Description Quick Ref. Name Functionality 0_0000 Analog Multiplexer MUX 1) Write `device control bits' to register address. 2) Read back register `control bits' 0_0001 Memory byte A RAM_A 0_0010 Memory byte B RAM_B 0_0011 Memory byte C RAM_C 0_0100 Memory byte D RAM_D 0_0101 Initialization Regulators Init REG 0_0110 Initialization Watchdog Init watchdog 0_0111 Initialization LIN and I/O Init LIN I/O 0_1000 Initialization Miscellaneous functions Init MISC 0_1001 Specific modes SPE_MOD E 1) Write `data byte' to register address. 2) Read back `data byte' from register address 1) Write `device initialization control bits' to register address. 2) Read back `initialization control bits' from register address 1) Write to register to select device Specific mode, using `Inverted Random Code' 2) Read `Random Code' 33903/4/5 66 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 13. Device registers with corresponding address (continued) 0_1010 Timer_A: watchdog & LP MCU consumption TIM_A 0_1011 Timer_B: Cyclic Sense & Cyclic Interrupt TIM_B 0_1100 Timer_C: watchdog LP & Forced Wake-up TIM_C 0_1101 Watchdog Refresh watchdog Watchdog Refresh Commands Mode register MODE 1) Write to register to select LP mode, with optional "Inverted Random code" and select Wake-up functionality 2) Read operations: Read back device `Current mode' Read `Random Code', Leave `Debug mode' 0_1110 0_1111 Regulator Control REG 1_0000 CAN interface control CAN 1_0001 Input Output control I/O 1_0010 Interrupt Control Interrupt 1_0011 LIN1 interface control LIN1 1_0100 LIN2 interface control LIN2 1) Write `timing values' to register address 2) Read back register `timing values' 1) Write `device control bits' to register address, to select device operation. 2) Read back register `control bits'. 3) Read device flags from each of the register addresses. 10.2.4 Complete SPI operation Table 14 is a compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described. Table 14. SPI capabilities with options MOSI/ MISO Control bits [15-14] Address [13-9] Parity/Next bits [8] Bit 7 Read back of "device control bits" (MOSI bit 7 = 0) OR Read specific device information (MOSI bit 7 = 1) MOSI 00 address 1 0 MISO Device Fixed Status (8 bits) MOSI 00 MISO Device Fixed Status (8 bits) Write device control bit to address selected by bits (13-9). MISO return 16 bits device status MOSI 01 MISO Device Fixed Status (8 bits) MOSI 10 Type of Command Reserved Read device flags and Wake-up flags, from register address (bit 13-9), and sub address (bit 7). MISO return fixed device status (bit 15-8) + flags from the selected address and subaddress. address address 1 Bits [6-0] 000 0000 Register control bits content 1 000 0000 Device ID and I/Os state (note) Control bits Device Extended Status (8 bits) Reserved MISO Reserved MISO 11 address MOSI Device Fixed Status (8 bits) address Reserved MISO 11 1 MOSI Device Fixed Status (8 bits) 0 Read of device flags form a register address, and sub address LOW (bit 7) 1 Read of device flags form a register address, and sub address HIGH (bit 7) Flags Flags Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity is selected and parity = 1. 10.2.5 Parity bit 8 10.2.5.1 Calculation The parity is used for the write-to-register command (bit 15,14 = 01). It is calculated based on the number of logic one contained in bits 15-9,7-0 sequence (this is the entire 16 bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even. 33903/4/5 NXP Semiconductors 67 SERIAL PERIPHERAL INTERFACE 10.2.5.2 Examples 1: MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0, because the command contains 7 bits with logic 1. Thus the Exact command will then be: MOSI [bit 15-0] = 01 00 011 0 01101001 10.2.5.3 Examples 2: MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1, because the command contains 4 bits with logic 1. Thus the Exact command will then be: MOSI [bit 15-0] = 01 00 011 1 0100 0000 10.2.5.4 Parity function selection All SPI commands and examples do not use parity functions. The parity function is optional. It is selected by bit 6 in INIT MISC register. If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be `0'. 10.3 Detail of control bits and register mapping The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100 10.3.1 MUX and RAM registers Table 15. MUX Register(42) MOSI First Byte [15-8] [b_15 b_14] 0_0000 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 000 P MUX_2 MUX_1 MUX_0 Int 2K I/O-att 0 0 0 Default state 0 0 0 0 0 0 0 0 Condition for default POR, 5 V-CAN off, any mode different from Normal Bits b7 b6 b5 Description MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT pin 000 All functions disable. No output voltage at MUX-OUT pin 001 VDD regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2.0 K (bit 3) 010 Device internal voltage reference (approx 2.5 V) 011 Device internal temperature sensor voltage 100 Voltage at I/O-0. Attenuation or gain is selected by bit 3. 101 Voltage at I/O-1. Attenuation or gain is selected by bit 3. 110 Voltage at VSUP/1 pin. Refer to electrical table for attenuation ratio (approx 5) 111 Voltage at VSENSE pin. Refer to electrical table for attenuation ratio (approx 5) b4 INT 2k - Select device internal 2.0 kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional to the VDD output current. 0 Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND. 1 Internal 2.0 kohm resistor enable. b3 I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain between I/O-0 (or I/O-1) and MUX-OUT pin 0 Gain is approx 2 for device with VDD = 5.0 V (Ref. to electrical table for exact gain value) Gain is approx 1.3 for device with VDD = 3.3 V (Ref. to electrical table for exact gain value) 1 Attenuation is approx 4 for device with VDD = 5.0 V (Ref. to electrical table for exact attenuation value) Attenuation is approx 6 for device with VDD = 3.3 V (Ref. to electrical table for exact attenuation value) Notes 42. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while 5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0). 33903/4/5 68 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 16. Internal memory registers A, B, C, and D, RAM_A, RAM_B, RAM_C, and RAM_D MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 0_0xxx [P/N] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01 00 _ 001 P Ram a7 Ram a6 Ram a5 Ram a4 Ram a3 Ram a2 Ram a1 Ram a0 Default state 0 0 0 0 0 0 0 0 Condition for default POR 01 00 _ 010 P Ram b7 Ram b6 Ram b5 Ram b4 Ram b3 Ram b2 Ram b1 Ram b0 Default state 0 0 0 0 0 0 0 0 01 00 _ 011 P Ram c7 Ram c6 Ram c5 Ram c4 Ram c3 Ram c2 Ram c1 Ram c0 Default state 0 0 0 0 0 0 0 0 Condition for default POR Condition for default POR 01 00 _ 100 P Ram d7 Ram d6 Ram d5 Ram d4 Ram d3 Ram d2 Ram d1 Ram d0 Default state 0 0 0 0 0 0 0 0 Condition for default POR 10.3.2 INIT registers Note: these registers can be written only in INIT mode Table 17. Initialization regulator registers, INIT REG (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0101 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 01 00 _ 101 P I/O-x sync VDDL rst[1] Default state 1 0 bit 5 bit 4 VDDL rst[0] VDD rstD[1] 0 Condition for default Bit bit 3 bit 2 bit 1 bit 0 VDD rstD[0] VAUX5/3 Cyclic on[1] Cyclic on[0] 0 0 0 0 0 POR Description b7 I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected 0 I/O-1 sense anytime 1 I/O-1 sense during I/O-0 activation b6, b5 VDDL RST[1] VDDL RST[0] - Select the VDD undervoltage threshold, to activate RST pin and/or INT 00 Reset at approx 0.9 VDD. 01 INT at approx 0.9 VDD, Reset at approx 0.7 VDD 10 Reset at approx 0.7 VDD 11 Reset at approx 0.9 VDD. b4, b3 VDD RSTD[1] VDD RSTD[0] - Select the RST pin low lev duration, after VDD rises above the VDD undervoltage threshold 00 1.0 ms 01 5.0 ms 10 10 ms 11 20 ms b2 [VAUX 5/3] - Select Vauxilary output voltage 0 VAUX = 3.3 V 1 VAUX = 5.0 V b1, b0 Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected 33903/4/5 NXP Semiconductors 69 SERIAL PERIPHERAL INTERFACE Bit Description 00 200 s (typical value. Ref. to dynamic parameters for exact value) 01 400 s (typical value. Ref. to dynamic parameters for exact value) 10 800 s (typical value. Ref. to dynamic parameters for exact value) 11 1600 s (typical value. Ref. to dynamic parameters for exact value) Table 18. Initialization watchdog registers, INIT watchdog (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0110 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 110 P WD2INT MCU_OC OC-TIM WD Safe WD_spi[1] WD_spi[0] WD N/Win Crank Default state 0 1 0 0 0 1 0 Condition for default Bit POR Description b7 WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command 0 Function disable. No constraint between INT occurrence and INT source read. 1 INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods. b6, b5 MCU_OC, OC-TIM - In LP VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold is defined in device electrical parameters (approx 1.5 mA) In LP mode, when watchdog is not selected no watchdog + 00 In LP VDD ON mode, VDD overcurrent has no effect no watchdog + 01 In LP VDD ON mode, VDD overcurrent has no effect no watchdog + 10 In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > 100 s (typically) is a wake-up event no watchdog + 11 In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms) In LP mode when watchdog is selected watchdog + 00 In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. watchdog + 01 In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. watchdog + 10 In LP VDD ON mode, VDD overcurrent for a time > 100 s (typically) is a wake-up event. watchdog + 11 In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a watchdog refresh condition. VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms) b4 WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse 0 SAFE pin is set low at the time of the RST pin low activation 1 SAFE pin is set low at the second consecutive time RST pulse b3, b2 WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation 00 Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI 01 Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits. 10 Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command. 33903/4/5 70 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Bit Description 11 Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command. b1 WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation 0 Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period 1 Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period) b0 Crank - Select the VSUP/1 threshold to disable VDD, while VSUP1 is falling toward GND 0 VDD disable when VSUP/1 is below typically 4.0 V (parameter VSUP-TH1), and device in Reset mode 1 VDD kept ON when VSUP/1 is below typically 4.0 V (parameter VSUP_TH1) Table 19. Initialization LIN and I/O registers, INIT LIN I/O (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0111 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 00 _ 111 P I/O-1 ovoff LIN_T2[1] LIN_T2[0] LIN_T/1[1] LIN_T/1[0] I/O-1 out-en I/O-0 out-en Cyc_Inv Default state 0 0 0 0 0 0 0 Condition for default Bit POR Description b7 I/O-1 ovoff - Select the deactivation of I/O-1 when VDD or VAUX overvoltage condition is detected 0 Disable I/O-1 turn off. 1 Enable I/O-1 turn off, when VDD or VAUX overvoltage condition is detected. b6, b5 LIN_T2[1], LIN_T2[0] - Select pin operation as LIN Master pin switch or I/O 00 pin is OFF 01 pin operation as LIN Master pin switch 10 pin operation as I/O: HS switch and Wake-up input 11 N/A b4, b3 LIN_T/1[1], LIN_T/1[0] - Select pin operation as LIN Master pin switch or I/O 00 pin is OFF 01 pin operation as LIN Master pin switch 10 pin operation as I/O: HS switch and Wake-up input 11 N/A b2 I/O-1 out-en- Select the operation of the I/O-1 as output driver (HS, LS) 0 Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input. 1 Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver. b1 I/O-0 out-en - Select the operation of the I/O-0 as output driver (HS, LS) 0 Disable HS and LS drivers of I/O-0 can only be used as input. 1 Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers. b0 Cyc_Inv - Select I/O-0 operation in device LP mode, when cyclic sense is selected 33903/4/5 NXP Semiconductors 71 SERIAL PERIPHERAL INTERFACE Bit Description 0 During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, I/O-0 is disable (HS and LS drivers OFF). 1 During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, the opposite driver of I/O_0 is actively set. Example: If I/0_0 HS is ON during active time, then I/O_O LS is turned ON at expiration of the active time, for the duration of the cyclic sense period. Table 20. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_1000 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 000 P LPM w RNDM SPI parity INT pulse INT width INT flash Dbg Res[2] Dbg Res[1] Dbg Res[0] Default state 0 0 0 0 0 0 0 Condition for default POR Bit Description b7 LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD ON. 0 Function disable: the LP mode can be entered without usage of Random Code 1 Function enabled: the LP mode is entered using the Random Code b6 SPI parity - Select usage of the parity bit in SPI write operation 0 Function disable: the parity is not used. The parity bit must always set to logic 0. 1 Function enable: the parity is used, and parity must be calculated. b5 INT pulse -Select INT pin operation: low level pulse or low level 0 INT pin will assert a low level pulse, duration selected by bit [b4] 1 INT pin assert a permanent low level (no pulse) b4 INT width - Select the INT pulse duration 0 INT pulse duration is typically 100 s. Ref. to dynamic parameter table for exact value. 1 INT pulse duration is typically 25 s. Ref. to dynamic parameter table for exact value. b3 INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode Function disable Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash mode. b2, b1, b0 Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric table for resistor range value.(43) 0xx Function disable 100 100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE mode B3 101 101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE mode B2 110 110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE mode B1 111 111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE mode A Notes 43. Bits b2,1 and 0 allow the following operation: First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt register (Ref. to device flag table). Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 = 1, this selection has higher priority than `hardware', and device will behave according to b2,b1 and b0 setting 33903/4/5 72 NXP Semiconductors SERIAL PERIPHERAL INTERFACE 10.3.3 Specific mode register Table 21. Specific mode register, SPE_MODE MOSI First Byte [15-8] [b_15 b_14] 01_001 [P/N] 01 01_ 001 P Default state Condition for default Bit b7, b6 bit 6 Sel_Mod[1] Sel_Mod[0] 0 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Rnd_C5b Rnd_C4b Rnd_C3b Rnd_C2b Rnd_C1b Rnd_C0b 0 0 0 0 0 POR Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command. RESET mode 01 INIT mode 10 FLASH mode 11 N/A 10.3.3.1 bit 7 Description 00 b5....b0 MOSI Second Byte, bits 7-0 [Rnd_C4b... Rnd_C0b] - Random Code inverted, these six bits are the inverted bits obtained from the SPE MODE Register read command. The SPE mode register is used for the following operation - Set the device in RESET mode, to exercise or test the RESET functions. - Go to INIT mode, using the Secure SPi command. - Go to FLASH mode (in this mode the watchdog timer can be extended up to 32 s). - Activate the SAFE pin by S/W. This mode (called Special mode) is accessible from the secured SPI command, which consist of 2 commands: 1) reading a random code and 2) then write the inverted random code plus mode selection or SAFE pin activation: Return to INIT mode is done as follow (this is done from Normal mode only): 1) Read random code: MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] MISO report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code) 2) Write INIT mode + random code inverted MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted) MISO : xxxx xxxx xxxx xxxx (don't care) SAFE pin activation: SAFE pin can be set low, only in INIT mode, with following commands: 1) Read random code: MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] MISO report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code) 2) Write INIT mode + random code bits 5:4 not inverted and random code bits 3:0 inverted MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted) MISO : xxxx xxxx xxxx xxxx (don't care) Return to Reset or Flash mode is done similarly to the go to INIT mode, except that the b7 and b6 are set according to the table above (b7, b6 = 00 - go to reset, b7, b6 = 10 - go to Flash). 33903/4/5 NXP Semiconductors 73 SERIAL PERIPHERAL INTERFACE 10.3.4 Timer registers Table 22. Timer register A, LP VDD overcurrent & watchdog period normal mode, TIM_A MOSI First Byte [15-8] [b_15 b_14] 01_010 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W/D_N[4] W/D_Nor[3] W/D_N[2] W/D_Nor[0] 1 1 1 0 01 01_ 010 P I_mcu[2] I_mcu[1] I_mcu[1] watchdog Nor[4] Default state 0 0 0 1 Condition for default POR LP VDD overcurrent (ms) b6, b5 b7 00 01 10 11 0 3 (def) 6 12 24 1 4 8 16 32 Watchdog period in device normal mode (ms) b4, b3 b2, b1, b0 000 001 010 011 100 101 110 111 00 2.5 5 10 20 40 80 160 320 01 3 6 12 24 48 96 192 384 10 3.5 7 14 28 56 112 224 448 11 4 8 16 32 64 128 256 (def) 512 Table 23. Timer register B, cyclic sense and cyclic INT, in device LP mode, TIM_B MOSI First Byte [15-8] [b_15 b_14] 01_011 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 01 01_ 011 P Cyc-sen[3] Default state 0 bit 5 bit 4 Cyc-sen[2] Cyc-sen[1] Cyc-sen[0] 0 0 bit 3 bit 2 bit 1 bit 0 Cyc-int[3] Cyc-int[2] Cyc-int[1] Cyc-int[0] 0 0 0 0 0 Condition for default POR Cyclic sense (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 3 6 12 24 48 96 192 384 1 4 8 16 32 64 128 256 512 Cyclic interrupt (ms) b3 b2, b1, b0 000 001 010 011 100 101 110 111 0 6 (def) 12 24 48 96 192 384 768 1 8 16 32 64 128 258 512 1024 33903/4/5 74 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 24. Timer register C, watchdog LP mode or flash mode and forced wake-up timer, TIM_C MOSI First Byte [15-8] [b_15 b_14] 01_100 [P/N] 01 01_ 100 P Default state MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 WD-LP-F[3] WD-LP-F[2] WD-LP-F[1] WD-LP-F[0] 0 0 0 bit 3 bit 2 bit 1 bit 0 FWU[3] FWU[2] FWU[1] FWU[0] 0 0 0 0 0 Condition for default POR Table 25. Typical timing values Watchdog in LP VDD ON mode (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 12 24 48 96 192 384 768 1536 1 16 32 64 128 256 512 1024 2048 Watchdog in flash mode (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 256 512 1024 2048 4096 8192 16384 32768 Forced wake-up (ms) b3 b2, b1, b0 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 64 128 258 512 1024 2048 4096 8192 10.3.5 Watchdog and mode registers Table 26. Watchdog refresh register, watchdog(44) MOSI First Byte [15-8] [b_15 b_14] 01_101 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 101 P 0 0 0 0 0 0 0 0 Default state 0 0 0 0 0 0 0 0 Condition for default POR Notes 44. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the watchdog and also to transition from INIT mode to Normal mode, and from Normal Request mode to Normal mode (after a wake-up of a reset) 33903/4/5 NXP Semiconductors 75 SERIAL PERIPHERAL INTERFACE . Table 27. MODE register, mode MOSI Second Byte, bits 7-0 MOSI First Byte [15-8] [b_15 b_14] 01_110 [P/N] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 110 P mode[4] mode[3] mode[2] mode[1] mode[0] Rnd_b[2] Rnd_b[1] Rnd_b[0] Default state N/A N/A N/A N/A N/A N/A N/A N/A Table 28. LP VDD off selection and FWU / cyclic sense selection b7, b6, b5, b4, b3 FWU Cyclic Sense 0 1100 OFF OFF 0 1101 OFF ON 0 1110 ON OFF 0 1111 ON ON Table 29. LP VDD on selection and operation mode b7, b6, b5, b4, b3 FWU Cyclic Sense Cyclic INT Watchdog 1 0000 OFF OFF OFF OFF 1 0001 OFF OFF OFF ON 1 0010 OFF OFF ON OFF 1 0011 OFF OFF ON ON 1 0100 OFF ON OFF OFF 1 0101 OFF ON OFF ON 1 0110 OFF ON ON OFF 1 0111 OFF ON ON ON 1 1000 ON OFF OFF OFF 1 1001 ON OFF OFF ON 1 1010 ON OFF ON OFF 1 1011 ON OFF ON ON 1 1100 ON ON OFF OFF 1 1101 ON ON OFF ON 1 1110 ON ON ON OFF 1 1111 ON ON ON ON b2, b1, b0 Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command. The usage of these bits are optional and must be previously selected in the INIT MISC register [See bit 7 (LPM w RNDM) in Table 20] Prior to enter in LP VDD ON or LP VDD OFF, the Wake-up flags must be cleared or read. This is done by the following SPI commands (See Table 39, Device flag, I/O real time and device identification): 0xE100 for CAN Wake-up clear 0xE380 for I/O Wake-up clear 0xE700 for LIN1 Wake-up clear 0xE900 for LIN2 Wake-up clear If Wake-up flags are not cleared, the device will enter into the selected LP mode and immediately Wake-up. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared in order to meet the low power current consumption specification. This is done by the following SPI command: 0xE180 (read CAN failure flags) When the device is in LP VDD ON mode, the Wake-up by a SPI command uses a write to `Normal Request mode', 0x5C10. 33903/4/5 76 NXP Semiconductors SERIAL PERIPHERAL INTERFACE 10.3.5.1 Mode register features The mode register includes specific functions and a `global SPI command' that allow the following: - read device current mode - read device Debug status - read state of SAFE pin - leave Debug state - release or turn off SAFE pin - read a 3 bit Random Code to enter in LP mode These global commands are built using the MODE register address bit [13-9], along with several combinations of bit [15-14] and bit [7]. Note, bit [8] is always set to 1. 10.3.5.2 Entering into LP mode using random code - LP mode using Random Code must be selected in INIT mode via bit 7 of the INIT MISC register. - In Normal mode, read the Random Code using 0x1D00 or 0x1D80 command. The 3 Random Code bits are available on MISO bits 2,1 and 0. - Write LP mode by inverting the 3 random bits. Example - Select LP VDD OFF without cyclic sense and FWU: 1. in hex: 0x5C60 to enter in LP VDD OFF mode without using the 3 random code bits. 2. if Random Code is selected, the commands are: - Read Random Code: 0x1D00 or 0x1D80, MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1], Rnd_[0]. - Write LP VDD OFF mode, using Random Code inverted: in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0]. Table 30 summarizes these commands Table 30. Device modes Global commands and effects MOSI Read device current mode, Leave debug mode. Keep SAFE pin as is. MOSI in hexadecimal: 1D 00 Read device current mode, Leave debug mode. Keep SAFE pin as is. MOSI in hexadecimal: DD 00 MISO reports Debug and SAFE state (bits 1,0) Read device current mode, Keep DEBUG mode Release SAFE pin (turn OFF). MOSI in hexadecimal: DD 80 MISO reports Debug and SAFE state (bits 1,0) bits 13-9 bit 8 bit 7 bits 6-0 00 01 110 1 0 000 0000 bit 15-8 bit 7-3 bit 2-0 Fix Status device current mode Random code MISO MOSI Read device current mode Release SAFE pin (turn OFF). MOSI in hexadecimal: 1D 80 bits 15-14 bits 15-14 bits 13-9 bit 8 00 01 110 1 MISO 1 000 0000 bit 7-3 bit 2-0 Fix Status device current mode Random code bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 11 01 110 1 0 000 0000 bit 15-8 bit 7-3 bit 2 bit 1 bit 0 Fix Status device current mode X SAFE DEBUG MISO MOSI bits 6-0 bit 15-8 MISO MOSI bit 7 bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0 11 01 110 1 1 000 0000 bit 15-8 bit 7-3 bit 2 bit 1 bit 0 Fix Status device current mode X SAFE DEBUG Table 31 describes MISO bits 7-0, used to decode the device's current mode. 33903/4/5 NXP Semiconductors 77 SERIAL PERIPHERAL INTERFACE Table 31. MISO bits 7-3 Device current mode, any of the above commands b7, b6, b5, b4, b3 MODE 0 0000 INIT 0 0001 FLASH 0 0010 Normal Request 0 0011 Normal mode 1 XXXX Low Power mode (Table 29) Table 32 describes the SAFE and DEBUG bit decoding. Table 32. SAFE and DEBUG status SAFE and DEBUG bits b1 description 0 SAFE pin ON, driver activated 1 SAFE pin OFF, not activated b0 description 0 Debug mode OFF 1 Debug mode Active 33903/4/5 78 NXP Semiconductors SERIAL PERIPHERAL INTERFACE 10.3.6 Regulator, CAN, I/O, INT and lin registers Table 33. Regulator register MOSI First Byte [15-8] [b_15 b_14] 01_111 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 01 01_ 111 P VAUX[1] VAUX[0] - 5V-can[1] 5V-can[0] VDD bal en Default state 0 0 N/A 0 0 N/A Condition for default POR Bits b7 b6 bit 1 bit 0 VDD bal auto VDD OFF en N/A N/A POR Description VAUX[1], VAUX[0] - Vauxilary regulator control 00 Regulator OFF 01 Regulator ON. undervoltage (UV) and Overcurrent (OC) monitoring flags not reported. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. 10 Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. 11 Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 25 s blanking time. b4 b3 5 V-can[1], 5 V-can[0] - 5V-CAN regulator control 00 Regulator OFF 01 Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags not reported. 1.0 ms blanking time for UV and OC detection. Note: by default when in Debug mode 10 Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active. 1.0 ms blanking time for UV and OC detection. 11 Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active after 25 s blanking time. b2 VDD bal en - Control bit to Enable the VDD external ballast transistor 0 External VDD ballast disable 1 External VDD ballast Enable b1 VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA 0 Disable the automatic activation of the external ballast 1 Enable the automatic activation of the external ballast, if VDD > typically 60 mA b0 VDD OFF en - Control bit to allow transition into LP VDD OFF mode (to prevent VDD turn OFF) 0 Disable Usage of LP VDD OFF mode 1 Enable Usage of LP VDD OFF mode 33903/4/5 NXP Semiconductors 79 SERIAL PERIPHERAL INTERFACE Table 34. CAN register(45) MOSI First byte [15-8] [b_15 b_14] 10_000 [P/N] 01 10_ 000P Default state Condition for default MOSI Second Byte, bits 7-0 bit 7 bit 6 CAN mod[1] CAN mod[0] 1 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Slew[1] Slew[0] Wake-up 1/3 - - CAN int 0 - - 0 0 note 0 POR Bits b7 b6 POR 0 POR Description CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-up enable / disable 00 CAN interface in Sleep mode, CAN Wake-up disable. 01 CAN interface in receive only mode, CAN driver disable. 10 CAN interface is in Sleep mode, CAN Wake-up enable. In device LP mode, CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT. 11 CAN interface in transmit and receive mode. b5 b4 Slew[1] Slew[0] - CAN driver slew rate selection 00/11 FAST 01 MEDIUM 10 SLOW b3 Wake-up 1/3 - Selection of CAN Wake-up mechanism 0 3 dominant pulses Wake-up mechanism 1 Single dominant pulse Wake-up mechanism b0 CAN INT - Select the CAN failure detection reporting 0 Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN) 1 Select INT generation as soon as a bus failure is detected, event if not fully identified Notes 45. The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is set in Normal mode, the CAN state is controlled by bits 7 and 6. 33903/4/5 80 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 35. I/O register MOSI First byte [15-8] [b_15 b_14] 10_001 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 001P I/O-3 [1] I/O-3 [0] I/O-2 [1] I/O-2 [0] I/O-1 [1] I/O-1 [0] I/O-0 [1] I/O-0 [0] Default state 0 0 0 0 0 0 0 0 Condition for default Bits b7 b6 Description I/O-3 [1], I/O-3 [0] - I/O-3 pin operation 00 I/O-3 driver disable, Wake-up capability disable 01 I/O-3 driver disable, Wake-up capability enable. 10 I/O-3 HS driver enable. 11 I/O-3 HS driver enable. b5 b4 I/O-2 [1], I/O-2 [0] - I/O-2 pin operation 00 I/O-2 driver disable, Wake-up capability disable 01 I/O-2 driver disable, Wake-up capability enable. 10 I/O-2 HS driver enable. 11 I/O-2 HS driver enable. b3 b2 I/O-1 [1], I/O-1 [0] - I/O-1 pin operation 00 I/O-1 driver disable, Wake-up capability disable 01 I/O-1 driver disable, Wake-up capability enable. 10 I/O-1 LS driver enable. 11 I/O-1 HS driver enable. b1 b0 POR I/O-0 [1], I/O-0 [0] - I/O-0 pin operation 00 I/O-0 driver disable, Wake-up capability disable 01 I/O-0 driver disable, Wake-up capability enable. 10 I/O-0 LS driver enable. 11 I/O-0 HS driver enable. 33903/4/5 NXP Semiconductors 81 SERIAL PERIPHERAL INTERFACE Table 36. INT register MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 010P CAN failure MCU req LIN2 fail LIN1fail I/O SAFE - Vmon Default state 0 0 0 0 0 0 0 0 Condition for default POR Bits Description b7 CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN overcurrent, Driver Overtemp, TXD-PD, RXD-PR, RX2HIGH, and CANBUS Dominate clamp) 0 INT disable 1 INT enable. b6 MCU req - Control bit to request an INT. INT will occur once when the bit is enable 0 INT disable 1 INT enable. b5 LIN2 fail - Control bit to enable INT when of failure on LIN2 interface 0 INT disable 1 INT enable. b4 LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface 0 INT disable 1 INT enable. b3 I/O - Bit to control I/O interruption: I/O failure 0 INT disable 1 INT enable. b2 SAFE - Bit to enable INT when of: Vaux overvoltage, VDD overvoltage, VDD Temp pre-warning, VDD undervoltage(46), SAFE resistor mismatch, RST terminal short to VDD, MCU request INT.(47) 0 INT disable 1 INT enable. b0 VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Overcurrent, VSUV, VSOV, VSENSELOW, 5V-CAN low or thermal shutdown, VAUX low or VAUX overcurrent 0 INT disable 1 INT enable. Notes 46. If VDD undervoltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 69. 47. Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request. 33903/4/5 82 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 37. LIN/1 Register(49) MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 011P Default state MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0] 0 0 0 Condition for default Bits b7 b6 0 bit 3 bit 2 bit 1 bit 0 - LIN T/1 on - VSUP ext 0 0 0 0 POR Description LIN mode [1], LIN mode [0] - LIN/1 interface mode control, Wake-up enable / disable 00 LIN/1 disable, Wake-up capability disable 01 not used 10 LIN/1 disable, Wake-up capability enable 11 LIN/1 Transmit Receive mode(48) b5 b4 bit 4 Slew rate[1], Slew rate[0] LIN/1 slew rate selection 00 Slew rate for 20 kbit/s baud rate 01 Slew rate for 10 kbit/s baud rate 10 Slew rate for fast baud rate 11 Slew rate for fast baud rate b2 LIN T/1 on 0 LIN/1 termination OFF 1 LIN/1 termination ON b0 VSUP ext 0 LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification 1 LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled. Notes 48. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in recessive state. An attempt to set TXD/RXD mode, while TXD-L is low, will be ignored and the LIN interface remains disabled. 49. In order to use the LIN interface, the 5V-CAN regulator must be set to ON. 33903/4/5 NXP Semiconductors 83 SERIAL PERIPHERAL INTERFACE Table 38. LIN2 register(51) MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] 01 10_ 100P MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0] Default state 0 0 0 Condition for default Bits b7 b6 0 bit 3 bit 2 bit 1 bit 0 - LIN T2 on - VSUP ext 0 0 0 0 POR Description LIN mode [1], LIN mode [0] - LIN 2 interface mode control, Wake-up enable / disable 00 LIN2 disable, Wake-up capability disable 01 not used 10 LIN2 disable, Wake-up capability enable 11 LIN2 Transmit Receive mode(50) b5 b4 bit 4 Slew rate[1], Slew rate[0] LIN 2slew rate selection 00 Slew rate for 20 kbit/s baud rate 01 Slew rate for 10 kbit/s baud rate 10 Slew rate for fast baud rate 11 Slew rate for fast baud rate b2 LIN T2 on 0 LIN 2 termination OFF 1 LIN 2 termination ON b0 VSUP ext 0 LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification 1 LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled. Notes 50. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in a recessive state. An attempt to set TXD/RXD mode while TXD-L is low, will be ignored and the LIN interface will remain disabled. 51. In order to use the LIN interface, the 5V-CAN regulator must be set to ON. 10.4 Flags and device status 10.4.1 Description The table below is a summary of the device flags, I/O real time level, device Identification, and includes examples of SPI commands (SPI commands do not use parity functions). They are obtained using the following commands. This command is composed of the following: bits 15 and 14: * [1 1] for failure flags * - [0 0] for I/O real time status, device identification and CAN LIN driver receiver real time state. * bit 13 to 9 are the register address from which the flags is to be read. * bit 8 = 1 (this is not parity bit function, as this is a read command). When a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure event has recovered). 33903/4/5 84 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 39. Device flag, I/O real time and device identification Bits 15-14 13-9 8 7 6 5 4 3 2 1 0 MOSI bits 15-7 MOSI MISO bits [15, 14] Address [13-9] bit 8 MISO bits [7-0], device response on MISO pin 8 Bits Device Fixed Status (bits 15...8) 11 0_1111 REG 1 Next 7 MOSI bits (bits 6.0) should be "000_0000" bit 7 bit 7 0 VAUX_LOW 1 - bit 6 bit 5 5V-CAN_ VAUX_overCU THERMAL SHUTDO RRENT WN REG 11 - - bit 4 bit 3 bit 2 bit 1 bit 0 5V-CAN_ UV 5V-CAN_ overCURR ENT VSENSE_ LOW VSUP_ underVOLT AGE IDD-OCNORMAL MODE RST_LOW (<100 ms) VSUP_ BATFAIL IDD-OC-LP VDDON VDD_ THERMAL SHUTDOW N MODE Hexa SPI commands to get Vreg Flags: MOSI 0x DF 00, and MOSI Ox DF 80 11 1_0000 CAN 0 CAN Wake-up - 1 CAN_UF CAN_F 1 CAN TXD dom CAN Bus Dom Overcurren clamp t CANH to VBAT CANH to VDD CANH to GND - - VSUP/2-UV VSUP/1-OV I/O_O thermal watchdog flash mode 50% INT service Timeout Reset request Hardware Leave Debug CAN RXD low(52) Rxd high Overtemp CANL to VBAT CANL to VDD CANL to GND Hexa SPI commands to get CAN Flags: MOSI 0x E1 00, and MOSI 0x E1 80 00 1_0000 CAN 1 1 CAN Driver State CAN Receiver State CAN WU en/dis - - - Hexa SPI commands to get CAN real time status: MOSI 0x 21 80 11 1_0001 I/O 0 HS3 short HS2 short to SPI parity to GND GND error 1 I/O_1-3 Wake-up CSB low >2.0 ms 1 I/O I/O_0-2 Wake-up SPI Wakeup FWU LP VDD OFF Hexa SPI commands to get I/O Flags and I/O Wake-up: MOSI 0x E3 00, and MOSI 0x E3 80 00 1_0001 I/O 1 I/O_3 state 1 I/O_2 state I/O_1 state I/O_0 state Hexa SPI commands to get I/O real time level: MOSI 0x 23 80 11 1_0010 SAFE 0 INT request RST high DBG resistor VDD temp Pre-warning VDD UV 1 - - - VDD low >100 ms VDD low RST 1 SAFE VDD V Overvoltag AUX_overVO LTAGE e RST low >100 ms - multiple Resets watchdog refresh failure id1 id0 Hexa SPI commands to get INT and RST Flags: MOSI 0x E5 00, and MOSI 0x E5 80 00 1_0010 SAFE 1 1 VDD (5.0 V or 3.3 V) device p/n 1 device p/n 0 id4 id3 id2 Hexa SPI commands to get device Identification: MOSI 0x 2580 example: MISO bit [7-0] = 1011 0100: MC33904, 5.0 V version, silicon Rev. C and D LIN/1 11 1_0011 LIN 1 1 0 - LIN1 Wake-up LIN1 Term short to GND LIN 1 Overtemp RXD1 low RXD1 high TXD1 dom LIN1 bus dom clamp Hexa SPI commands to get LIN 2 Flags: MOSI 0x E7 00 00 1_0011 LIN 1 1 1 LIN1 State LIN1 WU en/dis - - - - - - 33903/4/5 NXP Semiconductors 85 SERIAL PERIPHERAL INTERFACE Table 39. Device flag, I/O real time and device identification Hexa SPI commands to get LIN1 real time status: MOSI 0x 27 80 LIN2 11 1_0100 LIN 2 00 1_0100 LIN 2 1 0 - LIN2 Wake-up LIN2 Term short to GND LIN 2 Overtemp RXD2 low RXD2 high TXD2 dom LIN2 bus dom clamp Hexa SPI commands to get LIN 2 Flags: MOSI 0x E9 00 1 1 LIN2 State LIN2 WU en/dis - - - - - - Hexa SPI commands to get LIN2 real time status: MOSI 0x 29 80 Notes 52. Not available on `C' and `D' versions Table 40. Flag descriptions Flag Description REG Description Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold. Set / Reset condition Set: VAUX below threshold for t >100 s typically. Reset: VAUX above threshold and flag read (SPI) VAUX_overCUR Description Report that current out of VAUX regulator is above VAUX_OC threshold. RENT Set / Reset condition Set: Current above threshold for t >100 s. Reset: Current below threshold and flag read by SPI. 5 V-CAN_ THERMAL SHUTDOWN Description Report that the 5 V-CAN regulator has reached overtemperature threshold. Set / Reset condition Set: 5 V-CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Description Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold. Set / Reset condition Set: 5V-CAN below 5V-CAN UV for t >100 s typically. Reset: 5V-CAN > threshold and flag read (SPI) Description Report that the CAN driver output current is above threshold. Set / Reset condition Set: 5V-CAN current above threshold for t>100 s. Reset: 5V-CAN current below threshold and flag read (SPI) Description Reports that VSENSE pin is lower than the VSENSE LOW threshold. Set / Reset condition Set: VSENSE below threshold for t >100 s typically. Reset: VSENSE above threshold and flag read (SPI) VSUP_ Description Reports that VSUP/1 pin is lower than the VS1_LOW threshold. UNDERVOLTAG E Set / Reset condition Set: VSUP/1 below threshold for t >100 s typically. Reset: VSUP/1 above threshold and flag read (SPI) IDD-OCNORMAL MODE Description Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal mode. Set / Reset condition Set: current above threshold for t>100 s typically. Reset; current below threshold and flag read (SPI) VDD_ THERMAL SHUTDOWN Description Report that the VDD has reached overtemperature threshold, and was turned off. Set / Reset condition Set: VDD OFF due to thermal condition. Reset: VDD recover and flag read (SPI) RST_LOW (<100 ms) Description Report that the RST pin has detected a low level, shorter than 100 ms Set / Reset condition Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) VSUP_ BATFAIL Description Report that the device voltage at VSUP/1 pin was below BATFAIL threshold. Set / Reset condition Set: VSUP/1 below BATFAIL. Reset: VSUP/1 above threshold, and flag read (SPI) IDD-OC-LP VDDON mode Description Report that current out of VDD pin is higher that IDD-OC threshold LP, while device is in LP VDD ON mode. Set / Reset condition Set: current above threshold for t>100 s typically. Reset; current below threshold and flag read (SPI) VAUX_LOW 5V-CAN_UV 5V-can_ overcurrent VSENSE_ LOW 33903/4/5 86 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 40. Flag descriptions Flag Description CAN Description Report real time CAN bus driver state: 1 if Driver is enable, 0 if driver disable Set / Reset condition Set: CAN driver is enable. Reset: CAN driver is disable. Driver can be disable by SPI command (ex CAN set in RXD only mode) or following a failure event (ex: TXD Dominant). Flag read SPI command (0x2180) do not clear the flag, as it is "real time" information. Description Report real time CAN bus receiver state: 1 if Enable, 0 if disable Set / Reset condition Set: CAN bus receiver is enable. Reset: CAN bus receiver is disable. Receiver disable by SPI command (ex: CAN set in sleep mode). Flag read SPI command (0x2180) do not clear the flag, as it is "real time" information. Description Report real time CAN bus Wake-up receiver state: 1 if WU receiver is enable, 0 if disable Set / Reset condition Set: CAN Wake-up receiver is enable. Reset: CAN Wake-up receiver is disable. Wake-up receiver is controlled by SPI, and is active by default after device Power ON. SPI command (0x2180) do not change flag state. CAN Wake-up Description Report that Wake-up source is CAN Set / Reset condition Set: after CAN wake detected. Reset: Flag read (SPI) CAN Overtemp Description Report that the CAN interface has reach overtemperature threshold. Set / Reset condition Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Description Report that RXD pin is shorted to GND. Set / Reset condition Set: RXD low failure detected. Reset: failure recovered and flag read (SPI) Description Report that RXD pin is shorted to recessive voltage. Set / Reset condition Set: RXD high failure detected. Reset: failure recovered and flag read (SPI) Description Report that TXD pin is shorted to GND. CAN driver state CAN receiver state CAN WU enable RXD low(53) Rxd high TXD dom Set / Reset condition Set: TXD low failure detected. Reset: failure recovered and flag read (SPI) Bus Dom clamp Description Report that the CAN bus is dominant for a time longer than tDOM Set / Reset condition Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI) CAN Overcurrent Description Report that the CAN current is above CAN overcurrent threshold. Set / Reset condition Set: CAN current above threshold. Reset: current below threshold and flag read (SPI) Description Report that the CAN failure detection has not yet identified the bus failure Set / Reset condition Set: bus failure pre detection. Reset: CAN bus failure recovered and flag read Description Report that the CAN failure detection has identified the bus failure Set / Reset condition Set: bus failure complete detetction.Reset: CAN bus failure recovered and flag read Description Report CAN L short to VBAT failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) Description Report CANL short to VDD Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) Description Report CAN L short to GND failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) Description Report CAN H short to VBAT failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) Description Report CANH short to VDD Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) Description Report CAN H short to GND failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) CAN_UF CAN_F CANL to VBAT CANL to VDD CANL to GND CANH to VBAT CANH to VDD CANH to GND Notes 53. Not available on `C' and `D' versions 33903/4/5 NXP Semiconductors 87 SERIAL PERIPHERAL INTERFACE Table 40. Flag descriptions Flag Description I/O HS3 short to GND Description Report I/O-3 HS switch short to GND failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) HS2 short to GND Description Report I/O-2 HS switch short to GND failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) SPI parity error Description Report SPI parity error was detected. Set / Reset condition Set: failure detected. Reset: flag read (SPI) CSB low >2.0 ms Description Report SPI CSB was low for a time longer than typically 2.0 ms Set / Reset condition Set: failure detected. Reset: flag read (SPI) Description Report that VSUP/2 is below VS2_LOW threshold. Set / Reset condition Set VSUP/2 below VS2_LOW thresh. Reset VSUP/2 > VS2_LOW thresh and flag read (SPI) Description Report that VSUP/1 is above VS_HIGH threshold. Set / Reset condition Set VSUP/1 above VS_HIGH threshold. Reset VSUP/1 < VS_HIGH thresh and flag read (SPI) Description Report that the I/O-0 HS switch has reach overtemperature threshold. Set / Reset condition Set: I/O-0 HS switch thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI) Description Report that the watchdog period has reach 50% of its value, while device is in Flash mode. Set / Reset condition Set: watchdog period > 50%. Reset: flag read VSUP/2-UV VSUP/1-OV I/O-0 thermal watchdog flash mode 50% I/O-1-3 Wake- Description up Set / Reset condition Report that Wake-up source is I/O-1 or I/O-3 I/O-0-2 Wake- Description up Set / Reset condition Report that Wake-up source is I/O-0 or I/O-2 SPI Wake-up FWU INT service Timeout LP VDD OFF Reset request Hardware Leave Debug Set: after I/O-1 or I/O-3 wake detected. Reset: Flag read (SPI) Set: after I/O-0 or I/O-2 wake detected. Reset: Flag read (SPI) Description Report that Wake-up source is SPI command, in LP VDD ON mode. Set / Reset condition Set: after SPI Wake-up detected. Reset: Flag read (SPI) Description Report that Wake-up source is forced Wake-up Set / Reset condition Set: after Forced Wake-up detected. Reset: Flag read (SPI) Description Report that INT timeout error detected. Set / Reset condition Set: INT service timeout expired. Reset: flag read. Description Report that LP VDD OFF mode was selected, prior Wake-up occurred. Set / Reset condition Set: LP VDD OFF selected. Reset: Flag read (SPI) Description Report that RST source is an request from a SPI command (go to RST mode). Set / Reset condition Set: After reset occurred due to SPI request. Reset: flag read (SPI) Description Report that the device left the Debug mode due to hardware cause (voltage at DBG pin lower than typically 8.0 V). Set / Reset condition Set: device leave debug mode due to hardware cause. Reset: flag read. 33903/4/5 88 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Table 40. Flag descriptions Flag Description INT Description Report that INT source is an INT request from a SPI command. Set / Reset condition Set: INT occurred. Reset: flag read (SPI) Description Report that RST pin is shorted to high voltage. Set / Reset condition Set: RST failure detection. Reset: flag read. Description Report that the resistor at DBG pin is different from expected (different from SPI register content). Set / Reset condition Set: failure detected. Reset: correct resistor and flag read (SPI). Description Report that the VDD has reached overtemperature pre-warning threshold. Set / Reset condition Set: VDD thermal sensor above threshold. Reset: VDD thermal sensor below threshold and flag read (SPI) Description Reports that VDD pin is lower than the VDDUV threshold. Set / Reset condition Set: VDD below threshold for t >100 s typically. Reset: VDD above threshold and flag read (SPI) VDD Description Reports that VDD pin is higher than the typically VDD + 0.6 V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. overVOLTAGE Set / Reset condition Set: VDD above threshold for t >100 s typically. Reset: VDD below threshold and flag read (SPI) VAUX_overVOL Description Reports that VAUX pin is higher than the typically VAUX + 0.6 V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. TAGE Set / Reset condition Set: VAUX above threshold for t >100 s typically. Reset: VAUX below threshold and flag read (SPI) VDD LOW >100 ms Description Reports that VDD pin is lower than the VDDUV threshold for a time longer than 100 ms Set / Reset condition Set: VDD below threshold for t >100 ms typically. Reset: VDD above threshold and flag read (SPI) Description Report that VDD is below VDD undervoltage threshold. Set / Reset condition Set: VDD below threshold. Reset: fag read (SPI) Description 0: mean 3.3 V VDD version 1: mean 5.0 V VDD version Set / Reset condition N/A Description Describe the device part number: 00: MC33903 01: MC33904 10: MC33905S 11: MC333905D Set / Reset condition N/A Description Describe the silicon revision number 10010: silicon revision A (Pass 3.1) 10011: silicon revision B (Pass 3.2) 10100: silicon revision C and D Set / Reset condition N/A RST low >100 ms Description Report that the RST pin has detected a low level, longer than 100 ms (Reset permanent low) Set / Reset condition Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) Multiple Resets Description Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog refresh. Set / Reset condition Set: after detection of multiple reset pulses. Reset: flag read (SPI) watchdog refresh failure Description Report that a wrong or missing watchdog failure occurred. Set / Reset condition Set: failure detected. reset: flag read (SPI) INT request RST high DBG resistor VDD TEMP PREWARNING VDD UV VDD LOW VDD (5.0 V or 3.3 V) Device P/N1 and 0 Device id 4 to 0 33903/4/5 NXP Semiconductors 89 SERIAL PERIPHERAL INTERFACE Table 40. Flag descriptions Flag Description LIN/1/2 Description Report that the LIN/1/2 bus is dominant for a time longer than tDOM Set / Reset condition Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI) Description Report real time LIN interface TXD/RXD mode. 1 if LIN is in TXD/RXD mode. 0 is LIN is not in TXD/ RXD mode. Set / Reset condition Set: LIN in TXD RXD mode. Reset: LIN not in TXD/RXD mode. LIN not in TXD/RXD mode by SPI command (ex LIN set in Sleep mode) or following a failure event (ex: TxL Dominant). Flag read SPI command (0x2780 or 0x2980) do not clear it, as it is `real time' flag. Description Report real time LIN Wake-up receiver state. 1 if LIN Wake-up is enable, 0 if LIN Wake-up is disable (means LIN signal will not be detected and will not Wake-up the device). Set / Reset condition Set: LIN WU enable (LIN interface set in Sleep mode Wake-up enable). Reset: LIN Wake-up disable (LIN interface set in Sleep mode Wake-up disable). Flag read SPI command (0x2780 or 0x2980) do not clear the flag, as it is `real time' information. LIN/1/2 Wake-up Description Report that Wake-up source is LIN/1/2 Set / Reset condition Set: after LIN/1/2 wake detected. Reset: Flag read (SPI) LIN/1/2 Term short to GND Description Report LIN/1/2 short to GND failure Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) LIN/1/2 overtemp Description Report that the LIN/1/2 interface has reach overtemperature threshold. Set / Reset condition Set: LIN/1/2 thermal sensor above threshold. Reset: sensor below threshold and flag read (SPI) RXD-L/1/2 low Description Report that RXD/1/2 pin is shorted to GND. Set / Reset condition Set: RXD low failure detected. Reset: failure recovered and flag read (SPI) RXD-L/1/2 high Description Report that RXD/1/2pin is shorted to recessive voltage. Set / Reset condition Set: RXD high failure detected. Reset: failure recovered and flag read (SPI) TXD-L/1/2 dom Description Report that TXD/1/2 pin is shorted to GND. Set / Reset condition Set: TXD low failure detected. Reset: failure recovered and flag read (SPI) LIN/1/2 bus dom clamp LIN/1/2 State LIN/1/2 WU 10.4.2 Fix and extended device status For every SPI command, the device response on MISO is fixed status information. This information is either: Two Bytes Fix Status + Extended Status: when a device write command is used (MOSI bits 15-14, bits C1 C0 = 01) One Byte Fix Status: when a device read operation is performed (MOSI bits 15-14, bits C1 C0 = 00 or 11). Table 41. Status bits description Bits 15 14 13 12 11 10 9 8 7 6 MISO INT WU RST CANG LIN-G I/O-G SAFEG VREGG CANBUS CANLOC Bits 5 4 3 2 LIN2 LIN1 I/O-1 I/O-0 1 0 VREGVREG-0 1 Description INT Indicates that an INT has occurred and that INT flags are pending to be read. WU Indicates that a Wake-up has occurred and that Wake-up flags are pending to be read. RST Indicates that a reset has occurred and that the flags that report the reset source are pending to be read. CAN-G The INT, WU, or RST source is CAN interface. CAN local or CAN bus source. LIN-G The INT, WU, or RST source is LIN2 or LIN1 interface I/O-G The INT, WU, or RST source is I/O interfaces. SAFE-G The INT, WU, or RST source is from a SAFE condition VREG-G The INT, WU, or RST source is from a Regulator event, or voltage monitoring event CAN-LOC The INT, WU, or RST source is CAN interface. CAN local source. CAN-BUS The INT, WU, or RST source is CAN interface. CAN bus source. 33903/4/5 90 NXP Semiconductors SERIAL PERIPHERAL INTERFACE Bits Description LIN2 The INT, WU, or RST source is LIN2 interface LIN/LIN1 The INT, WU, or RST source is LIN1 interface I/O-0 The INT, WU, or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0) I/O-1 The INT, WU, or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1) VREG-1 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1) VREG-0 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0) 33903/4/5 NXP Semiconductors 91 TYPICAL APPLICATIONS 11 Typical applications * Optional 5.0 V (3.3 V) Q2 >2.2 F <10 k VBAT VBAUX VCAUX VAUX D1 VSUP 22 F (54) VSUP2 100 nF 1.0 k VBAT 22 k VSUP >1.0 F VDD DBG 5V-CAN VSENSE 100 nF I/O-0 100 nF CANH 4.7 nF 60 1.0 k option 1 option 1 INT INT MUX A/D 4.7 k * MCU SPI TXD RXD CAN CANL TXD-L1 RXD-L1 LIN1 TXD-L2 RXD-L2 LIN2 option 2 LIN1 LIN TERM2 1.0 k RST 1.0 k VSUP1/2 LIN BUS 1 VDD SPLIT LIN TERM1 VSUP1/2 >4.7 F RST MOSI SCLK MISO CS 60 CAN BUS Q1* VB VSUP1 I/O-1 LIN BUS 1 VE RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr N/C 1.0 k option 2 LIN2 GND SAFE VSUP VSUP Safe Circuitry Notes 54. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 F on VSUP1/VSUP2 pins Figure 42. 33905D typical application schematic 33903/4/5 92 NXP Semiconductors TYPICAL APPLICATIONS 5.0 V (3.3 V) Q2 >2.2 F <10 k VBAT VBAUX VCAUX VAUX D1 VSUP VSUP2 22 F 100 nF (55) 1.0 k VBAT >1.0 F VDD 5V-CAN VSENSE 22 k 100 nF VSUP I/O-0 4.7 nF INT MUX A/D TXD RXD CANH 60 INT I/O-3 4.7 k * CAN LIN1 RXD-L1 SPLIT MCU SPI TXD-L1 60 VDD RST I/O-1 VSUP >4.7 F RST MOSI SCLK MISO CS 100 nF CAN BUS Q1* VB VSUP1 DBG CANL LIN TERM1 VSUP1/2 1.0 k LIN BUS 1 VE RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr 1.0 k option 1 option 2 LIN1 GND SAFE VSUP VSUP Safe Circuitry Notes 55. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 F on VSUP1/VSUP2 pins Figure 43. 33905S typical application schematic 33903/4/5 NXP Semiconductors 93 TYPICAL APPLICATIONS * Optional 5V (3.3 V) Q2 >2.2 F <10 k VBAT VBAUX VCAUX VAUX VE D1 VSUP 22 F (56) VBAT 100 nF >1.0 F 1.0 k 100nF VSUP 22 k VSUP2 VB VSUP1 VDD VDD >4.7 F DBG 5V-CAN RST RST INT INT VSENSE MUX A/D MOSI SCLK MISO CS I/O-0 100 nF I/O-1 VBAT 22 k 4.7 k * MCU SPI TXD RXD I/O-2 VSUP Q1* RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr 100 nF CAN I/O-3 N/C CANH 60 CAN BUS 60 SPLIT 4.7 nF CANL GND SAFE VSUP VSUP OR function Safe Circuitry Notes 56. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 F on VSUP1/VSUP2 pins Figure 44. 33904 typical application schematic 33903/4/5 94 NXP Semiconductors TYPICAL APPLICATIONS VBAT D1 VSUP 22 F (57) VSUP1 100 nF >1.0 F VSUP2 VDD VDD >4.7 F DBG RST RST INT INT MOSI SCLK MISO CS SPI 5V-CAN VBAT I/O-0 22 k 100 nF MCU CANH 60 CAN BUS 60 TXD RXD SPLIT 4.7 nF CANL GND CAN N/C SAFE VSUP VSUP OR function Safe Circuitry Notes 57. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 F on VSUP1/VSUP2 pins Figure 45. 33903 typical application schematic 33903/4/5 NXP Semiconductors 95 TYPICAL APPLICATIONS VBAT Q1* D1 VSUP 22 F VBAT VSUP 100 nF 1.0 k 22 k >1.0 F VDD >4.7 F 5V-CAN VSENSE 100 nF VSUP 1.0 k LIN BUS 1 option1 INT MUX A/D option2 4.7 k (optional) CANL TXD RXD CAN LIN-T1 TXD-L1 RXD-L1 LIN1 LIN1 TXD-L2 RXD-L2 LIN2 1.0 k SPI MCU LIN-T2 VSUP 1.0 k LIN BUS 2 INT SPLIT CANH CAN BUS RST MOSI SCLK MISO CS 60 4.7 nF VDD RST IO-0 100 nF 60 VB VE DBG * = Optional option1 1.0 k option2 LIN2 GND SAFE VSUP VSUP Safe Circuitry Notes 58. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 F on VSUP pin Figure 46. 33903D typical application schematic 33903/4/5 96 NXP Semiconductors TYPICAL APPLICATIONS VBAT Q1 * D1 VSUP 22 F VSUP 100 nF 1.0 k VBAT 22 k VSUP >1.0 F VE 5V-CAN IO-0 CANH CAN BUS 4.7 nF SPLIT INT MUX A/D 4.7 k (optional) SPI MCU CAN TXD-L RXD-L CANL LIN LIN-T VSUP 1.0 k LIN BUS INT TXD RXD 60 VDD RST MOSI SCLK MISO CS IO-3 >4.7 F RST VSENSE 100 nF 100 nF 60 VB VDD DBG * = Optional option1 N/C 1.0 k option2 LIN GND SAFE VSUP VSUP Safe Circuitry Notes 59. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 F on VSUP pin 60. Leave N/C pins open. Figure 47. 33903S typical application schematic 33903/4/5 NXP Semiconductors 97 TYPICAL APPLICATIONS VBAT Q1* D1 VSUP 22 F VBAT VSUP 100 nF >1.0 F 1.0 k 22 k 100 nF 100 nF VE 5V-CAN IO-0 I/O-2 100 nF VDD RST INT INT MUX A/D MOSI SCLK MISO CS 22 k >4.7 F RST VSENSE VBAT VSUP VB VDD DBG * = Optional 4.7 k (optional) SPI TXD RXD MCU CAN IO-3 CANH 60 CAN BUS 60 4.7 nF SPLIT N/C CANL GND SAFE VSUP VSUP Safe Circuitry Notes 61. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 F on VSUP pin 62. Leave N/C pins open. Figure 48. 33903P typical application schematic 33903/4/5 98 NXP Semiconductors TYPICAL APPLICATIONS The following figure illustrates the application case where two reverse battery diodes can be used for optimization of the filtering and buffering capacitor at the VDD pin. This allows using a minimum value capacitor at the VDD pin to guarantee reset-free operation of the MCU during the cranking pulse and temporary (50 ms) loss of the VBAT supply. Applications without an external ballast on VDD and without using the VAUX regulator are illustrated as well. Q2 5.0 V/3.3 V Q2 VBAT 5.0 V/3.3 V D2 VBAT VBAUX VCAUX D1 C2 VAUX VSUP2 VE VSUP1 VB Q1 VBAUX VCAUX VAUX VSUP2 D1 VE VSUP1 VB C1 VDD Q1 VDD Partial View Partial View ex2: Split VSUP Supply ex1: Single VSUP Supply Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. Q2 5.0 V/3.3 V VBAT VBAT D1 D1 VBAUX VCAUX VAUX VSUP2 VE VSUP2 VSUP1 VBAUX VCAUX VAUX VE VSUP1 VB VB VDD VDD Partial View Partial View ex 3: No External Transistor, VDD ~100 mA Capability delivered by internal path transistor. ex 4: No External Transistor - No VAUX Figure 49. Application options 33903/4/5 NXP Semiconductors 99 PACKAGING 12 Packaging 12.1 SOIC 32 package dimensions For the most current package revision, visit www.NXP.com and perform a keyword search using the "98A" listed below. 33903/4/5 100 NXP Semiconductors PACKAGING 33903/4/5 NXP Semiconductors 101 PACKAGING 33903/4/5 102 NXP Semiconductors PACKAGING 12.2 SOIC 54 package dimensions 33903/4/5 NXP Semiconductors 103 PACKAGING 33903/4/5 104 NXP Semiconductors PACKAGING 33903/4/5 NXP Semiconductors 105 REVISION HISTORY 13 Revision 4.0 5.0 Revision history Date 9/2010 12/2010 6.0 4/2011 7.0 9/2011 8.0 1/2011 2/2012 9.0 4/2013 10.0 2/2014 11.0 8/2014 12.0 8/2016 13.0 5/2017 14.0 2/2018 Description of changes * * * * * * * * * * * * * * * * * * * * * * Initial Release - This document supersedes document MC33904_5. Initial release of document includes the MC33903 part number, the VDD 3.3 V version description, and the silicon revision rev. 3.2. Change details available upon request. Added 7.9. Cyclic INT operation during LP VDD on mode 47 Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device Removed . Drop voltage without external PNP pass transistor 19 for VDD=3.3 V devices Added VSUP1-3.3 to . VDD Voltage regulator, VDD pin 19. Added . Pull-up Current, TXD, VIN = 0 V 23 for VDD=3.3 V devices Revised 10.3.1. MUX and RAM registers 68 Revised 41. Status bits description 90 Added 10.3.5.2. Entering into LP mode using random code 77. Removed part numbers MCZ33905S3EK/R2, MCZ33904A3EK/R2 and MCZ33905D3EK/R2, and added part numbers MCZ33903BD3EK/R2, MCZ33903BD5EK/R2, MCZ33903BS3EK/R2 and MCZ33903BS5EK/R2. Voltage Supply was improved from 27V to 28V. Changed Classification from Advance Information to Technical Data. Updated Notes in Tables 8. Revised Tables 8; Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: to reflect a Typical value. Corrected typographical errors throughout. Added Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) parameter to Tables 8. Updated I/O pins (I/O-0: I/O-3) on page 33. Updated VOUT-5.0-EMC maximum Updated tLEAD parameter Added tCSLOW parameter Updated the Detail operation section to reflect the importance of acknowledging tLEAD and tCSLOW. Corrected typographical error in Tables 34 CAN REGISTER for Slew Rate bits b5,b4 Added 12 PCZ devices to the ordering information Bit label change on Table 39 from INT to SAFE Revised notes on Table 1 to include "C" version Split Falling Edge of CS to Rising Edge of SCLK to differentiate the "C" version Added "C" version note to Table 39 and Table 40 Added device ID 10100 Rev C, Pass 3.3 to Device id 4 to 0 Added Debug mode DBG voltage range parameter. Already detailed in text. Added the MC33903P device, making additions throughout the document, where applicable. * Changed all PC devices to MC devices. * * * * * * * * * * * * * * * * * * * No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to first paragraph. Added package type in Table 1. Added new parameter to Output Voltage on page 19 for VDD Added (22) Updated section 7.5.2.2. Watchdog in debug mode 40. Replaced "set" by "left". Changed tCS-TO in the Dynamic electrical characteristics from 2.5 to 2.0 Note added to MUX-output (MUXOUT) on page 33 of Functional pin description Added a paragraph in the SPI Detail operation section for the maximum tLEAD time in case the `CSB low' flag is set Added maximum tLEAD time in case the `CSB low' flag is set to 1 in the Dynamic electrical characteristics table Updated as per CIN 201608012I Added `D' version orderable part numbers to Table 1, Table 2, and Table 3 Updated note (2), (5), (9) Added note (3), (6), (10) (`C' versions are no longer recommended for new design) to Table 1, Table 2, and Table 3 Added reference to `D' version in the document where applicable Updated flag description for device id 4 to 0 in Table 40 Updated to NXP document format and style Updated Figure 29 to include 3.3 V information Updated workflow step 3 in Figure 30 (SPI commands: changed 0xDD00 to 0x1D80) Updated bit 1 description in Table 32 * * Updated note (7) (deleted "Output current limited to 100 mA") Updated values for VRST-VTH in Table 6 as per CIN 201712019I * * * * * * * * * * * * * Removed typ. and max. values for VRST-VTH (Low threshold, VDD = 5.0 V) Removed min. and typ. values for VRST-VTH (High threshold, VDD = 5.0 V) Removed typ. and max. values for VRST-VTH (Low threshold, VDD = 3.3 V) Removed min. and typ. values for VRST-VTH (High threshold, VDD = 3.3 V) 33903/4/5 106 NXP Semiconductors How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. Home Page: NXP.com There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits Web Support: http://www.nxp.com/support products herein. based on the information in this document. NXP reserves the right to make changes without further notice to any NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. (c) NXP B.V. 2018. Document Number: MC33903_4_5 Rev. 14.0 2/2018