W25X20BVSNIG TR - Winbond

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VITESSE

SEMICONDUCTOR CORPORATION

Page 1

3/8/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

SC9111

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

G52199-0, Rev. 1.2

Preliminary

Features

VSC9111 Block Diagram

• Integrated SONET/SDH Transport Overhead

Terminating Transceiver for use in STS-48/

STM-16 Applications

• Performs Byte Interleaved Multiplexing of

STS-12/STM-4 and STS-3/STM-1 SONET/

SDH Drop Side Data Streams

• Supports STS-48c/STM-4-16c Operation

• 16 bit PECL Interface to High-speed MUX/

DEMUX Transceivers

• Generic 8-bit Mi cropro cessor Interface

• Prepared for STS-192/STM-64 Applications

• +3.3V Power Supply

• +5V Tolerant TTL I/O

• Com pliant wi th SONET and SDH Require-

ments as Stated in ANSI T1.105, Bellcore

GR-253-COR E an d ITU-T G.707 Documents

• 0.35 Micron CMOS Technology

• Provides JTA G T AP Controller Conforming to

the IEEE 1149.1 Standard

• Thermally Enhanced 352 BGA Package

Section Generation

TSOP

Section Trace Buffer

SSTB

Line Side Interface

TLCLK+/-

TLOUT[15..0]+/-

TLCLKOUT+/-

TLPRTY+/-

RLPRTY+/-

RLIN[15..0]+/-

RLCLK+/-

Line Generation

TLOP

32 32

TXCLK_[A..D][1..4]

TXDAT_[A..D][1..4][1..0]

TXFP_[A..D][1..4]

TXCLKOUT_[A..D]

RXCLK_[A..D]

RXDAT_[A..D][1..4][1..0]

RXPRTY_[A..D][1..4]

INTB

RSTB

RDB

WRB

CSB

ALE

A[7..0]

D[7..0]

BERM

LOF

LOS

LOPC

RXRCLK TXRCLK

GPIO[7..0]

LIF

TXPRTY_[A..D][1..4]

JTAG TAP

TRSTB

TMS

TCK

TDI

TDO

RXFP_[A..D]

Byte

Interleaving

BIMX

Byte

Interleaving

BIDX

TXRST

TSPDAT1

TSPREN1

TSPFP1

TSPCLK1

TTOHFP

TTOHREN

TTOHCLK

TTOHEN

TXOHEN_[A..D]

Transport Overhead Insertion

TOAP

TTOH[3..0]

CLKRSTEN

TSPDAT2

TSPREN2

TSPFP2

TSPCLK2

Section Termination

RSOP Line Termination

RLOP

Transport Overhead Extraction

ROAP

RSPFP

RSPDAT1

RSPVALID1

RSPCLK1

RTOHVALID

RTOHCLK

RTOHFP

RTOH[3..0]

RSPDAT2

RSPVALID2

RSPCLK2

TLFP+/-

RLFP+/-

TLSYNC+/-

PMTICK

CPU

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC9111

ONET/SDH 2.5Gb/s

Transport Terminating Transceiv er

Page 2 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98 3/8/99

G52199-0, Rev. 1.2

Preliminary

Functional Overview

The VSC9111 is a SONET/SDH transport overhead terminating transceiver. It may be used as an interface

between four STS-12/STM-4 data streams or sixteen STS-3/S TM-1 data streams and a single STS-48 data

stream. It also supports transport o v erhead pr ocessing for STS-48 c data stre ams. When used in con junction with

a high-speed MUX/DEMUX transceiver, this device provides a complete solution for migrating from STS-12/

STS-3 to STS-48 interfaces in SONET/SDH/ATM multiplexers and terminals. The basic features of the receive

and transmit datapaths and features of other interfaces are listed below.

Receive Datapath:

· Performs framing on the A1 and A2 bytes. Supports 12 bit, 24 bit and 48 bit wide A1 A2 framing patterns

· Generates OOF, LOF and LOS alarm status

· Performs SONET d es crambling

· Terminates sectio n overhead bytes B1 and J0. S ect io n t race messages are extra cte d a nd checked for p ersis-

tency and mismatch. Provides > 1 min. accumulating counter for B1.

· Terminates line overhead bytes B2, K 1, K2, S1 and M1. De tects AIS-L and RDI-L and performs per sis-

tency checking (K1, K2, S1). Provides > 1 min. accumulating counters for B2 and M1.

· Extract s and seriali ses sec tion and line l e v el orde r wire, user, automatic protect ion swi tchin g, data commu-

nication cha nnels and syn chronization c hannels E1, F1, D1-D3, E2, K1 , K2, D4-D12 , S1 on dedica ted

pins.

· Extracts and serialises entire transport overhead on dedicated pins.

· Performs STS-48 to STS-12/STS-3 byte interleaved demultiplexing.

· Provides STS-3/STS-12 cross-connect functionality

Transmit Data path:

· Performs STS-12/ STS-3 to S TS-48 byte interleaved mult iplexing

· Provides STS-3/STS-12 cross-connect functionality

· Captures section and line level order wire, user, automatic protection switching, data communication and

synchronization channels E1, F1, D1-D3, E2, K1, K2, D4-D12, S1 from dedicated input pins and

(optionally) inserts these in corresponding transport overhead bytes.

· Captures entire transport overhead from dedicated input pins and (optionally) inserts in transmit transport

overhead.

· Line overhead generation by inserting B2, K1, K2, S1 and M1 and insertion of AIS-L and RDI-L.

· Block/Individual REI-L backreporting

· Section overhead generation by inserting A1, A2, J0/Z0 and B1 bytes

· Performs SONET scrambling

Line Interface:

· Differential 155.52 MHz PECL I/O interface data front-end MUX/DEMUX chipsets

· Provides parity bit and looped clock in Tx path

· Provides Tx and Rx frame pulses and Tx synchronous reset to support STS-192/STM-64 applications

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3/8/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

SC9111

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

G52199-0, Rev. 1.2

Preliminary

CPU and Test Interface:

· Generic m icroprocessor (CPU) interface used for device configuration, status and pe rformance infor ma-

tion extraction and test mode operations

· Provides optional hardware generated “ticks” for performance monitoring counter latching

· 8 bit data bus and 8 bit address bus

· Interrupt pin

· General Purpose IOs

· Standard 5 pin JTAG Test Access Port

Drop Interface:

· 32 bit databus which can be co nfigu re d as o ne 32 bi t bus for ST S-48 c operation, four 8 bi t bu sses f or ST S-

12 interfacing, or sixteen 2 bit busses for STS-3 interfacing.

· 77.76MHz operation

· Provides parity bits for receive and transmit interfaces

· Provides separate clock inputs for each STS-3/STS-12 transmit interface to allow point-to-point connec-

tions for improved signal integrity and system robustness

· Features phase synchronizing FIFOs on transmit interfaces to allow flexible system level clocking strate-

gies

Other Features:

· Section loopba ck mode. Provides termination and regeneration of section overhead. Regenerator applia-

tions

· Line loopback mode. Provides termination and regeneration of section and line overhead. Regenerator

applications where line DCC needs to be accessed/inserted.

· Facility loopback mode. For diagnostics/bypass.

· Equipment loopback mode. For diagnostics/bypass.

· Flexible e rror insertion capabilitie s. For dia gnostics/tester applic ations

· Bit Error R at e Monit or with four in depen dent BE R thresh ol d levels. Signa l De g ra de and S ign al F ai l alarm

status detection.

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC9111

ONET/SDH 2.5Gb/s

Transport Terminating Transceiv er

Page 4 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98 3/8/99

G52199-0, Rev. 1.2

Preliminary

Pin Definitions

Pin Name I/O Freq

Type Description

RLCLK+/- Parallel Line Receive

Clock IPECL

Clock reference for the 2.5Gb/s receive flow carried in

RLIN[ 15..0]. The clock f requency is nominall y 155.52MHz

equivalent to STS-48/STM-16 operation.

RLIN[15..0]+/- Parallel Line Receive

Data IPECL

Parallel data bus for the incoming STS-48/STM-16 data

stream. RLIN[15] is the most significant bit. RLIN[15] is the

first arriving bit on the serial data stream. RLIN[15..0] is

sampled on the rising edge of RLCLK+.

RLPRTY+/- Parallel Line Receive

Parity IPECL

Pari ty inp ut (even /od d pa rity ) for the parallel receive line

data, RLIN[15..0] (optionally include RLFP). RLPRTY is

sampled on the rising e dge of RLCLK+.

RLFP+/- Parallel Line Receive

Frame Pulse IPECL

Frame pul s e for the receive line interface. RLFP can be used

instead of the internal framing circuit (based on A1A2

patterns) for syn chronizing the rece ive processor. RLFP is

sampled on the rising e dge of RLCLK+.

RLFP is intended f or use in STS- 192/STM-64 a pplications.

RXRCLK Receiv e Reference

Clock O TTL Reference clock derived from RLCLK in a 78MHz/38MHz/

19MHz/8kHz version.

LOPC Loss of Optical

Carrier I TTL

LOPC is monitored and changes in the signal status may

cause ge neration of an interrupt. This allows monit or ing of

optical failures via the device CPU interface. When LOPC is

asserted, the receive processor is optionally clocked by the

transmit clock (derived from TLCLK).

CLKRSTEN Clock Reset Enable I TTL

If CLKRSTEN is asserted, all primary clock outputs

(TXRCLK, RXRCLK, TXCLKOUT_[A..D] and

RXCLK_[A..D]) will halt during master reset. If

CLKRSTEN is deasserted, all primary clock outputs will be

running during device master reset.

TLCLK+/- P arallel Line Transmit

Clock IPECL

Clock reference for the 2.5Gb/s transmit flow carried in

TLOUT[15..0]. The clock frequency is nominally

155.5 2M Hz eq uivalent to STS-48/STM -16 oper atio n.

TLCLKOUT+/- Parallel Line Transmit

Loop ed Clock OPECL

Looped TLCLK sign al . Tim in g for this cloc k is defined with

reference to the TLOUT data bus signals. The clock

frequency is nom inally 155.52MHz equivalent to STS-48/

STM-16 operation (same as TLCL K).

TLOUT[15..0]

+/- Parallel Line T ransmit

Data OPECL

Parallel data b u s for the outg oin g STS -48 / STM-1 6 data

stream. TL OUT [15 ] is t he m o st sign ifican t b it. TLOUT[1 5] is

the first transmitted bit on the serial data stream.

TLOUT[15..0] is generated on the rising edge of the

incoming TLCLK+.

TLPRTY+/- Parallel Line Transmit

Parity OPECL

Parity output (even/odd parity) for the parallel transmit line

data, TLOUT[15..0 ] (optionally includes TLFP). TLPRTY is

generated on the rising ed ge of TLCLK+.

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3/8/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

SC9111

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

G52199-0, Rev. 1.2

Preliminary

TLFP+/- P arallel Line Transmit

Frame Pulse OPECL

Frame pulse for the transmit line interf a ce. TLFP is a one

clock cycle wide pulse coincident with either the first framing

byte (A1), the first paylod byte (first byte following last Z0)

or a 24 clock cycle wide pulse coincident with the A2 framing

bytes. TLFP is generated on the rising edge of TLCLK+.

TLFP is intended for use in STS-192/STM-64 applications.

TLSYNC+/- Synchronization I PECL

TLSYNC is used for synchronously resetting the device

transmit processor only.

TLSYNC is intended for use in STS-192/STM-64

applications.

TXRCLK Transmit Reference

Clock O TTL Reference clock derived from TLCLK in a 78MHz/38MHz/

19MHz/8kHz version.

TXDAT_

[A..D][1..4][1..

Parallel Drop

T ransmit Data I TTL

STS-3/12/48 Transmit Data.

In STS-3 mode, TXDAT_A1[1..0 ] carri es STS-3 #1,

TXDAT_A2[1..0] carries STS-3 #2, …, TXDAT_D3[1..0]

carries STS-3 #15 and TXDAT_D4 carries STS-3 #16, i.e

each STS-3 interface is 2 bits wide. TXDAT_xN[1] is the

most significant bit. TXDAT_xN[1..0] is sa mp le d on the

rising edge of TXCLK_xN.

In STS-12 mode, TXDAT_A[1..4][1..0] carries STS-12 #1,

TXDAT_B[1..4][1..0] carries STS-12 #2, …, and

TXDAT_D[1..4][1..0] carries STS-12 #4, i.e. each STS-12

interface is 8 bits wide. TXDAT_x1[1] is the most significant

bit, TXDAT_x1[0] the second most significant bit, …, and

TXDAT_x4[0] the least significant bit. TXDAT_x[1..4][1..0]

is sampled on the rising ed ge of TXCLK_x1.

In STS-48 mode, TXDAT_[A..D][1..4][1..0] carries the STS-

48 data stream, i.e. TXDAT_ [A..D][1..4][1..0] is interpreted

as one 32 bit bus. TXDAT_A1[1] is the most significant bit,

TXDAT1_A1[0] the second most significant bit, …, and

TXDAT_D4[0] the least significant bit. TXDAT_

[A..D][1..4][1..0] is sampled on the rising edge of

TXCLK_A1.

x = [A,B,C,D], N = [1,2,3,4].

Pin Name I/O Freq

Type Description

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC9111

ONET/SDH 2.5Gb/s

Transport Terminating Transceiv er

Page 6 

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SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98 3/8/99

G52199-0, Rev. 1.2

Preliminary

TXFP_

[A..D][1..4] Parallel Drop

Transmit Frame Pulse I TTL

STS-3/ 12/48 Transmit Frame Pulse.

Frame reference for the STS-3/12/48 transmit flo ws carried in

TXDAT_xN. The frame pulses shall ha v e lo w-high transitio ns

coincid ent with the f irst pay load byte (i.e. f irst b yte following

last Z0) of the STS-3/12/48 frames (optionally the first

ove rhead byte, A1).

In STS-3 mode, TXFP_xN is a frame reference for

TXDAT_xN. TXFP_xN is sampled on the rising edge of

TXCLK_xN.

In STS-12 mode, TXFP_x1 is a frame reference for

TXDAT_x. TXFP_x2, TXFP_x3 and TXFP_x4 are unused.

TXFP_x1 is sampled on the r ising edge of TXCLK_x1.

In STS-48 mode, only TXFP_A1 is used. TXFP_A1 is

sampled on the rising edge of TXCLK_A1.

x = [A,B,C,D], N = [1,2,3,4].

TXPRTY_

[A..D][1..4] Parallel Drop

Transmit Parity I TTL

STS-3/12/48 Transmit Parity.

Parity (even/odd) over the parallel transmit STS-3/12/48 data

streams (TXD AT_xN).

In STS-3 mode, TXPRTY_xN is the parity over TXDAT_xN

(2 bit parity). TXPRTY_xN is sampled on the rising e dge of

TXCLK_xN.

In STS-12 mode, TXPRTY_x1 is the parity over TXDAT_xN

(8 bit parity). TXPRTY_x1 is sampled on the rising edge of

TXCLK_x1. Opt ionally, 2 bit paritie s can be used in this

mode (as describe d above for STS-3 mode).

In STS-48 mode, TXPRTY_A1 is the parity ov er TXD AT_xN

(32 bit pa rity ). TXP RTY_A1 is samp le d o n the risin g ed ge o f

TXCL K_A 1 .O pti on a lly, 2 bit or 8 bit parities ca n be use d in

this mode (as described above for ST S-3 and ST S-12 modes,

respectively).

TXOHEN_x is optionally included in parity.

x = [A,B,C,D], N = [1,2,3,4].

TXCLK_

[A..D][1..4] Parallel Drop

Transmit Clock I TTL

STS-3/12/48 Transmit Clock.

Clock reference for the STS-3/12/48 transmit flow carried in

TXDAT_xN. The clock frequency is nominally 77.76MHz

equivalent to STS-3/1 2/48 operation.

In STS-3 mode, all TXCLK_xN clocks ar e us e d.

In STS-12 mode, only TXCLK_x1 are used.

In STS-48 mode, only TXCLK_A1 is used.

x = [A,B,C,D], N = [1,2,3,4].

TXCLKOUT_

[A-D]

Parallel Drop

Transmit Clock

Source O TTL

STS-3/12/48 Transmit Clock Source.

Clock source for the transmit direction of the drop side STS-

3/12/48 interfaces. One clock is provided for each of the four

STS-12 (or quad STS-3) i nterfaces. T he clock fre quency is

nominally 77.76MHz equivalent to STS-3/12/48 operation.

Pin Name I/O Freq

Type Description

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3/8/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

SC9111

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

G52199-0, Rev. 1.2

Preliminary

TXRST Parallel Drop

Transmit Reset O TTL

STS-3/12/48 Transmit Interface Reset.

Indicates synchronisation errors on the STS-3/12/48 transmit

data str eams. Th e signal is used for resynchronizing the STS-

3/12 t ransmit flows. Synchroni zation st atus is base d on the

transmit frame pulses (TXFP_xN), which must be aligned

within +/- 2 clock cycles. TXRST changes on the rising edge

of TXCLKOUT_x.

x = [A,B,C,D], N = [1,2,3,4].

RXDAT_

[A..D][1..4][1..

Paralle l Drop Recei v e

Data O TTL

STS-3 /12 /4 8 R ece ive Data.

In STS-3 mode, RXDAT_A1[1..0] carries STS-3 #1,

RXDAT_A2[1..0] carries STS-3 #2, …, RXDAT_D3[1..0]

carries STS-3 #15 and RXDAT_D4[1..0] carries STS-3 #16,

i.e. each STS-3 interface is 2 bits wi de. RXDAT_xN[1] is the

most significant bit.

In STS-12 mode, RXDAT_A[1..4][1..0] carries STS-12 #1,

RXDAT_B[1..4][1..0] carries STS-12 #2, …, and

RXDAT_D[1..4][1..0 ] ca rries STS-12 #4, i.e. each STS-12

interface is 8 bits wide. RXDAT_x1[1] is the mos t significa nt

bit, RXDAT_x1[0 ] the second mo st significant bit, …, and

RXDAT_x4[0] the least significant bit.

In STS-48 mode, RXDAT_[A..D][1..4][1..0] carries the STS-

48 data stream, i.e. RXDAT_[A..D][1..4][1..0] is interpreted

as one 32 bit bus. RXDAT_A1[1] is the most significant bit,

…, and RXDAT_D4[0] the least significant bit.

RXDAT_xN changes on the fallin g e dge of RXCLKA-D.

x = [A,B,C,D], N = [1,2,3,4]

RXCLK_

[A..D] Para llel Drop Rec eiv e

Clock O TTL

STS-3 /12/48 R ece ive Cloc k .

Clock reference for t he S TS- 3/12/48 receive flow carried in

RXDAT_xN. The clock frequency is nominally 77.76MHz

equivalent to STS-3/1 2/48 operation.

x = [A,B,C,D], N = [1,2,3,4].

RXFP_

[A..D] Para llel Drop Rec eiv e

Frame Pulse O TTL

STS-3/12/48 Receiv e Frame Pulse.

Frame reference for the STS-3/12/48 receive flows carried in

RXDAT_xN. Th e frame pulse is a one clock cycle pulse

coincid ent with the f irst pay load byte (i.e . first b yte follo wing

last Z0) of the STS-3/12/48 frames (optionally the first

overhead byte, A1). RXFP_[A..D] changes on the falling

edge of RXCLK_[A..D].

In STS-3 mode, the frame pulse is only asserted during the

f irst cy cl e of the first paylo ad b y te (optio n al ly the first

ove rhead byte).

x = [A,B,C,D], N = [1,2,3,4].

Pin Name I/O Freq

Type Description

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC9111

ONET/SDH 2.5Gb/s

Transport Terminating Transceiv er

Page 8 

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SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98 3/8/99

G52199-0, Rev. 1.2

Preliminary

RXPRTY_

[A..D][1..4] Paralle l Drop Recei v e

Parity O TTL

STS-3/12 /4 8 Rece ive Parity.

Parity (even/odd) over the parallel receive STS-3/12/48 data

stream (RXD AT_xN).

In STS-3 mode, RXPRTY_xN is the parity over RXDAT_xN

(2 bit parity).

In STS-12 mode, RXPRTY_x1 is the parity over RXDATxN

(8 bit parity). Optionally, 2 bit parities can be used in this

mode (as describe d above for STS-3 mode).

In STS-48 mode , RXPR TY_A 1 is the parity o ver RXDAT_xN

(32 bit pari ty). Option ally, 2 bit or 8 bit pariti es can be use d in

this mode (as described above for ST S-3 and ST S-12 modes,

respectively).

RXPRTY_xN changes on the falling edge of RXCLK_x.

x = [A,B,C,D], N = [1,2,3,4].

LOS Loss Of Signal O TTL Status signal indicating if Loss Of Signal (LOS) has been

detected. The LOS status is also available in an internal status

LOF Loss Of Frame O TTL Status signal indicating if Loss Of Frame (LOF) has been

detected. The LOF status is also available in an internal status

RSPFP Receive Special

Purpos e Frame Pulse O TTL

Frame reference for special purpose serial output ports

RSPDAT_x. The frame pulse is a one clock cycle wide pulse

coincident with the first bit on the serial data streams. Active

high. RSPFP changes on the falling edge of RSPCLK_x.

X = [1,2].

RSPCLK_1 Receive Special

Purpose Clock 1 O TTL Clock reference for receiv e special purpose serial output port

1. The clock is a 2.16MHz, 50% duty-cycle signal (optionally

gapp e d to ma tc h the ba ndwid t h of RS PDAT_1.

RSPDAT_1 Receive Special

Purpose Data 1 O TTL Data output for special purpose serial port 1. RSPDAT_1

changes on the falling edge of RSPCLK_1.

RSPVALID_1 Receive Special

Purpose Valid 1 O TTL

Valid qualif ier for special purpose serial port 1. RSPVALID_1

is asserted (programmable level) when there is valid data on

RSPDAT_1. RSPVALID_1 changes on the falling edge of

RSPCLK_1.

RSPCLK_2 Receive Special

Purpose Clock 2 O TTL Clock reference for receiv e special purpose serial output port

2. The clock is a 2.16MHz, 50% duty-cycle signal (optionally

gapp e d to ma tc h the ba ndwid t h of RS PDAT_2.

RSPDAT_2 Receive Special

Purpose Data 2 O TTL Data output for special purpose serial port 2. RSPDAT_2

changes on the falling edge of RSPCLK_2.

RSPVALID_2 Receive Special

Purpose Valid 2 O TTL

Valid qualif ier for special purpose serial port 2. RSPVALID_2

is asserted (programmable level) when there is valid data on

RSPDAT_2. RSPVALID_2 changes on the falling edge of

RSPCLK_2.

RTOHCLK Receive Transport

Overhead Clock O TTL Clock reference for the receive transport overhead port. The

clock i s a 38.88MHz, 50% duty-cycle signal.

Pin Name I/O Freq

Type Description

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VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

SC9111

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

G52199-0, Rev. 1.2

Preliminary

RTOHVALID Receive Transport

Overhead Valid O TTL

Valid qu alifier for the receive transport overhead port.

RTOHVALID is asserted (programmable le vel) when there is

valid data on RTOH[3..0]. RTOHVALID changes on the

fallin g edge of RTOHCL K.

RTOHFP Receive Tr ansport

Overhead Frame P ul s e O TTL

Frame reference for the receive transport overhead port.

RTOHFP i s a one clock cycle wide pulse coincident wi th the

first bit(s) of the first A1 being output on RTOH[3..0].

RTOHFP changes on the fallin g edg e of RTOHCLK.

RTOH[3..0] Receive Transport

Overhead Data O TTL

Data output for the receive transport over hea d (section and

line) bytes extracted from the incoming STS-48 signal.

RTOH[3..0] changes on the fall ing edge of RTOHCLK.

Mode 1: RT OH[3] carries the transport overhead from STS-

12 #1 (first interleaved STS-12), RTOH[2] carries the

transport overhead from S TS-12 #2, etc.

Mode 2: RTOH[3..0] carries th e entire transport overhead in

the order the overhead bytes are received. The most

significant nibble (first received) is output first. RTOH[3] is

the most signif i can t bit.

TSPCLK_1 Transmit Special

Purpose Clock 1 O TTL Clock reference for the transmit special purpose serial input

port 1. The clock is a 2.16MHz, 50% duty-cycle signal

(optionally ga pped to match the bandwidth of TSPDAT_1 ).

TSPFP_1 Tr ansmit Sp ecial

Purpos e Frame Pulse

1O TTL

Frame reference for the special purpose serial output port

TSPDAT_1.

Mode 1 (TSPCLK_1 continu ous): The frame pulse is a one

clock cycle wide pulse indicating the start of a new data

stream on TSPDAT _1. When TSPFP _1 is asserted, the first

bit of TSPDAT_1 is sampled on the second rising edge

thereafter. TSPFP_1 changes on the falling edge of

TSPCLK_1.

Mode 2 (TSPCLK_1 gapped): The frame pulse is a one clock

cycle wide pu lse (variable width due to the gapped clock)

indicating t he start of a new data str e am on TS PDAT_1.

When TSPFP_1 is asserted, the first bit of TSPDAT_1 is

sampled o n t he second rising edge thereafter. TSPFP_1

changes on the falling edge of TSPCLK_1.

TSPREN_1 Transmit Special

Purpose Read Enable

1O TTL

Read enable signal for the TSPDAT_1 data stream. Th e

response latency from TSPREN_1 is asserted until

TSPD AT_1 is sampled is programmable. TSPREN_1 chan ges

on the fa llin g edg e of TSPCLK_1.

TSPDAT_1 Transmit Special

Purpose Data 1 I TTL Serial data input for transmit special purpose port 1.

TSPDAT_1 is sampled on the rising edge of TSPCLK_1.

TSPCLK_2 Transmit Special

Purpose Clock 2 O TTL Clock reference for the transmit special purpose serial input

port 2. The clock is a 2.16MHz, 50% duty-cycle signal

(optionally ga pped to match the bandwidth of TSPDAT_2 ).

Pin Name I/O Freq

Type Description

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC9111

ONET/SDH 2.5Gb/s

Transport Terminating Transceiv er

Page 10 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98 3/8/99

G52199-0, Rev. 1.2

Preliminary

TSPFP_2 Tr ansmit Sp ecial

Purpos e Frame Pulse

2O TTL

Frame reference for the special purpose serial output port

TSPDAT_2.

Mode 1 (TSPCLK_2 continu ous): The frame pulse is a one

clock cycle wide pulse indicating the start of a new data

stream on TSPDAT _2. When TSPFP _2 is asserted, the first

bit of TSPDAT_2 is sampled on the second rising edge

thereafter. TSPFP_2 changes on the falling edge of

TSPCLK_2.

Mode 2 (TSPCLK_2 gapped): The frame pulse is a one clock

cycle wide pu lse (variable width due to the gapped clock)

indicating t he start of a new data str e am on TS PDAT_2.

When TSPFP_2 is asserted, the first bit of TSPDAT_2 is

sampled o n t he second rising edge thereafter. TSPFP_2

changes on the falling edge of TSPCLK_2.

TSPREN_2 Transmit Special

Purpose Read Enable

2O TTL

Read enable signal for the TSPDAT_2 data stream. Th e

response latency from TSPREN_2 is asserted until

TSPD AT_2 is sampled is programmable. TSPREN_2 chan ges

on the fa llin g edg e of TSPCLK_2.

TSPDAT_2 Transmit Special

Purpose Data 2 I TTL Serial data input for transmit special purpose port 2.

TSPDAT_2 is sampled on the rising edge of TSPCLK_2.

TTOHCLK Transmit Tra nsport

Overhead Clock O TTL Clock reference for the transmit transport overhead port. The

clock i s a 38.88MHz, 50% duty-cycle signal.

TTOHFP Transmit Transport

Overhead Frame P ul s e O TTL

Frame reference for the transmit transport overhead port.

TTOHFP is a one clock cycle wide pulse indicating the start

of a new data stream on TTOH[3..0]. The response latency

from TTOHFP is asserted until the first bit on TTOH[3..0] is

sampled is programmable (see TTOHREN). TTOHFP

changes on the fallin g edge of TT OHCLK.

TTOHREN Transmit Tra nsport

Overhead Read

Enable O TTL

Read enable signal for the TTOH[3..0] data stream. The

response latency from TTOHREN is asserted until

TTOH[3..0] is sampled is programmable. TTOHREN

changes on the fallin g edge of TT OHCLK.

Pin Name I/O Freq

Type Description



VITESSE

SEMICONDUCTOR CORPORATION

Page 11

3/8/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

SC9111

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

G52199-0, Rev. 1.2

Preliminary

TTOHEN Transmit Tra nsport

Overhead Enable I TTL

Enable signal for th e TT OH[3 ..0 ] da ta st ream. If TTOHE N is

asserted, the corresponding byte will be inserted in the

corresponding transport overhead byte of the outgo ing STS-

48 data stream.

Mode 1: Transport overhead for each of the fou r STS-12

channels will be input in bit-serial format on the four data

inputs (see TTOH[3..0] description). If TTOHEN is asserted

during the first bit of an overhead byte, the corresponding

overhead byte on TTOH[3] will be enabled, if TTOHEN is

asserted during the third bit of an overhead byte, the

corresponding overhead byte on TTOH[2] will be enabled

(simil a r for TTOHEN asserti on during fifth and seventh bits).

Mode 2: Transport overhead for the entire STS-48 is input as

4-bit nibbles on the TTOH[3..0] port (see TTOH[3..0]

description). If TTOHEN is asser ted duri ng th e first nibble o f

an overhead byte, the corresponding overhead byte is enabled.

Note: The transmit section and line proc essing bloc ks can

selectively overwrite/modify overhead bytes inserted through

the TTOH interface.

TTOH[3..0] Transmit Tra nsport

Ovehead Data I TTL

Data input for the transport overhead (section and line) bytes

to be inserted in the outgoing STS-48 signal. TTOH[3..0] is

sampled on the rising edge of TTOHCLK.

Mode 1: TTOH[3] carries the transport overhead for STS-12

#1 (first int erl eave d STS-12 ), TT OH[2 ] carrie s the transport

overhead for STS-12 #2, etc.

Mode 2: TTOH[3..0] carries the entire ST S-48 transport

overhead i n t he order the overhead bytes are to be inserted.

The most signi ficant nibble (first received) is input first.

TTOH[3] is the most significant bit.

D[7..0] CP U Data B TTL Bidirectional data bus is used to transfer data for

microcontroller read/write access to internal UNI registers.

A[7..0] CPU Address I TTL Address bus selects spec ific internal registers during register

read/write access.

ALE CPU Address Latch

Enable I TTL

Controls internal latching of the address bus signals. When

lo w the add ress b us A[7..0 ] is latched in ternal. Wh en high the

internal address bus latches are transparent. This signal will

allow for interfacing to a multiplexed address/data bus. The

ALE signal has an internal pull-up resistor.

CSB CPU Chip Select

(active low) I TTL

Must always be asserted during register read/write access

cycles. The CSB signal is used in conjunction with either the

RDB or the WRB signal. Th e CSB sig nal has an in ternal pull-

up resistor .

WRB CPU Wr ite Enable

(active low) I TTL

Used for register write operations. The D[7..0] content is

written into the by A[7..0] selected register when WRB and

CSB are both asserted (low). The WRB sign al has an internal

pull-u p resistor.

Pin Name I/O Freq

Type Description

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC9111

ONET/SDH 2.5Gb/s

Transport Terminating Transceiv er

Page 12 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98 3/8/99

G52199-0, Rev. 1.2

Preliminary

RDB CPU Read Enable

(active low) I TTL

Used for register read operations. The D[7..0] will drive the

and CSB are both asserted (low). The RDB signal has an

internal pu ll-u p resistor.

INTB CPU Interrupt

(active low) O TTL

Asserted when an internal interrupt source is pending and the

interrupt is unmasked (enabled). The INTB signal is de-

asserted when the interrupt pending bits have been cleared.

The INTB is an open dr ain signal.

RSTB Chip Reset

(active low) I TTL

Async hronous re set of the de vice. The de vice is held in a rese t

state while the RSTB signal is low. The signal is schmitt-

trigged with an intern al pull-up resistor. All outpu ts are

tristated when RST B is a sserted.

PMTICK Performance

Monitoring Tick B TTL Output. Asserted when the internal PMTICK timer generates

a tick for latc hing pe rformance coun ters in the de vice. Inpu t:

A low-to-high tra n si tion will (o pti onal ly) trigger latching of

performance monitoring counters in the device.

GP IO[7..0] General Purpose

Input/Output BI TTL Individually configurable as inputs or outputs. Intended for

controlling monitoring external devices.

TDO JTAG Te st Data

Output O TTL

This signal carries test data out of the device via the IEEE

P1149.1 test access port. TDO is updated on the falling edge

of TCK. The TDO signal is a tristate output which is inactive

except when data scan shifting is in progress.

TDI JTAG Test Data Input I TTL The signal carries test data into the device via the IEEE

P1149.1 test access port. TDI is sampled on the rising edge of

TCK. TDI has an internal pull-up resistor.

TCK JTAG Test Clock I TTL Th is signal pro vides timin g for test opera tions that are carried

out using the IEEE P1149.1 test access port.

TMS JTAG Test Mode

Select I TTL This signal cont ro ls t he t es t opera tion s th at are car r ie d out

using the IEEE P1149.1 test access port. TMS is sampled on

the rising edge of TCK. TMS has an internal pull-up resistor.

TRSTB JTAG Test Reset

(active low) I TTL This signal provides an asynchronous test access port reset

via the IEEE P1149.1 test access port. TRSTB is a schmitt

triggered input with an internal pull-up resistor.

OE Chip Output Enable

(activ e high) I TTL When deasserted (set low), all TTL device outputs are

tristated. The OE signal has an internal pull-up.

Pin Name I/O Freq

Type Description



VITESSE

SEMICONDUCTOR CORPORATION

Page 13

3/8/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

SC9111

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

G52199-0, Rev. 1.2

Preliminary

Absolute Maximum Ratings

(1)

Power Supply Voltage (VDD) Potential to GND.................................................................................-0.5V to +4V

Power Supply Voltage (VDD5) Potential to GND................................................................................-0.5V to +6V

DC Input Voltage (PECL inputs)...........................................................................................-0.5V to VDD + 0.5V

DC Input Voltage (TTL inputs)............................................................................................ -0.5V to VDD5 + 0.5V

DC Output Voltage (TTL Outputs)........................................................................................-0.5V to VDD + 0.5V

DC Output Voltage (TTL 5V Tolerant Outputs) .................................................................. -0.5V to VDD5 + 0.5V

Output Current (TTL Outputs)................................................................................................................. +/-50mA

Output Current (PECL Outputs)................................................................................................................+/-50mA

Case Temperature Under Bias.........................................................................................................-55o to +125oC

Storage Temperature.....................................................................................................................-65oC to +150oC

Maximum Input ESD (Human Body Model).............................................................................................. 2000 V

Note: Caution: Stresses listed unde r “Absolute Maximum Rat ings” may be applied to devices one at a time without causing

permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended

periods may affect device reliability.

Recommended Operating Conditions

Power Supply Voltage (VDD)................................................................................................................+3.3V %

Power Supply Voltage (VDD5).............................................................................................................. +5.0V %

Operating Temperature Range* (T).................................................................................................... -40o to 85oC

* Lower limit of specification is ambient temperature and upper limit is case temperature.

10±

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC9111

ONET/SDH 2.5Gb/s

Transport Terminating Transceiv er

Page 14 

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98 3/8/99

G52199-0, Rev. 1.2

Preliminary

DC Characteristics

Table 1: PECL and TTL Inputs and Outputs

Power Dissipation

Table 2: Power Supply Currents

Notice

This document contains information on products that are in the preproduction phase of development. The

information contained in this document is based on test results and initial product characterization.

Characteristic data and other specifications are subject to change without notice. Therefore, the reader is

cautioned to confirm that this datasheet is current prior to placing orders.

Warning

Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or sys-

tems. Use of a Vit esse product in such applications without the written consent is prohibited .

Parameters Description Min Max Units Conditions

VOH Output HIGH voltage (TTL) 2.4 —V

IOH = -2,-4,-8,-16 mA

VOL Output LOW voltage (TTL) —0.5V

IOL = 2,4,8,16 mA

VIH Input HIGH voltage (TTL) 2.0 5.5 V —

VIL Input LOW voltage (TTL) 00.8V

—

IIT Input current (TTL) —10µA0V< VIN < 5V

VOCM O/P Common Mode Range (PECL) 1600 2300 mV At Min ∆VOUT

∆VOUT75 Differential Output Voltage (PECL) 1000 1500 mV 75Ω to VDD – 2.0 V

∆VOUT50 Differential Output Voltage (PECL) 900 1350 mV 50Ω to VDD – 2.0 V

VICM I/P Common Mode Range (PECL) 1500 1800 mV At Min ∆VIN

∆VIN Differential Input Voltage (PECL) 300 2600 mV —

IIP Input current (PECL) —1000µA0V< VIN < 3.3V

Parameter Description (Typ) (Max) Units

IDD Power supply current from VDD 550 833 mA

PDPo wer dissipation 2.5 3.0 W