FEDL610Q111-01 Issue Date: Sep. 26, 2013 ML610Q111/ML610Q112 8-bit Microcontroller GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers, PWM, UART, I2C bus interface (master/slave), synchronous serial port, voltage level supervisor analog comparators and 10-bit successive approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel processing. The Flash ROM that is installed as program memory, and the on-chip debug function that is installed, enable program debugging and programming on customer's board. FEATURES z CPU - 8-bit RISC CPU (CPU name: nX-U8/100) - Instruction system: 16-bit instructions - Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - On-Chip debug function - Minimum instruction execution time: 30.5us (@32.768kHz system clock) 0.122us (@8.192MHz system clock) z Internal memory - ML610Q111: Flash memory : Internal 24Kbyte Flash memory (12K x 16bit) for program including unusable 32byte test data area. Internal 4Kbyte Flash memory (2K x 16bit) for data. SRAM : Internal 2Kbyte data RAM (2K x 8bit) - ML610Q112: Flash memory : Internal 32Kbyte Flash memory (16K x 16bit) for program including unusable 32byte test data area. Internal 4Kbyte Flash memory (2K x 16bit) for data. SRAM : Internal 4Kbyte data RAM (4K x 8bit) - Flash Memory operating condition and specification Refer to the chapter Electrical characteristics "FLASH MEMORY SPECIFIACTION". z Interrupt controller - 1 non-maskable interrupt source (Internal source: 1(WDT)) - 30 maskable interrupt sources (Internal sources: 23, External source: 7) z Time base counter (TBC) - Low-speed time base counter: 1 channel - High-speed time base counter: 1 channel (This time base counter is divided by 1-16, then it can be used as a clock of the Timer and PWM.) 1/26 FEDL610Q111-01 ML610Q111/ML610Q112 z Watchdog timer (WDT) - Non-maskable interrupt and reset (Non-maskable interrupt is generated by the first overflow, and reset is generated by the second overflow) - Free running - Overflow period: 7 types selectable by software (23.4ms, 31.25ms, 62.5ms, 125ms, 500ms, 2s, and 8s) z Timer - 8-bit x 6 channels (16-bit configuration available, 16-bit x 3ch) - Supports auto reload timer mode/One shot timer mode - Timer count start/stop by software or external input trigger (Timer function with external trigger input supports for only 2ch. Selectable external pins/analog comparator output as an exeternal trigger.) - The effective minimum pulse width of the external trigger input: Timer clock 3 (about 183 ns @ 16.384 MHz) - Allows measurement of pulse width etc. using an external trigger input. - 8-selectable clock frequency as counter clock per channel z PWM - Resolution 16-bit - Single output x 3ch, Multiple three outputs x 1ch - Allows an output of the PWM signal in a cycle of about 122ns (@PLLCLK = 16.384MHz) to 2s (@LSCLK = 32.768kHz) - Supports one shot PWM mode - PWM start/stop by software and external trigger input (Selectable external pins, analog comparator output or timer interrupt as external trigger) - 3-selectable clock frequency as PWM clock per channel z UART - TXD/RXD x 2ch - Half-Duplex Communication - Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - Positive logic/negative logic selectable - Built-in baud rate generator z I2C bus interface - Master function: standard mode (100kbit/s@8MHz), Fast mode (400kbit/s@8MHz) - Slave function : standard mode (100kbit/s) z Synchronous serial port (SSIO) - 1ch - Master/slave selectable - LSB first/MSB first selectable - 8-bit length/16-bit length selectable z Successive approximation type A/D converter (SA-ADC) - 10-bit A/D converter - Analog Input 6ch (ML610Q111) 8ch (ML610Q112) 2/26 FEDL610Q111-01 ML610Q111/ML610Q112 z Analog comparator - 2ch ch0: Allows comparison of the voltage level of the two external pins or comparison of one external pin and internal reference voltage level. ch1: Allows comparison of one external pin and internal reference voltage level - Input common mode voltage range : VDD = 0.1V to VDD - 1.5V - Internal reference voltage : 0.1-0.8V (Selectable in 50mV increments) - Hysteresis (Comparator0 only): 20mV(Typ.) - Allows selection of with/without interrupt sampling and interrupt edge. z General-purpose ports (GPIO) - Input/output port 15ch (ML610Q111) 25ch (ML610Q112) z Reset - Reset by the RESET_N pin - Reset by power-on detection - Reset by the watchdog timer (WDT) 2nd overflow - Reset by the voltage level supervisor (VLS) function: Selectable by software z Voltage level supervisor (VLS) - 2ch ch0: It can be used for voltage level detection reset ch1: It can be used for voltage level detection interrupt - Judgment accuracy: 3.0% (Typ.) z Clock - Low-speed clock: Built-in RC oscillation (32.768kHz) - High-speed clock: Built-in PLL oscillation (16.384MHz) High-speed external clock (max. 8.192MHz) Maximum CPU clock is 8.192MHz. - Selection of high-speed clock mode by software: Built-in PLL oscillation External clock z Power management - HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states) - STOP mode: Stop of oscillation (Operations of CPU and peripheral circuits are stopped.) - Clock gear: The frequency of system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock). - Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. 3/26 FEDL610Q111-01 ML610Q111/ML610Q112 z Shipment - ML610Q111: 20-pin TSSOP: ML610Q111-xxxTD (blank product: ML610Q111-NNNTD) - ML610Q112: 32-pin LQFP: ML610Q112-xxxTC (blank product: ML610Q112-NNNTC) z Guaranteed operating range - Operating temperature (ambience): -40C to 105C (Flash write/erase: -20C to +85C) - Operating voltage: VDD=2.7V to 5.5V 4/26 FEDL610Q111-01 ML610Q111/ML610Q112 BLOCK DIAGRAM The block diagram is shown in figure 1. "*" means secondary function, tertiary function or quaternary function of each port. "( )*2" means the function of ML610Q112. CPU (nX-U8/100) EPSW1 - 3 GREG 0 - 15 PSW Timing Controller RESET_N TEST ALU RESET_N TEST Power EA PC Instruction Register RAM 2Kbyte (4Kbyte)*2 INT 1 Interrupt Controller VLS CMP0P CMP0M CMP0OUT* CMP1P CMP1OUT* DSR/CSR Data Memory (Flash) 4Kbyte RESET & TEST Clock Generator AIN0 to AIN5(AIN7)*2 LR Program Memory (Flash) 24Kbyte (32Kbyte)*2 BUS Controller Data-bus VDD VSS ECSR1 - 3 SP Instruction Decoder On-Chip ICE ELR1 - 3 INT 1 10bit-ADC INT 2 Analog Comparator x2 INT 1 INT 4 INT 6 WDT INT 2 INT 2 UART RXD0 TXD0* RXD1 TXD1* I2C Master/Slave SDA* SCL* SSIO SCK* SIN* SOUT* INT 1 INT 4 PWM TBC 8bit Timer x6 INT 7 GPIO PWMC* PWMD*, PWME* PWMF0* PWMF1* PWMF2* PA0 to PA2 PB0 to PB7 PC0 to PC3 (PC4 to PC7)*2 (PD0 to PD5)*2 Figure 1. ML610Q111/ML610Q112 Block Diagram 5/26 FEDL610Q111-01 ML610Q111/ML610Q112 PIN CONFIGURATION (TOP VIEW) z ML610Q111-xxxTD The pin layout is shown in figure 2. TM9OUT / PWMF0 / PC0 RESET_N TEST CMP1OUT / OUTCLK / PWMC / RXD0 / AIN2 / EXI4 / PB0 TXD1 / TXD0 / PWMD / AIN3 / EXI5 / PB1 PWME / RXD1 / EXI6 / PB2 TXD1 / SIN / EXI7 / PB3 CMP0OUT / CLKIN / PWME / EXI2 / PA2 TESTF TMFOUT / PC3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PC1 / PWMF1 PA0 / EXI0 / AIN0 / PWMC / OUTCLK / TM9OUT PB7 / AIN5 / RXD1 / LSCLK / PWMF0 / PWMC VDD VSS PB6 / AIN4 / CLKIN / SDA / PWMF1 PB5 / CMP0M / RXD0 / SCK / SCL / PWMF2 PB4 / CMP0P / SOUT / TXD0 / TXD1 PA1 / EXI1 / AIN1 / CMP1P / PWMD / LSCLK / TMFOUT PC2 / PWMF2 * PIN No.4-8, 12-15, 18, 19 can be used as external trigger of the Timer E-F and PWMC-F. Figure 2. ML610Q111 TSSOP20 Pin Configuration 6/26 FEDL610Q111-01 ML610Q111/ML610Q112 z ML610Q112-xxxTC The pin layout is shown in figure 3. TESTF PD2 TMFOUT / PC3 PD3 PD5 PD4 PWMF2 / PC2 CMP1P / AIN1 / EXI1 / PA1 / TMFOUT / LSCLK / PWMD 16 15 14 13 12 11 10 9 TXD1 / TXD0 / SOUT / CMP0P / PB4 17 8 PA2 / EXI2 / PWME / CLKIN / CMP0OUT PWMF2 / SCL / SCK / RXD0 / CMP0M / PB5 18 7 PWMF1 / SDA / CLKIN / AIN4 / PB6 19 6 PB3 / EXI7 / SIN / TXD1 PB2 / EXI6 / RXD1 / PWME N.C. 20 5 PB1 / EXI5 / AIN3 / PWMD / TXD0 / TXD1 VSS VDD 21 4 22 3 N.C. PB0 / EXI4 / AIN2 / RXD0 / PWMC / OUTCLK / CMP1OUT AIN7 / PC7 23 2 PD1 24 1 TEST PWMC / PWMF0 / LSCLK / RXD1 / AIN5 / PB7 25 26 27 28 29 30 31 32 RESET_N PD0 PC0 / PWMF0 / TM9OUT PC4 / SCL PC5 / SDA PC1 / PWMF1 PC6 / AIN6 PA0 / EXI0 / AIN0 / PWMC / OUTCLK / TM9OUT * PIN No.3, 5-8, 16-19, 24, 25 can be used as external trigger of the Timer E- F and PWMC-F. Figure 3. ML610Q112 LQFP32 Pin Configuration 7/26 FEDL610Q111-01 ML610Q111/ML610Q112 PIN LIST Table 1. ML610Q111/ML610Q112 Pin List PIN No. Primary function Secondary function Tertiary function Quaternary function 32 LQFP 20 TSSOP 21 16 VSS -- power supply -- -- -- -- -- -- -- -- -- 22 17 VDD -- power supply -- -- -- -- -- -- -- -- -- Name I/O Function Name I/O Function Name I/O Function Name I/O function 9 9 TESTF -- TEST -- -- -- -- -- -- -- -- -- 32 2 RESE T_N I SYSTEM -- -- -- -- -- -- -- -- -- 1 3 I/O -- -- -- -- -- -- -- -- 19 PWMC O PWM OUTCLK O SYSTEM TM9OUT O TIMER 16 12 PWMD O PWM LSCLK O SYSTEM TMFOUT O TIMER 8 8 PWME O PWM CLKIN I SYSTEM CMP0OUT O COMP 3 4 PWMC O PWM OUTCLK O SYSTEM CMP1OUT O COMP 5 5 PWMD O PWM TXD0 O UART TXD1 O UART 6 6 PWME O PWM -- -- -- -- -- -- 7 7 SIN I SSIO TXD1 O UART -- -- -- 17 13 SOUT O SSIO TXD0 O UART TXD1 O UART 18 14 SCK I/O SSIO SCL I/O I2C PWMF2 O PWM 19 15 CLKIN I SYSTEM SDA I/O I2C PWMF1 O PWM 24 18 TEST GPIO/ EXINT/ SA-ADC/ TIMER/ PWM GPIO/ EXINT/ SA-ADC/ COMP/ TIMER/ PWM GPIO/ EXINT/ TIMER/ PWM GPIO/ EXINT/ SA-ADC/ UART/ TIMER/ PWM GPIO/ EXINT/ SA-ADC/ TIMER/ PWM GPIO/ EXINT/ UART/ TIMER/ PWM GPIO/ EXINT/ TIMER/ PWM GPIO/ COMP GPIO/ UART/ COMP GPIO/ SA-ADC GPIO/ SA-ADC/ UART -- 25 TEST PA0/ EXI0/ AIN0/ TnTG*/ PmTG** PA1/ EXI1/ AIN1/ CMP1P/ TnTG*/ PmTG** PA2/ EXI2/ TnTG*/ PmTG** PB0/ EXI4/ AIN2/ RXD0/ TnTG*/ PmTG** PB1/ EXI5/ AIN3/ TnTG*/ PmTG** PB2/ EXI6/ RXD1/ TnTG*/ PmTG** PB3/ EXI7/ TnTG*/ PmTG** PB4/ CMP0P PB5/ RXD0/ CMP0M PB6/ AIN4 PB7/ AIN5/ RXD1 LSCLK O SYSTEM PWMF0 O PWM PWMC O PWM 30 1 PC0 I/O GPIO -- -- -- PWMF0 O PWM TM9OUT O TIMER 27 20 PC1 I/O GPIO -- -- -- PWMF1 O PWM -- -- -- 14 11 PC2 I/O GPIO -- -- -- PWMF2 O PWM -- -- -- 11 10 PC3 I/O GPIO -- -- -- -- -- -- TMFOUT O TIMER I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8/26 FEDL610Q111-01 ML610Q111/ML610Q112 PIN No. 32 LQFP 20 TSSOP Primary function Name I/O Function Secondary function Name Tertiary function Quaternary function I/O Function Name I/O Function Name I/O function 2 29 -- PC4 I/O GPIO SCL I/O IC -- -- -- -- -- -- 28 -- PC5 I/O GPIO SDA I/O I2C -- -- -- -- -- -- 26 -- PC6/ AIN6 I/O GPIO/ SA-ADC -- -- -- -- -- -- -- -- -- 23 -- PC7/ AIN7 I/O GPIO/ SA-ADC -- -- -- -- -- -- -- -- -- 31 -- PD0 I/O GPIO/ -- -- -- -- -- -- -- -- -- 2 -- PD1 I/O GPIO/ -- -- -- -- -- -- -- -- -- 10 -- PD2 I/O GPIO -- -- -- -- -- -- -- -- -- 12 -- PD3 I/O GPIO -- -- -- -- -- -- -- -- -- 13 -- PD4 I/O GPIO -- -- -- -- -- -- -- -- -- 15 -- PD5 I/O GPIO * : TnTG = TETG, TFTG. ** : PmTG = PCTG, PDTG, PETG, PFTG. -- -- -- -- -- -- -- -- -- 9/26 FEDL610Q111-01 ML610Q111/ML610Q112 PIN DESCRIPTION Table 2. ML610Q111/ML610Q112 Pin Description Pin name I/O Description Primary Secondary Tertiary, Quaternary Logic System RESET_N I CLKIN I LSCLK O OUTCLK O Reset input pin. When this pin is set to "L" level, system reset mode is set and the internal section is initialized. When this pin is set to "H" level subsequently, program Primary execution starts. A pull-up resistor is internally connected. High-speed clock input pin. This pin is used as the secondary function of PB6 pin and Secondary, also as the tertiary function of PA2 pin. Tertiary Low-speed clock output pin. This pin is used as the secondary function of PB7 pin and Secondary, also as the tertiary function of the PA1. Tertiary High-speed clock output pin. This pin is used as the tertiary function of the PA0 and PB0 Tertiary pin. General Purpose Input/Output Port PA0 to PA2 General-purpose input/output port. PB0 to PB7 I/O Since these pins have secondary, tertiary or quaternary functions, the pins cannot be used PC0 to PC7 as a port when the secondary, tertiary or quaternary functions are used. PD0 to PD5 O I TXD1 O RXD1 I -- -- -- Primary Positive Secondary Positive Secondary -- Secondary Positive UART0 data output pin. This pin is used as the tertiary function of the PB1 and PB4 pin. Tertiary UART0 data input pin. This pin is used as the primary function of the PB0 and PB5 pin Primary UART1 data output pin. This pin is used as the tertiary function of the PB3 pin and also Tertiary the quaternary function of the PB1 and PB4 pin. Quaternary UART1 data input pin. This pin is used as the primary function of the PB2 and PB7 pin. Primary Positive Positive Synchronous Serial I/O SIN I Synchronous serial data input pin. This pin is used as the secondary function of PB3 pin. Synchronous serial clock input/output pin. This pin is used as the secondary function of SCK I/O PB5 pin. Synchronous serial data output pin. This pin is used as the secondary function of PB4 SOUT O pin. UART TXD0 RXD0 Negative Positive Positive 2 I C Bus Interface SCL SDA Serial clock input/output. This pin is used as the tertiary function of the PB5 and the secondary function of the PC4 pin. Serial data input/output. This pin is used as the tertiary function of the PB6 and the I/O secondary function of the PC5 pin. I/O Tertiary Secondary Tertiary Secondary Positive Positive PWM PWMC O PWMC output pin. This pin is used as the secondary function of the PA0 and PB0 and Secondary also the quaternary function of the PB7 pin. Quaternary PWMD O PWMD output pin. This pin is used as the secondary function of the PA1 and PB1 pin. Secondary PWME O PWME output pin. This pin is used as the secondary function of the PA2 and PB2 pin. Secondary PWMF0 O PWMF0 output pin. This pin is used as the tertiary function of the PB7 and PC0 pin. PWMF1 O PWMF1 output pin. This pin is used as the tertiary function of the PC1 and also the Tertiary/ quaternary function of PB6 pin. Quaternary Tertiary Positive/ Negative Positive/ Negative Positive/ Negative Positive/ Negative Positive/ Negative 10/26 FEDL610Q111-01 ML610Q111/ML610Q112 PWMF2 Pin name O PWMF2 output pin. This pin is used as the tertiary function of the PC2 and also the Tertiary/ quaternary function of the PB5 pin. Quaternary I/O Description Positive/ Negative Primary Secondary Tertiary, Quaternary Logic Primary Positive/ negative Primary Positive/ negative External Interrupt EXI0 to 2 I EXI4 to 7 I External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the PA0 - PA2 pins. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the PB0 - PB3 pins. Timer TETE, TFTG I TM9OUT TMFOUT O O External clock input pin used for both Timer E and Timer F.These pins are used as the Primary primary function of the PA0-PA2, PB0-PB7 pins. Timer 9 output pin. This pin is used as the quaternary function of the PA0 and PC0 pin. Quaternary Timer F output pin. This pin is used as the quaternary function of the PA1 and PC3 pin. Quaternary Successive approximation type A/D converter AIN0 I Channel 0 analog input for successive approximation used as the primary function of the PA0 pin. AIN1 I Channel 1 analog input for successive approximation used as the primary function of the PA1 pin. AIN2 I Channel 2 analog input for successive approximation used as the primary function of the PB0 pin. AIN3 I Channel 3 analog input for successive approximation used as the primary function of the PB1 pin. AIN4 I Channel 4 analog input for successive approximation used as the primary function of the PB6 pin. AIN5 I Channel 5 analog input for successive approximation used as the primary function of the PB7 pin. AIN6 I Channel 6 analog input for successive approximation used as the primary function of the PC6 pin. AIN7 I Channel 7 analog input for successive approximation used as the primary function of the PC7 pin. type A/D converter. This pin is type A/D converter. This pin is type A/D converter. This pin is type A/D converter. This pin is type A/D converter. This pin is type A/D converter. This pin is type A/D converter. This pin is type A/D converter. This pin is -- Positive Positive Primary -- Primary -- Primary -- Primary -- Primary -- Primary -- Primary -- Primary -- Comparator CMP0P I CMP0M CMP0OUT CMP1P I O I CMP1OUT O Non-inverting input for comparator0. This pin is used as the primary function of the PB4 Primary pin. Inverting input for comparator0. This pin is used as the primary function of the PB5 pin. Primary Output for comparator0. This pin is used as the quaternary function of the PA2 pin. Quaternary Non-inverting input for comparator1. This pin is used as the primary function of the PA1 Primary pin. Output for comparator1. This pin is used as the quaternary function of the PB0 pin. Quaternary -- -- -- -- -- TEST TEST TESTF I/O Input/output pin for testing. A pull-down resistor is internally connected. -- Test pin for flash memory. A pull-down resistor is internally connected. -- -- Positive -- Power Supply VSS VDD -- -- -- -- -- -- Negative power supply pin. Positive power supply pin. 11/26 FEDL610Q111-01 ML610Q111/ML610Q112 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins for ML610Q111/ML610Q112 Table 3. Termination of Unused Pins Pin RESET_N TEST TESTF PA0 to PA2 PB0 to PB7 PC0 to PC7 PD0 to PD5 N.C. Recommended pin termination Open Open Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 12/26 FEDL610Q111-01 ML610Q111/ML610Q112 ELECTRICAL CHARACTERISTICS z ABSOLUTE MAXIMUM RATINGS (VSS=0V) z Parameter Symbol Condition Rating Unit Power supply voltage VDD Ta = 25C -0.3 to +7.0 V Input voltage VIN Ta = 25C -0.3 to VDD+0.3 V Output voltage VOUT Ta = 25C -0.3 to VDD+0.3 V Output current IOUT Ta = 25C -12 to +11 mA Power dissipation PD Ta = 25C 0.84 W Storage temperature TSTG -55 to 150 C RECOMMENDED OPERATING CONDITIONS (VSS=0V) z Parameter Symbol Condition Range Unit Operating temperature (ambience) TOP -40 to +105 C Operating voltage VDD 2.7 to 5.5 V Condition Rating Unit -40 to +105 -20 to +85 6000 80 Program flash and Data flash memory C C FLASH MEMORY SPECIFICATION (VSS= 0V) Parameter Symbol Operating temperature (ambience) TOPF Rewrite counts*1 CEPD CEPP At read At write/erase Data flash memory (4KB) Program flash memory Chip-erase cycles Block-erase 8 KB (Program flash memory) Erase unit Block-erase 4 KB (Data flash memory) Sector-erase 1 KB (Data flash memory) Erase time (max.) Chip-erase/Block-erase/Sector-erase 100 ms Write unit 1word(2bytes) Write time (max.) 1word(2bytes) 40 s Data retention*2 YDR 15 years 1 * : Rewrite counts is counted as one even if you erase suspend. *2: However, keep active time of the LSI from exceeding ten years. In addition, following capability of Flash memory is available; - security function: providing security ID for the protection of program code implemented in Flash memory - accidental-write protection: providing special sequence to protect accidental write data to Flash memory. By writing "0FAx" and"0F5x" sequentially, before write/erase, writing one word is available just only one time. - erase interrupt function: in the case of external interrupt during erasing flash memory, erase execution is suspended. And then the interrupt is activated. Please re-erase after interrupt execution. 13/26 FEDL610Q111-01 ML610Q111/ML610Q112 z DC CHARACTERISTICS (Supply Current) Parameter Symbol Supply current 1 IDD1 Supply current 2 IDD2 Supply current 3 Supply current 4 IDD3 IDD4 (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Measuring Condition CPU : In STOP state (All clock stop) VDD=5.0V CPU : In HALT state*1 (Only CR oscillation operates) VDD=5.0V CPU : CR32.768kHz operating state*2 (Only CR oscillation operates) VDD=5.0V CPU : CR8.192MHz 3 operating state* (CR and PLL oscillation operate) Unit Min. Typ. Max. 1 50 A 240 A circuit 1 250 A 4 6 mA VDD=5.0V *1 : LTBC and WDT are operating ,and significant bits of BLKCON0 to BLKCON7 registers are all "1". *2 : When the CPU operating rate is 100%. Minimum instruction execution time: Approx 30.52 s (at 32.768kHz system clock) 3 * : When the CPU operating rate is 100%. Minimum instruction execution time: Approx 122 ns (at 8.192MHz system clock) 14/26 FEDL610Q111-01 ML610Q111/ML610Q112 z DC CHARACTERISTICS (VLS, Comparator) Parameter VLS0 threshold voltage Symbol Condition Min. Typ -3.0% Typ -5.0% Typ -3.0% Typ -5.0% Ta=25C VVLS0F (VDD=fall) VLS0 threshold voltage (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Measuring Ta=25C VVLS0R (VDD=rise) VLS1=0 VLS1=1 Ta=25C VLS1 threshold voltage (VDD=fall) VLS1=2 VVLS1 Comparator0 Input offset voltage Comparator Referencevoltage error*1 VCMR VHYSP VCMOF VCMREF 2.92 3.6 3.9 4.2 VLS1=0 3.3 VLS1=2 Max. Typ -5.0% 3.6 3.9 Unit circuit Typ +3.0% Typ +5.0% Typ +3.0% Typ +5.0% 3.3 Typ -3.0% VLS1=3 Comparator0 In-phase input voltage range Comparator0 hysteresis 2.85 VLS1=3 VLS1=1 Typ. V Typ +3.0% 1 Typ +5.0% 4.2 0.1 VDD -1.5 Ta=25C , VDD = 5.0V 10 20 30 VDD = 5.0V 5 20 35 Ta=25C , VDD = 5.0V 7 Ta=25C -25 25 -50 50 V mV 1 * :Comparator input offset voltage is included. 15/26 FEDL610Q111-01 ML610Q111/ML610Q112 z DC CHARACTERISTICS (IO pins) Parameter Symbol Condition (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Measuring Min. Typ. Max. IOH=-3.0mA, VDD=4.5V* Ta= -40 to 85C VDD -0.7 IOH=-3.0mA, VDD=4.5V*1 VDD -0.8 IOL=+8.5mA, VDD=4.5V*1 Ta= -40 to 85C 0.6 IOL=+8.5mA, VDD=4.5V*1 0.7 VOL2 IOL=+3.0mA 0.4 Output leakage ( PA0-2, PB0-7, PC0-7, PD0-5 ) IOOH VOH = VDD (in high-impedance state) 1 IOOL VOL = VSS (in high-impedance state) -1 Input current 1 ( RESET_N ) IIH1 VIH1 = VDD 1 IIL1 VIL1 = VSS, VDD = 5.0V -650 -500 -350 Input current 2 ( TEST ) IIH2 VIH2= VDD = 5.0V 20 115 200 IIL2 VIL2 = VSS -1 IIH3 VIH3 = VDD = 5.0V (when pulled-down) 20 115 200 IIL3 VIL3 = VSS, VDD = 5.0V (when pulled-up) -200 -100 -20 IIH3Z VIH3 = VDD (in high-impedance stat) 1 IIL3Z VIH3 = VSS (in high-impedance stat) -1 1 VOH1 Output voltage1 ( TEST, PA0-2, PB0-7, PC0-7, PD0-5 ) VOL1 Output voltage2 (PB5, PB6 PC4, PC5) Input current 3 ( PA0-2, PB0-7, PC0-7, PD0-5 ) Unit circuit V 2 A 3 A 4 *1 : When the one terminal output state. Parameter Symbol Condition Input voltage 1 ( RESET_N, TEST, PA0-2, PB0-7, PC0-7, PD0-5 ) VIH1 Input pin capacitance ( PA0-2, PB0-7, PC0-7, PD0-5 ) (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Measuring Min. Typ. Max. 0.7 xVDD VDD Unit circuit V 2 VIL1 0 0.3 xVDD CIN f = 10kHz Ta = 25C 20 pF 16/26 FEDL610Q111-01 ML610Q111/ML610Q112 z MEASURING CIRCUITS Measuring circuit 1 Measuring circuit 2 (*2) VDD VIL VSS VDD Output pins (*1) Input pins Input pins Output pins VIH V VSS A CV CV : 1F Measuring circuit 3 Measuring circuit 4 (*2) VDD Output pins A VSS Input pins Input pins VIL A VDD Output pins (*3) VIH VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. *3: Measured at the specified input pins. 17/26 FEDL610Q111-01 ML610Q111/ML610Q112 z AC CHARACTERISTICS (Clock) Parameter (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Symbol 32kHz RC oscillation frequency Condition Min. Ta = -20 to 85C Typ. -3% Typ. -4% Ta = -20 to 85C Typ. -3% Typ. -4% fRCL PLL oscillation frequency *1 fPLL Typ. 32.768 16.384 Max. Typ. +3% Typ. +4% Typ. +3% Typ. +4% Unit kHz MHz *1 : 1024 clock average. Maximum CPU clock frequency is fPLL/2. z AC CHARACTERISTICS (Power on / Reset sequence) Parameter Symbol Reset pulse width PRST Reset noise elimination pulse width Power-on reset activation power rise time VDD (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Condition Min. Typ. Max. 100 PNRST 0.4 TPOR 10 Unit s ms 0.9*VDD 0.3*VDD RESET_N 0.3*VDD PRST 0.3*VDD PRST External Reset sequence 0.9*VDD VDD 0.1*VDD TPOR Power-on Reset sequence 18/26 FEDL610Q111-01 ML610Q111/ML610Q112 z AC CHARACTERISTICS (External Interrupt) (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Parameter Symbol Condition External interrupt disable period TNUL Interrupt: Enabled (MIE = 1), CPU: NOP operation Min. 2.5 x sysclk Rating Typ. Max. 3.5 x sysclk Unit PA0 - PA2, PB0 - PB3 (Rising-edge interrupt) tNUL PA0 - PA2, PB0 - PB3 (Falling-edge interrupt) tNUL PA0 - PA2, PB0 - PB3 (Both-edge interrupt) tNUL 19/26 FEDL610Q111-01 ML610Q111/ML610Q112 z AC CHARACTERISTICS (Synchronous Serial Port) (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Parameter Symbol Condition SCK input cycle (slave mode) tSCYC When high-speed oscillation is not active When high-speed oscillation is active SCKoutput cycle (master mode) tSCYC tSW When high-speed oscillation is not active When high-speed oscillation is active SCK input pulse width (slave mode) Min. Rating Typ. Max. 10 s 500 ns SCK*1 s 4 s 200 ns tSCYC x0.6 s 180 ns 80 ns ns ns tSCYC tSCYC SCK output pulse width tSW x0.4 x0.5 (master mode) SOUT output delay tSD (slave mode) SOUT output delay tSD (master mode) SIN input 50 tSS setup time (slave mode) SIN input 50 tSH hold time 1 * : Clock period selected with S0CK3-0 of the serial port 0 mode register(SIO0MOD1) Unit tSCYC tSW tSW SCK0 tSD tSD SOUT0 tSS tSH SIN0 20/26 FEDL610Q111-01 ML610Q111/ML610Q112 z z AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz) Parameter Symbol SCL clock frequency SCL hold time (start/restart condition) SCL"L" level time SCL"H" level time SCL setup time (restart condition) SDA hold time SDA setup time SDA setup time (stop condition) Bus-free time fSCL (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. 0 100 kHz tHD:STA 4.0 s tLOW tHIGH 4.7 4.0 s s tSU:STA 4.7 s tHD:DAT tSU:DAT 0 0.25 s s tSU:STO 4.0 s tBUF 4.7 s AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz) Parameter Symbol SCL clock frequency SCL hold time (start/restart condition) SCL"L" level time SCL"H" level time SCL setup time (restart condition) SDA hold time SDA setup time SDA setup time (stop condition) Bus-free time fSCL (VDD=2.7 to 5.5V, VSS=0V, Tj=-40 to +105C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. 0 400 kHz tHD:STA 0.6 s tLOW tHIGH 1.3 0.6 s s tSU:STA 0.6 s tHD:DAT tSU:DAT 0 0.1 s s tSU:STO 0.6 s tBUF 1.3 s start condition restart condition stop condition SDA SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 21/26 FEDL610Q111-01 ML610Q111/ML610Q112 z Electrical Characteristics of Successive Approximation Type A/D Converter Parameter Symbol Resolution Integral non-linearity error Differential non-linearity error Zero-scale error Full-scale error n INL Conversion time (VDD=2.7 to 5.5V, VSS=0V, Ta=-40 to +105C, unless otherwise specified) Rating Condition Min. Typ. Max. -4 10 +4 DNL -3 +3 VOFF FSE -4 -4 +4 +4 tCONV 102 Unit bit LSB /CH : period of OSCLK (more than 3MHz) VDD A - 10F Analog input RI 5k AIN + 0.1F VSS 22/26 FEDL610Q111-01 ML610Q111/ML610Q112 PACKAGE DIMENSIONS z ML610Q111-xxxTD Figure 4 TSSOP20 23/26 FEDL610Q111-01 ML610Q111/ML610Q112 z ML610Q112-xxxTC Figure 5 LQFP32 z Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/26 FEDL610Q111-01 ML610Q111/ML610Q112 REVISION HISTORY Page Document No. Date Previous Edition Current Edition Description FEDL610Q111-01 2013.9.26 Final edition 1 25/26 FEDL610Q111-01 ML610Q111/ML610Q112 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. 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Copyright 2013 LAPIS Semiconductor Co., Ltd. 26/26 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ROHM Semiconductor: ML610Q112-NNNTCZ07FL ML610Q111-NNNTDZ07FL ML610Q112 reference board ML610Q111 reference board